WO2019085577A1

WO2019085577A1 - Insulated gate bipolar transistor device and manufacturing method therefor, and power electronic equipment

Info

Publication number: WO2019085577A1
Application number: PCT/CN2018/099611
Authority: WO
Inventors: 史波
Original assignee: 格力电器（武汉）有限公司; 珠海格力电器股份有限公司
Priority date: 2017-10-31
Filing date: 2018-08-09
Publication date: 2019-05-09
Also published as: CN107706237B; CN107706237A

Abstract

The present invention provides an insulated gate bipolar transistor device and a manufacturing method therefor, and power electronic equipment, so as to improve the overall performance and the applicability of the insulated gate bipolar transistor device. The insulated gate bipolar transistor device comprises a gate structure, which comprises a plurality of plane gate units and a plurality of groove gate units; the plurality of plane gate units is positioned on the same layer; the plurality of groove gate units is positioned on one side of the plurality of the plane gate units, and is intersected with the layer of the plurality of plane gate units; and each plane gate unit is connected to at least two adjacent groove gate units.

Description

Edge gate bipolar transistor device and manufacturing method thereof, power electronic device

Technical field

The present invention relates to the field of power electronics, and in particular to an insulated gate bipolar transistor device, a method of fabricating the same, and a power electronic device.

Background technique

In the field of power electronics, Insulated Gate Bipolar Transistors (IGBTs) are the most representative power devices. The IGBT is a composite fully-regulated voltage-driven semiconductor power device composed of a Bipolar Junction Transistor (BJT) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS). Suitable for converter systems with DC voltages of 600V and above, such as AC motors, inverters, switching power supplies, lighting circuits, traction drives, etc.

At present, how to improve the comprehensive performance of IGBT devices and improve the applicability of IGBT devices is a technical problem to be solved.

Summary of the invention

An object of the embodiments of the present invention is to provide an IGBT device, a manufacturing method thereof, and a power electronic device to improve the overall performance of the IGBT device and improve the applicability of the IGBT device.

An embodiment of the present invention provides an IGBT device including a gate structure. The gate structure includes a plurality of planar gate cells and a plurality of trench gate cells, wherein: the plurality of planar gate cells are located on the same layer, and the plurality of trenches The trench gate unit is located at one side of the plurality of planar gate units and intersects a layer where the plurality of planar gate units are located, and each of the planar gate units is connected to at least two adjacent trench gate units.

Optionally, the plurality of trench gate cells are orthogonal to a plane where the plurality of planar gate cells are located.

Optionally, the plurality of trench gate units are arranged in an array, and the planar gate unit connects four adjacent trench gate units adjacent to each other in a row.

Optionally, the planar gate unit is a polysilicon planar gate unit, and the trench gate unit is a polysilicon trench gate unit.

Optionally, the overlapping width of the planar gate unit and the trench gate unit is 0.8-1.2 μm.

Optionally, the IGBT device specifically includes: an N-type semiconductor substrate, a P-type well, an N-type emitter, and a P-type well disposed on one side of the N-type semiconductor substrate and in a direction away from the N-type semiconductor substrate a dielectric layer, the gate structure, the second dielectric layer, the first metal layer, and the passivation protective layer, and sequentially disposed on the other side of the N-type semiconductor substrate and in a direction away from the N-type semiconductor substrate N-type field stop layer, P-type collector region and second metal layer; wherein:

The overall structure of the N-type semiconductor substrate, the P-type well and the N-type emitter has a trench opening away from the N-type field stop layer, and the trench gate unit is located in the trench;

The P-type well has a P-type contact region on a side away from the N-type semiconductor substrate, and the entire structure of the second dielectric layer, the first dielectric layer and the N-type emitter has a first-pass to the P-type contact region a contact hole; the second dielectric layer has a second contact hole leading to the gate structure;

The first metal layer includes an emitter metal connected to the P-type contact region through the first contact hole, and a gate connection metal connected to the gate structure through the second contact hole.

Optionally, the trench has a depth of 4 to 6 μm.

Optionally, the first contact hole is located between two adjacent planar gate units adjacent to each other in the row direction and between the two planar gate units adjacent to each other in the column direction.

Optionally, the gate connection metal includes a frame-shaped lead portion and a lead portion connected to the frame-shaped lead portion, wherein the frame-shaped lead portion is disposed around the gate structure and passes through the second contact hole and the gate Structural connection.

The IGBT device provided by the embodiment of the invention has a gate structure of a composite structure of a planar gate unit and a trench gate unit. With this design, the gate resistance can be effectively reduced; the IGBT device with respect to the trench gate structure, the gate input capacitance Smaller, thus improving the switching frequency of the device; compared with the trench gate structure of the IGBT device, the saturation voltage drop is increased, thereby reducing the short-circuit current and improving the short-circuit characteristics; and the IGBT device relative to the planar gate structure is balanced. Parameters of saturation voltage drop and short circuit characteristics, and the area of the chip is also reduced. The specific dimensions of the planar gate unit and the trench gate unit can be flexibly adjusted according to the parameter requirements of the device. Therefore, compared with the prior art, the performance of the IGBT device of the embodiment of the present invention is comprehensively improved, and the applicability is stronger.

The embodiment of the invention further provides a power electronic device, comprising the IGBT device described above according to any of the foregoing technical solutions. Since the IGBT device has the above-described advantageous effects, the electrical performance of the power electronic device is also better.

The embodiment of the invention further provides a method for fabricating an IGBT device, comprising the following steps:

Forming a gate structure, the gate structure includes a plurality of planar gate cells and a plurality of trench gate cells, wherein: the plurality of planar gate cells are located on a same level, and the plurality of trench gate cells are located in the plurality of planar gate cells One side intersects with a layer on which the plurality of planar gate units are located, and each of the planar gate units is connected to at least two adjacent trench gate units.

Optionally, the forming the gate structure, specifically includes:

Forming a first oxide film and a mask oxide layer on one side surface of the N-type semiconductor substrate;

Etching the first oxide film and the mask oxide layer to form a mask pattern, wherein the mask pattern includes a cutout region corresponding to the trench gate unit;

Etching the N-type semiconductor substrate through the hollow region of the mask pattern to form a trench;

Forming a second oxide film on the surface of the trench, the second oxide film and the etched first oxide film as the first dielectric layer;

Removing the etched mask oxide layer;

Forming the trench gate unit in the trench and the planar gate unit on the surface of the etched first oxide film.

Optionally, the foregoing manufacturing method further includes:

Forming a P-type well and an N-type emitter on a side of the N-type semiconductor substrate adjacent to the planar gate unit, wherein the P-type well, the N-type emitter, and the first dielectric layer are sequentially adjacent to the planar gate unit arrangement;

Forming a second dielectric layer on a side of the gate structure away from the first dielectric layer, the second dielectric layer having a first contact hole leading to the P-type well and a second contact hole leading to the gate structure, The first contact hole is located between two adjacent planar gate cells adjacent in the row direction and located between two adjacent planar gate cells adjacent in the column direction;

Forming a P-type contact region exposed to the first contact hole on a side of the P-type well adjacent to the N-type emitter;

Forming a first metal layer on a side of the second dielectric layer away from the gate structure, the first metal layer including an emitter metal connected to the P-type contact region through the first contact hole, and through the second contact a gate connection metal connected to the gate structure;

A passivation protective layer is formed on a side of the first metal layer away from the second dielectric layer.

Optionally, the foregoing manufacturing method further includes:

After forming the gate structure, an N-type field stop layer, a P-type collector region, and a second metal layer are sequentially formed on a side of the N-type semiconductor substrate away from the gate structure.

The IGBT device fabricated by the method of the above embodiment has comprehensively improved device performance and is more applicable.

DRAWINGS

The accompanying drawings, which are incorporated in the claims of the claims In the drawing:

1 is a top plan view of a planar gate structure of a conventional IGBT device;

2 is a top plan view of a trench gate structure of a conventional IGBT device;

3 is a top view of a resistance connection of a conventional trench gate structure;

4 is a perspective view showing a gate structure of an IGBT device according to an embodiment of the present invention;

5 is a top plan view of a gate structure of an IGBT device according to an embodiment of the present invention;

6 is a schematic longitudinal cross-sectional view of an IGBT device according to an embodiment of the present invention;

7 is a schematic structural view of a cell of an IGBT device according to an embodiment of the present invention;

8 is a top view showing a resistance connection of a gate structure of an IGBT device according to an embodiment of the present invention;

Figure 9 is a cross-sectional view taken along line A-A of Figure 5;

Figure 10 is a cross-sectional view taken along line B-B of Figure 5;

Figure 11 is a cross-sectional view taken along line C-C of Figure 5;

12 is a schematic diagram of an equivalent circuit of an IGBT device;

13 is a schematic view showing the comparison of the input capacitance of the gate structure of the present embodiment and the existing planar gate structure and trench gate structure;

14 is a schematic view showing a comparison of saturation voltage drop between a gate structure and a conventional planar gate structure and a trench gate structure according to the embodiment;

15 is a flow chart of a method for fabricating an IGBT device according to an embodiment of the present invention;

16a to 16i are schematic diagrams showing the process of fabricating an IGBT device according to an embodiment of the present invention.

Wherein, the above figures include the following reference numerals:

Existing technology section:

011, planar gate unit; 012, trench gate unit; 013, emitter contact hole; 072, gate connection metal.

Part of the embodiment of the invention:

1. Gate structure; 11, planar gate unit; 12, trench gate unit; 2. N-type semiconductor substrate; 3. P-type well; 4. N-type emitter; 5. First dielectric layer; Two dielectric layers; 7, a first metal layer; 8, a passivation protective layer; 9, an N-type field stop layer; 10, a P-type collector region; 13, a second metal layer; 14, a trench; Contact region; 16, first contact hole; 71, emitter metal; 72, gate connection metal; 721, frame lead portion; 722, lead portion; 51, first oxide film; , a second oxide film.

Detailed ways

It should be noted that the embodiments in the present invention and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments.

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is an embodiment of the invention, but not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of the present invention.

It is to be understood that the terms "first", "second" and the like in the specification and claims of the present invention are used to distinguish similar objects, and are not necessarily used to describe a particular order or order. It will be understood that the data so used may be interchanged where appropriate to facilitate the embodiments of the invention described herein. In addition, the terms "comprises" and "comprises" and "the" and "the" are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to Those steps or units may include other steps or units not explicitly listed or inherent to such processes, methods, products or devices.

In the prior art, the gate structure of the IGBT device generally adopts a planar gate structure as shown in FIG. 1 or a trench gate structure as shown in FIG. 2, wherein the planar gate structure includes a plurality of planar gate units 011, and a trench gate The structure includes a plurality of trench gate cells 012 that are located between adjacent planar gate cells 011 or trench gate cells 012. The IGBT device with planar gate structure has the advantages of low input capacitance, good short-circuit characteristics, simple process technology, etc., but also has defects such as large conduction voltage drop, large cell size and low integration degree; IGBT with respect to planar gate structure The IGBT device of the trench gate structure has the advantages of small on-voltage drop, small cell size and high integration, but also has defects such as large input capacitance, poor short-circuit characteristics and complicated process technology. Therefore, whether the planar gate structure or the trench gate structure is used, the parameter characteristics of the IGBT device cannot be well balanced.

In order to improve the overall performance of the IGBT device and improve the applicability of the IGBT device, an embodiment of the present invention provides an IGBT device, a manufacturing method thereof, and a power electronic device. In order to make the objects, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below.

As shown in FIG. 4 and FIG. 5, an IGBT device according to Embodiment 1 of the present invention includes a gate structure 1. The gate structure 1 includes a plurality of planar gate cells 11 and a plurality of trench gate cells 12, wherein: The planar gate unit 11 is located at the same level, and the plurality of trench gate units 12 are located at one side of the plurality of planar gate units 11 and intersect with a layer where the plurality of planar gate units 11 are located, and each of the planar gate units 11 and at least Two adjacent trench gate cells 12 are connected.

Referring to FIG. 4 and FIG. 5, in the embodiment of the present invention, the plurality of trench gate units 12 are orthogonal to the plane in which the plurality of planar gate units 11 are located. The plurality of trench gate cells 12 are arranged in an array, and the planar gate cells 11 connect four adjacent trench gate cells 12 adjacent to each other. It should be noted that, in other implementations of the present invention, the plane where the trench gate unit and the plurality of planar gate units are located may also be at an angle of less than 90 degrees; in addition, the planar gate unit and the trench gate unit may also be used. Other arrangement connections, for example, a planar gate unit connecting adjacent three trench gate units, etc., are not specifically limited herein.

In one embodiment, the planar gate cell 11 is a polysilicon planar gate cell and the trench gate cell 12 is a polysilicon trench gate cell. As shown in FIG. 5, FIG. 6, and FIG. 9 to FIG. 11, the IGBT device specifically includes an N-type semiconductor substrate 2 which is sequentially disposed on one side of the N-type semiconductor substrate 2 and in a direction away from the N-type semiconductor substrate 2. P-well 3, N-type emitter 4, first dielectric layer 5, aforementioned gate structure 1, second dielectric layer 6, first metal layer 7 and passivation protective layer 8, and N-type semiconductor substrate An N-type field stop layer 9, a P-type collector region 10, and a second metal layer 13 disposed on the other side of 2 and in a direction away from the N-type semiconductor substrate 2; wherein: N-type semiconductor substrate 2, P-type The overall structure of the well 3 and the N-type emitter 4 has a trench 14 opening away from the N-type field stop layer 9, the trench gate unit 12 is located in the trench 14; and the P-well 3 is away from the N-type semiconductor substrate 2 The side has a P-type contact region 15, the overall structure of the second dielectric layer 6, the first dielectric layer 5 and the N-type emitter 4 has a first contact hole 16 leading to the P-type contact region 15, and the second dielectric layer 6 has a pass a second contact hole (not shown) to the gate structure 1; the first metal layer 7 includes an emitter metal 71 connected to the P-type contact region 15 through the first contact hole 16, and a second contact hole The gate structure 1 is connected to the gate connection metal 72 (shown in FIG. 8). The gate connection metal 72 specifically includes a frame-shaped lead portion 721 and a lead portion 722 connected to the frame-shaped lead portion 721, wherein the frame-shaped lead portion The 721 is disposed around the gate structure 1 and connected to the gate structure 1 through the second contact hole.

As shown in FIG. 5, in this embodiment, the first contact hole 16 is located between the two planar gate cells 11 adjacent in the row direction and between the two planar gate cells 11 adjacent in the column direction. FIG. 7 shows a cell structure in the structure shown in FIG. 5. As can be seen from FIG. 5 and FIG. 7, the planar gate unit 11, the trench gate unit 12, and the first contact hole 16 are arranged in a compact manner. Smaller size and higher integration.

Figure 12 shows an equivalent circuit diagram of the IGBT device. When the IGBT device is in operation, during the gate turn-on process, the gate drive source charges the gate input capacitor Cies (Cies=Cge+Cgc), and the magnitude of the gate resistor Rg is inversely proportional to the peak current of the input capacitor Cies. The size of the capacitor Cies is proportional to the magnitude of the gate charge Qg, and the device operating frequency f is inversely proportional to the gate resistance Rg and the input capacitance Cies.

Referring to FIG. 3 and FIG. 8 , in the embodiment of the present invention, the trench gate unit 12 and the planar gate unit 11 are integrally connected in a crisscross network, which is equivalent to paralleling more resistors, thereby being effective. The gate resistance Rg is lowered. In the prior art shown in FIG. 3, the gate connection metal 072 is electrically connected to the trench gate unit 012.

The simulation comparison results of the IGBT device of the embodiment of the present invention and the input capacitor Cies of the IGBT device of the conventional trench gate structure and the IGBT device of the planar gate structure are shown in FIG. 13, and it can be seen that the IGBT is compared with the trench gate structure. The input capacitance Cies of the IGBT device of the embodiment of the present invention is effectively reduced.

The simulation comparison results of the IGBT device of the embodiment of the present invention and the saturation voltage drop Vce of the IGBT device of the conventional trench gate structure and the IGBT device of the planar gate structure are shown in FIG. 14, and it can be seen that the IGBT is compared with the planar gate structure. The rate of change of the saturation voltage drop Vce of the IGBT device of the embodiment of the present invention is relatively small.

According to the above simulation analysis, the IGBT device adopts the gate structure design of the embodiment of the invention, which can effectively reduce the gate resistance; the gate input capacitance is smaller than the IGBT device of the trench gate structure, thereby improving the switching of the device. Frequency; compared with the trench gate structure of the IGBT device, the saturation voltage drop is increased, thereby reducing the short-circuit current and improving the short-circuit characteristics; and the IGBT device of the planar gate structure balances the parameters of the saturation voltage drop and the short-circuit characteristic. And the area of the chip is also reduced. A cell structure of the IGBT device is shown in FIG. 7, wherein the specific dimensions of the planar gate unit 11 and the trench gate unit 12, such as W1, W2, etc., can be adjusted by simulation and layout design to meet different devices. Parameter requirements. Compared with the prior art, the performance of the IGBT device of the embodiment of the invention is comprehensively improved, and the applicability is stronger.

In the above embodiment of the present invention, as shown in FIG. 7, the overlapping width c of the planar gate unit 11 and the trench gate unit 12 is 0.8 to 1.2 μm to achieve reliable connection of the planar gate unit 11 and the trench gate unit 12. The depth of the trench is 4 to 6 μm, which can be flexibly adjusted according to the parameter requirements of different devices.

An embodiment of the present invention further provides a power electronic device, including the IGBT device of any of the foregoing technical solutions. Since the IGBT device has the above-described advantageous effects, the electrical performance of the power electronic device is also better. The specific type of power electronic equipment is not limited, and may be, for example, an AC motor, a frequency converter, a switching power supply, a lighting device, or a traction drive device.

Based on the same inventive concept, an embodiment of the present invention further provides a method for fabricating an IGBT device, including the following steps:

Forming a gate structure, the gate structure includes a plurality of planar gate cells and a plurality of trench gate cells, wherein: the plurality of planar gate cells are on the same layer, and the plurality of trench gate cells are located on one side of the plurality of planar gate cells, and Each of the planar gate cells is connected to at least two adjacent trench gate cells.

As shown in FIG. 15, in a specific embodiment of the present invention, a method for fabricating an IGBT device specifically includes the following steps:

Step 101, as shown in FIG. 16a, a first oxide film 51 and a mask oxide layer 100 are sequentially formed on one surface of the N-type semiconductor substrate 2. The N-type semiconductor substrate can adopt an N-type single crystal silicon wafer. First, a protective thin oxide layer is formed on the surface of the N-type single crystal silicon wafer by using a growth process as a first oxide film, and then a growth process is continuously formed. The layer thickness oxide layer serves as a mask oxide layer.

Step 102, as shown in FIG. 16b, etching the first oxide film 51 and the mask oxide layer 100 to form a mask pattern including a cutout region corresponding to the trench gate unit. This step can be accomplished by photolithography and etching processes.

Step 103, as shown in FIG. 16c, etching the N-type semiconductor substrate 2 through the hollow region of the mask pattern to form the trench 14. The etching of the N-type semiconductor substrate can be performed by a plasma etching process, and the depth of the trench is in the range of 4 to 6 μm, and the specific depth can be flexibly adjusted according to the parameter requirements of different devices.

Step 104, as shown in FIG. 16d, a second oxide film 52 is formed on the surface of the trench 14, and the second oxide film 52 and the etched first oxide film 51 serve as a first dielectric layer of the IGBT device. Similar to the first oxide film, the second oxide film can be formed on the surface of the trench by a growth process to protect the surface of the trench.

Step 105, removing the etched mask oxide layer. At this time, the second oxide film and the etched first oxide film serve as a first dielectric layer for isolating the N-type semiconductor substrate from the subsequently fabricated gate structure.

Step 106, as shown in Fig. 16e, forms a trench gate unit 12 located in the trench, and a planar gate unit 11 on the surface of the etched first oxide film 51. Specifically, first, a thick polysilicon layer is deposited on the side of the first dielectric layer away from the N-type semiconductor substrate by chemical vapor deposition, and the trench is filled, and then the trench gate unit is formed by photolithography and etching processes. And the pattern of the planar gate unit, that is, the pattern forming the gate structure. After this step is completed, the gate structure is completed.

Step 107, as shown in FIG. 16f, a P-type well 3 and an N-type emitter 4, a P-type well 3, an N-type emitter 4 and a first medium are formed on a side of the N-type semiconductor substrate 2 close to the planar gate unit 11. The layer structures of the layers 5 are sequentially arranged in the direction close to the planar gate unit 11. Specifically, first, a P-type impurity is doped on the side of the N-type semiconductor substrate close to the planar gate unit by ion implantation and thermal diffusion, so that a P-type well is formed, and then the P-type well is approached by ion implantation and thermal diffusion processes. One side of the planar gate unit is doped with an N-type impurity to form an N-type emitter.

Step 108, as shown in FIG. 16g, forming a second dielectric layer 6 on a side of the gate structure away from the first dielectric layer 5, the second dielectric layer 6 having a first contact hole 16 leading to the P-type well 3 and a path A second contact hole (not shown) of the gate structure, as shown in FIG. 5, is such that the first contact hole 16 is located between the two planar gate units 11 adjacent to each other in the row direction and is located along the column direction. Between two adjacent planar gate units 11 . The second dielectric layer may be an oxide film layer, deposited by chemical vapor deposition, and then patterned by the photolithography and etching processes to form the first contact hole and the second contact hole.

Step 109, as shown in FIG. 16g, a P-type contact region 15 exposed to the first contact hole 16 is formed on a side of the P-type well 3 close to the N-type emitter 4. Specifically, a P-type impurity is doped in a region where the P-type well is exposed to the first contact hole by an ion implantation and a thermal diffusion process, thereby forming a P-type contact region.

Step 110: As shown in FIG. 16h, a first metal layer is formed on a side of the second dielectric layer 6 away from the gate structure, and the first metal layer includes an emitter metal 71 connected to the P-type contact region 15 through the first contact hole. And a gate connection metal connected to the gate structure through the second contact hole. Specifically, a metal layer is sputtered by physical vapor deposition, and then a pattern of the first metal layer is formed by photolithography and etching processes.

Step 111, as shown in FIG. 16h, a passivation protective layer 8 is formed on a side of the first metal layer away from the second dielectric layer 6, and the passivation protective layer 8 exposes part of the emitter metal 71 to be electrically connected to the outside. In addition, the passivation protective layer 8 also protects the device from environmental moisture and impurities.

Step 112, as shown in Fig. 16i, an N-type field stop layer 9, a P-type collector region 10, and a second metal layer 13 are sequentially formed on the side of the N-type semiconductor substrate 2 away from the gate structure. The N-type field stop layer and the P-type collector region are formed by an ion implantation and diffusion process, and the second metal layer is formed by a physical vapor deposition process.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

An insulated gate bipolar transistor device comprising a gate structure, wherein the gate structure comprises a plurality of planar gate cells and a plurality of trench gate cells, wherein: the plurality of planar gate cells are on the same level The plurality of trench gate cells are located on one side of the plurality of planar gate cells and intersect with a layer on which the plurality of planar gate cells are located, each of the planar gate cells and at least two adjacent cells The trench gate cell connections are described.
The insulated gate bipolar transistor device of claim 1 wherein said plurality of trench gate cells are orthogonal to a plane in which said plurality of planar gate cells are located.
The insulated gate bipolar transistor device according to claim 1, wherein said plurality of trench gate cells are arranged in an array, said planar gate cells having four adjacent rows adjacent to each other The trench gate unit is connected.
The insulated gate bipolar transistor device according to claim 1, wherein said planar gate unit is a polysilicon planar gate unit, and said trench gate unit is a polysilicon trench gate unit.
The insulated gate bipolar transistor device according to claim 1, wherein an overlap width of said planar gate unit and said trench gate unit is 0.8 to 1.2 μm.
The insulated gate bipolar transistor device according to claim 1, wherein said insulated gate bipolar transistor device comprises: an N-type semiconductor substrate on one side of said N-type semiconductor substrate a P-type well, an N-type emitter, a first dielectric layer, the gate structure, a second dielectric layer, a first metal layer, and a passivation protective layer disposed in sequence away from the direction of the N-type semiconductor substrate, and An N-type field stop layer, a P-type collector region, and a second metal layer disposed on the other side of the N-type semiconductor substrate and sequentially disposed away from the N-type semiconductor substrate; wherein:

The overall structure of the N-type semiconductor substrate, the P-type well, and the N-type emitter has a trench opening away from the N-type field stop layer, the trench gate unit being located in the trench ;

a side of the P-type well away from the N-type semiconductor substrate has a P-type contact region, and an overall structure of the second dielectric layer, the first dielectric layer and the N-type emitter has a a first contact hole of the P-type contact region; the second dielectric layer has a second contact hole leading to the gate structure;

The first metal layer includes an emitter metal connected to the P-type contact region through the first contact hole, and a gate connection metal connected to the gate structure through the second contact hole.
The insulated gate bipolar transistor device according to claim 6, wherein the trench has a depth of 4 to 6 μm.
The insulated gate bipolar transistor device according to claim 6, wherein said first contact hole is located between two adjacent said planar gate cells in a row direction and adjacent to two adjacent columns Between the planar gate units.
The insulated gate bipolar transistor device according to claim 6, wherein the gate connection metal comprises a frame-shaped lead portion and a lead portion connected to the frame-shaped lead portion, wherein the frame-shaped lead A portion is disposed around the gate structure and connected to the gate structure through the second contact hole.
A power electronic device comprising the insulated gate bipolar transistor device according to any one of claims 1 to 9.
A method for fabricating an insulated gate bipolar transistor device, comprising the steps of: forming a gate structure, the gate structure comprising a plurality of planar gate cells and a plurality of trench gate cells, wherein: The planar gate cells are located at the same level, the plurality of trench gate cells are located on one side of the plurality of planar gate cells, and intersect with a layer where the plurality of planar gate cells are located, each of the planar gate cells and At least two adjacent ones of the trench gate cells are connected.
The method of claim 11 , wherein the forming the gate structure comprises:

Forming a first oxide film and a mask oxide layer on one side surface of the N-type semiconductor substrate;

Etching the first oxide film and the mask oxide layer to form a mask pattern, the mask pattern including a cutout region corresponding to the trench gate unit;

Etching the N-type semiconductor substrate through the cutout region of the mask pattern to form a trench;

Forming a second oxide film on the surface of the trench, the second oxide film and the etched first oxide film as a first dielectric layer;

Removing the etched mask oxide layer;

Forming the trench gate unit in the trench, and a planar gate unit on the surface of the etched first oxide film.
The manufacturing method according to claim 12, wherein the manufacturing method further comprises:

Forming a P-type well and an N-type emitter on a side of the N-type semiconductor substrate adjacent to the planar gate unit, the P-type well, the N-type emitter, and the first dielectric layer being adjacent to The directions of the planar gate units are arranged in sequence;

Forming a second dielectric layer on a side of the gate structure away from the first dielectric layer, the second dielectric layer having a first contact hole leading to the P-type well and a gate structure a second contact hole, the first contact hole being located between two adjacent planar gate cells adjacent to the row and located between two adjacent planar gate cells adjacent to the column;

Forming a P-type contact region exposed to the first contact hole on a side of the P-type well adjacent to the N-type emitter;

Forming a first metal layer on a side of the second dielectric layer away from the gate structure, the first metal layer including an emitter metal connected to the P-type contact region through the first contact hole, and Connecting a metal to the gate connected to the gate structure through the second contact hole;

A passivation protective layer is formed on a side of the first metal layer away from the second dielectric layer.
The manufacturing method according to claim 12, wherein the manufacturing method further comprises:

After forming the gate structure, an N-type field stop layer, a P-type collector region, and a second metal layer are sequentially formed on a side of the N-type semiconductor substrate away from the gate structure.