WO2019085490A1 - 一种像素电路及其驱动方法、显示装置 - Google Patents

一种像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2019085490A1
WO2019085490A1 PCT/CN2018/091232 CN2018091232W WO2019085490A1 WO 2019085490 A1 WO2019085490 A1 WO 2019085490A1 CN 2018091232 W CN2018091232 W CN 2018091232W WO 2019085490 A1 WO2019085490 A1 WO 2019085490A1
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Prior art keywords
film transistor
thin film
voltage
state
storage capacitor
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PCT/CN2018/091232
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English (en)
French (fr)
Inventor
赵敏
李素华
王鹏
朱朝月
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云谷（固安）科技有限公司
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Publication of WO2019085490A1 publication Critical patent/WO2019085490A1/zh
Priority to US16/422,309 priority Critical patent/US11049449B2/en

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • H—ELECTRICITY
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Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • the organic light emitting display device is a display device using an organic light emitting diode as a light emitting device, and has the characteristics of high contrast, thin thickness, wide viewing angle, fast response speed, low power consumption, etc., and is increasingly applied to various displays and illuminations. field.
  • a plurality of pixel circuits may be generally included.
  • a plurality of pixel circuits are generally supplied with a power supply voltage from the same power source, and the power supply voltage can determine a current flowing through the light-emitting diodes in the pixel circuit.
  • the main purpose of the present application is to provide a pixel circuit, a driving method thereof, and a display device, which are intended to solve the problem that the brightness of the display device is uneven due to the difference in current flowing through the LED due to the power supply voltage drop. The problem.
  • the pixel circuit proposed by the present application includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, a light emitting diode, and Storage capacitor,
  • a gate of the first thin film transistor is respectively connected to a drain of the second thin film transistor, a source of the third thin film transistor, and one end of the storage capacitor, and a source and an initial of the second thin film transistor a voltage signal line is connected, and the other end of the storage capacitor is respectively connected to a drain of the fourth thin film transistor and a source of the fifth thin film transistor, and a source of the fourth thin film transistor is connected to a reference voltage signal line ;
  • a source of the first thin film transistor is respectively connected to a drain of the fifth thin film transistor, a drain of the sixth thin film transistor, and a source of the seventh thin film transistor, and a source of the sixth thin film transistor
  • the pole is connected to the first power source, and the drain of the seventh thin film transistor is connected to the data line;
  • a drain of the first thin film transistor is respectively connected to a drain of the third thin film transistor and an anode of the light emitting diode, and a cathode of the light emitting diode is connected to a second power source.
  • the first power source is configured to supply a power voltage to the first thin film transistor
  • the reference voltage signal line is used to provide a reference voltage
  • the initial voltage signal line is for providing an initial voltage, and the initial voltage is used to initialize a gate of the first thin film transistor and the one end of the storage capacitor;
  • the data line is used to provide a data voltage.
  • the reference voltage and the initial voltage are negative voltages.
  • the gate of the second thin film transistor is connected to the first scan line, and when the first scan signal provided by the first scan line controls the second thin film transistor to be in an on state, the initial a voltage is initialized to a gate of the first thin film transistor and the one end of the storage capacitor;
  • a gate of the fourth thin film transistor is connected to the second scan line, and when the second scan signal provided by the second scan line controls the fourth thin film transistor to be in an on state, the reference voltage is Applying a voltage to the other end of the storage capacitor;
  • a gate of the third thin film transistor and a gate of the seventh thin film transistor are connected to a third scan line, and the third thin film transistor is controlled by a third scan signal provided by the third scan line
  • the threshold voltage of the first thin film transistor is compensated when the seventh thin film transistor is in an on state
  • a gate of the fifth thin film transistor and a gate of the sixth thin film transistor are connected to a fourth scan line, and the fifth thin film transistor is controlled when a fourth scan signal provided by the fourth scan line
  • a current flows through the light emitting diode.
  • the fourth scan line controls the fifth thin film transistor and the sixth thin film transistor to be in an on state
  • the first power source respectively goes to a source and a source of the first thin film transistor M1.
  • a voltage is applied to the other end of the storage capacitor, and a current flowing through the LED is independent of the first power source by the storage capacitor.
  • the first thin film transistor is a driving thin film transistor, and the first thin film transistor is a P-type thin film transistor;
  • the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor are each independently an N-type thin film transistor or P-type thin film transistor.
  • the embodiment of the present application further provides a driving method of a pixel circuit for driving the pixel circuit described above, where the driving method includes:
  • the first scan signal controls the second thin film transistor to change from an off state to an on state, and an initial voltage initializes a gate of the first thin film transistor and one end of the storage capacitor, and a second scan signal Controlling the fourth thin film transistor from an off state to an on state, a reference voltage applying a voltage to the other end of the storage capacitor, and a third scan signal controlling the third thin film transistor and the seventh thin film transistor to be in an off state a fourth scan signal controls the fifth thin film transistor and the sixth thin film transistor to change from an on state to an off state;
  • the first scan signal controls the second thin film transistor to change from an on state to an off state
  • the second scan signal controls the fourth thin film transistor to change from an on state to an off state
  • the third scan signal control station The third thin film transistor and the seventh thin film transistor are changed from an off state to an on state to compensate a threshold voltage of the first thin film transistor, and a fourth scan signal controls the fifth thin film transistor and the sixth The thin film transistor is in an off state;
  • the first scan signal controls the second thin film transistor to be in an off state
  • the second scan signal controls the fourth thin film transistor to be in an off state
  • the third scan signal controls the third thin film transistor and the seventh
  • the thin film transistor is changed from the on state to the off state
  • the fourth scan signal controls the fifth thin film transistor and the sixth thin film transistor to change from an off state to an on state, and a current flows through the light emitting diode, the light emitting diode Glowing.
  • the gate voltage of the first thin film transistor and the voltage of the one end of the storage capacitor are Vint, and the voltage of the other end of the storage capacitor is Vref, wherein Vint is the initial voltage, and Vref is the reference voltage.
  • the gate of the first thin film transistor is connected to the drain, and the data voltage applies a voltage to the source of the first thin film transistor, so that the gate of the first thin film transistor
  • the voltage is Vdata+Vth
  • the threshold voltage of the first thin film transistor is compensated, wherein Vth is a threshold voltage of the first thin film transistor.
  • the first power source applies a voltage to a source of the first thin film transistor and the other end of the storage capacitor, and a voltage of the other end of the storage capacitor Changing from Vref to VDD, the gate voltage of the first thin film transistor is VDD-Vref+Vdata+Vth under the action of the storage capacitor, so that the current flowing through the light emitting diode is independent of the first power source Where VDD is the first power source.
  • the embodiment of the present application further provides a display device, which includes the pixel circuit described above.
  • the pixel circuit provided by the embodiment of the present application includes seven thin film transistors, a storage capacitor, and a light emitting diode. During the light emitting phase of the light emitting diode, the pixel circuit can compensate for the power supply voltage, so that the current and the input through the light emitting diode
  • the data voltage in the pixel circuit is related to the reference voltage, and is independent of the power supply voltage, thereby effectively avoiding the problem that the display device displays unevenness due to the difference in current flowing into each of the light-emitting diodes due to the power supply voltage drop.
  • the pixel circuit provided by the embodiment of the present application can also compensate the threshold voltage of the driving thin film transistor, thereby effectively avoiding the problem that the display device is unevenly displayed due to the difference in threshold voltage of the driving thin film transistor.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application.
  • FIG. 2 is a timing diagram of a method for driving a pixel circuit according to an embodiment of the present application.
  • the first thin film transistor is a driving thin film transistor, and specifically may be a P-type thin film transistor; the second thin film transistor, the third thin film transistor, and the The fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor may all be P-type thin film transistors, or both may be N-type thin film transistors, or at least one of them may be
  • the P-type thin film transistor is the N-type thin film transistor, and the embodiment of the present application is not specifically limited.
  • different types of thin film transistors may be different in scan signals provided by different scan lines.
  • the first thin film transistor to the seventh thin film transistor are both P-type thin film transistors. Description.
  • the light emitting diode may be an LED or an OLED, and is not specifically limited herein.
  • the embodiment of the present application can be described by taking the light emitting diode as an OLED as an example.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application.
  • the pixel circuit is as follows.
  • the pixel circuit includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, and a seventh thin film.
  • the transistor M7 is a P-type thin film transistor
  • the light-emitting diode D1 is an OLED.
  • the circuit connection structure of the pixel circuit shown in FIG. 1 is as follows:
  • the gate of the first thin film transistor M1 is respectively connected to the drain of the second thin film transistor M2, the source of the third thin film transistor M3, and one end of the storage capacitor C (point N2 shown in FIG. 1), and the first thin film transistor M1
  • the source is connected to the drain of the fifth thin film transistor M5, the drain of the sixth thin film transistor M6, and the source of the seventh thin film transistor M7, respectively, and the drain of the first thin film transistor M1 and the drain of the third thin film transistor M3, respectively.
  • a source of the second thin film transistor M2 is connected to an initial voltage signal line
  • the source of the fourth thin film transistor M4 is connected to the reference voltage signal line, and the drain of the fourth thin film transistor M4 is respectively connected to the source of the fifth thin film transistor M5 and the other end of the storage capacitor C (N1 point shown in FIG. 1). ;
  • a source of the sixth thin film transistor M6 is connected to the first power source VDD;
  • a drain of the seventh thin film transistor M7 is connected to the data line
  • the cathode of the light emitting diode D1 is connected to the second power source VSS.
  • the first power source VDD may be a positive voltage and used to supply a power voltage to the first thin film transistor M1.
  • the first thin film transistor M1 can output a current under the action of the first power source VDD, and the current flows into the light emitting diode D1, so that the light emitting diode D1 emits light.
  • the current flows into the second power source VSS, and the second power source VSS may be a negative voltage.
  • the data voltage signal line can be used to provide a data voltage Vdata
  • the reference voltage signal line can be used to provide a reference voltage Vref
  • the initial voltage signal line can be used to provide an initial voltage Vint.
  • the initial voltage Vint can be initialized to the gate of the first thin film transistor M1 and one end of the storage capacitor C (the N2 point shown in FIG. 1, that is, the right plate of the storage capacitor C).
  • the reference voltage Vref and the initial voltage Vint may both be negative voltages.
  • S1 is a first scan signal provided by a first scan line
  • S2 is a second scan signal provided by a second scan line
  • S3 is a third scan signal provided by a third scan line
  • S4 is a fourth scan signal provided by the fourth scan line, wherein:
  • a gate of the second thin film transistor M2 is connected to the first scan line, and a first scan signal S1 provided by the first scan line can control the second thin film transistor M2 to be in an on state or an off state;
  • a gate of the fourth thin film transistor M4 is connected to the second scan line, and a second scan signal S2 provided by the second scan line can control the fourth thin film transistor M4 to be in an on state or an off state;
  • the gate of the third thin film transistor M3 and the gate of the seventh thin film transistor M7 are connected to the third scan line, and the third scan signal S3 provided by the third scan line can control the third thin film transistor M3 and the seventh thin film transistor.
  • M7 is in an on state or an off state;
  • a gate of the fifth thin film transistor M5 and a gate of the sixth thin film transistor M6 are connected to the fourth scan line, and a fourth scan signal S4 provided by the fourth scan line can control the fifth thin film transistor M5 and the sixth
  • the thin film transistor M6 is in an on state or an off state.
  • the initial voltage Vint may pass through the second thin film transistor M2 to the gate of the first thin film transistor M1 and one end of the storage capacitor C ( A voltage is applied to the N2 point shown in FIG. 1 , that is, the right plate of the storage capacitor C), and the gate of the first thin film transistor M1 and the right plate of the storage capacitor C are initialized;
  • the reference voltage Vref may pass through the fourth thin film transistor M4 to the other end of the storage capacitor C (N1 point shown in FIG. 1, that is, the left side of the storage capacitor C) The voltage is applied to the pixel circuit, and the reference voltage Vref is input to the pixel circuit.
  • the voltage of the left plate of the storage capacitor C (point N1 shown in FIG. 1) is Vref.
  • the gate of the first thin film transistor M1 is connected to the drain, and the data voltage Vdata passes through the seventh thin film transistor M7 to the first film.
  • a voltage is applied to the source of the transistor M1, and the gate of the first thin film transistor M1 is charged through the drain of the first thin film transistor M1.
  • the gate voltage and the drain voltage of the first thin film transistor M1 are both Vdata. +Vth, where Vth is a threshold voltage of the first thin film transistor M1;
  • the first power supply VDD applies a voltage to the source of the first thin film transistor M1 through the sixth thin film transistor M6, at the first power supply.
  • VDD the current flows through the light emitting diode D1, and the light emitting diode D1 emits light.
  • the light emitting diode D1 emits light, compensation of the threshold voltage of the first thin film transistor M1 can be achieved.
  • the first power supply VDD may also pass through the fifth thin film transistor M5 to the other end of the storage capacitor C (
  • the N1 point shown in FIG. 1 that is, the left plate of the storage capacitor C is applied with a voltage, so that the left plate voltage of the storage capacitor C is changed from Vref to VDD, and accordingly, the right plate of the storage capacitor C is shown (FIG. 1).
  • the voltage of N2 point is changed from Vdata+Vth to VDD-Vref+Vdata+Vth, that is, the gate voltage of the first thin film transistor M1 becomes VDD-Vref+Vdata+Vth.
  • the first power supply VDD acting on the source of the first thin film transistor M1 is The VDD in the gate voltage of the first thin film transistor M1 cancels each other, so that the current flowing through the light emitting diode D1 is independent of the first power supply VDD, and the compensation of the first power supply VDD is realized. Since the current flowing through the light emitting diode D1 is independent of the first power source VDD, it is possible to effectively avoid the influence of the power source voltage drop generated by the first power source VDD on the display device uniformity.
  • FIG. 2 is a timing diagram of a driving method of a pixel circuit according to an embodiment of the present application, and a driving method of the pixel circuit corresponding to the timing chart may be used to drive the pixel circuit shown in FIG. 1.
  • the driving method of the pixel circuit corresponding to the timing chart shown in FIG. 2 may include three stages: a first stage t1, a second stage t2, and a third stage t3, wherein S1 may be the one described in the embodiment shown in FIG.
  • the first scan signal provided by the first scan line, S2 may be the second scan signal provided by the second scan line described in the embodiment shown in FIG. 1, and S3 may be recorded in the embodiment shown in FIG.
  • the third scan signal provided by the third scan line, S4 may be the fourth scan signal provided by the fourth scan line as described in the embodiment shown in FIG. 1.
  • the driving method of the pixel circuit corresponding to the timing chart shown in FIG. 2 specifically includes:
  • the first scan signal S1 controls the second thin film transistor M2 to change from the off state to the on state
  • the initial voltage Vint initializes the gate of the first thin film transistor M1 and one end of the storage capacitor C
  • the second scan signal S2 controls the fourth thin film transistor M4 to change from the off state to the on state
  • the reference voltage Vref applies a voltage to the other end of the storage capacitor C
  • the third scan signal S3 controls the third thin film transistor M3 and the seventh thin film transistor M7 to be in an off state.
  • the fourth scan signal S4 controls the fifth thin film transistor M5 and the sixth thin film transistor M7 to change from an on state to an off state
  • the first scan signal S1 controls the second thin film transistor M2 to change from the on state to the off state
  • the second scan signal S2 controls the fourth thin film transistor M4 to change from the on state to the off state
  • the third scan signal S3 Controlling the third thin film transistor M3 and the seventh thin film transistor M7 from an off state to an on state, compensating for a threshold voltage of the first thin film transistor M1, and the fourth scan signal S4 controls the fifth thin film transistor M5 and the sixth thin film transistor M6 In the cutoff state;
  • the first scan signal S1 controls the second thin film transistor M2 to be in an off state
  • the second scan signal S2 controls the fourth thin film transistor M4 to be in an off state
  • the third scan signal S3 controls the third thin film transistor M3 and the seventh thin film.
  • the transistor M7 is turned from the on state to the off state
  • the fourth scan signal S4 controls the fifth thin film transistor M5 and the sixth thin film transistor M6 to be turned from the off state to the on state, the current flows through the light emitting diode D1, and the light emitting diode D1 emits light.
  • the first scan signal S1 changes from a high level to a low level
  • the second scan signal S2 changes from a high level to a low level
  • the third scan signal S3 maintains a high level
  • the fourth scan signal S4 is at a low level.
  • the second thin film transistor M2 is turned from the off state to the on state
  • the third thin film transistor M4 is turned off
  • the third thin film transistor M3 and the seventh thin film transistor M7 are turned off.
  • the fifth thin film transistor M5 and the sixth thin film transistor M6 are turned from the on state to the off state.
  • the initial voltage Vint is applied to the gate of the first thin film transistor M1 and the right plate of the storage capacitor C (the point N2 shown in FIG. 1) through the second thin film transistor M2, so that the gate of the first thin film transistor M1 Both the voltage and the right plate voltage of the storage capacitor C become Vint, and the initialization of the gate of the first thin film transistor M1 and the right plate of the storage capacitor C is realized.
  • the reference voltage Vref is applied to the left plate of the storage capacitor C (point N1 shown in FIG. 1) through the fourth thin film transistor M4, so that the left plate voltage of the storage capacitor C becomes Vref, and the reference voltage Vref is written into the pixel. Circuit.
  • the second thin film transistor M2 is changed from the on state to the off state, the fourth thin film transistor M4 is turned from the on state, and the third thin film transistor M3 and the seventh thin film transistor M7 are turned off.
  • the fifth thin film transistor M5 and the sixth thin film transistor M6 are still in an off state.
  • the gate of the first thin film transistor M1 is connected to the drain through the third thin film transistor M3, and the data voltage Vdata is applied to the source of the first thin film transistor M1 through the seventh thin film transistor M7, so that the first thin film transistor M1
  • the source voltage is Vdata
  • the data voltage Vdata can pass through the drain of the first thin film transistor M1 to the gate of the first thin film transistor M1, and charge the gate of the first thin film transistor M1.
  • the gate voltage and the drain voltage of the first thin film transistor M1 are both Vdata+Vth.
  • the second thin film transistor M2 is in an off state
  • the fourth thin film transistor M4 is in an off state
  • the third thin film transistor M3 and the seventh thin film transistor M7 are turned from an on state to an off state
  • the fifth thin film transistor M5 and the sixth thin film are The transistor M6 is changed from the off state to the on state.
  • the first power source VDD applies a voltage to the source of the first thin film transistor M1 through the sixth thin film transistor M6, so that the source voltage of the first thin film transistor M1 becomes VDD, and the first power source VDD passes through the fifth thin film transistor.
  • M5 applies a voltage to the left plate of the storage capacitor C (point N1 shown in FIG. 1), so that the voltage of the left plate of the storage capacitor C changes from Vref to VDD, and accordingly, the right plate of the storage capacitor C (FIG. 1)
  • the N2 point voltage is changed from Vdata+Vth to VDD-Vref+Vdata+Vth. Since the gate voltage of the first thin film transistor M1 is equal to the right plate voltage of the storage capacitor C, the gate of the first thin film transistor M1 is The pole voltage is VDD-Vref+Vdata+Vth.
  • the first thin film transistor M1 Under the action of the first power source VDD, the first thin film transistor M1 generates a driving current, and the driving current flows through the light emitting diode D1, so that the light emitting diode D1 emits light.
  • the current flowing through the LED D1 can be expressed as:
  • ⁇ is the electron mobility of the first thin film transistor M1
  • C ox is the gate oxide capacitance per unit area of the first thin film transistor M1
  • W/L is the aspect ratio of the first thin film transistor M1
  • Vs is the first thin film transistor
  • the source voltage VDD, Vg of M1 is the gate voltage VDD-Vref+Vdata+Vth of the first thin film transistor M1.
  • the current flowing through the light-emitting diode D1 is related to the data voltage and the reference voltage Vref, and is independent of the first power supply VDD, and is also independent of the threshold voltage of the first thin film transistor M1, thereby realizing compensation for the first power supply VDD.
  • the influence of the power supply voltage drop of the first power source VDD on the display effect is avoided, the uniformity of the display of the display device is ensured, and at the same time, the threshold voltage of the first thin film transistor M1 is compensated, and the first thin film transistor M1 is avoided.
  • the difference in threshold voltage causes the display device to display a problem of unevenness.
  • the driving method of the pixel circuit provided by the embodiment of the present application can compensate the power supply voltage during the light emitting phase of the light emitting diode, so that the current flowing through the light emitting diode is related to the data voltage and the reference voltage input into the pixel circuit, and the power source The voltage is independent, thereby effectively avoiding the problem that the display device displays unevenness due to the difference in current flowing into each of the light-emitting diodes due to the power supply voltage drop.
  • the embodiment of the present application further provides a display device, and the display device may include the pixel circuit described above.

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Abstract

本申请公开一种像素电路及其驱动方法、显示装置，该像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管以及存储电容。本申请实施例提供的像素电路，在发光二极管的发光阶段，可以实现对电源电压的补偿，使得流经发光二极管的电流与输入该像素电路中的数据电压以及参考电压有关，与电源电压无关，从而有效避免由于电源电压降导致的流入每一个发光二极管的电流不同，显示装置显示不均匀的问题。

Description

一种像素电路及其驱动方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
有机发光显示装置是一种应用有机发光二极管作为发光器件的显示装置，具有对比度高、厚度薄、视角广、反应速度快、低功耗等特点，被越来越多地应用到各个显示以及照明领域。
现有的有机发光显示装置中，通常可以包含多个像素电路，多个像素电路通常由同一电源提供电源电压，电源电压可以决定流经像素电路中发光二极管的电流。
然而，在实际应用中，电源电压在多个像素电路间传输时不可避免的产生电源电压降(IR drop)，导致作用在每一个像素电路的实际电源电压不同，进而导致流经每一个发光二极管的电流不同，显示装置显示的亮度不均匀。
发明内容
本申请的主要目的是提供一种像素电路及其驱动方法、显示装置，旨在解决现有的显示装置中，由于电源电压降导致的流经发光二极管的电流不同，显示装置显示的亮度不均匀的问题。
为实现上述目的，本申请提出的像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管以及存储电容，
所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的漏极、所述第三薄膜晶体管的源极以及所述存储电容的一端连接，所述第二薄膜晶体管的源极与初始电压信号线连接，所述存储电容的另一端分别与所述第四薄膜晶体管的漏极以及所述第五薄膜晶体管的源极连接，所述第四薄膜晶体管的源极与参考电压信号线连接；
所述第一薄膜晶体管的源极分别与所述第五薄膜晶体管的漏极、所述第六薄膜晶体管的漏极以及所述第七薄膜晶体管的源极连接，所述第六薄膜晶 体管的源极与第一电源连接，所述第七薄膜晶体管的漏极与数据线连接；
所述第一薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源连接。
可选地，所述第一电源用于为所述第一薄膜晶体管提供电源电压；
所述发光二极管发光时电流流入所述第二电源。
可选地，所述参考电压信号线用于提供参考电压；
所述初始电压信号线用于提供初始电压，所述初始电压用于对所述第一薄膜晶体管的栅极以及所述存储电容的所述一端进行初始化；
所述数据线用于提供数据电压。
可选地，所述参考电压以及所述初始电压为负电压。
可选地，所述第二薄膜晶体管的栅极与第一扫描线连接，当由所述第一扫描线提供的第一扫描信号控制所述第二薄膜晶体管处于导通状态时，所述初始电压对所述第一薄膜晶体管的栅极以及所述存储电容的所述一端进行初始化；
所述第四薄膜晶体管的栅极与第二扫描线连接，当由所述第二扫描线提供的第二扫描信号控制所述第四薄膜晶体管处于导通状态时，所述参考电压向所述存储电容的所述另一端施加电压；
所述第三薄膜晶体管的栅极以及所述第七薄膜晶体管的栅极与第三扫描线连接，当由所述第三扫描线提供的第三扫描信号控制所述第三薄膜晶体管以及所述第七薄膜晶体管处于导通状态时，对所述第一薄膜晶体管的阈值电压进行补偿；
所述第五薄膜晶体管的栅极以及所述第六薄膜晶体管的栅极与第四扫描线连接，当由所述第四扫描线提供的第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管处于导通状态时，电流流经所述发光二极管。
可选地，当所述第四扫描线控制所述第五薄膜晶体管以及所述第六薄膜晶体管处于导通状态时，所述第一电源分别向所述第一薄膜晶体管M1的源极以及所述存储电容的所述另一端施加电压，在所述存储电容的作用下，流经所述发光二极管的电流与所述第一电源无关。
可选地，所述第一薄膜晶体管为驱动薄膜晶体管，且所述第一薄膜晶体管为P型薄膜晶体管；
所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所 述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管分别独立地为N型薄膜晶体管或P型薄膜晶体管。
本申请实施例还提供一种像素电路的驱动方法，用于驱动上述记载的所述像素电路，所述驱动方法包括：
第一阶段，第一扫描信号控制所述第二薄膜晶体管由截止状态变为导通状态，初始电压对所述第一薄膜晶体管的栅极、所述存储电容的一端进行初始化，第二扫描信号控制所述第四薄膜晶体管由截止状态变为导通状态，参考电压向所述存储电容的另一端施加电压，第三扫描信号控制所述第三薄膜晶体管以及所述第七薄膜晶体管处于截止状态，第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管由导通状态变为截止状态；
第二阶段，第一扫描信号控制所述第二薄膜晶体管由导通状态变为截止状态，第二扫描信号控制所述第四薄膜晶体管由导通状态变为截止状态，第三扫描信号控制所述第三薄膜晶体管以及所述第七薄膜晶体管由截止状态变为导通状态，对所述第一薄膜晶体管的阈值电压进行补偿，第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管处于截止状态；
第三阶段，第一扫描信号控制所述第二薄膜晶体管处于截止状态，第二扫描信号控制所述第四薄膜晶体管处于截止状态，第三扫描信号控制所述第三薄膜晶体管以及所述第七薄膜晶体管由导通状态变为截止状态，第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管由截止状态变为导通状态，电流流经所述发光二极管，所述发光二极管发光。
可选地，在所述第一阶段，所述第一薄膜晶体管的栅极电压以及所述存储电容的所述一端的电压为Vint，所述存储电容的所述另一端的电压为Vref，其中，Vint为所述初始电压，Vref为所述参考电压。
可选地，在所述第二阶段，所述第一薄膜晶体管的栅极与漏极连接，数据电压向所述第一薄膜晶体管的源极施加电压，使得所述第一薄膜晶体管的栅极电压为Vdata+Vth，对所述第一薄膜晶体管的阈值电压进行补偿，其中，Vth为所述第一薄膜晶体管的阈值电压。
可选地，在所述第三阶段，所述第一电源向所述第一薄膜晶体管的源极以及所述存储电容的所述另一端施加电压，所述存储电容的所述另一端的电压由Vref变为VDD，在所述存储电容的作用下，所述第一薄膜晶体管的栅极电压为VDD-Vref+Vdata+Vth，使得流经所述发光二极管的电流与所述第一电 源无关，其中，VDD为所述第一电源。
本申请实施例还提供一种显示装置，该显示装置包括上述记载的所述像素电路。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果：
本申请实施例提供的像素电路，包括七个薄膜晶体管、一个存储电容以及一个发光二极管，在发光二极管的发光阶段，该像素电路可以实现对电源电压的补偿，使得流经发光二极管的电流与输入该像素电路中的数据电压以及参考电压有关，与电源电压无关，从而有效避免由于电源电压降导致的流入每一个发光二极管的电流不同，显示装置显示不均匀的问题。
此外，本申请实施例提供的像素电路还可以对驱动薄膜晶体管阈值电压进行补偿，有效避免由于驱动薄膜晶体管阈值电压的不同导致的显示装置显示不均匀的问题。
附图说明
图1为本申请实施例提供的一种像素电路的结构示意图；
图2为本申请实施例提供的一种像素电路的驱动方法的时序图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
需要说明的是，在本申请实施例提供的像素电路中，所述第一薄膜晶体管为驱动薄膜晶体管，具体可以为P型薄膜晶体管；所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管可以均为P型薄膜晶体管，也可以均为N型薄膜晶体管，还可以是其中至少一者为P型薄膜晶体管，其余的为N型薄膜晶体管，本申请实施例不做具体限定。
本申请实施例中，不同类型的薄膜晶体管，不同扫描线提供的扫描信号可以不同，本申请实施例可以以所述第一薄膜晶体管至所述第七薄膜晶体管均是P型薄膜晶体管为例进行说明。
所述发光二极管可以是LED，也可以是OLED，这里也不做具体限定。本申请实施例可以以所述发光二极管是OLED为例进行说明。
以下结合附图，详细说明本申请各实施例提供的技术方案。
图1为本申请实施例提供的一种像素电路的结构示意图。所述像素电路如下所述。
如图1所示，所述像素电路包括第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、存储电容C以及发光二极管D1。
其中，图1所示的像素电路中，第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7均为P型薄膜晶体管，发光二极管D1为OLED。
图1所示的像素电路的电路连接结构如下所述：
第一薄膜晶体管M1的栅极分别与第二薄膜晶体管M2的漏极、第三薄膜晶体管M3的源极以及存储电容C的一端(图1所示的N2点)连接，第一薄膜晶体管M1的源极分别与第五薄膜晶体管M5的漏极、第六薄膜晶体管M6的漏极以及第七薄膜晶体管M7的源极连接，第一薄膜晶体管M1的漏极分别与第三薄膜晶体管M3的漏极以及发光二极管D1的阳极连接；
第二薄膜晶体管M2的源极与初始电压信号线连接；
第四薄膜晶体管M4的源极与参考电压信号线连接，第四薄膜晶体管M4的漏极分别与第五薄膜晶体管M5的源极以及存储电容C的另一端(图1所示的N1点)连接；
第六薄膜晶体管M6的源极第一电源VDD连接；
第七薄膜晶体管M7的漏极与数据线连接；
发光二极管D1的阴极与第二电源VSS连接。
本申请实施例中，所述第一电源VDD可以是正电压，并用于为第一薄膜晶体管M1提供电源电压。第一薄膜晶体管M1在第一电源VDD的作用下，可以输出电流，该电流流入发光二极管D1，使得发光二极管D1发光。在发光二极管D1发光时，该电流流入第二电源VSS，第二电源VSS可以是负电压。
所述数据电压信号线可以用于提供数据电压Vdata，所述参考电压信号线可以用于提供参考电压Vref，初始电压信号线可以用于提供初始电压Vint。初始电压Vint可以对第一薄膜晶体管M1的栅极以及存储电容C的一端(图1所示的N2点，即存储电容C的右极板)进行初始化。本申请实施例中，参考电压Vref以及初始电压Vint可以均为负电压。
图1所示的像素电路中，S1为由第一扫描线提供的第一扫描信号，S2为第由二扫描线提供的第二扫描信号，S3为由第三扫描线提供的第三扫描信号，S4为由第四扫描线提供的第四扫描信号，其中：
第二薄膜晶体管M2的栅极与所述第一扫描线连接，由所述第一扫描线提供的第一扫描信号S1可以控制第二薄膜晶体管M2处于导通状态或截止状态；
第四薄膜晶体管M4的栅极与所述第二扫描线连接，由所述第二扫描线提供的第二扫描信号S2可以控制第四薄膜晶体管M4处于导通状态或截止状态；
第三薄膜晶体管M3的栅极以及第七薄膜晶体管M7的栅极与第三扫描线连接，由所述第三扫描线提供的第三扫描信号S3可以控制第三薄膜晶体管M3以及第七薄膜晶体管M7处于导通状态或截止状态；
第五薄膜晶体管M5的栅极以及第六薄膜晶体管M6的栅极与所述第四扫描线连接，由所述第四扫描线提供的第四扫描信号S4可以控制第五薄膜晶体管M5以及第六薄膜晶体管M6处于导通状态或截止状态。
本申请实施例中，当第一扫描信号S1控制第二薄膜晶体管M2处于导通状态时，初始电压Vint可以通过第二薄膜晶体管M2向第一薄膜晶体管M1的栅极以及存储电容C的一端(图1所示的N2点，即存储电容C的右极板)施加电压，对第一薄膜晶体管M1的栅极以及存储电容C的右极板进行初始化；
当第二扫描信号S2控制第四薄膜晶体管M4处于导通状态时，参考电压Vref可以通过第四薄膜晶体管M4向存储电容C的另一端(图1所示的N1点，即存储电容C的左极板)施加电压，参考电压Vref输入所述像素电路，存储电容C的左极板(图1所示的N1点)电压为Vref。
当第三扫描信号S3控制第三薄膜晶体管M3以及第七薄膜晶体管M7处于导通状态时，第一薄膜晶体管M1的栅极与漏极连接，数据电压Vdata通过第七薄膜晶体管M7向第一薄膜晶体管M1的源极施加电压，并通过第一薄膜晶体管M1的漏极向第一薄膜晶体管M1的栅极充电，电路状态稳定后，第一薄膜晶体管M1的栅极电压以及漏极电压均为Vdata+Vth，其中，Vth为第一薄膜晶体管M1的阈值电压；
当第四扫描信号S4控制第五薄膜晶体管M5以及第六薄膜晶体管M6处于导通状态时，第一电源VDD通过第六薄膜晶体管M6向第一薄膜晶体管M1的源极施加电压，在第一电源VDD的作用下，该有电流流经发光二极管D1，发光二极管D1发光。在发光二极管D1发光时，可以实现对第一薄膜晶体管M1 阈值电压的补偿。
本申请实施例中，当第四扫描信号S4控制第五薄膜晶体管M5以及第六薄膜晶体管M6处于导通状态时，第一电源VDD还可以通过第五薄膜晶体管M5向存储电容C的另一端(图1所示的N1点，即存储电容C的左极板)施加电压，使得存储电容C的左极板电压由Vref变为VDD，相应地，存储电容C的右极板(图1所示的N2点)电压由Vdata+Vth变为VDD-Vref+Vdata+Vth，即第一薄膜晶体管M1的栅极电压变为VDD-Vref+Vdata+Vth。这样，在第一电源VDD向第一薄膜晶体管M1的源极施加电压，电流流经发光二极管D1时，在所述电流的公式中，作用在第一薄膜晶体管M1源极的第一电源VDD与第一薄膜晶体管M1栅极电压中的VDD相互抵消，使得流经发光二极管D1的电流与第一电源VDD无关，实现对第一电源VDD的补偿。由于流经发光二极管D1的电流与第一电源VDD无关，因此，可以有效避免第一电源VDD产生的电源电压降对显示装置显示均匀性的影响。
图2为本申请实施例提供的一种像素电路的驱动方法的时序图，所述时序图对应的像素电路的驱动方法可以用于驱动图1所示的像素电路。
图2所示的时序图对应的像素电路的驱动方法可以包括三个阶段：第一阶段t1、第二阶段t2以及第三阶段t3，其中，S1可以是图1所示实施例中记载的由所述第一扫描线提供的第一扫描信号，S2可以是图1所示实施例中记载的由所述第二扫描线提供的第二扫描信号，S3可以是图1所示实施例中记载的由所述第三扫描线提供的第三扫描信号，S4可以是图1所示实施例中记载的由所述第四扫描线提供的第四扫描信号。
图2所示的时序图对应的像素电路的驱动方法，具体包括：
第一阶段t1，第一扫描信号S1控制第二薄膜晶体管M2由截止状态变为导通状态，初始电压Vint对第一薄膜晶体管M1的栅极、存储电容C的一端进行初始化，第二扫描信号S2控制第四薄膜晶体管M4由截止状态变为导通状态，参考电压Vref向存储电容C的另一端施加电压，第三扫描信号S3控制第三薄膜晶体管M3以及第七薄膜晶体管M7处于截止状态，第四扫描信号S4控制第五薄膜晶体管M5以及第六薄膜晶体管M7由导通状态变为截止状态；
第二阶段t2，第一扫描信号S1控制第二薄膜晶体管M2由导通状态变为截止状态，第二扫描信号S2控制第四薄膜晶体管M4由导通状态变为截止状态，第三扫描信号S3控制第三薄膜晶体管M3以及第七薄膜晶体管M7由截止状态 变为导通状态，对第一薄膜晶体管M1的阈值电压进行补偿，第四扫描信号S4控制第五薄膜晶体管M5以及第六薄膜晶体管M6处于截止状态；
第三阶段t3，第一扫描信号S1控制第二薄膜晶体管M2处于截止状态，第二扫描信号S2控制第四薄膜晶体管M4处于截止状态，第三扫描信号S3控制第三薄膜晶体管M3以及第七薄膜晶体管M7由导通状态变为截止状态，第四扫描信号S4控制第五薄膜晶体管M5以及第六薄膜晶体管M6由截止状态变为导通状态，电流流经发光二极管D1，发光二极管D1发光。
下面分别针对上述三个阶段进行具体分析：
针对第一阶段t1：
由于第一扫描信号S1由高电平变为低电平，第二扫描信号S2由高电平变为低电平，第三扫描信号S3保持高电平，第四扫描信号S4由低电平变为高电平，因此，第二薄膜晶体管M2由截止状态变为导通状态，第四薄膜晶体管M4由截止状态变为导通状态，第三薄膜晶体管M3以及第七薄膜晶体管M7处于截止状态，第五薄膜晶体管M5以及第六薄膜晶体管M6由导通状态变为截止状态。
此时，初始电压Vint通过第二薄膜晶体管M2向第一薄膜晶体管M1的栅极以及存储电容C的右极板(图1所示的N2点)施加电压，使得第一薄膜晶体管M1的栅极电压以及存储电容C的右极板电压均变为Vint，实现对第一薄膜晶体管M1的栅极以及存储电容C的右极板的初始化。
参考电压Vref通过第四薄膜晶体管M4向存储电容C的左极板(图1所示的N1点)施加电压，使得存储电容C的左极板电压变为Vref，参考电压Vref写入所述像素电路。
针对第二阶段t2：
由于第一扫描信号S1由低电平变为高电平，第二扫描信号S2由低电平变为高电平，第三扫描信号S3由高电平变为低电平，第四扫描信号S4保持高电平，因此，第二薄膜晶体管M2由导通状态变为截止状态，第四薄膜晶体管M4由导通状态变为截止状态，第三薄膜晶体管M3以及第七薄膜晶体管M7由截止状态变为导通状态，第五薄膜晶体管M5以及第六薄膜晶体管M6仍处于截止状态。
此时，第一薄膜晶体管M1的栅极通过第三薄膜晶体管M3与漏极连接，数据电压Vdata通过第七薄膜晶体管M7向第一薄膜晶体管M1的源极施加电压， 使得第一薄膜晶体管M1的源极电压为Vdata，该数据电压Vdata可以经过第一薄膜晶体管M1的漏极作用在第一薄膜晶体管M1的栅极，并对第一薄膜晶体管M1的栅极进行充电，电路稳定后，由第一薄膜晶体管M1的特性可知，第一薄膜晶体管M1的栅极电压以及漏极电压均为Vdata+Vth。这样，在发光二极管D1的发光阶段，可以实现对第一薄膜晶体管M1阈值电压的补偿，其中，Vth为第一薄膜晶体管M1的阈值电压。
针对第三阶段t3：
由于第一扫描信号S1保持高电平，第二扫描信号S2保持高电平，第三扫描信号S3由低电平变为高电平，第四扫描信号S4由高电平变为低电平，因此，第二薄膜晶体管M2处于截止状态，第四薄膜晶体管M4处于截止状态，第三薄膜晶体管M3以及第七薄膜晶体管M7由导通状态变为截止状态，第五薄膜晶体管M5以及第六薄膜晶体管M6由截止状态变为导通状态。
此时，第一电源VDD通过第六薄膜晶体管M6向第一薄膜晶体管M1的源极施加电压，使得第一薄膜晶体管M1的源极电压变为VDD，同时，第一电源VDD通过第五薄膜晶体管M5向存储电容C的左极板(图1所示的N1点)施加电压，使得存储电容C的左极板电压由Vref变为VDD，相应地，存储电容C的右极板(图1所示的N2点)电压由Vdata+Vth变为VDD-Vref+Vdata+Vth，由于第一薄膜晶体管M1的栅极电压与存储电容C的右极板电压相等，因此，第一薄膜晶体管M1的栅极电压为VDD-Vref+Vdata+Vth。
在第一电源VDD的作用下，第一薄膜晶体管M1产生驱动电流，该驱动电流流经发光二极管D1，使得发光二极管D1发光。
在第三阶段t3，流经发光二极管D1的电流可以表示为：
Figure PCTCN2018091232-appb-000001
其中，μ为第一薄膜晶体管M1的电子迁移率，C ox为第一薄膜晶体管M1单位面积的栅氧化层电容，W/L为第一薄膜晶体管M1的宽长比，Vs为第一薄膜晶体管M1的源极电压VDD，Vg为第一薄膜晶体管M1的栅极电压VDD-Vref+Vdata+Vth。
由上述公式可知，流经发光二极管D1的电流与数据电压以及参考电压Vref有关，与第一电源VDD无关，也与第一薄膜晶体管M1的阈值电压无关，实现了对第一电源VDD的补偿，避免了第一电源VDD的电源电压降对显示效 果的影响，保证了显示装置显示的均匀性，同时，实现了对第一薄膜晶体管M1的阈值电压的补偿，避免了由于第一薄膜晶体管M1的阈值电压的不同导致的显示装置显示不均匀的问题。
本申请实施例提供的像素电路的驱动方法，在发光二极管的发光阶段，可以实现对电源电压的补偿，使得流经发光二极管的电流与输入该像素电路中的数据电压以及参考电压有关，与电源电压无关，从而有效避免由于电源电压降导致的流入每一个发光二极管的电流不同，显示装置显示不均匀的问题。
本申请实施例还提供一种显示装置，所述显示装置可以包括上述记载的所述像素电路。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种像素电路，其中，所述像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管以及存储电容，
    所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的漏极、所述第三薄膜晶体管的源极以及所述存储电容的一端连接，所述第二薄膜晶体管的源极与初始电压信号线连接，所述存储电容的另一端分别与所述第四薄膜晶体管的漏极以及所述第五薄膜晶体管的源极连接，所述第四薄膜晶体管的源极与参考电压信号线连接；
    所述第一薄膜晶体管的源极分别与所述第五薄膜晶体管的漏极、所述第六薄膜晶体管的漏极以及所述第七薄膜晶体管的源极连接，所述第六薄膜晶体管的源极与第一电源连接，所述第七薄膜晶体管的漏极与数据线连接；
    所述第一薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源连接。
  2. 如权利要求1所述的像素电路，其中，
    所述第一电源用于为所述第一薄膜晶体管提供电源电压；
    所述发光二极管发光时电流流入所述第二电源。
  3. 如权利要求1所述的像素电路，其中，
    所述参考电压信号线用于提供参考电压；
    所述初始电压信号线用于提供初始电压，所述初始电压用于对所述第一薄膜晶体管的栅极以及所述存储电容的所述一端进行初始化；
    所述数据线用于提供数据电压。
  4. 如权利要求3所述的像素电路，其中，
    所述参考电压以及所述初始电压为负电压。
  5. 如权利要求4所述的像素电路，其中，
    所述第二薄膜晶体管的栅极与第一扫描线连接，当由所述第一扫描线提供的第一扫描信号控制所述第二薄膜晶体管处于导通状态时，所述初始电压 对所述第一薄膜晶体管的栅极以及所述存储电容的所述一端进行初始化；
    所述第四薄膜晶体管的栅极与第二扫描线连接，当由所述第二扫描线提供的第二扫描信号控制所述第四薄膜晶体管处于导通状态时，所述参考电压向所述存储电容的所述另一端施加电压；
    所述第三薄膜晶体管的栅极以及所述第七薄膜晶体管的栅极与第三扫描线连接，当由所述第三扫描线提供的第三扫描信号控制所述第三薄膜晶体管以及所述第七薄膜晶体管处于导通状态时，对所述第一薄膜晶体管的阈值电压进行补偿；
    所述第五薄膜晶体管的栅极以及所述第六薄膜晶体管的栅极与第四扫描线连接，当由所述第四扫描线提供的第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管处于导通状态时，电流流经所述发光二极管。
  6. 如权利要求5所述的像素电路，其中，
    当所述第四扫描线控制所述第五薄膜晶体管以及所述第六薄膜晶体管处于导通状态时，所述第一电源分别向所述第一薄膜晶体管M1的源极以及所述存储电容的所述另一端施加电压，在所述存储电容的作用下，流经所述发光二极管的电流与所述第一电源无关。
  7. 如权利要求1至6任一项所述的像素电路，其中，
    所述第一薄膜晶体管为驱动薄膜晶体管，且所述第一薄膜晶体管为P型薄膜晶体管；
    所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管分别独立地为N型薄膜晶体管或P型薄膜晶体管。
  8. 一种如权利要求1至7任一项所述的像素电路的驱动方法，其中，所述驱动方法包括：
    第一阶段，第一扫描信号控制所述第二薄膜晶体管由截止状态变为导通状态，初始电压对所述第一薄膜晶体管的栅极、所述存储电容的一端进行初始化，第二扫描信号控制所述第四薄膜晶体管由截止状态变为导通状态，参考电压向所述存储电容的另一端施加电压，第三扫描信号控制所述第三薄膜 晶体管以及所述第七薄膜晶体管处于截止状态，第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管由导通状态变为截止状态；
    第二阶段，第一扫描信号控制所述第二薄膜晶体管由导通状态变为截止状态，第二扫描信号控制所述第四薄膜晶体管由导通状态变为截止状态，第三扫描信号控制所述第三薄膜晶体管以及所述第七薄膜晶体管由截止状态变为导通状态，对所述第一薄膜晶体管的阈值电压进行补偿，第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管处于截止状态；
    第三阶段，第一扫描信号控制所述第二薄膜晶体管处于截止状态，第二扫描信号控制所述第四薄膜晶体管处于截止状态，第三扫描信号控制所述第三薄膜晶体管以及所述第七薄膜晶体管由导通状态变为截止状态，第四扫描信号控制所述第五薄膜晶体管以及所述第六薄膜晶体管由截止状态变为导通状态，电流流经所述发光二极管，所述发光二极管发光。
  9. 如权利要求8所述的像素电路的驱动方法，其中，
    在所述第一阶段，所述第一薄膜晶体管的栅极电压以及所述存储电容的所述一端的电压为Vint，所述存储电容的所述另一端的电压为Vref，其中，Vint为所述初始电压，Vref为所述参考电压。
  10. 如权利要求8所述的像素电路的驱动方法，其中，
    在所述第二阶段，所述第一薄膜晶体管的栅极与漏极连接，数据电压向所述第一薄膜晶体管的源极施加电压，使得所述第一薄膜晶体管的栅极电压为Vdata+Vth，对所述第一薄膜晶体管的阈值电压进行补偿，其中，Vth为所述第一薄膜晶体管的阈值电压。
  11. 如权利要求8至10任一项所述的像素电路的驱动方法，其中，
    在所述第三阶段，所述第一电源向所述第一薄膜晶体管的源极以及所述存储电容的所述另一端施加电压，所述存储电容的所述另一端的电压由Vref变为VDD，在所述存储电容的作用下，所述第一薄膜晶体管的栅极电压为VDD-Vref+Vdata+Vth，使得流经所述发光二极管的电流与所述第一电源无关，其中，VDD为所述第一电源。
  12. 一种显示装置，其中，所述显示装置包括如权利要求1至7任一项所述的像素电路。
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