CN207474028U - 一种像素电路和显示装置 - Google Patents

一种像素电路和显示装置 Download PDF

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Publication number
CN207474028U
CN207474028U CN201721426889.5U CN201721426889U CN207474028U CN 207474028 U CN207474028 U CN 207474028U CN 201721426889 U CN201721426889 U CN 201721426889U CN 207474028 U CN207474028 U CN 207474028U
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film transistor
tft
thin film
voltage
pixel circuit
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周至奕
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Kunshan Govisionox Optoelectronics Co Ltd
Kunshan Guoxian Photoelectric Co Ltd
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Kunshan Guoxian Photoelectric Co Ltd
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Priority to CN201721426889.5U priority Critical patent/CN207474028U/zh
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Publication of CN207474028U publication Critical patent/CN207474028U/zh
Priority to PCT/CN2018/092162 priority patent/WO2019085511A1/zh
Priority to TW107208828U priority patent/TWM570515U/zh
Priority to US16/434,751 priority patent/US10902776B2/en
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请公开一种像素电路和显示装置，该像素电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管、存储电容以及补偿模块。本申请实施例提供的像素电路中包含补偿模块，该补偿模块可以在像素电路的发光阶段，对作用在像素电路中的电源电压进行补偿，使得流经发光二极管的电流与电源电压无关，进而可以避免由于电源电压降导致的流经发光二极管的电流不同，显示装置显示不均匀性的问题。

Description

一种像素电路和显示装置
技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路和显示装置。
背景技术
有机发光显示装置是一种应用有机发光二极管作为发光器件的显示装置，具有对比度高、厚度薄、视角广、反应速度快、低功耗等特点，被越来越多地应用到各个显示以及照明领域。
现有的有机发光显示装置中，通常可以包含多个像素电路，每个像素电路中，通常可以包含电源，驱动薄膜晶体管以及发光二极管，在像素电路的发光阶段，该电源可以作用于驱动薄膜晶体管，使得驱动薄膜晶体管输出电流，该电流流经发光二极管，使得发光二极管发光。
通常，流经发光二极管的电流可以由电源提供的电源电压决定，电源电压越大，流经发光二极管的电流越大，显示装置的亮度越高。然而，在实际应用中，显示装置中包含的多个像素电路通常由同一个电源提供电源电压，该电源电压在传输过程中不可避免的会产生电源电压降(IR drop)，导致作用在每一个像素电路的实际电源电压不同，进而导致流经每一个发光二极管的电流不同，显示装置显示的亮度不均匀。
实用新型内容
本申请实施例提供一种像素电路和显示装置，用于解决现有的显示装置中，由于电源电压降导致的流经发光二极管的电流不同，显示装置显示的亮度不均匀的问题。
本申请实施例提供一种像素电路，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管、存储电容以及补偿模块，其中：
所述第一薄膜晶体管的栅极分别与所述第三薄膜晶体管的源极、所述第四薄膜晶体管的源极以及所述存储电容的一端连接，所述第四薄膜晶体管的漏极与参考电压信号线连接，所述存储电容的另一端分别与所述第七薄膜晶体管的漏极以及所述补偿模块的输出端连接，所述补偿模块的输入端与补偿电压信号线连接；
所述第一薄膜晶体管的源极分别与所述第二薄膜晶体管的漏极、所述第五薄膜晶体管的漏极以及所述第七薄膜晶体管的源极连接，所述第二薄膜晶体管的源极与数据电压信号线连接，所述第五薄膜晶体管的源极与第一电源连接；
所述第一薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第六薄膜晶体管的源极连接，所述第六薄膜晶体管的漏极与所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源连接。
优选地，所述补偿模块用于提供补偿电压，所述补偿模块控制所述补偿电压通过所述存储电容施加至所述第一薄膜晶体管的栅极，并对所述第一电源提供的电源电压进行补偿，使得流经所述发光二极管的电压与所述第一电源无关。
优选地，所述补偿电压为正电压，所述补偿电压大于所述第一电源提供的电源电压；或，
所述补偿电压为负电压，所述补偿电压与所述参考信号线提供的参考电压由同一电源提供。
优选地，所述第一电源，用于为所述第一薄膜晶体管提供电源电压；
所述发光二极管发光时电流流入所述第二电源。
优选地，所述参考电压信号线用于提供参考电压，所述参考电压为负电压，并用于对所述第一薄膜晶体管的栅极进行初始化。
优选地，所述第四薄膜晶体管的栅极与第一扫描线连接，所述第一扫描线提供的第一扫描信号控制所述第四薄膜晶体管处于导通状态时，对所述第一薄膜晶体管的栅极进行初始化；
所述第二薄膜晶体管的栅极以及所述第三薄膜晶体管的栅极与第二扫描线连接，所述第二扫描线提供的第二扫描信号控制所述第二薄膜晶体管以及所述第三薄膜晶体管处于导通状态时，对所述第一薄膜晶体管的阈值电压进行补偿；
所述第五薄膜晶体管的栅极、所述第六薄膜晶体管的栅极以及所述第七薄膜晶体管的栅极与发光控制线连接，所述发光控制线提供的发光控制信号控制所述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管处于导通状态时，电流流经所述发光二极管。
优选地，所述补偿模块包括：补偿电压信号线以及第八薄膜晶体管，其中：
所述补偿电压信号线用于提供所述补偿电压；
所述第八薄膜晶体管的源极与所述补偿电压信号线连接，漏极分别与所述第七薄膜晶体管的漏极以及所述存储电容的另一端连接，栅极与所述第二扫描线连接。
优选地，所述第二扫描信号控制所述第八薄膜晶体管处于导通状态时，所述补偿电压信号线与所述存储电容的另一端连接，所述补偿电压向所述存储电容施加电压；
所述发光控制信号控制所述第五薄膜晶体管以及所述第七薄膜晶体管处于导通状态时，所述第一电源与所述存储电容的另一端连接，所述第一电源向所述存储电容的另一端施加电压，在所述存储电容的作用下，流经所述发光二极管的电流与所述补偿电压有关，与所述第一电源无关。
优选地，所述第一薄膜晶体管为P型薄膜晶体管；
所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管以及所述第八薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
本申请实施例还提供一种显示装置，该显示装置包括上述记载的所述像素电路。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果：
本申请实施例提供的像素电路中包含补偿模块，该补偿模块可以在像素电路的发光阶段，对作用在像素电路中的电源电压进行补偿，使得流经发光二极管的电流与电源电压无关，进而可以避免由于电源电压降导致的流经发光二极管的电流不同，显示装置显示不均匀性的问题。
此外，本申请实施例提供的像素电路还可以实现对驱动薄膜晶体管阈值电压的补偿，有效避免由于驱动薄膜晶体管阈值电压的不同导致的显示装置显示不均匀的问题。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为现有技术中的一种像素电路的结构示意图；
图2为本申请实施例提供的一种像素电路的结构示意图；
图3为本申请实施例提供的另一种像素电路的结构示意图；
图4为本申请实施例提供的一种像素电路的驱动方法的时序图。
具体实施方式
现有的有机发光显示装置中，通常包含多个像素电路，多个像素电路通常由同一个电源提供电源电压，该电源电压可以决定流经像素电路中发光二极管的电流。然而，由于电源电压在传输过程中会不可避免地存在电源电压降，因此，实际作用在每一个像素电路上的电源电压不同，导致流经每一个像素电路中发光二极管的电流不同，显示装置显示不均匀。
图1为现有的显示装置中包含的像素电路的结构示意图，如图1所示，在该像素电路的发光阶段，流经发光二极管D1的电流由电源VDD提供的电源电压决定，其中，电源VDD提供的电源电压越大，流经发光二极管D1的电流越大，显示装置的亮度越高。
但是，当电源VDD提供的电源电压产生电源电压降时，作用在显示装置中每一个像素电路的实际电源电压不同，导致流经发光二极管D1的电流也不同，显示装置显示的亮度不均匀。
近年来，随着显示技术的飞速发展，显示装置的分辨率越来越高，对显示装置的高亮度要求也越来越高，使得显示装置中的电流比较大。针对电源电压而言，由于电源电压具有同时提供像素电路的驱动电流以及流经发光二极管的电流的作用，因此，电源电压产生的电流比较大，这样，电源电压在传输过程中产生的电源电压降将会增加，导致流经图1所示像素电路中发光二极管的电流的差异性更大，显示装置显示不均匀性的现象更为明显。
由此可见，有必要提供一种像素电路，可以避免图1所示的像素电路中，电源电压对显示装置显示不均匀的影响。
为了解决现有技术中存在的上述问题，本申请实施例提供一种像素电路和显示装置，对图1所示的像素电路的电路结构进行改进，并增加了补偿模块，该补偿模块可以在像素电路的发光阶段，对作用在像素电路中的电源电压进行补偿，使得流经发光二极管的电流与电源电压无关，进而可以避免电源电压降导致的流经发光二极管的电流不同，显示装置显示的不均匀性的问题。
下面结合本申请具体实施例及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，在本申请实施例提供的像素电路中，所述第一薄膜晶体管为驱动薄膜晶体管，具体可以为P型薄膜晶体管；所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管以及所述第八薄膜晶体管可以是均为P型薄膜晶体管，也可以是均为N型薄膜晶体管，还可以是其中至少一个为P型薄膜晶体管，其余的为N型薄膜晶体管，本申请实施例不做具体限定。
所述发光二极管可以是LED，也可以是OLED，这里也不做具体限定。
以下结合附图，详细说明本申请各实施例提供的技术方案。
图2为本申请实施例提供的一种像素电路的结构示意图。所述像素电路如下所述。
如图2所示，所述像素电路包括第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、存储电容Cst、发光二极管D1以及补偿模块。
其中，图2所示的像素电路中，第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7均为P型薄膜晶体管，发光二极管D1为OLED。
图2所示的像素电路的电路连接结构如下所述：
第一薄膜晶体管M1的栅极分别与第三薄膜晶体管M3的源极、第四薄膜晶体管M4的源极以及存储电容Cst的一端(图2所示的B点)连接，源极分别与第二薄膜晶体管M2的漏极、第五薄膜晶体管M5的漏极以及第七薄膜晶体管M7的源极连接，漏极分别与第三薄膜晶体管M3的漏极以及第六薄膜晶体管M6的源极连接；
第二薄膜晶体管M2的源极与数据电压信号线连接；
第四薄膜晶体管M4的漏极与参考电压信号线连接；
第五薄膜晶体管M5的源极与第一电源VDD连接；
第六薄膜晶体管M6的漏极与发光二极管D1的阳极连接；
第七薄膜晶体管M7的漏极与存储电容Cst的另一端(图2所示的A点)连接；
发光二极管D1的阴极与第二电源VSS连接；
所述补偿模块的输出端分别与第七薄膜晶体管M7的漏极以及存储电容Cst的另一端(图2所示的A点)连接。
需要说明的是，在实际应用中，图1所示的第三薄膜晶体管M3可以由两个共栅极的薄膜晶体管代替，这样，在所述像素电路的工作过程中，所述两个共栅极的薄膜晶体管可以降低第三薄膜晶体管M3所在支路的漏电流。同理，第四薄膜晶体管M4也可以由两个共栅极的薄膜晶体管代替，以降低第四薄膜晶体管M4所在支路的漏电流。此外，针对图1中的其他可以视为开关管的薄膜晶体管而言，也可以根据实际需要将其中一个或多个薄膜晶体管分别由两个共栅极的薄膜晶体管代替，以降低其所在支路的漏电流，本申请实施例不做具体限定。
本申请实施例中，所述第一电源VDD可以是正电压，并用于为第一薄膜晶体管M1提供电源电压，第一薄膜晶体管M1在第一电源VDD的作用下，可以输出电流，该电流流入发光二极管D1，使得发光二极管D1发光，在发光二极管D1发光时，该电流流入第二电源VSS，第二电源VSS可以是负电压。
所述数据电压信号线可以用于提供数据电压Vdata，所述参考电压信号线可以用于提供参考电压VREF。本申请实施例中，参考电压VREF可以为负电压，并用于对第一薄膜晶体管M1的栅极进行初始化。
本申请实施例中，所述补偿模块可以用于提供补偿电压，并且，所述补偿模块可以控制所述补偿电压通过存储电容Cst向第一薄膜晶体管M1的栅极施加电压，这样，在所述像素电路工作的过程中，所述补偿电压可以对第一电源VDD提供的所述电源电压进行补偿，使得流经发光二极管D1的电流与第一电源VDD无关。
需要说明的是，本申请实施例中，所述补偿电压可以是正电压，也可以是负电压，其中，当所述补偿电压为正电压时，所述补偿电压可以大于第一电源VDD；当所述补偿电压为负电压时，所述补偿电压与参考电压VREF可以由同一电源提供，此时，数据电压Vdata可以是负电压，且可以小于所述补偿电压。
图2所示的像素电路中，S1为第一扫描线提供的第一扫描信号，S2为第二扫描线提供的第二扫描信号，EM为发光控制线提供的发光控制信号，其中：
第四薄膜晶体管M4的栅极与所述第一扫描线连接，所述第一扫描线提供的第一扫描信号S1可以控制第四薄膜晶体管M4处于导通状态或截止状态；
第二薄膜晶体管M2的栅极以及第三薄膜晶体管M3的栅极与所述第二扫描线连接，所述第二扫描线提供的第二扫描信号S2可以控制第二薄膜晶体管M2以及第三薄膜晶体管M3处于导通状态或截止状态；
第五薄膜晶体管M5的栅极、第六薄膜晶体管M6的栅极以及第七薄膜晶体管M7的栅极与所述发光控制线连接，所述发光控制线提供的发光控制信号EM可以控制第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7处于导通状态或截止状态。
本申请实施例中，在第一扫描信号S1控制第四薄膜晶体管M4处于导通状态时，参考电压VREF可以通过第四薄膜晶体管M4向第一薄膜晶体管M1的栅极施加电压，对第一薄膜晶体管M1的栅极进行初始化；
在第二扫描信号S2控制第二薄膜晶体管M2以及第三薄膜晶体管M3处于导通状态时，针对第一薄膜晶体管M1而言，第一薄膜晶体管M1的栅极与漏极连接，数据电压Vdata通过第二薄膜晶体管M2向第一薄膜晶体管M1的源极施加电压，电路状态稳定后，第一薄膜晶体管M1的源极电压为Vdata，栅极电压以及漏极电压为Vdata-Vth，实现对第一薄膜晶体管M1阈值电压的补偿，其中，Vth为第一薄膜晶体管M1的阈值电压；
在发光控制信号EM控制第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7处于导通状态时，第一电源VDD可以通过第五薄膜晶体管M5向第一薄膜晶体管M1的源极施加电压，第一薄膜晶体管M1可以产生电流，该电流流经发光二极管D1，使得发光二极管D1发光。
此外，发光控制信号EM在控制第五薄膜晶体管M5以及第七薄膜晶体管M7处于导通状态时，第一电源VDD还可以与存储电容Cst的另一端(图2所示的A点)连接，此时，所述补偿模块可以控制所述补偿电压与存储电容Cst断开，使得存储电容Cst的上极板(图2所示的A点)电压可以由所述补偿电压变为VDD，这样，在存储电容Cst的作用下，可以使得流经发光二极管D1的电流与补偿电压VIN有关，与第一电源VDD无关，实现对第一电源VDD进行补偿，使得第一电源VDD产生的电源电压降不会影响流经发光二极管D1的电流，保证显示装置显示的均匀性。
在本申请提供的另一实施例中，所述补偿模块可以包含补偿电压信号线以及第八薄膜晶体管，其中，所述补偿电压信号线可以用于提供补偿电压，所述第八薄膜晶体管可以是P型薄膜晶体管，也可以是N型薄膜晶体管。
图3为本申请实施例提供的另一像素电路的结构示意图。其中，图3与图2相比，将图2所示的补偿模块替换为所述补偿电压信号线以及第八薄膜晶体管M8。
图3中，VIN为所述补偿电压信号线提供的补偿电压，第八薄膜晶体管M8为P型薄膜晶体管，其中，第八薄膜晶体管M8的源极与所述补偿电压信号线连接，漏极分别与第七薄膜晶体管M7的漏极以及存储电容Cst的另一端(图3所示的A点)连接，栅极与所述第二扫描线连接。
图3所示的像素电路中，第二扫描线S2可以控制第八薄膜晶体管M8处于导通状态或截止状态，在第二扫描线S2控制第八薄膜晶体管M8处于导通状态时，补偿电压VIN可以向存储电容Cst的上极板(图3所示的A点)施加电压，使得存储电容Cst的上极板电压为VIN。
这样，在发光控制信号EM控制第五薄膜晶体管M5以及第七薄膜晶体管M7处于导通状态时，第一电源VDD与存储电容Cst的另一端(图3所示的A点)连接，第一电源VDD向存储电容Cst的上极板施加电压，可以使得存储电容Cst的上极板电压由VIN变为VDD，这样，在存储电容Cst的作用下，流经发光二极管D1的电流与补偿电压VIN有关，与第一电源VDD无关，可以实现对第一电源VDD的补偿，使得第一电源VDD产生的电源电压降不会影响流经发光二极管D1的电流，保证显示装置显示的均匀性。
图4为本申请实施例提供的一种像素电路的驱动方法的时序图，所述像素电路的驱动方法可以用于驱动图2或图3所示的像素电路。下面以驱动图3所示的像素电路为例进行说明。
图4所示的时序图在驱动图3所示的像素电路时，工作周期可以包括三个阶段：第一阶段t1、第二阶段t2以及第三阶段t3，其中，S1为第一扫描线提供的第一扫描信号，可以用于控制图3所示的第四薄膜晶体管M4处于导通状态或截止状态，S2为第二扫描线提供的第二扫描信号，可以用于控制图3所示的第二薄膜晶体管M2、第三薄膜晶体管M3以及第八薄膜晶体管M8处于导通状态或截止状态，EM为发光控制线提供的发光控制信号，可以用于控制图3所示的第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7处于导通状态或截止状态，Vdata为数据电压信号线提供的数据电压。
下面分别针对上述三个阶段进行说明：
针对第一阶段t1：
由于第一扫描信号S1由高电平变为低电平，第二扫描信号S2保持高电平，发光控制信号EM由低电平变为高电平，因此，第四薄膜晶体管M4处于导通状态，第二薄膜晶体管M2、第三薄膜晶体管M3以及第八薄膜晶体管M8处于截止状态，第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7处于截止状态。
此时，参考电压VREF通过第四薄膜晶体管M4向第一薄膜晶体管M1的栅极以及存储电容Cst的下极板(图3所示的B点)施加电压，对第一薄膜晶体管M1的栅极以及存储电容Cst的下极板进行初始化。
在初始化后，第一薄膜晶体管M1的栅极电压等于VREF，存储电容Cst的下极板电压也为VREF。
针对第二阶段t2：
由于第一扫描信号S1由低电平变为高电平，第二扫描信号S2由高电平变为低电平，发光控制信号EM保持高电平，因此，第四薄膜晶体管M4由导通状态变为截止状态，第二薄膜晶体管M2、第三薄膜晶体管M3以及第八薄膜晶体管M8由截止状态变为导通状态，第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7仍处于截止状态。
此时，第一薄膜晶体管M1的栅极与漏极连接，数据电压Vdata通过第二薄膜晶体管M2向第一薄膜晶体管M1的源极施加电压，此时，第一薄膜晶体管M1的源极电压为Vdata，由于在第一阶段t1第一薄膜晶体管M1的栅极电压为VREF，因此，第一薄膜晶体管M1处于导通状态，数据电压Vdata经过第一薄膜晶体管M1以及第三薄膜晶体管M3作用在第一薄膜晶体管M1的栅极，最终使得第一薄膜晶体管M1的栅极电压和漏极电压均为Vdata-Vth，第一薄膜晶体管M1处于截止状态，这样，可以实现对第一薄膜晶体管M1阈值电压的补偿，其中，Vth为第一薄膜晶体管M1的阈值电压。
此外，补偿电压VIN通过第八薄膜晶体管M8向存储电容Cst的上极板施加电压，使得存储电容Cst的上极板电压变为VIN。此时，由于存储电容Cst的下极板电压等于第一薄膜晶体管M1的栅极电压，因此，存储电容Cst的下极板电压为Vdata-Vth，存储电容Cst的下极板与上极板之间的压差为Vdata-Vth-VIN。
针对第三阶段t3：
由于第一扫描信号S1保持高电平，第二扫描信号S2由低电平变为高电平，发光控制信号EM由高电平变为低电平，因此，第四薄膜晶体管M4仍处于截止状态，第二薄膜晶体管M2、第三薄膜晶体管M3以及第八薄膜晶体管M8由导通状态变为截止状态，第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7由截止状态变为导通状态。
此时，第一电源VDD通过第五薄膜晶体管M5以及第七薄膜晶体管M7向存储电容Cst的上极板施加电压，使得存储电容Cst的上极板电压变为VDD，由于此时存储电容Cst的耦合作用，存储电容Cst的下极板与上极板之间的压差不变，因此，存储电容Cst的下极板电压为VDD+Vdata-Vth-VIN，由于第一薄膜晶体管M1的栅极电压与存储电容Cst的下极板电压相等，因此，第一薄膜晶体管M1的栅极电压为VDD+Vdata-Vth-VIN。
第一电源VDD通过第五薄膜晶体管M5向第一薄膜晶体管M1的源极施加电压，使得第一薄膜晶体管M1的源极电压为VDD，第一薄膜晶体管M1导通，电流流经发光二极管D1，发光二极管D1发光。
在第三阶段t3，流经发光二极管D1的电流可以表示为：
其中，μ为第一薄膜晶体管M1的电子迁移率，Cox为第一薄膜晶体管M1单位面积的栅氧化层电容，W/L为第一薄膜晶体管M1的宽长比。
由上述公式可知，流经发光二极管D1的电流与补偿电压VIN有关，与第一电源VDD无关，也与第一薄膜晶体管M1的阈值电压无关，实现了对第一电源VDD的补偿，避免了第一电源VDD的电源电压降对显示效果的影响，保证了显示装置显示的均匀性，同时，实现了对第一薄膜晶体管M1的阈值电压的补偿，避免了由于第一薄膜晶体管M1的阈值电压的不同导致的显示装置显示不均匀的问题。
需要说明的是，在实际应用中，补偿电压VIN也存在一定的压降，但是，由于补偿电压VIN仅需要给存储电容Cst充电，不参与对像素电路的驱动，因此，补偿电压VIN产生的电流远小于第一电源VDD产生的电流，进而产生的压降也远小于第一电源VDD产生的压降，也就是说，本申请实施例由补偿电压VIN决定流经发光二极管D1的电流，可以有效改善电源电压将导致的显示装置的不均匀性。
在实际应用中，使用本申请实施例提供的像素电路，以补偿电压VIN＝4.6V，数据电压Vdata＝2V，第一电源VDD＝4.3/4.4/4.5/4.6/4.7/4.8V进行仿真，可以得到仿真结果：第一电源VDD变化时，流经发光二极管D1的电流最小值与最大值的比值约为92％，使用图1所示的像素电路在相同的电压参数下进行仿真，可以得到，流经发光二极管D1的电流最小值与最大值的比值约为67％。由此可见，在第一电源VDD发生变化时，本申请实施例提供的像素电路中流经发光二极管D1的电流的变化小于图1中流经发光二极管D1的电流的变化，因此，本申请实施例提供的像素电路可以有效改善了显示装置显示的均匀性。
此外，使用本申请实施例提供的像素电路，以补偿电压VIN＝4.6V，数据电压Vdata＝2V，第一电源VDD＝4.6V进行仿真，可以得到补偿电压VIN对存储电容Cst进行充电时产生的电流约为2pA，远小于第一电源VDD作用于第一薄膜晶体管M1时产生的电流306nA，这样，由于补偿电压VIN产生的电流小于第一电源VDD产生的电流，因此，补偿电压VIN从一个像素电路传输至其他像素电路时产生的压降也小于第一电源VDD产生的电源电压降，由此可见，相较于第一电源VDD，由补偿电压VIN决定流经发光二极管D1的电流可以有效改善显示装置的显示均匀性。
本申请实施例提供的像素电路中包含补偿模块，该补偿模块可以在像素电路的发光阶段，对作用在驱动薄膜晶体管上的电源电压进行补偿，使得流经发光二极管的电流与电源电压无关，进而可以避免由于电源电压降导致的流经发光二极管的电流不同，显示装置显示不均匀性的问题。
此外，本申请实施例提供的像素电路还可以实现对驱动薄膜晶体管阈值电压的补偿，有效避免由于驱动薄膜晶体管的阈值电压的不同导致的显示装置显示不均匀的问题。
本申请实施例还提供一种显示装置，所述显示装置可以包括上述记载的所述像素电路。
本领域的技术人员应明白，尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

1.一种像素电路，其特征在于，包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管、存储电容以及补偿模块，其中：
所述第一薄膜晶体管的栅极分别与所述第三薄膜晶体管的源极、所述第四薄膜晶体管的源极以及所述存储电容的一端连接，所述第四薄膜晶体管的漏极与参考电压信号线连接，所述存储电容的另一端分别与所述第七薄膜晶体管的漏极以及所述补偿模块的输出端连接；
所述第一薄膜晶体管的源极分别与所述第二薄膜晶体管的漏极、所述第五薄膜晶体管的漏极以及所述第七薄膜晶体管的源极连接，所述第二薄膜晶体管的源极与数据电压信号线连接，所述第五薄膜晶体管的源极与第一电源连接；
所述第一薄膜晶体管的漏极分别与所述第三薄膜晶体管的漏极以及所述第六薄膜晶体管的源极连接，所述第六薄膜晶体管的漏极与所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源连接。
2.如权利要求1所述的像素电路，其特征在于，
所述补偿模块用于提供补偿电压，所述补偿模块控制所述补偿电压通过所述存储电容施加至所述第一薄膜晶体管的栅极，并对所述第一电源提供的电源电压进行补偿，使得流经所述发光二极管的电压与所述第一电源无关。
3.如权利要求2所述的像素电路，其特征在于，
所述补偿电压为正电压，所述补偿电压大于所述第一电源提供的电源电压；或，
所述补偿电压为负电压，所述补偿电压与所述参考信号线提供的参考电压由同一电源提供。
4.如权利要求3所述的像素电路，其特征在于，
所述第一电源，用于为所述第一薄膜晶体管提供电源电压；
所述发光二极管发光时电流流入所述第二电源。
5.如权利要求4所述的像素电路，其特征在于，
所述参考电压信号线用于提供参考电压，所述参考电压为负电压，并用于对所述第一薄膜晶体管的栅极进行初始化。
6.如权利要求5所述的像素电路，其特征在于，
所述第四薄膜晶体管的栅极与第一扫描线连接，所述第一扫描线提供的第一扫描信号控制所述第四薄膜晶体管处于导通状态时，对所述第一薄膜晶体管的栅极进行初始化；
所述第二薄膜晶体管的栅极以及所述第三薄膜晶体管的栅极与第二扫描线连接，所述第二扫描线提供的第二扫描信号控制所述第二薄膜晶体管以及所述第三薄膜晶体管处于导通状态时，对所述第一薄膜晶体管的阈值电压进行补偿；
所述第五薄膜晶体管的栅极、所述第六薄膜晶体管的栅极以及所述第七薄膜晶体管的栅极与发光控制线连接，所述发光控制线提供的发光控制信号控制所述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管处于导通状态时，电流流经所述发光二极管。
7.如权利要求6所述的像素电路，其特征在于，所述补偿模块包括：补偿电压信号线以及第八薄膜晶体管，其中：
所述补偿电压信号线用于提供所述补偿电压；
所述第八薄膜晶体管的源极与所述补偿电压信号线连接，漏极分别与所述第七薄膜晶体管的漏极以及所述存储电容的另一端连接，栅极与所述第二扫描线连接。
8.如权利要求7所述的像素电路，其特征在于，
所述第二扫描信号控制所述第八薄膜晶体管处于导通状态时，所述补偿电压信号线与所述存储电容的另一端连接，所述补偿电压向所述存储电容施加电压；
所述发光控制信号控制所述第五薄膜晶体管以及所述第七薄膜晶体管处于导通状态时，所述第一电源与所述存储电容的另一端连接，所述第一电源向所述存储电容的另一端施加电压，在所述存储电容的作用下，流经所述发光二极管的电流与所述补偿电压有关，与所述第一电源无关。
9.如权利要求8所述的像素电路，其特征在于，
所述第一薄膜晶体管为P型薄膜晶体管；
所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管以及所述第八薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
10.一种显示装置，其特征在于，包括：如权利要求1至9任一项所述的像素电路。
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