WO2019075749A1 - 模拟读取电路及影像传感模块 - Google Patents

模拟读取电路及影像传感模块 Download PDF

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Publication number
WO2019075749A1
WO2019075749A1 PCT/CN2017/107113 CN2017107113W WO2019075749A1 WO 2019075749 A1 WO2019075749 A1 WO 2019075749A1 CN 2017107113 W CN2017107113 W CN 2017107113W WO 2019075749 A1 WO2019075749 A1 WO 2019075749A1
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Prior art keywords
sampling
sensing
reset
analog
average
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PCT/CN2017/107113
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English (en)
French (fr)
Inventor
曾千鉴
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/107113 priority Critical patent/WO2019075749A1/zh
Priority to CN201780001413.3A priority patent/CN108064446B/zh
Priority to EP17929413.7A priority patent/EP3611919A4/en
Publication of WO2019075749A1 publication Critical patent/WO2019075749A1/zh
Priority to US16/682,711 priority patent/US20200084405A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/618—Noise processing, e.g. detecting, correcting, reducing or removing noise for random or high-frequency noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to an analog reading circuit and an image sensing module, and more particularly to an analog reading circuit and an image sensing module capable of improving signal to noise ratio and reducing circuit area and power consumption.
  • Correlated Multiple Sampling (CMS) technology has the advantage of improving signal-to-noise ratio (SNR), which has been applied to Column Analog-to-Digital Converter (Column ADC) in image sensing module.
  • SNR signal-to-noise ratio
  • the analog to digital converter only needs to perform analog to digital conversion on multiple analog pixel values of a pixel column in the pixel array.
  • an analog-to-digital converter employing correlated multi-sampling is performed in a digital domain, which requires a high sampling rate.
  • the column analog-to-digital converter has the disadvantage of occupying a large circuit area and large power consumption.
  • different analog-to-digital converters for different pixel columns may also have mismatch problems, where the analog-to-digital converters do not match, that is, different analog-to-digital converters convert the same analog value into different digital values. .
  • an object of some embodiments of the present application is to provide an analog read circuit and an image sensing module that can perform correlated multi-sampling in an analog domain to improve the disadvantages of the prior art.
  • an embodiment of the present application provides an analog read circuit coupled between a pixel circuit and an analog-to-digital converter, the pixel circuit including a transfer gate, a reset transistor, a select gate, and a pixel output terminal.
  • the analog read circuit includes an amplifier including a first input and a first output, wherein the first output is configured to output a read result of the analog read circuit to the analog to digital converter;
  • the sensing multiple sampling unit is coupled to the pixel output end, the first input end, and the first output end, and includes a plurality of sensing sample averaging units, where the plurality of sensing sampling averaging units comprise multiple sensing units a capacitor; wherein, in the selection interval, the sensing multiplex sampling unit performs a plurality of sensing sampling operations on the pixel values of the pixel output end at a plurality of sensing sampling times, respectively, to generate a plurality of sensing sampling results; wherein In the output interval, the sensing multiple sampling unit performs a sensing averaging operation on the plurality of sampling results, the amplifier outputs the reading result, and the reading result is related Sensing the average of the plurality of sampling results of the sensing.
  • the first sensing sampling averaging unit of the plurality of sensing sampling averaging units performs one sensing sampling operation, in a pair In a first sensing sampling interval of the first sensing sampling operation, a connection between the first sensing capacitance and the pixel output end corresponding to the first sensing sampling averaging unit is conductive, The connection between the sensing capacitance of the remaining sensing sample averaging unit and the pixel output is an open circuit.
  • the plurality of sensing capacitors have a plurality of first ends and a plurality of second ends, and in the output interval, a connection between the plurality of first ends of the plurality of sensing capacitors is Turning on, the connection between the plurality of second ends of the plurality of sensing capacitors is conductive to perform the sensing averaging operation.
  • a connection between the plurality of sensing capacitors and the first input terminal is conductive, and a connection between the plurality of sensing capacitors and the first output end is Turning on, the amplifier outputs the read result.
  • the first sensing sampling averaging unit of the plurality of sensing sampling averaging units includes a first sampling switch coupled to the first end of the first sensing capacitor of the first sensing sampling averaging unit
  • the first average switch is coupled to the first sensing capacitor: and the second average switch is coupled between the first sensing capacitor and the first input end.
  • the first average switch is coupled between the first sensing capacitor and another sensing capacitor.
  • the first sensing sampling average unit further includes a second sampling switch, one end of the second sampling switch is coupled to the first sensing capacitor, and the other end receives a common mode voltage.
  • the plurality of sensing sampling times are after the transmission gate is turned on.
  • the amplifier further includes a second input end and a second output end
  • the analog read circuit further includes a reset multi-sampling unit coupled to the pixel output end, the second input end, and the a second output end comprising a plurality of reset sample averaging units, the reset plurality of sample averaging units comprising a plurality of reset capacitors; wherein, in the selection interval, the reset multiplex sampling unit is reset in multiple Sampling time respectively performing a reset sampling operation on the pixel value of the pixel output end to generate a plurality of reset sampling results; wherein, in the output interval, the resetting the multi-sampling unit to the plurality of sampling results Performing a reset averaging operation, the amplifier outputs the read result, the read result being related to a subtraction result between a reset average of the plurality of reset sample results and the sense average.
  • a first reset sampling average unit in the plurality of reset sampling average units performs a reset sampling operation, corresponding to In the first reset sampling interval of the first reset sampling operation, a connection between the first reset capacitance corresponding to the first reset sampling average unit and the pixel output terminal is turned on, and the remaining weight is
  • the connection between the reset capacitance of the sample averaging unit and the pixel output is an open circuit.
  • the plurality of reset capacitors have a plurality of first ends and a plurality of second ends, and in the output interval, a connection between the plurality of first ends of the plurality of reset capacitors is Turning on, the connection between the plurality of second ends of the plurality of reset capacitors is turned on to perform the reset averaging operation.
  • a connection between the plurality of reset capacitors and the first input terminal The junction is turned on, the connection between the plurality of reset capacitors and the second output terminal is turned on, and the amplifier outputs the read result.
  • the first reset sampling average unit of the plurality of reset sampling average units includes a third sampling switch coupled to the first end of the first reset capacitor of the first reset sampling average unit
  • the third average switch is coupled to the first reset capacitor: and the fourth average switch is coupled between the first reset capacitor and the first input terminal.
  • the third average switch is coupled between the first reset capacitor and the first output terminal.
  • the third average switch is coupled between the first reset capacitor and another reset capacitor.
  • the first reset sampling average unit further includes a fourth sampling switch, one end of the fourth sampling switch is coupled to the first reset capacitor, and the other end receives a common mode voltage.
  • the plurality of reset sampling times are before the transfer gate is turned on and after the reset transistor is turned on.
  • An embodiment of the present application provides an image sensing module including a plurality of pixel circuits arranged in an array, each pixel circuit including a transfer gate, a reset transistor, a selection gate, and a pixel output terminal; an analog-to-digital converter; analog reading a circuit coupled between the plurality of pixel circuits and the analog to digital converter, the analog read circuit including an amplifier, including a first input end and a first output end, wherein the first output end is And outputting the read result of the analog read circuit to the analog-to-digital converter; and sensing the multi-sampling unit, coupled to the pixel output end, the first input end, and the first output end, including multiple Sensing sampling averaging units, the plurality of sensing sampling averaging units comprising a plurality of sensing capacitors; wherein, in the selecting interval, the sensing multiplex sampling unit outputs the pixels to the plurality of sensing sampling times respectively Performing a plurality of sensing sampling operations on the pixel values of the terminal to generate a plurality
  • the invention utilizes an analog read circuit to perform correlated multi-sampling operations and averaging operations on analog pixel values in the analog domain to improve the system signal-to-noise ratio.
  • the operation time required for the analog reading circuit of the present application is extremely short, it can be applied to the image sensing module of the global analog-to-digital converter, and the advantages of reducing the circuit area and power consumption can be achieved.
  • FIG. 1 is a schematic diagram of an image sensing module according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an analog read circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of multiple signals in an embodiment of the present application.
  • FIG. 4 is an equivalent circuit diagram of a sensing multiple sampling unit in a selection interval according to an embodiment of the present application
  • FIG. 5 is an equivalent circuit diagram of the sensing multi-sampling unit of FIG. 4 in an output interval
  • FIG. 6 is a schematic diagram of sensing a multiple sampling unit according to Embodiment 1 of the present application.
  • FIG. 7 is a schematic diagram of a plurality of signals applied to the sensing multiple sampling unit of FIG. 6;
  • FIG. 8 is a schematic diagram of an analog read circuit of the embodiment of the present application.
  • FIG. 9 is a schematic diagram of a plurality of signals applied to the sensing multiple sampling unit of FIG. 8;
  • FIG. 10 is an equivalent circuit diagram of the sensing multiple sampling unit of FIG. 8 in a selection interval
  • FIG. 11 is an equivalent circuit diagram of the sensing multi-sampling unit of FIG. 8 in an output section.
  • FIG. 1 is a schematic diagram of an image sensing module 10 according to an embodiment of the present application.
  • the image sensing module 10 includes a plurality of pixel circuits PX, an analog read circuit 12 and an analog-to-digital converter (ADC) 14.
  • the plurality of pixel circuits PX are arranged in an array and coupled to the analog read circuit 12, and the analog read circuit 12 reads the analog pixel values V PX corresponding to each of the pixel circuits PX at different times to generate an analog read result VRO,
  • the read result VRO is output to the analog to digital converter 14.
  • the analog read circuit 12 can perform a Correlated Multiple Sampling (CMS) operation on the analog pixel value V PX in an Analog Domain to improve the signal-to-noise ratio of the read result VRO. That is, the analog reading circuit 12 can sample the analog pixel value V PX at different times to generate a plurality of sampling results, and perform an average operation on the plurality of sampling results to output the reading result VRO, and the reading result VRO is related. The average of multiple sampled results. The noise energy can be reduced by averaging operation, thereby improving the signal to noise ratio.
  • CMS Correlated Multiple Sampling
  • FIG. 2 is a schematic diagram of an analog read circuit 22 and a pixel circuit PX according to an embodiment of the present application.
  • Analog read circuit 22 can be used to implement analog read circuit 12 of FIG.
  • FIG. 2 only shows a single pixel circuit PX.
  • the analog read circuit 22 is coupled between the pixel output terminal N PX of the pixel circuit PX and the analog-to-digital converter 14, the pixel circuit PX outputs a pixel value V PX at the pixel output terminal N PX , and the analog read circuit 22 includes a sensing The multi-sampling unit 24 and an amplifier 26, the sensing multi-sampling unit 24 is coupled to the pixel output terminal N PX , the negative input terminal of the amplifier 26 (labeled with a "-" sign), and an output terminal.
  • the positive input terminal (labeled with a "+" sign) of the amplifier 26 receives a fixed voltage V SG
  • the fixed voltage V SG can be a ground voltage or a signal ground voltage.
  • the sensing multi-sampling unit 24 can perform sampling operations on the pixel values V PX for two different sensing sampling times (t S1 , t S2 ) to generate two sensing samples.
  • the sensing multiple sampling unit 24 can average the two sampling results obtained in the sampling phase, and output the reading result VRO, wherein the reading result VRO is related to the two The average of the sampled results.
  • the sensing multi-sampling unit 24 includes sensing sampling averaging units 241, 242.
  • the sensing sampling averaging unit 241 includes a sensing capacitor CS1, sampling switches SS1a, SS1b, and average switches SB1a, SB1b, and sensing sampling averaging units.
  • 242 includes a sensing capacitor CS2, sampling switches SS2a, SS2b and average switches SB2a, SB2b, sampling switches SS1a, SS1b are controlled by signal ⁇ S1 , sampling switches SS2a, SS2b are controlled by signal ⁇ S2 , average switches SB1a, SB1b, SB2a, SB2b are controlled by signal H.
  • sampling switches SS1b and SS2b are respectively coupled to the sensing capacitors CS1 and CS2, and the other end receives the common mode voltage Vcm.
  • the average switch SB1a is coupled between the sensing capacitor CS1 and the sensing capacitor CS2.
  • the average switch SB2a is coupled between the sensing capacitor CS2 and the output of the amplifier 26.
  • the average switches SB1b and SB2b are coupled to the sensing capacitor CS1. , between CS2 and the negative input of amplifier 26.
  • the pixel circuit PX may include a photodiode PD, a transfer gate Q TX , a reset transistor Q RST , a buffer transistor QD, a selection gate Q SEL , and a pixel output terminal N PX .
  • the transfer gate Q TX , the reset transistor Q RST and the select gate Q SEL are respectively controlled by the transfer signal TX, the reset signal RST and the select signal SEL, and the pixel circuit PX outputs the pixel value V PX at the pixel output terminal N PX .
  • FIG. 3 is a timing diagram of the selection signal SEL, the transmission signal TX, the signals ⁇ S1 , ⁇ S2 , and H.
  • the select gate Q SEL corresponding to the pixel circuit PX is turned on (ie, the select signal SEL is high, wherein the select signal SEL is high) is called the select interval T SEL ).
  • the transmission gate Q TX is turned on, and the photoelectrons stored in the photodiode PD are captured to the node FD of the pixel circuit PX.
  • the sampling switches SS1a, SS1b and the sampling switches SS2a, SS2b are turned on in the sensing sampling interval T S1 and the sensing sampling interval T S2 , respectively.
  • the first end of the sensing capacitor CS1 is connected to the pixel output terminal N PX (ie, the connection between the sensing capacitor CS1 and the pixel output terminal N PX is a guide
  • the second terminal of the sensing capacitor CS1 receives the common mode voltage Vcm, and the connection between the first end of the sensing capacitor CS2 and the pixel output terminal N PX is an open circuit.
  • the sensing sample averaging units 241, 242 can be regarded as sensing sampling operations on the pixel values V PX at times t S1 , t S2 corresponding to the falling edges of the signals ⁇ S1 , ⁇ S2 , respectively.
  • the sensing multi-sampling unit 24 (the portion related to the charge change) is equivalent to the map.
  • the sensing multi-sampling unit 24 completes the sampling operation (or when the selection gate Q SEL is turned from on to off), in the output interval T A (the output interval T A may be the aforementioned amplification phase), averaging The switches SB1a, SB1b, SB2a, and SB2b are all turned on, and the sampling switches SS1a, SS1b, SS2a, and SS2b are all open.
  • the sensing multi-sampling unit 24 (the portion related to the charge change) is equivalent to that depicted in FIG. The equivalent circuit shown. As shown in FIG.
  • the first ends of the sensing capacitors CS1, CS2 are connected to each other (the first ends of the sensing capacitors CS1, CS2 are electrically connected to each other), and the second ends of the sensing capacitors CS1, CS2 are sensed.
  • the charges stored in the sensing capacitor CS1 and the sensing capacitor CS2 can be shared with each other (ie, charge sharing). ))
  • the effect of averaging the two sensed sampling results is achieved.
  • the first ends of the sensing capacitors CS1 and CS2 are coupled to the output end of the amplifier 26, the second ends of the sensing capacitors CS1 and CS2 are coupled to the negative input terminal of the amplifier 26, and the amplifier 26 can output the reading result VRO.
  • the reading result VRO is related to the sensing average of the two sensing sampling results.
  • the two sensing sample averaging units (241 and 242) of the sensing multi-sampling unit 24 can select two different sensing sampling times t S1 , t S2 in the interval T SEL , respectively for the pixel value V PX-- perform 2 sensing sampling operations to generate 2 sensing sampling results; and in the output interval T A , average the two sensing sampling results, so that the sensing multiple sampling unit 24 can output correlation
  • the average read result VRO is sensed.
  • the sensing multiple sampling unit of the present application is not limited to including two sensing sampling average units, and the sensing multiple sampling unit may include M sensing sampling average units (where M is greater than 2), which may be selected in the selection interval.
  • M different sensing sampling times t S1 ⁇ t SM in the T SEL , performing M sensing sampling operations on the pixel values V PX-- respectively, and generating M sensing sampling results; and in the output interval T A
  • averaging the M sensing sampling results to obtain a sensing average of the M sensing sampling results, so that the sensing multi-sampling unit 24 can output the reading result VRO related to the sensing average.
  • FIG. 6 is a schematic diagram of a sensing multiple sampling unit 64 according to Embodiment 1 of the present application
  • FIG. 7 is a timing of signals ⁇ S1 ⁇ S4 and H applied to the sensing multiple sampling unit 64.
  • the principle of operation of the sensing multi-sampling unit 64 is similar to that of the sensing multi-sampling unit 24, and thus will not be described again.
  • the image sensing module can first guide the reset transistor Q RST of the pixel circuit PX.
  • the pixel value V PX of the pixel output terminal N PX is read by the analog read circuit (the pixel value at this time is called the reset pixel value V PX , R ), after the transmission gate Q TX is turned on, the analog reading circuit can read the pixel value V PX of the pixel output terminal N PX again (the pixel value at this time is called the signal pixel value V PX, S ), and simulate The read circuit can output the read result VRO such that the read result is related to the subtraction result of the signal pixel value V PX,S and the reset pixel value V PX, R .
  • the analog read circuit 12 can also read the reset pixel value V PX,R by using the correlated multiple sampling (CMS) after the transistor Q RST is turned on and before the transfer gate Q TX is turned on, that is, the present application
  • the analog read circuit may reset the sampling operation for the reset pixel value V PX, R multiple times to generate a plurality of reset sampling results, and perform a reset averaging operation on the plurality of reset sampling results to obtain the plurality of weights
  • the reset average of the sampling results is set, and the reading result VRO output by the reading circuit may be related to the subtraction result of the sensing average and the reset average.
  • FIG. 8 is a schematic diagram of an analog reading circuit 82 according to the embodiment of the present application
  • FIG. 9 is a signal ⁇ R1 ⁇ ⁇ R4 and ⁇ S1 ⁇ ⁇ applied to the sensing multi-sampling unit 84.
  • the timing diagram of S4 , H, the analog read circuit 82 includes a sense multisampling unit 84S, a reset multisampling unit 84R, and an amplifier 86.
  • the amplifier 86 is a fully differential operational amplifier.
  • the sensing multiple sampling unit 84S is coupled to the pixel output terminal N PX and the first input end of the amplifier 86 and the first output end.
  • the reset multiple sampling unit 84R is coupled to the pixel output terminal N.
  • the reset multiple sampling unit 84R includes four reset sampling average units 841R-844R, and the reset sampling average unit 841R includes a reset capacitor CR1, sampling switches RS1a, RS1b, and average switches RB1a, RB1b, and the sampling switches RS1a, RS1b are controlled.
  • the average switches RB1a, RB1b are controlled by signal H.
  • the circuit configurations of the reset sampling averaging units 842R to 844R are similar to the reset sampling averaging unit 841R, wherein the sampling switches RS2a, RS2b are controlled by the signal ⁇ R2 , the sampling switches RS3a, RS3b are controlled by the signal ⁇ R3 , and the sampling switch RS4a RS4b is controlled by signal ⁇ R4 , and average switches RB2a, RB2b, RB3a, RB3b, RB4a, RB4b are controlled by signal H.
  • the average switch RB1a is coupled between the reset capacitor CR1 and the reset capacitor CR2
  • the average switch RB2a is coupled between the reset capacitor CR2 and the reset capacitor CR3
  • the average switch RB3a is coupled to the reset capacitor.
  • the average switch RB4a is coupled between the reset capacitor CR4 and the second output of the amplifier 86.
  • the internal circuit structure of the sensing multi-sampling unit 84S is the same as the sensing multi-sampling unit 64/reset multi-sampling unit 84R, and thus will not be described again.
  • the reset transistor Q RST is turned on before the reset interval T RST , and the reset transistor Q RST is turned on to reset the multi-sampling unit 84R respectively (corresponding to the T R1 ⁇ T of the reset sampling interval) R4 ) reset sampling time t R1 ⁇ t R4 to perform a reset sampling operation on the pixel value V PX of the pixel output terminal N PX , and generate 4 reset sampling results as the amount of charge change in the reset capacitors CR1 ⁇ CR4;
  • the transmission gate Q TX is turned on in the transmission interval T TX , and the sensing multiple sampling unit 84S senses the sampling time t S1 ⁇ t respectively (corresponding to T S1 ⁇ T S4 of the sensing sampling interval) after the transmission gate Q TX is turned on.
  • S4 performs a sensing sampling operation on the pixel value V PX of the pixel output terminal N PX , and generates 4 sensing sampling results as the amount of charge change in the sensing capacitors CS1 CS CS4 .
  • the average switches SB1a to SB4a, SB1b to SB4b are all open in the selection interval T SEL , and the sensing multi-sampling unit 84S and the reset multi-sampling unit 84R (the portion related to the charge change) are equivalent to those illustrated in FIG. 10 . Equivalent circuit.
  • the average switches SB1a SB SB4a , SB1b SB SB4b are all turned on, the sampling switches SS1a ⁇ SS4a, SS1b ⁇ SS4b are all open, the sensing multiple sampling unit 84S and the reset multiple sampling unit 84R (related to The portion of the charge change is equivalent to the equivalent circuit shown in FIG. As shown in FIG. 11, since the first ends of the sensing capacitors CS1 CS CS4 are connected to each other, the second ends of the sensing capacitors CS1 CS CS4 are connected to each other, and therefore, the charges stored in the sensing capacitors CS1 CS CS4 can be mutually connected to each other.
  • the first end and the second end of the sensing capacitors CS1 CS CS4 are connected to the first input end and the first output end of the fully differential amplifier 86, the first end and the second end of the reset capacitors CR1 CR CR4 are connected to The second input and the second output of the fully differential amplifier 86, therefore, the result of the subtraction between the read result VRO-related sense average and the reset average output by the fully differential amplifier 86.
  • the analog read circuit of the present application can perform correlated multi-sampling on the analog pixel value V PX in the analog domain and perform averaging operations in the analog domain, and the required operation time is extremely short, so it can be applied to
  • the image sensing module 10 with a global analog to digital converter (Global ADC) in other words, the analog to digital converter 14 can be a global analog to digital converter, that is, the image sensing module 10 can include only a single analog to digital converter 14, The analog-to-digital converter 14 needs to perform analog-to-digital conversion on the pixel values of all the pixel circuits PX of the image sensing module 10.
  • the image sensing module of the present application does not need to include multiple analog-to-digital converters (such as a column analog-to-digital converter (Column ADC) corresponding to a column in the pixel array), which can reduce circuit area and power consumption. In case of high signal-to-noise bit points with multiple sampling operations.
  • analog-to-digital converters such as a column analog-to-digital converter (Column ADC) corresponding to a column in the pixel array
  • the present invention utilizes an analog read circuit to perform correlated multi-sampling operations and averaging operations on analog pixel values in the analog domain to improve system signal-to-noise ratio.
  • the operation time required for the analog reading circuit of the present application is extremely short, it can be applied to the image sensing module with the global analog-to-digital converter, and the advantages of reducing the circuit area and power consumption can be achieved.

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Abstract

本申请提供了一种模拟读取电路，耦接于像素电路的像素输出端，所述模拟读取电路包括放大器以及感测多重采样单元；其中，于选择区间中，所述感测多重采样单元于多个感测采样时间分别对所述像素输出端的像素值进行多次感测采样操作，产生多个感测采样结果；其中，于输出区间中，所述感测多重采样单元对所述多个采样结果进行感测平均操作，所述放大器输出读取结果，所述读取结果相关于所述多个感测采样结果的感测平均。

Description

模拟读取电路及影像传感模块 技术领域
本申请涉及一种模拟读取电路及影像传感模块，尤其涉及一种可提升信噪比并降低电路面积及功耗的模拟读取电路及影像传感模块。
背景技术
相关多重采样(Correlated Multiple Sampling，CMS)技术具有提升信噪比的优点，其已应用于影像传感模块中的列模数转换器(Column Analog-to-Digital Converter，Column ADC)中，其中列模数转换器仅需对像素阵列中某一像素列的多个模拟像素值进行模数转换。现有技术中，采用相关多重采样的模数转换器是于数字域(Digital Domain)中进行，其需要较高的采样率(Sampling Rate)。也因采用相关多重采样的模数转换器对采样率的需求较高，因此不适合应用在需要对像素阵列中所有模拟像素值进行模数转换的全局模数转换器(Global ADC)。
然而，相较于全局模数转换器，列模数转换器具有占用较大电路面积及功耗大的缺点。除此之外，对应不同像素列的不同模数转换器可能亦存在有不匹配(Mismatch)的问题，其中模数转换器不匹配即为不同模数转换器将同一模拟值转换成为不同数字值。
因此，现有技术实有改进的必要。
发明内容
因此，本申请部分实施例的目的即在于提供一种可于模拟域(Analog Domain)中执行相关多重采样的模拟读取电路及影像传感模块，以改善现有技术的缺点。
为了解决上述技术问题，本申请实施例提供了一种模拟读取电路，耦接于像素电路与模数转换器之间，所述像素电路包括传输闸、重置晶体管、选择闸及像素输出端，所述模拟读取电路包括放大器，包括第一输入端以及第一输出端，其中所述第一输出端用来输出所述模拟读取电路的读取结果至所述模数转换器；以及感测多重采样单元，耦接于像素输出端、所述第一输入端以及所述第一输出端，包括多个感测采样平均单元，所述多个感测采样平均单元包括多个感测电容；其中，于选择区间中，所述感测多重采样单元于多个感测采样时间分别对所述像素输出端的像素值进行多次感测采样操作，产生多个感测采样结果；其中，于输出区间中，所述感测多重采样单元对所述多个采样结果进行感测平均操作，所述放大器输出所述读取结果，所述读取结果相关于所述多个感测采样结果的感测平均。
例如，于所述选择区间中多个感测采样时间的第一感测采样时间，所述多个感测采样平均单元中的第一感测采样平均单元进行一次感测采样操作，于对 应于所述第一感测采样操作的第一感测采样区间中，对应于所述第一感测采样平均单元的第一感测电容与所述像素输出端之间的连结为导通，其余感测采样平均单元的感测电容与所述像素输出端之间的连结为断路。
例如，所述多个感测电容具有多个第一端以及多个第二端，于所述输出区间中，所述多个感测电容的所述多个第一端彼此之间的连结为导通，所述多个感测电容的所述多个第二端彼此之间的连结为导通，以进行所述感测平均操作。
例如，于所述输出区间中，所述多个感测电容与所述第一输入端之间的连结为导通，所述多个感测电容与所述第一输出端之间的连结为导通，所述放大器输出所述读取结果。
例如，所述多个感测采样平均单元中的第一感测采样平均单元包括第一采样开关，耦接于所述第一感测采样平均单元的第一感测电容的第一端与所述像素输出端之间；第一平均开关，耦接于所述第一感测电容：以及第二平均开关，耦接于所述第一感测电容与所述第一输入端之间。
例如，所述第一平均开关耦接于所述第一感测电容与另一感测电容之间。
例如，所述第一感测采样平均单元还包括第二采样开关，所述第二采样开关的一端耦接于所述第一感测电容，另一端接收共模电压。
例如，所述多个感测采样时间位于所述传输闸导通之后。
例如，所述放大器还包括第二输入端以及第二输出端，所述模拟读取电路还包括重置多重采样单元，耦接于所述像素输出端、所述第二输入端以及所述第二输出端，包括多个重置采样平均单元，所述重置多个采样平均单元包括多个重置电容；其中，于所述选择区间中，所述重置多重采样单元于多个重置采样时间分别对所述像素输出端的像素值进行多次重置采样操作，产生多个重置采样结果；其中，于所述输出区间中，所述重置多重采样单元对所述多个采样结果进行重置平均操作，所述放大器输出所述读取结果，所述读取结果相关于所述多个重置采样结果的重置平均与所述感测平均之间的相减结果。
例如，于所述选择区间中多个重置采样时间的第一重置采样时间，所述多个重置采样平均单元中的第一重置采样平均单元进行一次重置采样操作，于对应于所述第一重置采样操作的第一重置采样区间中，对应于所述第一重置采样平均单元的第一重置电容与所述像素输出端之间的连结为导通，其余重置采样平均单元的重置电容与所述像素输出端之间的连结为断路。
例如，所述多个重置电容具有多个第一端以及多个第二端，于所述输出区间中，所述多个重置电容的所述多个第一端彼此之间的连结为导通，所述多个重置电容的所述多个第二端彼此之间的连结为导通，以进行所述重置平均操作。
例如，于所述输出区间中，所述多个重置电容与所述第一输入端之间的连 结为导通，所述多个重置电容与所述第二输出端之间的连结为导通，所述放大器输出所述读取结果。
例如，所述多个重置采样平均单元中的第一重置采样平均单元包括第三采样开关，耦接于所述第一重置采样平均单元的第一重置电容的第一端与所述像素输出端之间；第三平均开关，耦接于所述第一重置电容：以及第四平均开关，耦接于所述第一重置电容与所述第一输入端之间。
例如，所述第三平均开关耦接于所述第一重置电容与所述第一输出端之间。
例如，所述第三平均开关耦接于所述第一重置电容与另一重置电容之间。
例如，所述第一重置采样平均单元还包括第四采样开关，所述第四采样开关的一端耦接于所述第一重置电容，另一端接收共模电压。
例如，所述多个重置采样时间位于所述传输闸导通之前且于所述重置晶体管导通之后。
本申请实施例提供了一种影像传感模块，包括多个像素电路，排列成阵列，每一像素电路包括传输闸、重置晶体管、选择闸及像素输出端；模数转换器；模拟读取电路，耦接于所述多个像素电路与所述模数转换器之间，所述模拟读取电路包括放大器，包括第一输入端以及第一输出端，其中所述第一输出端用 来输出所述模拟读取电路的读取结果至所述模数转换器；以及感测多重采样单元，耦接于像素输出端、所述第一输入端以及所述第一输出端，包括多个感测采样平均单元，所述多个感测采样平均单元包括多个感测电容；其中，于选择区间中，所述感测多重采样单元于多个感测采样时间分别对所述像素输出端的像素值进行多次感测采样操作，产生多个感测采样结果；其中，于输出区间中，所述感测多重采样单元对所述多个采样结果进行感测平均操作，所述放大器输出所述读取结果，所述读取结果相关于所述多个感测采样结果的感测平均。
本发明利用模拟读取电路，于模拟域中对模拟像素值进行相关多重采样操作以及平均操作，以提升系统信噪比。另外，由于本申请模拟读取电路所需的操作时间极短，可应用于全局模数转换器的影像传感模块，而可达到缩小电路面积及功耗的优点。
附图说明
图1为本申请实施例一影像传感模块的示意图；
图2为本申请实施例一模拟读取电路的示意图；
图3为本申请实施例多个信号的示意图；
图4为本申请实施一感测多重采样单元于选择区间的等效电路图；
图5为图4的感测多重采样单元于输出区间的等效电路图；
图6本申请实施例一感测多重采样单元的示意图；
图7为施加于图6的感测多重采样单元的多个信号示意图；
图8本申请实施例一模拟读取电路的示意图；
图9为施加于图8的感测多重采样单元的多个信号示意图；
图10为图8的感测多重采样单元于选择区间的等效电路图；
图11为图8的感测多重采样单元于输出区间的等效电路图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
图1为本申请实施例一影像传感模块10的示意图。影像传感模块10包括多个像素电路PX、一模拟读取电路(Readout)12以及一模数转换器(Analog-to-Digital Converter，ADC)14。多个像素电路PX排列成一阵列并耦接于模拟读取电路12，模拟读取电路12于不同时间读取对应于每一个像素电路PX的模拟像素值VPX，以产生模拟读取结果VRO，并将读取结果VRO输出至模数转换器14。更进一步地，模拟读取电路12可在模拟域(Analog Domain)中对模拟像素值VPX进行相关多重采样(Correlated Multiple Sampling，CMS)操作，以提升读取结果VRO的信噪比。也就是说，模拟读取电路12可于不同时间对模拟像素值VPX进行采样而产生多个采样结果，并对多个采样结果进行平均操作而输出读取结果VRO，而读取结果VRO相关于多个采样结果的平均。藉由平均操作可降低噪声能量，藉此提升信噪比。
具体来说，请参考图2，图2为本申请实施例一模拟读取电路22以及像素 电路PX的示意图。模拟读取电路22可用来实现图1中的模拟读取电路12。为了方便说明，图2仅绘示单一像素电路PX。模拟读取电路22耦接于像素电路PX的像素输出端NPX与模数转换器14之间，像素电路PX于像素输出端NPX输出像素值VPX，模拟读取电路22包括一感测多重采样单元24以及一放大器26，感测多重采样单元24耦接于像素输出端NPX、放大器26的负输入端(标示有「－」号)以及输出端。另外，放大器26的正输入端(标示有「+」号)接收一固定电压VSG，固定电压VSG可为一接地电压或一信号接地(Signal Ground)电压。
于一采样阶段(Sampling Phase)中，感测多重采样单元24可于2个不同的感测采样时间(tS1、tS2)，分别对像素值VPX进行采样操作而产生两个感测采样结果；于一放大阶段(Amplifying Phase)中，感测多重采样单元24可将采样阶段中取得的2个采样结果进行平均操作，并输出读取结果VRO，其中读取结果VRO相关于该2个采样结果的平均。
详细来说，感测多重采样单元24包括感测采样平均单元241、242，感测采样平均单元241包括一感测电容CS1、采样开关SS1a、SS1b以及平均开关SB1a、SB1b，感测采样平均单元242包括一感测电容CS2、采样开关SS2a、SS2b以及平均开关SB2a、SB2b，采样开关SS1a、SS1b受控于信号ΦS1，采样开关SS2a、SS2b受控于信号ΦS2，平均开关SB1a、SB1b、SB2a、SB2b受控于信号H。采样开关SS1b、SS2b的一端分别耦接于感测电容CS1、CS2，另一端接收共模电压Vcm。平均开关SB1a耦接于感测电容CS1与感测电容CS2之 间，平均开关SB2a耦接于感测电容CS2与放大器26的输出端之间，平均开关SB1b、SB2b分别耦接于感测电容CS1、CS2与放大器26的负输入端之间。
另外，像素电路PX的电路结构简述如下。如图2所示，像素电路PX可包括感光二极管(Photo Diode)PD、传输闸QTX、重置晶体管QRST、缓冲晶体管QD、选择闸QSEL及像素输出端NPX。传输闸QTX、重置晶体管QRST及选择闸QSEL分别受控于传输信号TX、重置信号RST及选择信号SEL，像素电路PX于像素输出端NPX输出像素值VPX。
像素电路PX及模拟读取电路22的操作说明如下。请参考图3，图3为选择信号SEL、传输信号TX、信号ΦS1、ΦS2、H的时序图。当模拟读取电路22欲读取像素电路PX时，对应于像素电路PX的选择闸QSEL导通(即选择信号SEL为高电位，其中选择信号SEL为高电位称为选择区间TSEL)。于选择区间TSEL中(采样阶段位于选择区间TSEL中)，传输闸QTX导通，此时储存于感光二极管PD的光电子被汲取至像素电路PX的节点FD。于传输区间TTX导通之后，采样开关SS1a、SS1b以及采样开关SS2a、SS2b分别于感测采样区间TS1以及感测采样区间TS2导通。当采样开关SS1a、SS1b于感测采样区间TS1导通时，感测电容CS1的第一端连接于像素输出端NPX(即感测电容CS1与像素输出端NPX之间的连结为导通)，感测电容CS1的第二端接收共模电压Vcm，而感测电容CS2的第一端与像素输出端NPX之间的连结为断路。同理，当采样开关SS2a、SS2b导通时，感测电容CS2的第一端连接于像素输出端NPX(即感测电容CS2与像素输出端NPX之间的连结为导通)，感测电容CS2的第二端接 收共模电压Vcm，而感测电容CS1的第一端与像素输出端NPX之间的连结为断路。更精确地说，感测采样平均单元241、242可视为分别于对应于信号ΦS1、ΦS2的下降沿(Falling Edge)的时间tS1、tS2对像素值VPX进行感测采样操作，而感测电容CS1、CS2中的电荷变化量可视为感测采样操作的感测采样结果。另外，平均开关SB1a、SB1b、SB2a、SB2b于选择区间TSEL皆为断路，换句话说，于选择区间TSEL中，感测多重采样单元24(相关于电荷变化的部份)等效于图4所绘示的等效电路。
另一方面，当感测多重采样单元24完成采样操作之后(或当选择闸QSEL由导通转为断路后)，于输出区间TA中(输出区间TA可为前述放大阶段)，平均开关SB1a、SB1b、SB2a、SB2b皆为导通，采样开关SS1a、SS1b、SS2a、SS2b皆为断路，此时感测多重采样单元24(相关于电荷变化的部份)等效于图5所绘示的等效电路。如图5所示，感测电容CS1、CS2的第一端相互连结(因感测电容CS1、CS2的第一端彼此之间的连结为导通)，感测电容CS1、CS2的第二端相互连结(因感测电容CS1、CS2的第二端彼此之间的连结为导通)，因此，储存于感测电容CS1与感测电容CS2的电荷可彼此相互分享(即电荷分享(Charge Sharing))而达到对该2个感测采样结果进行平均操作的效果。另外，感测电容CS1、CS2的第一端耦接于放大器26的输出端，感测电容CS1、CS2的第二端耦接于放大器26的负输入端，放大器26即可输出读取结果VRO，而读取结果VRO相关于该2个感测采样结果的感测平均。
简言之，感测多重采样单元24的2个感测采样平均单元(241及242)可 于选择区间TSEL中的2个不同的感测采样时间tS1、tS2，分别对像素值VPX--进行2次感测采样操作，而产生2个感测采样结果；并于输出区间TA中，对该2个感测采样结果进行平均操作，使得感测多重采样单元24可输出相关于该感测平均的读取结果VRO。
需注意的是，本申请的感测多重采样单元不限于包括2个感测采样平均单元，感测多重采样单元可包括M个感测采样平均单元(其中M大于2)，其可于选择区间TSEL中的M个不同的感测采样时间tS1～tSM，分别对像素值VPX--进行M次感测采样操作，而产生M个感测采样结果；并于输出区间TA中，对该M个感测采样结果进行平均操作以取得该M个感测采样结果的感测平均，使得感测多重采样单元24可输出相关于该感测平均的读取结果VRO。
举例来说，请参考图6及图7，图6本申请实施例一感测多重采样单元64的示意图，图7为施加于感测多重采样单元64的信号ΦS1～ΦS4、H的时序图。感测多重采样单元64包括感测采样平均单元641、642、643、644(即M＝4的实施例)。感测多重采样单元64的操作原理与感测多重采样单元24的原理类似，故于此不再赘述。
另一方面，为了使读取结果VRO更能反应像素电路PX中感光二极管PD的感光程度，于传输闸QTX导通前，影像传感模块可先将像素电路PX的重置晶体管QRST导通，并于晶体管QRST导通后且传输闸QTX导通前，利用模拟读取电路读取像素输出端NPX的像素值VPX(此时的像素值称为重置像素值 VPX,R)，于传输闸QTX导通后，模拟读取电路可再次读取于像素输出端NPX的像素值VPX(此时的像素值称为信号像素值VPX,S)，模拟读取电路可输出读取结果VRO，使得读取结果相关于信号像素值VPX,S与重置像素值VPX,R的相减结果。其中，于晶体管QRST导通后且传输闸QTX导通前，模拟读取电路12亦可利用相关多重采样(CMS)读取重置像素值VPX,R，也就是说，本申请的模拟读取电路可对重置像素值VPX,R多次重置采样操作以产生多个重置采样结果，并对该多个重置采样结果进行重置平均操作，以取得该多个重置采样结果的重置平均，而读取电路所输出的读取结果VRO可相关于感测平均与重置平均的相减结果。
具体来说，请参考图8及图9，图8本申请实施例一模拟读取电路82的示意图，图9为施加于感测多重采样单元84的信号ΦR1～ΦR4、ΦS1～ΦS4、H的时序图，模拟读取电路82包括一感测多重采样单元84S、一重置多重采样单元84R以及一放大器86。放大器86为一全差分运算放大器，感测多重采样单元84S耦接于像素输出端NPX以及放大器86的第一输入端以及第一输出端，重置多重采样单元84R耦接于像素输出端NPX以及放大器86的第二输入端以及第二输出端。
重置多重采样单元84R包括4个重置采样平均单元841R～844R，重置采样平均单元841R包括一重置电容CR1、采样开关RS1a、RS1b以及平均开关RB1a、RB1b，采样开关RS1a、RS1b受控于信号ΦR1，平均开关RB1a、RB1b受控于信号H。重置采样平均单元842R～844R的电路结构均与重置采样平均 单元841R类似，其中，采样开关RS2a、RS2b受控于信号ΦR2，采样开关RS3a、RS3b受控于信号ΦR3，采样开关RS4a、RS4b受控于信号ΦR4，平均开关RB2a、RB2b、RB3a、RB3b、RB4a、RB4b受控于信号H。值得注意的是，平均开关RB1a耦接于重置电容CR1与重置电容CR2之间，平均开关RB2a耦接于重置电容CR2与重置电容CR3之间，平均开关RB3a耦接于重置电容CR3与重置电容CR4之间，而平均开关RB4a耦接于重置电容CR4与放大器86的第二输出端之间。感测多重采样单元84S的内部电路结构与感测多重采样单元64/重置多重采样单元84R相同，故于此不再赘述。
于选择区间TSEL中，重置晶体管QRST先于重置区间TRST导通，重置晶体管QRST导通后重置多重采样单元84R分别于(对应于重置采样区间的TR1～TR4)重置采样时间tR1～tR4对像素输出端NPX的像素值VPX进行重置采样操作，而产生4个重置采样结果为重置电容CR1～CR4中的电荷变化量；接着，传输闸QTX于传输区间TTX导通，传输闸QTX导通后感测多重采样单元84S分别于(对应于感测采样区间的TS1～TS4)感测采样时间tS1～tS4对像素输出端NPX的像素值VPX进行感测采样操作，而产生4个感测采样结果为感测电容CS1～CS4中的电荷变化量。另外，平均开关SB1a～SB4a、SB1b～SB4b于选择区间TSEL皆为断路，感测多重采样单元84S及重置多重采样单元84R(相关于电荷变化的部份)等效于图10所绘示的等效电路。
于输出区间TA中，平均开关SB1a～SB4a、SB1b～SB4b皆为导通，采样开关SS1a～SS4a、SS1b～SS4b皆为断路，感测多重采样单元84S及重置多重 采样单元84R(相关于电荷变化的部份)等效于图11所绘示的等效电路。如图11所示，由于感测电容CS1～CS4的第一端皆彼此相连，感测电容CS1～CS4的第二端皆彼此相连，因此，储存于感测电容CS1～CS4的电荷可彼此相互分享而达到对该4个感测采样结果进行感测平均操作的效果，而产生该4个感测采样结果的感测平均；另一方面，由于重置电容CR1～CR4的第一端皆彼此相连，重置电容CR1～CR4的第二端皆彼此相连，因此，储存于重置电容CR1～CR4的电荷可彼此相互分享而达到对该4个重置采样结果进行重置平均操作的效果，而产生该4个重置采样结果的重置平均。另外，由于感测电容CS1～CS4的第一端及第二端连接于全差分放大器86的第一输入端及第一输出端，重置电容CR1～CR4的第一端及第二端连接于全差分放大器86的第二输入端及第二输出端，因此，全差分放大器86所输出的读取结果VRO相关感测平均与重置平均之间的相减结果。
需注意的是，本申请的模拟读取电路可在模拟域中对模拟像素值VPX进行相关多重采样，并在模拟域中进行平均操作，其所需的操作时间极短，因此可应用于搭配全局模数转换器(Global ADC)的影像传感模块10，换句话说，模数转换器14可为全局模数转换器，即影像传感模块10可仅包括单一模数转换器14，而模数转换器14需对影像传感模块10所有像素电路PX的像素值进行模数转换。换句话说，本申请的影像传感模块不需包括多个模数转换器(如对应像素阵列中某一列的列模数转换器(Column ADC))，其可在缩小电路面积及功耗的情况下，具有多重采样操作的高信噪比特点。
综上所述，本发明利用模拟读取电路，于模拟域中对模拟像素值进行相关多重采样操作以及平均操作，以提升系统信噪比。另外，由于本申请模拟读取电路所需的操作时间极短，可应用于搭配全局模数转换器的影像传感模块，而可达到缩小电路面积及功耗的优点。
以上所述仅为本申请的部分实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种模拟读取电路，耦接于像素电路与模数转换器之间，所述像素电路包括传输闸、重置晶体管、选择闸及像素输出端，其特征在于，所述模拟读取电路包括：
    放大器，包括第一输入端以及第一输出端，其中所述第一输出端用来输出所述模拟读取电路的读取结果至所述模数转换器；以及
    感测多重采样单元，耦接于像素输出端、所述第一输入端以及所述第一输出端，包括多个感测采样平均单元，所述多个感测采样平均单元包括多个感测电容；
    其中，于选择区间中，所述感测多重采样单元于多个感测采样时间分别对所述像素输出端的像素值进行多次感测采样操作，产生多个感测采样结果；
    其中，于输出区间中，所述感测多重采样单元对所述多个采样结果进行感测平均操作，所述放大器输出所述读取结果，所述读取结果相关于所述多个感测采样结果的感测平均。
  2. 如权利要求1所述的模拟读取电路，其特征在于，于所述选择区间中多个感测采样时间的第一感测采样时间，所述多个感测采样平均单元中的第一感测采样平均单元进行一次感测采样操作，于对应于所述第一感测采样操作的第一感测采样区间中，对应于所述第一感测采样平均单元的第一感测电容与所述像素输出端之间的连结为导通，其余感测采样平均单元的感测电容与所述像素输出端之间的连结为断路。
  3. 如权利要求1所述的模拟读取电路，其特征在于，所述多个感测电容具有多个第一端以及多个第二端，于所述输出区间中，所述多个感测电容的所述多个第一端彼此之间的连结为导通，所述多个感测电容的所述多个第二端彼此之间的连结为导通，以进行所述感测平均操作。
  4. 如权利要求1所述的模拟读取电路，其特征在于，于所述输出区间中，所述多个感测电容与所述第一输入端之间的连结为导通，所述多个感测电容与所述第一输出端之间的连结为导通，所述放大器输出所述读取结果。
  5. 如权利要求1所述的模拟读取电路，其特征在于，所述多个感测采样平均单元中的第一感测采样平均单元包括：
    第一采样开关，耦接于所述第一感测采样平均单元的第一感测电容的第一端与所述像素输出端之间；
    第一平均开关，耦接于所述第一感测电容：以及
    第二平均开关，耦接于所述第一感测电容与所述第一输入端之间。
  6. 如权利要求5所述的模拟读取电路，其特征在于，所述第一平均开关耦接于所述第一感测电容与所述第一输出端之间。
  7. 如权利要求5所述的模拟读取电路，其特征在于，所述第一平均开关耦接于所述第一感测电容与另一感测电容之间。
  8. 如权利要求5所述的模拟读取电路，其特征在于，所述第一感测采样平均单元还包括第二采样开关，所述第二采样开关的一端耦接于所述第一感测电容，另一端接收共模电压。
  9. 如权利要求1所述的模拟读取电路，其特征在于，所述多个感测采样时间位于所述传输闸导通之后。
  10. 如权利要求1所述的模拟读取电路，其特征在于，所述放大器还包括第二输入端以及第二输出端，所述模拟读取电路还包括：
    重置多重采样单元，耦接于所述像素输出端、所述第二输入端以及所述第二输出端，包括多个重置采样平均单元，所述重置多个采样平均单元包括多个重置电容；
    其中，于所述选择区间中，所述重置多重采样单元于多个重置采样时间分别对所述像素输出端的像素值进行多次重置采样操作，产生多个重置采样结果；
    其中，于所述输出区间中，所述重置多重采样单元对所述多个采样结果进行重置平均操作，所述放大器输出所述读取结果，所述读取结果相关于所述多个重置采样结果的重置平均与所述感测平均之间的相减结果。
  11. 如权利要求10所述的模拟读取电路，其特征在于，于所述选择区间中多个重置采样时间的第一重置采样时间，所述多个重置采样平均单元中的第一重置采样平均单元进行一次重置采样操作，于对应于所述第一重置采样操作的第一重置采样区间中，对应于所述第一重置采样平均单元的第一重置电容与所述像素输出端之间的连结为导通，其余重置采样平均单元的重置电容与所述像素输出端之间的连结为断路。
  12. 如权利要求10所述的模拟读取电路，其特征在于，所述多个重置电容具有多个第一端以及多个第二端，于所述输出区间中，所述多个重置电容的所述多个第一端彼此之间的连结为导通，所述多个重置电容的所述多个第二端彼此之间的连结为导通，以进行所述重置平均操作。
  13. 如权利要求10所述的模拟读取电路，其特征在于，于所述输出区间中，所述多个重置电容与所述第一输入端之间的连结为导通，所述多个重置电容与所述第二输出端之间的连结为导通，所述放大器输出所述读取结果。
  14. 如权利要求10所述的模拟读取电路，其特征在于，所述多个重置采样平均单元中的第一重置采样平均单元包括：
    第三采样开关，耦接于所述第一重置采样平均单元的第一重置电容的第一端与所述像素输出端之间；
    第三平均开关，耦接于所述第一重置电容：以及
    第四平均开关，耦接于所述第一重置电容与所述第一输入端之间。
  15. 如权利要求14所述的模拟读取电路，其特征在于，所述第三平均开关耦接于所述第一重置电容与所述第一输出端之间。
  16. 如权利要求14所述的模拟读取电路，其特征在于，所述第三平均开关耦接于所述第一重置电容与另一重置电容之间。
  17. 如权利要求14所述的模拟读取电路，其特征在于，所述第一重置采样平均单元还包括第四采样开关，所述第四采样开关的一端耦接于所述第一重置电容，另一端接收共模电压。
  18. 如权利要求10所述的模拟读取电路，其特征在于，所述多个重置采样时间位于所述传输闸导通之前且于所述重置晶体管导通之后。
  19. 一种影像传感模块，包括：
    多个像素电路，排列成阵列，每一像素电路包括传输闸、重置晶体管、选择闸及像素输出端；
    模数转换器；
    模拟读取电路，耦接于所述多个像素电路与所述模数转换器之间，所述模拟读取电路为权利要求1-18中任意一项所述的模拟读取电路。
  20. 如权利要求19所述的影像传感模块，其特征在于，所述模数转换器为全局模数转换器。
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EP3611919A1 (en) 2020-02-19
CN108064446A (zh) 2018-05-22
EP3611919A4 (en) 2020-03-25
US20200084405A1 (en) 2020-03-12

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