WO2019071759A1 - Oled面板的制作方法及oled面板 - Google Patents

Oled面板的制作方法及oled面板 Download PDF

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Publication number
WO2019071759A1
WO2019071759A1 PCT/CN2017/113673 CN2017113673W WO2019071759A1 WO 2019071759 A1 WO2019071759 A1 WO 2019071759A1 CN 2017113673 W CN2017113673 W CN 2017113673W WO 2019071759 A1 WO2019071759 A1 WO 2019071759A1
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Prior art keywords
layer
electrode
auxiliary electrode
disposed
via hole
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PCT/CN2017/113673
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English (en)
French (fr)
Inventor
唐甲
任章淳
张晓星
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/742,517 priority Critical patent/US10756292B2/en
Publication of WO2019071759A1 publication Critical patent/WO2019071759A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an OLED panel and an OLED panel.
  • OLED Organic Light Emitting Display
  • OLED has self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast ratio, near 180° viewing angle, wide temperature range, and flexible display.
  • a large-area full-color display and many other advantages have been recognized by the industry as the most promising display device.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor (TFT) matrix addressing. class.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • TFT thin film transistor
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • the OLED device generally includes a substrate, an anode disposed on the substrate, a hole injection layer disposed on the anode, a hole transport layer disposed on the hole injection layer, and a light-emitting layer disposed on the hole transport layer.
  • the principle of illumination of OLED devices is that semiconductor materials and organic luminescent materials are driven by electric fields, causing luminescence by carrier injection and recombination.
  • an OLED device generally uses an ITO pixel electrode and a metal electrode as anodes and cathodes of the device, respectively.
  • electrons and holes are injected from the cathode and the anode to the electron injection layer and the hole injection layer, respectively, and electrons and holes.
  • the holes migrate to the light-emitting layer through the electron transport layer and the hole transport layer, respectively, and meet in the light-emitting layer to form excitons and excite the light-emitting molecules, and the latter emits visible light through radiation relaxation.
  • the auxiliary electrode transmits the voltage to be applied to the cathode through the auxiliary electrode to solve the problem of uneven display caused by the IR drop of the cathode, so that the screen display of the OLED panel is uniformly stable.
  • a spacer Pillar
  • IJP inkjet printing
  • An object of the present invention is to provide a method for fabricating an OLED panel, which has an auxiliary electrode connected to a cathode, which can improve the display unevenness of the OLED panel caused by the IR drop of the cathode.
  • Another object of the present invention is to provide an OLED panel having an auxiliary electrode connected to a cathode, which can improve the display unevenness of the OLED panel caused by the IR drop of the cathode.
  • the present invention first provides a method for fabricating an OLED panel, comprising the following steps:
  • Step S1 providing a TFT substrate
  • the TFT substrate includes: a base substrate; and a TFT and an auxiliary electrode disposed on the base substrate and spaced apart; the TFT has a source;
  • Step S2 forming a flat layer on the TFT substrate and patterning, forming a first via hole and a second via hole respectively exposing the source and the auxiliary electrode on the flat layer;
  • Step S3 forming a spaced anode and a lap electrode on the flat layer
  • the anode is connected to the source via the first via, and the lap electrode is connected to the auxiliary electrode via the second via; the lap electrode is formed with a corner having a sharp shape;
  • Step S4 forming a pixel defining layer on the flat layer, the anode, and the lap electrode, the pixel defining layer is provided with a first opening exposing the anode, and the pixel defining layer is exposed with a corner formed on the lap electrode a sharply shaped area;
  • Step S5 sequentially forming a hole injection layer, a hole transport layer, and a light-emitting layer on the anode in the first opening; forming an electron transport layer and an electron injection layer on the light-emitting layer, the pixel defining layer, and the lap electrode in sequence; And cathode;
  • step S6 a voltage is applied between the auxiliary electrode and the cathode, and the electron transport layer and the electron injection layer in a region having a sharp shape corresponding to the corner are broken, and the cathode and the overlap electrode are directly connected.
  • a plurality of third via holes are formed on the lap electrode, and a sidewall of each of the third via holes forms a sharp angle with an upper surface of the lap electrode;
  • the pixel defining layer exposes a region on the lap electrode on which a plurality of third via holes are formed
  • the electron transport layer, the electron injection layer, and the cathode are also sequentially formed on the flat layer exposed by the plurality of third via holes;
  • step S6 after a voltage is applied between the auxiliary electrode and the cathode, a portion of the electron transport layer and the electron injection layer corresponding to the sharp corner between the sidewall of the third via and the upper surface of the overlap electrode is formed.
  • the plurality of second openings are formed to be removed, and the cathode is connected to the lap electrode through the second opening.
  • the TFT includes: an active layer disposed above the substrate, a gate insulating layer and a gate sequentially disposed on the active layer, an interlayer insulating layer covering the active layer and the gate, and being disposed between the layers a source and a drain on the insulating layer;
  • the auxiliary electrode includes a first sub-auxiliary electrode disposed on the interlayer insulating layer and spaced apart from the source and the drain; the second via exposing the first sub-auxiliary electrode;
  • the interlayer insulating layer is provided with a fourth via hole and a fifth via hole on both sides of the active layer, and the source and the drain pass through the fourth via hole and the fifth via hole respectively and the active layer Connected on both sides;
  • the TFT substrate further includes: a passivation layer covering the interlayer insulating layer, the source and the drain, and the first sub-auxiliary electrode; and the passivation layer is provided with the source and the first sub-auxiliary electrode respectively exposed a seventh via hole and an eighth via hole; in the step S2, the flat layer is formed on the passivation layer, and the first via hole and the second via hole are respectively located above the seventh via hole and the eighth via hole .
  • the auxiliary electrode further includes a second sub-auxiliary electrode disposed on the base substrate;
  • the TFT substrate further includes: a metal light shielding layer disposed on the base substrate and spaced apart from the second sub auxiliary electrode; and a buffer layer disposed on the base substrate and covering the metal light shielding layer and the second sub auxiliary electrode;
  • the active layer is disposed on the buffer layer and correspondingly located above the metal light shielding layer, and the interlayer insulating layer is disposed on the buffer layer and covers the active layer and the gate;
  • the buffer layer and the interlayer insulating layer are provided with a sixth via hole exposing the second sub auxiliary electrode, and the first sub auxiliary electrode is connected to the second sub auxiliary electrode via the sixth via hole.
  • the plurality of third via holes are arranged in an array, and the openings of the plurality of third via holes are rectangular, triangular, or circular.
  • the invention also provides an OLED panel comprising:
  • a TFT substrate comprising: a base substrate; and a TFT and an auxiliary electrode disposed on the base substrate and spaced apart; the TFT has a source;
  • a flat layer disposed on the TFT substrate, wherein the flat layer is provided with a first via hole and a second via hole respectively exposing the source and the auxiliary electrode;
  • a lap electrode disposed on the flat layer and spaced apart from the anode; the lap electrode is connected to the auxiliary electrode via the second via hole; the lap electrode is formed with a corner having a sharp shape;
  • a pixel defining layer disposed on the flat layer, the anode, and the lap electrode; the pixel defining layer is provided with a first opening exposing the anode, and the pixel defining layer is exposed with a corner formed on the lap electrode a sharply shaped area;
  • a hole injection layer, a hole transport layer, and a light-emitting layer disposed in sequence on the anode in the first opening;
  • An electron transport layer disposed in sequence on the light emitting layer, the pixel defining layer, and the lap electrode, The electron injecting layer and the cathode; the electron transporting layer and the electron injecting layer corresponding to the region having the sharp corner are broken, and the cathode is directly connected to the overlapping electrode.
  • a plurality of third via holes are formed on the lap electrode, and a sidewall of each of the third via holes forms a sharp angle with an upper surface of the lap electrode;
  • the pixel defining layer exposes a region of the lap electrode on which the third via is provided;
  • the electron transport layer, the electron injection layer, and the cathode are also sequentially disposed on the flat layer exposed by the plurality of third via holes;
  • a plurality of second openings are formed on the electron transport layer and the electron injection layer at a sharp angle between the sidewall of the corresponding third via and the upper surface of the lap electrode; the cathode is overlapped by the second opening Electrode connection.
  • the TFT includes: an active layer disposed above the substrate, a gate insulating layer and a gate sequentially disposed on the active layer, an interlayer insulating layer covering the active layer and the gate, and being disposed between the layers a source and a drain on the insulating layer;
  • the auxiliary electrode includes a first sub-auxiliary electrode disposed on the interlayer insulating layer and spaced apart from the source and the drain; the second via exposing the first sub-auxiliary electrode;
  • the interlayer insulating layer is provided with a fourth via hole and a fifth via hole on both sides of the active layer, and the source and the drain pass through the fourth via hole and the fifth via hole respectively and the active layer Connected on both sides;
  • the TFT substrate further includes: a passivation layer covering the interlayer insulating layer, the source and the drain, and the first sub-auxiliary electrode; and the passivation layer is provided with a surface respectively exposing the source and the first sub-auxiliary electrode.
  • the seventh via hole and the eighth via hole are disposed on the passivation layer, and the first via hole and the second via hole are respectively located above the seventh via hole and the eighth via hole.
  • the auxiliary electrode further includes a second sub-auxiliary electrode disposed on the base substrate;
  • the TFT substrate further includes: a metal light shielding layer disposed on the base substrate and spaced apart from the second sub auxiliary electrode; and a buffer layer disposed on the base substrate and covering the metal light shielding layer and the second sub auxiliary electrode;
  • the source layer is disposed on the buffer layer and correspondingly located above the metal light shielding layer, wherein the interlayer insulating layer is disposed on the buffer layer and covers the active layer and the gate;
  • the buffer layer and the interlayer insulating layer are provided with a sixth via hole exposing the second sub auxiliary electrode, and the first sub auxiliary electrode is connected to the second sub auxiliary electrode via the sixth via hole.
  • the plurality of third via holes are arranged in an array, and the openings of the plurality of third via holes are rectangular, triangular, or circular.
  • the invention also provides a method for manufacturing an OLED panel, comprising the following steps:
  • Step S1 providing a TFT substrate
  • the TFT substrate includes: a base substrate; and a TFT and an auxiliary electrode disposed on the base substrate and spaced apart; the TFT has a source;
  • Step S2 forming a flat layer on the TFT substrate and patterning, forming a first via hole and a second via hole respectively exposing the source and the auxiliary electrode on the flat layer;
  • Step S3 forming a spaced anode and a lap electrode on the flat layer
  • the anode is connected to the source via the first via, and the lap electrode is connected to the auxiliary electrode via the second via; the lap electrode is formed with a corner having a sharp shape;
  • Step S4 forming a pixel defining layer on the flat layer, the anode, and the lap electrode, the pixel defining layer is provided with a first opening exposing the anode, and the pixel defining layer is exposed with a corner formed on the lap electrode a sharply shaped area;
  • Step S5 sequentially forming a hole injection layer, a hole transport layer, and a light-emitting layer on the anode in the first opening; forming an electron transport layer and an electron injection layer on the light-emitting layer, the pixel defining layer, and the lap electrode in sequence; And cathode;
  • Step S6 applying a voltage between the auxiliary electrode and the cathode, causing the electron transport layer and the electron injection layer in a region having a sharp shape corresponding to the corner to be broken, so that the cathode and the lap electrode are directly connected;
  • the lap electrode is formed with a plurality of third via holes, and a sidewall of each of the third via holes forms a sharp angle with the upper surface of the lap electrode;
  • the pixel defining layer exposes a region on the lap electrode on which a plurality of third via holes are formed
  • the electron transport layer, the electron injection layer, and the cathode are also sequentially formed on the flat layer exposed by the plurality of third via holes;
  • step S6 after a voltage is applied between the auxiliary electrode and the cathode, a portion of the electron transport layer and the electron injection layer corresponding to the sharp corner between the sidewall of the third via and the upper surface of the overlap electrode is formed. Removing to form a plurality of second openings, the cathode being connected to the lap electrode through the second opening;
  • the TFT includes: an active layer disposed above the substrate, a gate insulating layer and a gate sequentially disposed on the active layer, an interlayer insulating layer covering the active layer and the gate, and a source and a drain on the interlayer insulating layer;
  • the auxiliary electrode includes a first sub-auxiliary electrode disposed on the interlayer insulating layer and spaced apart from the source and the drain; the second via exposing the first sub-auxiliary electrode;
  • the interlayer insulating layer is provided with a fourth via hole and a fifth via hole on both sides of the active layer, and the source and the drain pass through the fourth via hole and the fifth via hole respectively and the active layer Connected on both sides;
  • the TFT substrate further includes: a passivation layer covering the interlayer insulating layer, the source and the drain, and the first sub-auxiliary electrode; and the passivation layer is provided with the source and the first sub-auxiliary electrode respectively exposed a seventh via hole and an eighth via hole; in the step S2, the flat layer is formed on the passivation layer, and the first via hole and the second via hole are respectively located above the seventh via hole and the eighth via hole ;
  • the auxiliary electrode further includes a second sub-auxiliary electrode disposed on the base substrate;
  • the TFT substrate further includes: gold disposed on the base substrate and spaced apart from the second sub-auxiliary electrode a light shielding layer, and a buffer layer disposed on the base substrate and covering the metal light shielding layer and the second sub auxiliary electrode; the active layer is disposed on the buffer layer and correspondingly located above the metal light shielding layer, the interlayer insulating layer Provided on the buffer layer and covering the active layer and the gate;
  • the buffer layer and the interlayer insulating layer are provided with a sixth via hole exposing the second sub auxiliary electrode, and the first sub auxiliary electrode is connected to the second sub auxiliary electrode via the sixth via hole;
  • the plurality of third via holes are arranged in an array, and the openings of the plurality of third via holes are rectangular, triangular, or circular.
  • an anode connected to a source of a TFT and a lap electrode connected to the auxiliary electrode are formed on the TFT substrate, and corners are formed on the lap electrode It has a sharp shape, so that the subsequently produced electron transport layer and the electron injection layer have a thin film thickness corresponding to a region having a sharp shape at the corner, and then the corresponding corner is obtained by applying a voltage between the auxiliary electrode and the cathode.
  • the electron transport layer and the electron injection layer in the region having the sharp shape are broken, and the cathode is directly connected to the lap electrode, thereby being electrically connected to the auxiliary electrode, so that the OLED panel can input a signal to the cathode through the auxiliary electrode during display, which is effective.
  • the problem of uneven display of the OLED panel caused by the IR drop of the cathode is improved.
  • the OLED panel provided by the invention has an auxiliary electrode connected to the cathode, which can improve the problem of uneven display of the OLED panel caused by the IR drop of the cathode.
  • FIG. 1 is a flow chart of a method of fabricating an OLED panel of the present invention
  • step S1 is a schematic diagram of step S1 of the method for fabricating an OLED panel of the present invention
  • step S2 is a schematic diagram of step S2 of the method for fabricating an OLED panel of the present invention
  • step S3 is a schematic diagram of step S3 of the method for fabricating an OLED panel of the present invention.
  • FIG. 5 is a schematic plan view showing a region in which a third via is formed by a lap electrode in step S3 of the method for fabricating an OLED panel of the present invention
  • step S4 is a schematic diagram of step S4 of the method for fabricating an OLED panel of the present invention.
  • step S5 is a schematic diagram of step S5 of the method for fabricating an OLED panel of the present invention.
  • FIG. 8 is an enlarged schematic view showing a position of a third via hole after the step S5 in the method for fabricating the OLED panel of the present invention.
  • FIG. 9 is a schematic diagram of step S6 of the method for fabricating an OLED panel of the present invention and the present invention Schematic diagram of the structure of the OLED panel;
  • FIG. 10 is an enlarged schematic view showing the position of the third via hole after the step S6 of the method for fabricating the OLED panel of the present invention.
  • the present invention provides a method for fabricating an OLED panel, including the following steps:
  • Step S1 please refer to FIG. 2, providing a TFT substrate 100;
  • the TFT substrate 100 includes a base substrate 110 and a TFT 120 and an auxiliary electrode 130 which are spaced apart from each other on the base substrate 110.
  • the TFT 120 has a source 121.
  • the TFT 120 is a top gate thin film transistor, and includes an active layer 122 disposed on the substrate substrate 110, and sequentially on the active layer 122.
  • the gate insulating layer 123 and the gate electrode 124, the interlayer insulating layer 125 covering the active layer 122 and the gate electrode 124, and the source electrode 121 and the drain electrode 126 which are provided on the interlayer insulating layer 125 are provided.
  • the TFT 120 can also be a Bottom gate thin film transistor, which does not affect the implementation of the present invention.
  • the TFT 120 may be a low temperature polysilicon (LTPS) thin film transistor, an oxide semiconductor (Oxide) thin film transistor, a solid phase crystallization (SPC) thin film transistor, or other thin film transistor commonly used in OLED display technology.
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • SPC solid phase crystallization
  • the auxiliary electrode 130 includes a first sub-auxiliary electrode 131 disposed on the interlayer insulating layer 125 and spaced apart from the source 121 and the drain 126;
  • the interlayer insulating layer 125 is provided with a fourth via 1251 and a fifth via 1252 above the active layer 122.
  • the source 121 and the drain 126 pass through the fourth via 1251 and the fifth.
  • the via 1252 is connected to both sides of the active layer 122.
  • the auxiliary electrode 130 further includes a second sub-auxiliary electrode 132 disposed on the base substrate 110.
  • the TFT 120 in the embodiment shown in FIG. 2 is a top gate type thin film transistor
  • the TFT substrate 100 further includes a metal light shielding layer 140 disposed on the base substrate 110 and spaced apart from the second sub auxiliary electrode 132.
  • a buffer layer 150 disposed on the base substrate 110 and covering the metal light shielding layer 140 and the second sub auxiliary electrode 132;
  • the active layer 122 is disposed on the buffer layer 150 and correspondingly located above the metal light shielding layer 140
  • the interlayer insulating layer 125 is disposed on the buffer layer 150 and covers the active layer 122 and the gate electrode 124.
  • the buffer layer 150 and the interlayer insulating layer 125 are provided with a sixth via hole 151 exposing the second sub auxiliary electrode 132.
  • the first sub auxiliary electrode 131 passes through the sixth via 151 is connected to the second sub auxiliary electrode 132.
  • the second sub-auxiliary electrode 132 can be formed by the same mask as the metal light shielding layer 140.
  • the TFT substrate 100 further includes: a passivation layer 160 covering the interlayer insulating layer 125 , the source 121 , the drain 126 , and the first sub auxiliary electrode 131 ; the passivation layer 160
  • the seventh via hole 161 and the eighth via hole 162 which respectively expose the source electrode 121 and the first sub auxiliary electrode 131 are provided.
  • Step S2 referring to FIG. 3, a flat layer 200 is formed on the TFT substrate 100, and the flat layer 200 is patterned to form first vias 210 exposing the source electrodes 121 and the auxiliary electrodes 130, respectively. Two vias 220.
  • the flat layer 200 is formed on the passivation layer 160, and the first via hole 210 and the second via hole 220 are respectively located above the seventh via hole 161 and the eighth via hole 162.
  • the second via 220 exposes the first sub-auxiliary electrode 131.
  • Step S3 please refer to FIG. 4 and FIG. 5, forming a spaced anode 310 and a lap electrode 320 on the flat layer 200;
  • the anode 310 is connected to the source 121 via the first via 210, and the lap electrode 320 is connected to the auxiliary electrode 130 via the second via 220.
  • the lap electrode 320 is formed with a corner having a sharp shape.
  • the lap electrode 320 is formed with a plurality of third via holes 321 , and a sidewall of each of the third via holes 321 forms a sharp angle with the upper surface of the lap electrode 320 .
  • the plurality of third via holes 321 are arranged in an array so that the subsequently produced cathode can be uniformly connected with the lap electrode 320.
  • the openings of the plurality of third via holes 321 are all rectangular, and the regions in which the overlapping electrodes 320 are formed with the plurality of third via holes 321 are formed into a grid.
  • the shape of the opening of the third through hole 321 is not limited to a rectangular shape.
  • the triangular shape, the circular shape, or other shapes may be selected according to actual product requirements, and the opening shapes of the plurality of third through holes 321 may be the same or Differently, this does not affect the implementation of the present invention.
  • the anode 310 and the lap electrode 320 may be selected from the same material or different materials, and the thickness may be the same or different.
  • the anode material layer can be patterned by forming an anode material layer on the flat layer 200 to obtain the anode 310 and the lap joint.
  • the electrode 320 has a sharp shape formed on the lap electrode 320.
  • Step S4 referring to FIG. 6, forming on the flat layer 200, the anode 310, and the lap electrode 320
  • a pixel defining layer 400 is disposed on the pixel defining layer 400 with a first opening 410 exposing the anode 310, and the pixel defining layer 400 exposes a region on the lap electrode 320 formed with a corner having a sharp shape.
  • the pixel defining layer 400 exposes a region of the lap electrode 320 on which the plurality of third via holes 321 are formed.
  • the first opening 410 defines a pixel area of the OLED panel.
  • the hydrophilicity and hydrophobicity of the pixel defining layer 400 is determined according to the manner in which the OLED functional layer (hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer) is subsequently formed in the first opening 410.
  • the OLED functional layer is subsequently formed by evaporation in the first opening 410
  • the pixel defining layer 400 selects a conventional non-hydrophobic material
  • the OLED functional layer is subsequently formed by inkjet printing in the first opening 410
  • the pixel defining layer 400 selects a conventional hydrophobic material.
  • Step S5 referring to FIG. 7 and FIG. 8, a hole injection layer 510, a hole transport layer 520, and a light-emitting layer 530 are sequentially formed on the anode 310 in the first opening 410; in the light-emitting layer 530, the pixel defining layer 400, An electron transport layer 540, an electron injection layer 550, and a cathode 600 are sequentially formed on the lap electrode 320.
  • the electron transport layer 540 , the electron injection layer 550 , and the cathode 600 are sequentially formed on the flat layer 200 exposed by the plurality of third via holes 321 . .
  • the lap electrode 320 is formed with a corner having a sharp shape, specifically, a plurality of third vias 321 are formed, and the sidewalls of each of the third vias 321 are overlapped.
  • a sharp corner is formed between the upper surfaces of the electrodes 320. Therefore, after the electron transport layer 540 and the electron injection layer 550 are sequentially formed on the lap electrode 320, the electron transport layer 540 and the electron injection layer 550 have sharp shapes corresponding to the corners.
  • the region corresponding to the sharp corner between the side wall of the third via 321 and the upper surface of the lap electrode 320 is thin.
  • Step S6 referring to FIG. 9 and FIG. 10, a voltage is applied between the auxiliary electrode 130 and the cathode 600, and the electron transport layer 540 and the electron injection layer 550 having the sharp corners corresponding to the corners are broken, so that the cathode 600 is broken. Directly connected to the lap electrode 320.
  • the electron transport layer 540 and the electron injection layer 550 are disposed on the sidewall of the third via 321 and the upper surface of the lap electrode 320. A portion of the sharp corner is removed to form a plurality of second openings 541, and the cathode 600 is connected to the lap electrode 320 through the second opening 541.
  • a voltage is applied between the first auxiliary electrode 131 and the cathode 600 in the step S6.
  • the electron transport layer 540 and the electron injection layer 550 correspond to the corners
  • the region having a sharp shape, that is, the film thickness corresponding to the sharp corner between the side wall of the third via 321 and the upper surface of the lap electrode 320 is thin, and thus is applied between the auxiliary electrode 130 and the cathode 600.
  • an electric field is formed between the auxiliary electrode 130 and the lap electrode 320 and the cathode 600, and the electron transport layer 540 and the electron injection layer 550 corresponding to the region having a sharp corner are broken down, that is, the third via 321 is also correspondingly
  • the sharp corner portion between the sidewall and the upper surface of the lap electrode 320 is removed to form a plurality of second openings 541, thereby connecting the cathode 600 and the lap electrode 320, thereby connecting the cathode 600 and the lap electrode 320 and
  • the auxiliary electrode 130 is turned on, so that the obtained OLED panel can input a signal to the cathode 600 through the auxiliary electrode 130 when displayed, thereby achieving an effect of improving display unevenness of the OLED panel caused by the IR drop of the cathode 600.
  • the present invention further provides an OLED panel manufactured by using the above method for fabricating an OLED panel, comprising:
  • the TFT substrate 100 includes: a substrate substrate 110, and a TFT 120 and an auxiliary electrode 130 disposed on the substrate substrate 110; the TFT 120 has a source 121;
  • the flat layer 200 disposed on the TFT substrate 100, the flat layer 200 is provided with a first via 210 and a second via 220 respectively exposing the source 121 and the auxiliary electrode 130;
  • a lap electrode 320 disposed on the flat layer 200 and spaced apart from the anode 310; the lap electrode 320 is connected to the auxiliary electrode 130 via the second via 220; the lap electrode 320 is formed with a corner Has a sharp shape;
  • a pixel disposed on the flat layer 200, the anode 310, and the lap electrode 320 defines a layer 400;
  • the pixel defining layer 400 is provided with a first opening 410 exposing the anode 310, and the pixel defining layer 400 is exposed
  • a region having a sharp shape at a corner is formed on the electrode 320;
  • the electron injection layer 550 is broken down to directly connect the cathode 600 to the lap electrode 320.
  • the lap electrode 320 is formed with a plurality of third via holes 321 , and a sidewall of each of the third via holes 321 forms a sharp angle with the upper surface of the lap electrode 320 ;
  • the pixel defining layer 400 exposes a region of the lap electrode 320 on which the third via 321 is disposed;
  • the electron transport layer 540, the electron injection layer 550, and the cathode 600 are also sequentially disposed on the flat layer 200 exposed by the plurality of third via holes 321;
  • a plurality of second openings 541 are formed on the electron transport layer 540 and the electron injection layer 550 at a sharp angle between the sidewall of the third via 321 and the upper surface of the lap electrode 320.
  • the cathode 600 passes the The second opening 541 is connected to the lap electrode 320.
  • the openings of the plurality of third via holes 321 are all rectangular, and the regions in which the overlapping electrodes 320 are formed with the plurality of third via holes 321 are formed into a grid.
  • the shape of the opening of the third through hole 321 is not limited to a rectangular shape.
  • the triangular shape, the circular shape, or other shapes may be selected according to actual product requirements, and the opening shapes of the plurality of third through holes 321 may be the same or Differently, this does not affect the implementation of the present invention.
  • the TFT 120 is a top gate thin film transistor, and includes an active layer 122 disposed on the substrate 110 , and sequentially on the active layer 122 .
  • the gate insulating layer 123 and the gate electrode 124, the interlayer insulating layer 125 covering the active layer 122 and the gate electrode 124, and the source electrode 121 and the drain electrode 126 which are provided on the interlayer insulating layer 125 are provided.
  • the TFT 120 can also be a Bottom gate thin film transistor, which does not affect the implementation of the present invention.
  • the TFT 120 may be a low temperature polysilicon (LTPS) thin film transistor, an oxide semiconductor (Oxide) thin film transistor, a solid phase crystallization (SPC) thin film transistor, or other thin film transistor commonly used in OLED display technology.
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • SPC solid phase crystallization
  • the auxiliary electrode 130 includes a first sub-auxiliary electrode 131 disposed on the interlayer insulating layer 125 and spaced apart from the source 121 and the drain 126;
  • the interlayer insulating layer 125 is provided with a fourth via 1251 and a fifth via 1252 above the active layer 122.
  • the source 121 and the drain 126 pass through the fourth via 1251 and the fifth.
  • the via 1252 is connected to both sides of the active layer 122.
  • the auxiliary electrode 130 further includes a second sub-auxiliary electrode 132 disposed on the base substrate 110.
  • the TFT 120 in the embodiment shown in FIG. 9 is a top gate type thin film transistor
  • the TFT substrate 100 further includes a metal light shielding layer 140 disposed on the base substrate 110 and spaced apart from the second sub auxiliary electrode 132.
  • a buffer layer 150 disposed on the base substrate 110 and covering the metal light shielding layer 140 and the second sub auxiliary electrode 132.
  • the active layer 122 is disposed on the buffer layer 150 and correspondingly located above the metal light shielding layer 140.
  • the interlayer insulating layer 125 is disposed on the buffer layer 150 and covers the active layer 122 and the gate electrode 124.
  • the buffer layer 150 and the interlayer insulating layer 125 are provided with a sixth via hole 151 exposing the second sub auxiliary electrode 132.
  • the first sub auxiliary electrode 131 is connected to the second sub auxiliary electrode 132 via the sixth via 151.
  • the TFT substrate 100 further includes: a passivation layer 160 covering the interlayer insulating layer 125 , the source 121 , the drain 126 , and the first sub auxiliary electrode 131 ; the passivation layer 160
  • the seventh via hole 161 and the eighth via hole 162 which respectively expose the source electrode 121 and the first sub auxiliary electrode 131 are provided.
  • the flat layer 200 is formed on the passivation layer 160 , and the first via hole 210 and the second via hole 220 are respectively located above the seventh via hole 161 and the eighth via hole 162 .
  • the second via 220 exposes the first sub-auxiliary electrode 131.
  • the plurality of third via holes 321 are arranged in an array so that the cathode 600 can be uniformly connected to the lap electrode 320 .
  • the anode 310 and the lap electrode 320 may be selected from the same material or different materials, and the thickness may be the same or different.
  • the first opening 410 defines a pixel area of the OLED panel.
  • the hydrophilicity and hydrophobicity of the pixel defining layer 400 is determined according to the manner in which the hole injection layer 510, the hole transport layer 520, the light emitting layer 530, the electron transport layer 540, and the electron injection layer 550 are fabricated, when the hole injection layer 510 is empty.
  • the hole transport layer 520, the light-emitting layer 530, the electron transport layer 540, and the electron injection layer 550 are formed by evaporation.
  • the pixel defining layer 400 selects a conventional non-hydrophobic material, and when the hole injection layer 510, the hole transport layer 520, and the light-emitting layer Layer 530, electron transport layer 540, and electron injection layer 550 are fabricated by inkjet printing, and pixel defining layer 400 selects a conventional hydrophobic material.
  • the lap electrode 320 is formed with a corner having a sharp shape, specifically, a plurality of third via holes 321 are formed.
  • the sidewall of each of the third via holes 321 forms a sharp angle with the upper surface of the lap electrode 320. Therefore, after the electron transport layer 540 and the electron injection layer 550 are sequentially formed on the lap electrode 320, the electron transport layer is formed.
  • the electron injection layer 540 and the electron injection layer 550 have a thin film thickness in a region having a sharp shape corresponding to the corner, that is, a region corresponding to a sharp corner between the sidewall of the third via 321 and the upper surface of the lap electrode 320, and thus
  • the electron transport layer 540 and the electron injection layer 550 having a sharp shape corresponding to the corners are broken down, that is, the electron transport layer 540 and the electron injection layer 550 are removed.
  • a plurality of second openings 541 are formed in a sharp corner between the sidewall of the third via 321 and the upper surface of the lap electrode 320, thereby directly connecting the cathode 600 and the lap electrode 320, thereby making the cathode 600 and the lap
  • the electrode 320 and the auxiliary electrode 130 are turned on, When the OLED panel is displayed, a signal can be input to the cathode 600 through the auxiliary electrode 130, thereby achieving an effect of improving display unevenness of the OLED panel caused by the IR drop of the cathode 600.
  • an anode connected to a source of the TFT and a lap electrode connected to the auxiliary electrode are formed on the TFT substrate, and a corner is sharply formed on the lap electrode.
  • Shape so that the subsequent fabrication of the electron transport layer and the electron injection layer correspond
  • the region having a sharp shape at the corner has a thin film thickness, and after the voltage is applied between the auxiliary electrode and the cathode, the electron transport layer and the electron injection layer in the region having the sharp corner corresponding to the corner are broken.
  • the cathode is directly connected to the lap electrode, and is further electrically connected to the auxiliary electrode, so that the OLED panel can input a signal to the cathode through the auxiliary electrode during display, thereby effectively improving the display unevenness of the OLED panel caused by the IR drop of the cathode.
  • the OLED panel of the present invention has an auxiliary electrode connected to the cathode, which can improve the problem of uneven display of the OLED panel caused by the IR drop of the cathode.

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Abstract

本发明提供一种OLED面板的制作方法及OLED面板。本发明的OLED面板的制作方法，在TFT基板上制作与TFT的源极连接的阳极、及与辅助电极连接的搭接电极，并在搭接电极上形成有边角具有尖锐的形状，使得后续制作的电子传输层及电子注入层对应该边角具有尖锐的形状的区域具有较薄的膜厚，进而通过向辅助电极与阴极之间施加电压后，使对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使阴极与搭接电极直接连接，进而与辅助电极导通，使OLED面板在显示时能够通过辅助电极向阴极输入信号，有效地改善了由阴极的IR压降导致的OLED面板显示不均的问题。

Description

OLED面板的制作方法及OLED面板 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED面板的制作方法及OLED面板。
背景技术
有机发光二极管显示装置(Organic Light Emitting Display，OLED)具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管(TFT)矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
OLED器件通常包括：基板、设于基板上的阳极、设于阳极上的空穴注入层、设于空穴注入层上的空穴传输层、设于空穴传输层上的发光层、设于发光层上的电子传输层、设于电子传输层上的电子注入层、及设于电子注入层上的阴极。OLED器件的发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致发光。具体的，OLED器件通常采用ITO像素电极和金属电极分别作为器件的阳极和阴极，在一定电压驱动下，电子和空穴分别从阴极和阳极注入到电子注入层和空穴注入层，电子和空穴分别经过电子传输层和空穴传输层迁移到发光层，并在发光层中相遇，形成激子并使发光分子激发，后者经过辐射弛豫而发出可见光。
大尺寸的OLED面板在工作时会因为其阴极具有较大的电阻而在其不同位置产生不同的IR压降(IR Drop)，导致OLED面板的亮度不均，因此，需要额外制作与阴极连接的辅助电极，通过辅助电极传输应施加在阴极上的电压，解决阴极的IR压降导致的显示不均的问题，使OLED面板的画面显示均一稳定。现有技术中一般会在OLED面板上制作纵剖面呈倒梯形的隔离柱(Pillar)来实现辅助电极与阴极的连接，隔离柱的原材料的选择性较少，会增加OLED面板的成本并使OLED面板的制作工艺变得复杂，尤其是针对喷墨打印(IJP)方式制作的OLED面板，制作隔离柱的工艺实现 更加困难。
发明内容
本发明的目的在于提供一种OLED面板的制作方法，制得的OLED面板具有与阴极连接的辅助电极，能够改善由阴极的IR压降导致的OLED面板显示不均的问题。
本发明的另一目的在于提供一种OLED面板，具有与阴极连接的辅助电极，能够改善由阴极的IR压降导致的OLED面板显示不均的问题。
为实现上述目的，本发明首先提供一种OLED面板的制作方法，包括如下步骤：
步骤S1、提供TFT基板；
所述TFT基板包括：衬底基板、及设于衬底基板上且间隔的TFT及辅助电极；所述TFT具有源极；
步骤S2、在TFT基板上形成平坦层并进行图案化，在平坦层上形成分别暴露所述源极、及辅助电极的第一过孔、及第二过孔；
步骤S3、在平坦层上形成间隔的阳极、及搭接电极；
所述阳极经第一过孔与源极连接，所述搭接电极经第二过孔与辅助电极连接；所述搭接电极上形成有边角具有尖锐的形状；
步骤S4、在平坦层、阳极、及搭接电极上形成像素界定层，所述像素界定层上设有暴露阳极的第一开口，且所述像素界定层暴露搭接电极上形成有边角具有尖锐的形状的区域；
步骤S5、于第一开口内的阳极上依次形成空穴注入层、空穴传输层、及发光层；在发光层、像素界定层、及搭接电极上依次形成电子传输层、电子注入层、及阴极；
步骤S6、向辅助电极与阴极之间施加电压，使对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使阴极与搭接电极直接连接。
所述搭接电极上形成有多个第三过孔，每一第三过孔的侧壁均与搭接电极的上表面之间形成尖角；
所述像素界定层暴露搭接电极上形成有多个第三过孔的区域；
所述步骤S5中，所述电子传输层、电子注入层、及阴极还依次形成在多个第三过孔暴露出的平坦层上；
所述步骤S6中，向辅助电极与阴极之间施加电压后，使电子传输层及电子注入层上对应所述第三过孔的侧壁与搭接电极的上表面之间的尖角的部分被去除而形成多个第二开口，阴极通过第二开口与搭接电极连接。
所述TFT包括：设于衬底基板上方的有源层、于有源层上依次设置的栅极绝缘层及栅极、覆盖有源层及栅极的层间绝缘层、及设于层间绝缘层上且间隔的源极及漏极；
所述辅助电极包括设于层间绝缘层上且与源极、及漏极均间隔的第一子辅助电极；所述第二过孔暴露出所述第一子辅助电极；
所述层间绝缘层上设有位于有源层两侧上方的第四过孔及第五过孔，所述源极及漏极分别通过第四过孔及第五过孔与有源层的两侧连接；
所述TFT基板还包括：覆盖层间绝缘层、源极、漏极、及第一子辅助电极的钝化层；所述钝化层上设有分别暴露出源极及第一子辅助电极的第七过孔及第八过孔；所述步骤S2中，所述平坦层形成于钝化层上，所述第一过孔及第二过孔分别位于第七过孔及第八过孔上方。
所述辅助电极还包括设于衬底基板上的第二子辅助电极；
所述TFT基板还包括：设于衬底基板上且与第二子辅助电极间隔的金属遮光层、及设于衬底基板上且覆盖金属遮光层及第二子辅助电极的缓冲层；所述有源层设于缓冲层上且对应位于金属遮光层上方，所述层间绝缘层设于缓冲层上且覆盖有源层及栅极；
所述缓冲层及层间绝缘层上设有暴露第二子辅助电极的第六过孔，所述第一子辅助电极经所述第六过孔与第二子辅助电极连接。
所述多个第三过孔呈阵列式排布，所述多个第三过孔的开口形状为矩形、三角形、或圆形。
本发明还提供一种OLED面板，包括：
TFT基板；所述TFT基板包括：衬底基板、及设于衬底基板上且间隔的TFT及辅助电极；所述TFT具有源极；
设于所述TFT基板上的平坦层，所述平坦层上设有分别暴露所述源极及辅助电极的第一过孔、及第二过孔；
设于所述平坦层上的阳极；所述阳极经第一过孔与源极连接；
设于所述平坦层上且与所述阳极间隔的搭接电极；所述搭接电极经第二过孔与辅助电极连接；所述搭接电极上形成有边角具有尖锐的形状；
设于所述平坦层、阳极、及搭接电极上的像素界定层；所述像素界定层上设有暴露阳极的第一开口，且所述像素界定层暴露搭接电极上形成有边角具有尖锐的形状的区域；
于所述第一开口内的阳极上依次设置的空穴注入层、空穴传输层、及发光层；
于所述发光层、像素界定层、及搭接电极上依次设置的电子传输层、 电子注入层、及阴极；对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使所述阴极与搭接电极直接连接。
所述搭接电极上形成有多个第三过孔，每一第三过孔的侧壁均与搭接电极的上表面之间形成尖角；
所述像素界定层暴露搭接电极上设有第三过孔的区域；
所述电子传输层、电子注入层、及阴极还依次设于多个第三过孔暴露出的平坦层上；
所述电子传输层及电子注入层上对应第三过孔的侧壁与搭接电极的上表面之间的尖角设有多个第二开口；所述阴极通过所述第二开口与搭接电极连接。
所述TFT包括：设于衬底基板上方的有源层、于有源层上依次设置的栅极绝缘层及栅极、覆盖有源层及栅极的层间绝缘层、及设于层间绝缘层上且间隔的源极及漏极；
所述辅助电极包括设于层间绝缘层上且与源极、及漏极均间隔的第一子辅助电极；所述第二过孔暴露出所述第一子辅助电极；
所述层间绝缘层上设有位于有源层两侧上方的第四过孔及第五过孔，所述源极及漏极分别通过第四过孔及第五过孔与有源层的两侧连接；
所述TFT基板还包括：覆盖层间绝缘层、源极、漏极、第一子辅助电极的钝化层；所述钝化层上设有分别暴露出源极及第一子辅助电极的第七过孔及第八过孔；所述平坦层设于钝化层上，所述第一过孔及第二过孔分别位于第七过孔及第八过孔上方。
所述辅助电极还包括设于衬底基板上的第二子辅助电极；
所述TFT基板还包括：设于衬底基板上且与第二子辅助电极间隔的金属遮光层、及设于衬底基板上覆盖金属遮光层及第二子辅助电极的缓冲层；所述有源层设于缓冲层上且对应位于金属遮光层上方，所述层间绝缘层设于缓冲层上且覆盖有源层及栅极；
所述缓冲层及层间绝缘层上设有暴露第二子辅助电极的第六过孔，所述第一子辅助电极经所述第六过孔与第二子辅助电极连接。
所述多个第三过孔呈阵列式排布，所述多个第三过孔的开口形状为矩形、三角形、或圆形。
本发明还提供一种OLED面板的制作方法，包括如下步骤：
步骤S1、提供TFT基板；
所述TFT基板包括：衬底基板、及设于衬底基板上且间隔的TFT及辅助电极；所述TFT具有源极；
步骤S2、在TFT基板上形成平坦层并进行图案化，在平坦层上形成分别暴露所述源极、及辅助电极的第一过孔、及第二过孔；
步骤S3、在平坦层上形成间隔的阳极、及搭接电极；
所述阳极经第一过孔与源极连接，所述搭接电极经第二过孔与辅助电极连接；所述搭接电极上形成有边角具有尖锐的形状；
步骤S4、在平坦层、阳极、及搭接电极上形成像素界定层，所述像素界定层上设有暴露阳极的第一开口，且所述像素界定层暴露搭接电极上形成有边角具有尖锐的形状的区域；
步骤S5、于第一开口内的阳极上依次形成空穴注入层、空穴传输层、及发光层；在发光层、像素界定层、及搭接电极上依次形成电子传输层、电子注入层、及阴极；
步骤S6、向辅助电极与阴极之间施加电压，使对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使阴极与搭接电极直接连接；
其中，所述搭接电极上形成有多个第三过孔，每一第三过孔的侧壁均与搭接电极的上表面之间形成尖角；
所述像素界定层暴露搭接电极上形成有多个第三过孔的区域；
所述步骤S5中，所述电子传输层、电子注入层、及阴极还依次形成在多个第三过孔暴露出的平坦层上；
所述步骤S6中，向辅助电极与阴极之间施加电压后，使电子传输层及电子注入层上对应所述第三过孔的侧壁与搭接电极的上表面之间的尖角的部分被去除而形成多个第二开口，阴极通过第二开口与搭接电极连接；
其中，所述TFT包括：设于衬底基板上方的有源层、于有源层上依次设置的栅极绝缘层及栅极、覆盖有源层及栅极的层间绝缘层、及设于层间绝缘层上且间隔的源极及漏极；
所述辅助电极包括设于层间绝缘层上且与源极、及漏极均间隔的第一子辅助电极；所述第二过孔暴露出所述第一子辅助电极；
所述层间绝缘层上设有位于有源层两侧上方的第四过孔及第五过孔，所述源极及漏极分别通过第四过孔及第五过孔与有源层的两侧连接；
所述TFT基板还包括：覆盖层间绝缘层、源极、漏极、及第一子辅助电极的钝化层；所述钝化层上设有分别暴露出源极及第一子辅助电极的第七过孔及第八过孔；所述步骤S2中，所述平坦层形成于钝化层上，所述第一过孔及第二过孔分别位于第七过孔及第八过孔上方；
其中，所述辅助电极还包括设于衬底基板上的第二子辅助电极；
所述TFT基板还包括：设于衬底基板上且与第二子辅助电极间隔的金 属遮光层、及设于衬底基板上且覆盖金属遮光层及第二子辅助电极的缓冲层；所述有源层设于缓冲层上且对应位于金属遮光层上方，所述层间绝缘层设于缓冲层上且覆盖有源层及栅极；
所述缓冲层及层间绝缘层上设有暴露第二子辅助电极的第六过孔，所述第一子辅助电极经所述第六过孔与第二子辅助电极连接；
其中，所述多个第三过孔呈阵列式排布，所述多个第三过孔的开口形状为矩形、三角形、或圆形。
本发明的有益效果：本发明提供的OLED面板的制作方法，在TFT基板上制作与TFT的源极连接的阳极、及与辅助电极连接的搭接电极，并在搭接电极上形成有边角具有尖锐的形状，使得后续制作的电子传输层及电子注入层对应该边角具有尖锐的形状的区域具有较薄的膜厚，进而通过向辅助电极与阴极之间施加电压后，使对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使阴极与搭接电极直接连接，进而与辅助电极导通，使OLED面板在显示时能够通过辅助电极向阴极输入信号，有效地改善了由阴极的IR压降导致的OLED面板显示不均的问题。本发明提供的OLED面板，具有与阴极连接的辅助电极，能够改善由阴极的IR压降导致的OLED面板显示不均的问题。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的OLED面板的制作方法的流程图；
图2为本发明的OLED面板的制作方法的步骤S1的示意图；
图3为本发明的OLED面板的制作方法的步骤S2的示意图；
图4为本发明的OLED面板的制作方法的步骤S3的示意图；
图5为本发明的OLED面板的制作方法的步骤S3中搭接电极形成有第三过孔的区域的俯视示意图；
图6为本发明的OLED面板的制作方法的步骤S4的示意图；
图7为本发明的OLED面板的制作方法的步骤S5的示意图；
图8为本发明的OLED面板的制作方法在步骤S5后第三过孔所在位置的放大示意图；
图9为本发明的OLED面板的制作方法的步骤S6的示意图暨本发明的 OLED面板的结构示意图；
图10为本发明的OLED面板的制作方法在步骤S6后第三过孔所在位置的放大示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种OLED面板的制作方法，包括如下步骤：
步骤S1、请参阅图2，提供TFT基板100；
所述TFT基板100包括：衬底基板110、及设于衬底基板110上且间隔的TFT120及辅助电极130；所述TFT120具有源极121。
具体地，在图2所示的实施例中，所述TFT120为顶栅型(Top gate)的薄膜晶体管，包括：设于衬底基板110上方的有源层122、于有源层122上依次设置的栅极绝缘层123及栅极124、覆盖有源层122及栅极124的层间绝缘层125、及设于层间绝缘层125上且间隔的源极121及漏极126。当然，所述TFT120也可为底栅型(Bottom gate)的薄膜晶体管，这并不会影响本发明的实现。
具体地，所述TFT120可为低温多晶硅(LTPS)薄膜晶体管、氧化物半导体(Oxide)薄膜晶体管、固相晶化(SPC)薄膜晶体管、或其他常用于OLED显示技术中的薄膜晶体管。
具体地，请参阅图2，所述辅助电极130包括设于层间绝缘层125上且与源极121、及漏极126均间隔的第一子辅助电极131；
所述层间绝缘层125上设有位于有源层122两侧上方的第四过孔1251及第五过孔1252，所述源极121及漏极126分别通过第四过孔1251及第五过孔1252与有源层122的两侧连接。
具体地，所述辅助电极130还包括设于衬底基板110上的第二子辅助电极132。
具体地，针对图2所示的实施例中的TFT120为顶栅型薄膜晶体管，所述TFT基板100还包括：设于衬底基板110上且与第二子辅助电极132间隔的金属遮光层140、及设于衬底基板110上且覆盖金属遮光层140及第二子辅助电极132的缓冲层150；所述有源层122设于缓冲层150上且对应位于金属遮光层140上方，所述层间绝缘层125设于缓冲层150上且覆盖有源层122及栅极124；所述缓冲层150及层间绝缘层125上设有暴露第二子辅助电极132的第六过孔151，所述第一子辅助电极131经所述第六过孔 151与第二子辅助电极132连接。
进一步地，该第二子辅助电极132可与金属遮光层140通过同一道光罩形成。
具体地，请参阅图2，所述TFT基板100还包括：覆盖层间绝缘层125、源极121、漏极126、及第一子辅助电极131的钝化层160；所述钝化层160上设有分别暴露出源极121及第一子辅助电极131的第七过孔161及第八过孔162。
步骤S2、请参阅图3，在TFT基板100上形成平坦层200，对所述平坦层200进行图案化，形成分别暴露所述源极121、及辅助电极130的第一过孔210、及第二过孔220。
具体地，请参阅图3，所述平坦层200形成于钝化层160上，所述第一过孔210及第二过孔220分别位于第七过孔161及第八过孔162上方，所述第二过孔220暴露出所述第一子辅助电极131。
步骤S3、请参阅图4及图5，在平坦层200上形成间隔的阳极310、及搭接电极320；
所述阳极310经第一过孔210与源极121连接，所述搭接电极320经第二过孔220与辅助电极130连接；所述搭接电极320上形成有边角具有尖锐的形状。
具体地，请参阅图5，所述搭接电极320上形成有多个第三过孔321，每一第三过孔321的侧壁均与搭接电极320的上表面之间形成尖角。
优选地，请参阅图5，所述多个第三过孔321呈阵列式排布，以便于后续制得的阴极能够与搭接电极320均匀连接。
具体地，在图5所示的实施例中，所述多个第三过孔321的开口形状均为矩形，对应地使搭接电极320形成有多个第三过孔321的区域形成网格状结构，当然，所述第三过孔321的开口形状并不限于矩形，也可以根据实际产品需求选择三角形、圆形、或其他形状，同时多个第三过孔321的开口形状可以相同或不同，这并不会影响本发明的实现。
具体地，所述阳极310与搭接电极320可选择相同材料或不同材料，厚度可相同也可不同。
进一步地，当所述阳极310与搭接电极320采用相同的材料，且厚度相同时，可通过在平坦层200上形成一阳极材料层，对阳极材料层进行图案化而得到阳极310及搭接电极320，并在搭接电极320上形成边角具有尖锐的形状。
步骤S4、请参阅图6，在平坦层200、阳极310、及搭接电极320上形 成像素界定层400，所述像素界定层400上设有暴露阳极310的第一开口410，且所述像素界定层400暴露搭接电极320上形成有边角具有尖锐的形状的区域。
具体地，所述像素界定层400暴露搭接电极320上形成有多个第三过孔321的区域。
具体地，所述第一开口410限定出OLED面板的像素区域。
具体地，所述像素界定层400的亲疏水性根据后续在第一开口410中制作OLED功能层(空穴注入层、空穴传输层、发光层、电子传输层、电子注入层)的方式做决定，当后续在第一开口410中采用蒸镀方式制作OLED功能层，则像素界定层400选择常规的非疏水性材料，当后续在第一开口410中采用喷墨打印的方式制作OLED功能层，则像素界定层400选择常规的疏水性材料。
步骤S5、请参阅图7及图8，于第一开口410内的阳极310上依次形成空穴注入层510、空穴传输层520、及发光层530；在发光层530、像素界定层400、及搭接电极320上依次形成电子传输层540、电子注入层550、及阴极600。
具体地，请参阅图7及图8，所述步骤S5中，所述电子传输层540、电子注入层550、及阴极600还依次形成在多个第三过孔321暴露出的平坦层200上。
具体地，请参阅图8，由于搭接电极320上形成有边角具有尖锐的形状，具体为形成有多个第三过孔321，且每一第三过孔321的侧壁均与搭接电极320的上表面之间形成尖角，因此在搭接电极320上依次形成电子传输层540及电子注入层550后，该电子传输层540及电子注入层550在对应该边角具有尖锐的形状的区域也即对应第三过孔321的侧壁与搭接电极320的上表面之间的尖角的区域的膜厚较薄。
步骤S6、请参阅图9及图10，向辅助电极130与阴极600之间施加电压，使对应边角具有尖锐的形状的区域的电子传输层540及电子注入层550被击穿，使阴极600与搭接电极320直接连接。
具体地，所述步骤S6中，向辅助电极130与阴极600之间施加电压后，使电子传输层540及电子注入层550上对应第三过孔321的侧壁与搭接电极320的上表面之间的尖角的部分被去除而形成多个第二开口541，阴极600通过第二开口541与搭接电极320连接。
优选地，所述步骤S6中向第一辅助电极131与阴极600之间施加电压。
需要说明的是，由于电子传输层540及电子注入层550在对应该边角 具有尖锐的形状的区域也即对应第三过孔321的侧壁与搭接电极320的上表面之间的尖角的区域的膜厚较薄，因此在向辅助电极130与阴极600之间施加电压后，辅助电极130及搭接电极320与阴极600之间形成电场，将对应边角具有尖锐的形状的区域的电子传输层540及电子注入层550击穿，也即将对应第三过孔321的侧壁与搭接电极320的上表面之间的尖角的部分被去除而形成多个第二开口541，从而使阴极600和搭接电极320连接，进而使阴极600与搭接电极320及辅助电极130导通，使得到的OLED面板在显示时能够通过辅助电极130向阴极600输入信号，实现改善由阴极600的IR压降导致的OLED面板显示不均的效果。
请参阅图9及图10，并结合图5，基于同一发明构思，本发明还提供一种采用上述的OLED面板的制作方法制作的OLED面板，包括：
TFT基板100；所述TFT基板100包括：衬底基板110、及设于衬底基板110上且间隔的TFT120及辅助电极130；所述TFT120具有源极121；
设于所述TFT基板100上的平坦层200，所述平坦层200上设有分别暴露所述源极121及辅助电极130的第一过孔210、及第二过孔220；
设于所述平坦层200上的阳极310；所述阳极310经第一过孔210与源极121连接；
设于所述平坦层200上且与所述阳极310间隔的搭接电极320；所述搭接电极320经第二过孔220与辅助电极130连接；所述搭接电极320上形成有边角具有尖锐的形状；
设于所述平坦层200、阳极310、及搭接电极320上的像素界定层400；所述像素界定层400上设有暴露阳极310的第一开口410，且所述像素界定层400暴露搭接电极320上形成有边角具有尖锐的形状的区域；
于所述第一开口410内的阳极310上依次设置的空穴注入层510、空穴传输层520、及发光层530；
于所述发光层530、像素界定层400、及搭接电极320上依次设置的电子传输层540、电子注入层550、及阴极600；对应边角具有尖锐的形状的区域的电子传输层540及电子注入层550被击穿，使所述阴极600与搭接电极320直接连接。
具体地，所述搭接电极320上形成有多个第三过孔321，每一第三过孔321的侧壁均与搭接电极320的上表面之间形成尖角；
所述像素界定层400暴露搭接电极320上设有第三过孔321的区域；
所述电子传输层540、电子注入层550、及阴极600还依次设于多个第三过孔321暴露出的平坦层200上；
所述电子传输层540及电子注入层550上对应第三过孔321的侧壁与搭接电极320的上表面之间的尖角设有多个第二开口541；所述阴极600通过所述第二开口541与搭接电极320连接。
具体地，在图5所示的实施例中，所述多个第三过孔321的开口形状均为矩形，对应地使搭接电极320形成有多个第三过孔321的区域形成网格状结构，当然，所述第三过孔321的开口形状并不限于矩形，也可以根据实际产品需求选择三角形、圆形、或其他形状，同时多个第三过孔321的开口形状可以相同或不同，这并不会影响本发明的实现。
具体地，在图9所示的实施例中，所述TFT120为顶栅型(Top gate)的薄膜晶体管，包括：设于衬底基板110上方的有源层122、于有源层122上依次设置的栅极绝缘层123及栅极124、覆盖有源层122及栅极124的层间绝缘层125、及设于层间绝缘层125上且间隔的源极121及漏极126。当然，所述TFT120也可为底栅型(Bottom gate)的薄膜晶体管，这并不会影响本发明的实现。
具体地，所述TFT120可为低温多晶硅(LTPS)薄膜晶体管、氧化物半导体(Oxide)薄膜晶体管、固相晶化(SPC)薄膜晶体管、或其他常用于OLED显示技术中的薄膜晶体管。
具体地，请参阅图9，所述辅助电极130包括设于层间绝缘层125上且与源极121、及漏极126均间隔的第一子辅助电极131；
所述层间绝缘层125上设有位于有源层122两侧上方的第四过孔1251及第五过孔1252，所述源极121及漏极126分别通过第四过孔1251及第五过孔1252与有源层122的两侧连接。
具体地，所述辅助电极130还包括设于衬底基板110上的第二子辅助电极132。
具体地，针对图9所示的实施例中的TFT120为顶栅型薄膜晶体管，所述TFT基板100还包括：设于衬底基板110上且与第二子辅助电极132间隔的金属遮光层140、及设于衬底基板110上覆盖金属遮光层140及第二子辅助电极132的缓冲层150；所述有源层122设于缓冲层150上且对应位于金属遮光层140上方，所述层间绝缘层125设于缓冲层150上且覆盖有源层122及栅极124；所述缓冲层150及层间绝缘层125上设有暴露第二子辅助电极132的第六过孔151，所述第一子辅助电极131经所述第六过孔151与第二子辅助电极132连接。
具体地，请参阅图9，所述TFT基板100还包括：覆盖层间绝缘层125、源极121、漏极126、及第一子辅助电极131的钝化层160；所述钝化层160 上设有分别暴露出源极121及第一子辅助电极131的第七过孔161及第八过孔162。
具体地，请参阅图9，所述平坦层200形成于钝化层160上，所述第一过孔210及第二过孔220分别位于第七过孔161及第八过孔162上方，所述第二过孔220暴露出所述第一子辅助电极131。
具体地，请参阅图5，所述多个第三过孔321呈阵列式排布，以便于阴极600能够与搭接电极320均匀连接。
具体地，所述阳极310与搭接电极320可选择相同材料或不同材料，厚度可相同也可不同。
具体地，所述第一开口410限定出OLED面板的像素区域。
具体地，所述像素界定层400的亲疏水性根据空穴注入层510、空穴传输层520、发光层530、电子传输层540、电子注入层550的制作方式决定，当空穴注入层510、空穴传输层520、发光层530、电子传输层540、电子注入层550采用蒸镀方式制作，则像素界定层400选择常规的非疏水性材料，当空穴注入层510、空穴传输层520、发光层530、电子传输层540、电子注入层550采用喷墨打印的方式制作，则像素界定层400选择常规的疏水性材料。
需要说明的是，请参阅图9及图10，并同时参考图8，本发明中，由于搭接电极320上形成有边角具有尖锐的形状，具体为形成有多个第三过孔321，且每一第三过孔321的侧壁均与搭接电极320的上表面之间形成尖角，因此在搭接电极320上依次形成电子传输层540及电子注入层550后，该电子传输层540及电子注入层550在对应该边角具有尖锐的形状的区域也即对应第三过孔321的侧壁与搭接电极320的上表面之间的尖角的区域的膜厚较薄，因此可通过向辅助电极130与阴极600之间施加电压，将对应边角具有尖锐的形状的区域的电子传输层540及电子注入层550击穿，也即去除电子传输层540及电子注入层550对应第三过孔321的侧壁与搭接电极320的上表面之间的尖角的部分而形成多个第二开口541，从而使阴极600和搭接电极320直接连接，进而使阴极600与搭接电极320及辅助电极130导通，使该OLED面板在显示时能够通过辅助电极130向阴极600输入信号，实现改善由阴极600的IR压降导致的OLED面板显示不均的效果。
综上所述，本发明的OLED面板的制作方法，在TFT基板上制作与TFT的源极连接的阳极、及与辅助电极连接的搭接电极，并在搭接电极上形成有边角具有尖锐的形状，使得后续制作的电子传输层及电子注入层对应该 边角具有尖锐的形状的区域具有较薄的膜厚，进而通过向辅助电极与阴极之间施加电压后，使对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使阴极与搭接电极直接连接，进而与辅助电极导通，使OLED面板在显示时能够通过辅助电极向阴极输入信号，有效地改善了由阴极的IR压降导致的OLED面板显示不均的问题。本发明的OLED面板，具有与阴极连接的辅助电极，能够改善由阴极的IR压降导致的OLED面板显示不均的问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种OLED面板的制作方法，包括如下步骤：
    步骤S1、提供TFT基板；
    所述TFT基板包括：衬底基板、及设于衬底基板上且间隔的TFT及辅助电极；所述TFT具有源极；
    步骤S2、在TFT基板上形成平坦层并进行图案化，在平坦层上形成分别暴露所述源极、及辅助电极的第一过孔、及第二过孔；
    步骤S3、在平坦层上形成间隔的阳极、及搭接电极；
    所述阳极经第一过孔与源极连接，所述搭接电极经第二过孔与辅助电极连接；所述搭接电极上形成有边角具有尖锐的形状；
    步骤S4、在平坦层、阳极、及搭接电极上形成像素界定层，所述像素界定层上设有暴露阳极的第一开口，且所述像素界定层暴露搭接电极上形成有边角具有尖锐的形状的区域；
    步骤S5、于第一开口内的阳极上依次形成空穴注入层、空穴传输层、及发光层；在发光层、像素界定层、及搭接电极上依次形成电子传输层、电子注入层、及阴极；
    步骤S6、向辅助电极与阴极之间施加电压，使对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使阴极与搭接电极直接连接。
  2. 如权利要求1所述的OLED面板的制作方法，其中，所述搭接电极上形成有多个第三过孔，每一第三过孔的侧壁均与搭接电极的上表面之间形成尖角；
    所述像素界定层暴露搭接电极上形成有多个第三过孔的区域；
    所述步骤S5中，所述电子传输层、电子注入层、及阴极还依次形成在多个第三过孔暴露出的平坦层上；
    所述步骤S6中，向辅助电极与阴极之间施加电压后，使电子传输层及电子注入层上对应所述第三过孔的侧壁与搭接电极的上表面之间的尖角的部分被去除而形成多个第二开口，阴极通过第二开口与搭接电极连接。
  3. 如权利要求1所述的OLED面板的制作方法，其中，所述TFT包括：设于衬底基板上方的有源层、于有源层上依次设置的栅极绝缘层及栅极、覆盖有源层及栅极的层间绝缘层、及设于层间绝缘层上且间隔的源极及漏极；
    所述辅助电极包括设于层间绝缘层上且与源极、及漏极均间隔的第一 子辅助电极；所述第二过孔暴露出所述第一子辅助电极；
    所述层间绝缘层上设有位于有源层两侧上方的第四过孔及第五过孔，所述源极及漏极分别通过第四过孔及第五过孔与有源层的两侧连接；
    所述TFT基板还包括：覆盖层间绝缘层、源极、漏极、及第一子辅助电极的钝化层；所述钝化层上设有分别暴露出源极及第一子辅助电极的第七过孔及第八过孔；所述步骤S2中，所述平坦层形成于钝化层上，所述第一过孔及第二过孔分别位于第七过孔及第八过孔上方。
  4. 如权利要求3所述的OLED面板的制作方法，其中，所述辅助电极还包括设于衬底基板上的第二子辅助电极；
    所述TFT基板还包括：设于衬底基板上且与第二子辅助电极间隔的金属遮光层、及设于衬底基板上且覆盖金属遮光层及第二子辅助电极的缓冲层；所述有源层设于缓冲层上且对应位于金属遮光层上方，所述层间绝缘层设于缓冲层上且覆盖有源层及栅极；
    所述缓冲层及层间绝缘层上设有暴露第二子辅助电极的第六过孔，所述第一子辅助电极经所述第六过孔与第二子辅助电极连接。
  5. 如权利要求2所述的OLED面板的制作方法，其中，所述多个第三过孔呈阵列式排布，所述多个第三过孔的开口形状为矩形、三角形、或圆形。
  6. 一种OLED面板，包括：
    TFT基板；所述TFT基板包括：衬底基板、及设于衬底基板上且间隔的TFT及辅助电极；所述TFT具有源极；
    设于所述TFT基板上的平坦层，所述平坦层上设有分别暴露所述源极及辅助电极的第一过孔、及第二过孔；
    设于所述平坦层上的阳极；所述阳极经第一过孔与源极连接；
    设于所述平坦层上且与所述阳极间隔的搭接电极；所述搭接电极经第二过孔与辅助电极连接；所述搭接电极上形成有边角具有尖锐的形状；
    设于所述平坦层、阳极、及搭接电极上的像素界定层；所述像素界定层上设有暴露阳极的第一开口，且所述像素界定层暴露搭接电极上形成有边角具有尖锐的形状的区域；
    于所述第一开口内的阳极上依次设置的空穴注入层、空穴传输层、及发光层；
    于所述发光层、像素界定层、及搭接电极上依次设置的电子传输层、电子注入层、及阴极；对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使所述阴极与搭接电极直接连接。
  7. 如权利要求6所述的OLED面板，其中，所述搭接电极上形成有多个第三过孔，每一第三过孔的侧壁均与搭接电极的上表面之间形成尖角；
    所述像素界定层暴露搭接电极上设有第三过孔的区域；
    所述电子传输层、电子注入层、及阴极还依次设于多个第三过孔暴露出的平坦层上；
    所述电子传输层及电子注入层上对应第三过孔的侧壁与搭接电极的上表面之间的尖角设有多个第二开口；所述阴极通过所述第二开口与搭接电极连接。
  8. 如权利要求6所述的OLED面板，其中，所述TFT包括：设于衬底基板上方的有源层、于有源层上依次设置的栅极绝缘层及栅极、覆盖有源层及栅极的层间绝缘层、及设于层间绝缘层上且间隔的源极及漏极；
    所述辅助电极包括设于层间绝缘层上且与源极、及漏极均间隔的第一子辅助电极；所述第二过孔暴露出所述第一子辅助电极；
    所述层间绝缘层上设有位于有源层两侧上方的第四过孔及第五过孔，所述源极及漏极分别通过第四过孔及第五过孔与有源层的两侧连接；
    所述TFT基板还包括：覆盖层间绝缘层、源极、漏极、第一子辅助电极的钝化层；所述钝化层上设有分别暴露出源极及第一子辅助电极的第七过孔及第八过孔；所述平坦层设于钝化层上，所述第一过孔及第二过孔分别位于第七过孔及第八过孔上方。
  9. 如权利要求8所述的OLED面板，其中，所述辅助电极还包括设于衬底基板上的第二子辅助电极；
    所述TFT基板还包括：设于衬底基板上且与第二子辅助电极间隔的金属遮光层、及设于衬底基板上覆盖金属遮光层及第二子辅助电极的缓冲层；所述有源层设于缓冲层上且对应位于金属遮光层上方，所述层间绝缘层设于缓冲层上且覆盖有源层及栅极；
    所述缓冲层及层间绝缘层上设有暴露第二子辅助电极的第六过孔，所述第一子辅助电极经所述第六过孔与第二子辅助电极连接。
  10. 如权利要求7所述的OLED面板，其中，所述多个第三过孔呈阵列式排布，所述多个第三过孔的开口形状为矩形、三角形、或圆形。
  11. 一种OLED面板的制作方法，包括如下步骤：
    步骤S1、提供TFT基板；
    所述TFT基板包括：衬底基板、及设于衬底基板上且间隔的TFT及辅助电极；所述TFT具有源极；
    步骤S2、在TFT基板上形成平坦层并进行图案化，在平坦层上形成分 别暴露所述源极、及辅助电极的第一过孔、及第二过孔；
    步骤S3、在平坦层上形成间隔的阳极、及搭接电极；
    所述阳极经第一过孔与源极连接，所述搭接电极经第二过孔与辅助电极连接；所述搭接电极上形成有边角具有尖锐的形状；
    步骤S4、在平坦层、阳极、及搭接电极上形成像素界定层，所述像素界定层上设有暴露阳极的第一开口，且所述像素界定层暴露搭接电极上形成有边角具有尖锐的形状的区域；
    步骤S5、于第一开口内的阳极上依次形成空穴注入层、空穴传输层、及发光层；在发光层、像素界定层、及搭接电极上依次形成电子传输层、电子注入层、及阴极；
    步骤S6、向辅助电极与阴极之间施加电压，使对应边角具有尖锐的形状的区域的电子传输层及电子注入层被击穿，使阴极与搭接电极直接连接；
    其中，所述搭接电极上形成有多个第三过孔，每一第三过孔的侧壁均与搭接电极的上表面之间形成尖角；
    所述像素界定层暴露搭接电极上形成有多个第三过孔的区域；
    所述步骤S5中，所述电子传输层、电子注入层、及阴极还依次形成在多个第三过孔暴露出的平坦层上；
    所述步骤S6中，向辅助电极与阴极之间施加电压后，使电子传输层及电子注入层上对应所述第三过孔的侧壁与搭接电极的上表面之间的尖角的部分被去除而形成多个第二开口，阴极通过第二开口与搭接电极连接；
    其中，所述TFT包括：设于衬底基板上方的有源层、于有源层上依次设置的栅极绝缘层及栅极、覆盖有源层及栅极的层间绝缘层、及设于层间绝缘层上且间隔的源极及漏极；
    所述辅助电极包括设于层间绝缘层上且与源极、及漏极均间隔的第一子辅助电极；所述第二过孔暴露出所述第一子辅助电极；
    所述层间绝缘层上设有位于有源层两侧上方的第四过孔及第五过孔，所述源极及漏极分别通过第四过孔及第五过孔与有源层的两侧连接；
    所述TFT基板还包括：覆盖层间绝缘层、源极、漏极、及第一子辅助电极的钝化层；所述钝化层上设有分别暴露出源极及第一子辅助电极的第七过孔及第八过孔；所述步骤S2中，所述平坦层形成于钝化层上，所述第一过孔及第二过孔分别位于第七过孔及第八过孔上方；
    其中，所述辅助电极还包括设于衬底基板上的第二子辅助电极；
    所述TFT基板还包括：设于衬底基板上且与第二子辅助电极间隔的金属遮光层、及设于衬底基板上且覆盖金属遮光层及第二子辅助电极的缓冲 层；所述有源层设于缓冲层上且对应位于金属遮光层上方，所述层间绝缘层设于缓冲层上且覆盖有源层及栅极；
    所述缓冲层及层间绝缘层上设有暴露第二子辅助电极的第六过孔，所述第一子辅助电极经所述第六过孔与第二子辅助电极连接；
    其中，所述多个第三过孔呈阵列式排布，所述多个第三过孔的开口形状为矩形、三角形、或圆形。
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