WO2019071742A1

WO2019071742A1 - Nano silver solder paste double-sided interconnected silicon carbide mos device-based modular encapsulation method

Info

Publication number: WO2019071742A1
Application number: PCT/CN2017/112768
Authority: WO
Inventors: 梅云辉; 谢宜静; 付善灿; 陆国权; 李欣
Original assignee: 天津大学
Priority date: 2017-10-13
Filing date: 2017-11-24
Publication date: 2019-04-18
Also published as: CN107910324A

Abstract

A module based on a nano silver solder paste double-sided interconnected silicon carbide metal oxide semiconductor (MOS) device and an encapsulation method; the module consists of a power terminal (1), an upper direct bonded copper (DBC) substrate (2), a lower DBC substrate (3), nano silver solder paste (4), a buffer layer (5), n pairs of silicon carbide fast recovery epitaxial diode (FRED) chips (6) and silicon carbide MOS chips (7), a gate resistor (8), a thick aluminium wire (9), silica gel and molded resin; connecting lower surfaces of the silicon carbide MOS chips (7), lower surfaces of the silicon carbide FRED chips (6) and a lower surface of the buffer layer (5) in parallel at the lower DBC substrate (3); likewise performing the same connection on the upper DBC substrate (2); connecting upper surfaces of the silicon carbide MOS chips (7) and the silicon carbide FRED chips (6) to an upper surface of the buffer layer (5) of the upper DBC substrate (2), the buffer layer (5) of the lower DBC substrate (3) likewise being connected to the silicon carbide MOS chips (7) and the silicon carbide FRED chips (6) of the upper DBC substrate (2). The power chip and the buffer layer (5) are connected to the DBC substrates (2, 3) by using nano silver solder paste (4), thus having the advantages of a low sintering temperature, a high melting point and high heat conductivity.

Description

Modular packaging method based on nano silver solder paste double-sided interconnected silicon carbide MOS device

Technical field

The invention relates to the technical field of power electronic device packaging, in particular to a modular packaging method based on a nano silver solder paste double-sided interconnected silicon carbide MOS device.

Background technique

Silicon carbide power semiconductor devices have the advantages of high breakdown voltage strength, wide band gap, and high thermal conductivity. These characteristics make silicon carbide devices superior to silicon devices and are suitable for applications such as high power density and high switching frequency. At the same time, the ultimate operating temperature of conventional silicon devices is only 200 ° C, while silicon carbide based power devices can operate at ambient temperatures above 500 ° C. Therefore, silicon carbide power devices can be used in many harsh environments, such as aerospace and aircraft.

However, silicon carbide devices generate a large amount of heat dissipation under high frequency, high voltage, and high current operating conditions, which affects device reliability. In order to ensure the reliable operation of semiconductor devices, high current capability and low package interconnect resistance are one of the key issues in the device package design. The single-sided package structure of the conventional semiconductor power device is not efficient in heat dissipation, and the heat generated inside can be discharged only from the lower surface of the semiconductor power chip. In recent years, the double-sided package structure has received increasing attention because it can greatly improve the heat dissipation efficiency of semiconductor power devices. The package structure allows heat generated inside the semiconductor power device to be discharged from both the upper surface and the lower surface of the semiconductor power chip. At the same time, the package structure removes the wire bonding and can effectively reduce the parasitic inductance of the semiconductor power device.

However, the package of double-sided interconnected silicon carbide MOS devices has not been reported, mainly because the switching speed of a single silicon carbide MOS chip is relatively fast, causing multiple (such as more than 8 chips) silicon carbide chips in parallel to cause current failure. The problem of current sharing. At the same time, because the working environment temperature of the silicon carbide MOS chip is relatively high, the use of the traditional solder alloy as the chip connecting material has become another factor restricting the application of the double-sided interconnected silicon carbide MOS module package.

Summary of the invention

In order to solve this problem, an object of the present invention is to provide a modular packaging method based on a nano silver solder paste double-sided interconnected silicon carbide MOS device with good current sharing and high temperature resistance. A method of reducing the switching speed by connecting one gate resistor in series with each silicon carbide MOS chip in the module realizes uniformity of current sharing of the plurality of chips. The use of nano silver solder paste as a chip connecting material solves the high temperature application problem of the double-sided interconnected silicon carbide MOS device.

The technical solution of the invention patent is as follows:

A modular packaging method based on nano silver solder paste double-sided interconnected silicon carbide MOS device: by power terminal 1, upper DBC substrate 2, lower DBC substrate 3, nano silver solder paste 4, buffer layer 5, n-silicon carbide FRED chip 6 and silicon carbide MOS chip 7, gate resistor 8, thick aluminum wire 9, silicone gel and molding resin composition. The lower surface of the silicon carbide MOS chip, the lower surface of the silicon carbide FRED chip, and the lower surface of the buffer layer are respectively connected in parallel on the lower DBC substrate, and the upper DBC substrate is connected in the same manner; then the silicon carbide MOS chip and the silicon carbide FRED are The upper surface of the chip is connected to the upper surface of the buffer layer of the upper DBC substrate. Similarly, the buffer layer of the lower DBC substrate is connected to the silicon carbide MOS chip and the silicon carbide FRED chip of the upper DBC substrate.

A modular packaging method based on a nano silver solder paste double-sided interconnected silicon carbide MOS device, the steps are as follows:

(1) It is preferable that the upper surface of the silicon carbide MOS chip and the silicon carbide FRED chip are plated with a film by magnetron sputtering.

(2) Preferably, the nano-silver solder paste is uniformly coated on the lower DBC substrate by means of stencil printing, and then the lower surface of the silicon carbide MOS chip, the silicon carbide FRED chip and the buffer layer is mounted on the surface of the solder paste.

(3) Repeat step (2) on the upper DBC substrate.

(4) Preferably, the mounted upper DBC substrate and the lower DBC substrate are subjected to low temperature pressureless sintering in a formic acid atmosphere at a sintering temperature of 250 ° C to 300 ° C and a holding time of 15 to 45 minutes.

(5) Preferably, a SnAgCu solder tab or a SnAg solder tab is placed on the upper surface of the silicon carbide MOS chip, the silicon carbide FRED chip, and the buffer layer of the lower DBC substrate, and then the upper DBC substrate is placed on the lower DBC substrate, and finally the assembled double-sided surface is completed. The module is placed in a vacuum reflow oven for soldering.

(6) Preferably, the double-sided module is sealed and sealed by a liquid silicone gel, the temperature is 130 ° C -200 ° C, the holding time is 40-90 min, and finally the double-sided module filled with glue is plastic-sealed.

Preferably the buffer layer is a molybdenum or molybdenum copper alloy.

Preferably, the chip material of the power semiconductor device uses silicon carbide.

Preferably, the silicon carbide MOS chip, the silicon carbide FRED chip and the buffer layer of the double-sided interconnected silicon carbide MOS device are connected to the DBC substrate by a low-temperature pressureless sintered connection of nano silver.

Preferably, the sintered joint of the nanosilver solder paste is carried out in a formic acid environment.

Preferably, the DBC substrate comprises an alumina ceramic DBC substrate, an alumina ceramic DBA substrate, a silicon nitride AMB, and an aluminum nitride DBC.

Compared with the prior art, the present invention has the following advantages:

(1) In the invention patent, the full-silicon carbide semiconductor power device was first developed and developed, that is, the materials of the MOS chip and the FRED chip were all made of silicon carbide.

(2) The current sharing current of the plurality of chips of the double-sided interconnected silicon carbide MOS module prepared by the invention patent is substantially the same.

(3) In the invention patent, the connection between the power chip and the buffer layer and the DBC substrate is performed by using a nano silver solder paste having a low sintering temperature (275 ° C), a high melting point (960 ° C), and a high thermal conductivity (240 W·m ^{-1 ).} · K ^-1 ) and other advantages.

DRAWINGS

1 is a schematic view showing the structure of a DBC substrate according to the present invention;

2 is a schematic view showing the connection of a double-sided interconnected silicon carbide MOS device according to the present invention;

3 is a schematic view of a positioning fixture of a double-sided interconnected silicon carbide MOS device according to the present invention.

4 is a schematic view showing the assembly of a double-sided interconnected silicon carbide MOS device of the present invention.

Among them: 1-power terminal, 2-low DBC substrate, 3-upper DBC substrate, 4-nano silver solder paste, 5-buffer layer, 6-silicon carbide FRED chip, 7-silicon carbide MOS chip, 8-gate resistor , 9-thick aluminum wire

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The method for using a low-temperature sintered nano silver double-sided interconnected silicon carbide MOS device comprises the following steps:

Step 1: The ultrasonic connection technology is used to realize the connection between the power terminal 1 of the double-sided interconnected silicon carbide MOS device and the upper DBC substrate and the lower DBC substrate electrode region. The material of the power terminal and the electrode region of the DBC substrate is pure copper.

Step 2: As shown in FIG. 1, 2 is a lower DBC substrate, and 3 is an upper DBC substrate. The impurities on the surface of the lower DBC substrate 2 and the upper DBC substrate 3 are removed by ultrasonic cleaning and plasma cleaning. The nanosilver solder paste 4 is then printed on the lower DBC substrate 2 and the upper DBC substrate 3 using a steel mesh. Next, the lower DBC substrate 2 and the upper DBC substrate 3 are placed in a vacuum sintering furnace to perform primary sintering of the nano silver solder paste. The sintering temperature was 260 ° C and the holding time was 20 minutes.

Step 3: taking out the lower DBC substrate 2 and the upper DBC substrate 3 for secondary stencil printing nano silver solder paste. Then, the buffer layer 5, the silicon carbide FRED chip 6, and the silicon carbide MOS chip 7 are simultaneously attached to the lower DBC substrate 2 and the upper DBC substrate 3, respectively. The buffer layer 5, the silicon carbide MOS chip 6, and the silicon carbide FRED chip 7 are lightly pressed to sufficiently wet the nano silver solder paste 4 before sintering. At the same time, the gate resistor 8 is bonded to the DBC substrate by the nano silver solder paste 4. Finally, the lower DBC substrate 2 and the upper DBC substrate 3 which have been mounted are placed in a formic acid environment to perform secondary sintering connection of the nano silver solder paste.

Step 4: The thick aluminum wire 9 is used to realize the connection between the gate of the high-power silicon carbide MOS chip and the electrode region of the DBC substrate. One end of the thick aluminum wire 9 is connected to the gate of the high-power silicon carbide MOS chip by the wire bonding technique, and the other end is connected to the electrode region of the DBC substrate. At the same time, the height of the aluminum wire bonding cannot exceed the height of the buffer layer, as shown in FIG.

Step 5: Applying a nano silver solder paste on the upper surface of the buffer layer 5, the silicon carbide FRED chip 6, and the silicon carbide MOS chip 7. Then place the lower DBC substrate 2 in the positioning fixture, as shown in Figure 3, and then reverse the same size. The symmetric upper DBC substrate 3 is inverted and placed lightly on top of the lower DBC substrate 2 to effect assembly of the double-sided interconnected silicon carbide MOS device. Finally, the assembled double-sided interconnected silicon carbide MOS device was placed in a vacuum reflow oven for low temperature pressureless sintering, as shown in FIG.

Step 6. Fill the silicone gel, place the module in a vacuum oven and incubate for 1 hour in an environment of 150 ° C to cure the silicone gel. Finally, the plastic encapsulation technology is used to realize the surrounding resin encapsulation of the module of the double-sided interconnected silicon carbide MOS device.

Claims

A module based on nano silver solder paste double-sided interconnected silicon carbide MOS device; comprising power terminal 1, upper DBC substrate 2, lower DBC substrate 3, nano silver solder paste 4, buffer layer 5, n-silicon carbide FRED chip 6 And a silicon carbide MOS chip 7, a gate resistor 8, a thick aluminum wire 9, a silicone gel, and a molded resin; characterized in that the lower surface of the silicon carbide MOS chip, the lower surface of the silicon carbide FRED chip, and the buffer are respectively The lower surface of the layer is parallelly connected in parallel to the lower DBC substrate; the same connection is made to the upper DBC substrate; then the upper surface of the silicon carbide MOS chip and the silicon carbide FRED chip are connected to the upper surface of the buffer layer of the upper DBC substrate, and the lower DBC substrate is similarly The buffer layer is interconnected with the silicon carbide MOS chip and the silicon carbide FRED chip of the upper DBC substrate.
A module packaging method based on a nano silver solder paste double-sided interconnected silicon carbide MOS device according to claim 1, comprising the steps of:

(1) The upper surface of the silicon carbide MOS chip and the silicon carbide FRED chip is plated with a film by magnetron sputtering;

(2) uniformly coating the nano silver solder paste on the lower DBC substrate by means of stencil printing, and then mounting the lower surface of the silicon carbide MOS chip, the silicon carbide FRED chip and the buffer layer on the surface of the solder paste;

(3) repeating step (2) on the upper DBC substrate;

(4) The upper DBC substrate and the lower DBC substrate are placed in a formic acid environment for low temperature pressureless sintering, the sintering temperature is 250 ° C -300 ° C, and the holding time is 15-45 min;

(5) Place a SnAgCu soldering piece or a SnAg soldering piece on the upper surface of the silicon carbide MOS chip, the silicon carbide FRED chip and the buffer layer of the lower DBC substrate, then place the upper DBC substrate on the lower DBC substrate, and finally assemble the completed double-sided module. Soldering in a vacuum reflow oven;

(6) The silicon dioxide gel is sealed to protect the double-sided module, the temperature is 130°C-200°C, the holding time is 40-90min, and the double-sided module finished by the glue is finally plasticized.
The method of claim 2 wherein the buffer layer is a molybdenum or molybdenum copper alloy.
The method of claim 2 wherein the chip material is silicon carbide.
The method of claim 2 wherein the silicon carbide MOS chip, the silicon carbide FRED chip and the buffer layer in the double-sided interconnected silicon carbide MOS device are connected to the DBC substrate by a nano silver low temperature pressureless sintered connection.
The method of claim 2 wherein the sintered bond of the nanosilver solder paste is carried out in a formic acid environment.
The method of claim 2 wherein the DBC substrate comprises an alumina ceramic DBC substrate, an alumina ceramic DBA substrate, a silicon nitride AMB or an aluminum nitride DBC.