WO2019062209A1 - 一种pcb布局布线的方法和结构 - Google Patents

一种pcb布局布线的方法和结构 Download PDF

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WO2019062209A1
WO2019062209A1 PCT/CN2018/090980 CN2018090980W WO2019062209A1 WO 2019062209 A1 WO2019062209 A1 WO 2019062209A1 CN 2018090980 W CN2018090980 W CN 2018090980W WO 2019062209 A1 WO2019062209 A1 WO 2019062209A1
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area
layer
qpi
pcb
layout
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PCT/CN2018/090980
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李德恒
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郑州云海信息技术有限公司
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Publication of WO2019062209A1 publication Critical patent/WO2019062209A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09318—Core having one signal plane and one power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently

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  • the present invention relates to the field of PCB (Printed Circuit Board) signal and power layout and wiring technology, and particularly relates to a method and structure of PCB layout and wiring.
  • PCB Printed Circuit Board
  • the PCB board is the core of the server, and its design directly determines the stability of the server.
  • the PCB is mainly composed of a signal line and a power supply. In design, the signal and power supply design should be comprehensively considered, and a high-quality PCB circuit board should be designed while minimizing the design cost.
  • the existing motherboard design scheme is a 12-layer board. According to the top-down order, the layout design and signal power supply planning are as follows:
  • TOP BOT layer PCIE
  • DDR high-speed line
  • L3, L4, L9 L10 layer walk high-speed line and miscellaneous line
  • L6, L7 layer take Power power surface.
  • Each layer of the above design has adjacent ground for reference, and has a complete two-layer power plane and four ground planes, which is an optimal design method without considering cost.
  • a method for PCB layout and routing which provides a reference layer for signal routing by dividing a local area into a ground plane by dividing a signal line, a power level, and a ground plane of the PCB in a reference plane of the signal trace. And the return path saves wiring space.
  • the PCB adopts a 10-layer board, wherein the QPI signal lines of the L3 layer and the L10 layer of the original 12-layer board are respectively laid to the L5 layer and the L6 layer, and the design and signal power layout of each laminate are planned as follows:
  • the layout of the PCB includes: a PCH and a PCIE slot placement area, a DIMM slot and a CPU placement area, and a QPI trace area, where the QPI trace area is used to connect two CPUs, wherein:
  • the QPI signal trace is placed in the area corresponding to the QPI trace area, and the corresponding reference plane is the ground plane of the L4 layer, and the other areas are the power planes;
  • L4 layer The area corresponding to the QPI cable area and the DIMM slot and the CPU placement area is the ground plane, and the other areas are the power planes.
  • QPI signal routing is placed in the area corresponding to the QPI routing area, high-speed lines and miscellaneous lines are placed corresponding to the PCH and PCIE slot placement areas, and the corresponding DIMM slot and CPU placement area are set to the ground plane;
  • L7 layer The area corresponding to the QPI signal trace of the L6 layer and the area of the high-speed line and the miscellaneous line are ground planes, providing reference for the QPI signal of the L6 layer and other high-speed lines, and the power supply is provided in other areas.
  • the signal includes a signal trace, a power plane, and a ground plane, wherein a reference plane and a return path are provided for the signal trace by dividing the local area into a ground plane at a reference level of the signal trace , saving wiring space.
  • the PCB is a 10-layer board structure, and the layout of the PCB stack is as follows:
  • the layout of the PCB includes: PCH and PCIE slot placement area, DIMM slot and CPU placement area, QPI routing area (connecting two CPUs), wherein:
  • the QPI signal trace is placed in the area corresponding to the QPI trace area, and the corresponding reference plane is the ground plane of the L4 layer, and the other areas are the power planes;
  • L4 layer The area corresponding to the QPI cable area and the DIMM slot and the CPU placement area is the ground plane, and the other areas are the power planes.
  • QPI signal routing is placed in the area corresponding to the QPI routing area, high-speed lines and miscellaneous lines are placed corresponding to the PCH and PCIE slot placement areas, and the corresponding DIMM slot and CPU placement area are set to the ground plane;
  • L7 layer The area corresponding to the QPI signal trace of the L6 layer and the area of the high-speed line and the miscellaneous line are ground planes, providing reference for the QPI signal of the L6 layer and other high-speed lines, and the power supply is provided in other areas.
  • the invention no longer complies with the traditional signal and power supply separate layout mode, the signal power supply and the ground mixed layout and wiring, thereby improving the design density of the board, and reasonably planning the power, ground and signal line layout design areas, thereby reducing the number of PCB layers and saving costs. .
  • Figure 1 is a schematic diagram of a board layout
  • Figure 2 is a schematic diagram of the L4 layer planning
  • Figure 3 is a schematic diagram of the L5 layer plan
  • Figure 4 is a schematic diagram of the L6 layer planning
  • Figure 5 is a schematic diagram of the L7 layer plan.
  • a method for PCB layout and routing, the implementation steps of the method are as follows:
  • PCH Plate Controller Hub, integrated south bridge
  • PCIE peripheral component interconnect express
  • high-speed serial Computer expansion bus standard high-speed serial Computer expansion bus standard
  • DIMM Dual-Inline-Memory-Modules
  • CPU placement area QPI (Quick Path Interconnect, public system interface) routing area
  • the QPI cabling area is used to connect two CPUs (Central Processing Units);
  • the PCB adopts a 10-layer board stack, which is L1 (TOP), L2, L3, L4, L5, L6, L7, L8 and L10 (BOT) from top to bottom respectively;
  • the DDR (Double Rate Synchronous Dynamic Random Access Memory) of the L3 layer and the L8 layer are not changed, and the QPI signal is adjusted to the L5 layer and the L6 layer;
  • the QPI signal trace is placed in the area corresponding to the QPI trace area, and the corresponding reference plane is the ground plane of the L4 layer, and the other areas are power planes, as shown in FIG. 2;
  • L4 layer the area corresponding to the QPI routing area and the DIMM slot and the CPU placement area is the ground plane, and the other areas are the power planes, as shown in FIG. 3;
  • QPI signal routing is placed in the area corresponding to the QPI routing area, and high-speed lines and miscellaneous lines are placed corresponding to the PCH and PCIE slot placement areas, and the corresponding DIMM slot and CPU placement area are set to the ground plane, as shown in FIG. 4 Shown
  • L7 layer The area corresponding to the QPI signal trace of the L6 layer and the area of the high-speed line and the miscellaneous line are ground planes, providing reference for the QPI signal of the L6 layer and other high-speed lines, and the power supply is provided in other areas, as shown in FIG. 5.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明公开了一种PCB布局布线的方法和结构，所述方法通过将PCB的信号走线、电源层面和地层面混合布局，在信号走线的参考层面，通过划分局部区域为地平面，为信号走线提供参考层面和回流路径。所述结构包括信号走线、电源层面和地层面，其中，在信号走线的参考层面，通过划分局部区域为地平面，为信号走线提供参考层面和回流路径。本发明不再遵从传统的信号和电源分开布局方式，信号电源和地混合布局布线，从而提高板卡设计密度，合理规划电源、地及信号线Layout设计区域，从而可以降低PCB层数，节省成本。

Description

一种PCB布局布线的方法和结构
本申请要求于2017年09月26日提交中国专利局、申请号为201710881052.8、发明名称为“一种PCB布局布线的方法和结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及PCB(Printed Circuit Board,印制电路板)信号及电源布局布线技术领域，具体涉及一种PCB布局布线的方法和结构。
背景技术
随着互联网、大数据的快速发展，云计算时代的到来，云计算中心、大数据中心得以快速发展和壮大，随之而来的服务器和存储的需求及使用也越来越多。服务器和存储作为云计算、大数据的数据处理和储存的支撑，直接决定了整个系统的稳定性。
而PCB板作为服务器的核心，其设计的好坏直接决定了服务器的稳定性。PCB主要由信号线和电源组成，在设计时要综合考虑信号及电源设计，在尽量降低设计成本的同时设计出高质量的PCB电路板。
现有主板设计方案为12层板，其按照自上而下的顺序，各层叠层设计及信号电源规划如下：
Figure PCTCN2018090980-appb-000001
Figure PCTCN2018090980-appb-000002
其中：TOP、BOT层布PCIE、DDR高速线，L2，L5，L8，L11层铺完整的地层；L3，L4，L9，L10层走高速线及杂线，L6，L7层走Power电源面。以上设计每层信号线都有临近的地作参考，有完整的两层电源面、四层地平面，为在不考虑成本情况下的最优设计方法。
现有设计技术方案电源、地、信号具有足够的布局布线空间，而且有部分空间剩余，在现阶段对服务器成本越来越敏感的情况下，存在着过设计的现象，不利于提升产品市场竞争力。
发明内容
本发明的发明目的是：针对上述问题，本发明提供一种PCB布局布线的方法和结构。
为了达到上述发明目的，本发明所采用的技术方案为：
一种PCB布局布线的方法，所述方法通过将PCB的信号走线、电源层面和地层面混合布局，在信号走线的参考层面，通过划分局部区域为地平面，为信号走线提供参考层面和回流路径，节省了布线空间。
所述PCB采用10层板，其中原12层板的L3层和L10层的QPI信号线分别铺设到L5层和L6层，各叠层的设计及信号电源布局规划如下：
Figure PCTCN2018090980-appb-000003
Figure PCTCN2018090980-appb-000004
所述PCB的布局包括：PCH和PCIE插槽摆放区，DIMM槽与CPU摆放区，QPI走线区，所述QPI走线区用于连接两个CPU，其中：
L5层：对应QPI走线区的区域摆放QPI信号走线，其对应参考面为L4层的地平面，其他区域为电源面；
L4层：对应QPI走线区和DIMM槽与CPU摆放区的区域为地平面，其他区域为电源面。
L6层：对应QPI走线区的区域摆放QPI信号走线，对应PCH和PCIE插槽摆放区摆放高速线和杂线，对应DIMM槽与CPU摆放区设置为地平面；
L7层：对应L6层的QPI信号走线的区域和高速线和杂线的区域，为地平面，给L6层的QPI信号及其它高速线提供参考，其他区域铺电源。
一种PCB布局布线的结构，所述结构包括信号走线、电源层面和地层面，其中，在信号走线的参考层面，通过划分局部区域为地平面，为信号走线提供参考层面和回流路径，节省了布线空间。
所述PCB为10层板结构，PCB叠层的布局规划如下：
Figure PCTCN2018090980-appb-000005
所述PCB的布局包括：PCH和PCIE插槽摆放区，DIMM槽与CPU摆放区，QPI走线区(连接两个CPU)，其中：
L5层：对应QPI走线区的区域摆放QPI信号走线，其对应参考面为L4层的地平面，其他区域为电源面；
L4层：对应QPI走线区和DIMM槽与CPU摆放区的区域为地平面，其他区域为电源面。
L6层：对应QPI走线区的区域摆放QPI信号走线，对应PCH和PCIE插槽摆放区摆放高速线和杂线，对应DIMM槽与CPU摆放区设置为地平面；
L7层：对应L6层的QPI信号走线的区域和高速线和杂线的区域，为地平面，给L6层的QPI信号及其它高速线提供参考，其他区域铺电源。
本发明的有益效果为：
本发明不再遵从传统的信号和电源分开布局方式，信号电源和地混合布局布线，从而提高板卡设计密度，合理规划电源、地及信号线Layout设计区域，从而可以降低PCB层数，节省成本。
附图说明
图1为板卡Layout示意图；
图2为L4层规划示意图；
图3为L5层规划示意图；
图4为L6层规划示意图；
图5为L7层规划示意图。
具体实施方式
根据说明书附图，结合具体实施方式对本发明进一步说明：
一种PCB布局布线的方法，所述方法的实现步骤如下：
1)、确定PCB形状，并在PCB上将主要芯片摆放在合理位置，如图1所示，划分为PCH(Platform Controller Hub，集成南桥)和PCIE(peripheral component interconnect express)，高速串行计算机扩展总线标准)插槽摆放区，DIMM(Dual-Inline-Memory-Modules，双列直插式存储模块)槽与CPU摆放区，QPI(Quick Path Interconnect，公共系统接口)走线区，该QPI走线区用于连接两个CPU(Central Processing Unit，中央处理器)；
2)、PCB采用10层板叠层，该10层板叠层自上而下依次分别为L1(TOP)、 L2、L3、L4、L5、L6、L7、L8和L10(BOT)；
3)、L1(TOP)，L2，L3，L8，L9，L10(BOT)按照传统设计方式规划布局布线，其中：
第L3层和第L8层的DDR(Double Data Rate，双倍速率同步动态随机存储器)不作变动，QPI信号调整到第L5层和第L6层；
原设计的12层改成10层后，减去2层信号层的高速线和杂线，调整到10层设计的第L3层和第L8层，
L5层：对应QPI走线区的区域摆放QPI信号走线，其对应参考面为L4层的地平面，其他区域为电源面，如图2所示；
L4层：对应QPI走线区和DIMM槽与CPU摆放区的区域为地平面，其他区域为电源面，如图3所示；
L6层：对应QPI走线区的区域摆放QPI信号走线，对应PCH和PCIE插槽摆放区摆放高速线和杂线，对应DIMM槽与CPU摆放区设置为地平面，如图4所示；
L7层：对应L6层的QPI信号走线的区域和高速线和杂线的区域，为地平面，给L6层的QPI信号及其它高速线提供参考，其他区域铺电源，如图5所示。
具体布局如下：
Figure PCTCN2018090980-appb-000006
实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (8)

  1. 一种PCB布局布线的方法，其特征在于，所述方法通过将PCB的信号走线、电源层面和地层面混合布局，在信号走线的参考层面，通过划分局部区域为地平面，为信号走线提供参考层面和回流路径。
  2. 根据权利要求1所述的一种PCB布局布线的方法，其特征在于，所述PCB采用10层板，各叠层的设计及信号电源布局规划如下：
    Figure PCTCN2018090980-appb-100001
  3. 根据权利要求2所述的一种PCB布局布线的方法，其特征在于，所述PCB的布局包括：PCH和PCIE插槽摆放区，DIMM槽与CPU摆放区，QPI走线区，其中：
    L5层：对应QPI走线区的区域摆放QPI信号走线，其对应参考面为L4层的地平面，其他区域为电源面；
    L4层：对应QPI走线区和DIMM槽与CPU摆放区的区域为地平面，其他区域为电源面。
  4. 根据权利要求3所述的一种PCB布局布线的方法，其特征在于：
    L6层：对应QPI走线区的区域摆放QPI信号走线，对应PCH和PCIE插槽摆放区摆放高速线和杂线，对应DIMM槽与CPU摆放区设置为地平面；
    L7层：对应L6层的QPI信号走线的区域和高速线和杂线的区域，为地平面，给L6层的QPI信号及其它高速线提供参考，其他区域铺电源。
  5. 一种PCB布局布线的结构，其特征在于，所述结构包括信号走线、电源层面和地层面，其中，在信号走线的参考层面，通过划分局部区域为地平面，为信号走线提供参考层面和回流路径。
  6. 根据权利要求5所述的一种PCB布局布线的结构，其特征在于，所述PCB为10层板结构，PCB叠层的布局规划如下：
    Figure PCTCN2018090980-appb-100002
  7. 根据权利要求6所述的一种PCB布局布线的结构，其特征在于，所述PCB的布局包括：PCH和PCIE插槽摆放区，DIMM槽与CPU摆放区，QPI走线区，其中：
    L5层：对应QPI走线区的区域摆放QPI信号走线，其对应参考面为L4层的地平面，其他区域为电源面；
    L4层：对应QPI走线区和DIMM槽与CPU摆放区的区域为地平面，其他区域为电源面。
  8. 根据权利要求7所述的一种PCB布局布线的结构，其特征在于：
    L6层：对应QPI走线区的区域摆放QPI信号走线，对应PCH和PCIE插槽摆放区摆放高速线和杂线，对应DIMM槽与CPU摆放区设置为地平面；
    L7层：对应L6层的QPI信号走线的区域和高速线和杂线的区域，为地平面，给L6层的QPI信号及其它高速线提供参考，其他区域铺电源。
PCT/CN2018/090980 2017-09-26 2018-06-13 一种pcb布局布线的方法和结构 WO2019062209A1 (zh)

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