WO2019061591A1 - 阵列基板、显示面板以及显示装置 - Google Patents

阵列基板、显示面板以及显示装置 Download PDF

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Publication number
WO2019061591A1
WO2019061591A1 PCT/CN2017/106962 CN2017106962W WO2019061591A1 WO 2019061591 A1 WO2019061591 A1 WO 2019061591A1 CN 2017106962 W CN2017106962 W CN 2017106962W WO 2019061591 A1 WO2019061591 A1 WO 2019061591A1
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Prior art keywords
numbered
shift registers
scan
odd
array substrate
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PCT/CN2017/106962
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English (en)
French (fr)
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李文英
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/739,747 priority Critical patent/US10580509B2/en
Publication of WO2019061591A1 publication Critical patent/WO2019061591A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • the liquid crystal display is applied to mobile communication devices and PCs due to its high display quality, low price and convenient carrying.
  • Display terminals such as Compute, computer, TV (Television, TV).
  • the panel driving technology of TV liquid crystal displays is gradually adopting GOA (Gate Driver).
  • GOA Gate Driver
  • array substrate gate drive technology which uses the original process of the flat panel display panel to make the driver circuit of the horizontal scanning line of the panel on the substrate around the display area.
  • GOA technology can simplify the manufacturing process of the flat panel display panel, eliminating the level The bonding process in the scan line direction increases productivity and reduces product cost.
  • a plurality of shift registers 10 of a conventional liquid crystal display device are used to supply scan signals for a plurality of scan lines Gn of an array substrate, which includes a plurality of first shift registers 11 and a plurality of second shifts.
  • Bit register 12 The plurality of first shift registers 11 are disposed on the left side of the display area AA of the array substrate, and are respectively connected to one ends of the plurality of scanning lines Gn.
  • the plurality of second shift registers 12 are disposed on the right side of the display area AA of the array substrate, and are respectively connected to the other ends of the plurality of scanning lines Gn.
  • the first shift register 11 of the first stage and the second shift register 12 of the first stage are both connected to the start signal STV, and the plurality of first shift registers 11 and the plurality of second shift registers 12 respectively
  • a low frequency clock signal LC1, a second low frequency clock signal LC2, a direct current low voltage VSS, and a high frequency clock signal of the high frequency clock signals CK1-CK4 are connected.
  • At least four signal lines need to be disposed on both sides of the display area AA for transmitting one of the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and the high frequency clock signal CK1-CK4 Therefore, the plurality of shift registers 10 need to occupy a large space of the array substrate, and a narrow bezel cannot be realized.
  • the technical problem to be solved by the present invention is to provide an array substrate, a display panel and a display device, which can reduce the space occupied by the shift register, realize a narrow bezel, and improve the user experience.
  • the present invention adopts a technical solution to provide a display panel including an array substrate, the array substrate including a plurality of scan lines, a plurality of data lines, a plurality of shift registers, and a plurality of switch units a plurality of scan lines and a plurality of data lines are intersected to form a plurality of pixel units; each shift register is configured to input a scan signal to one end of the corresponding scan line, and the other end of each scan line is connected to the corresponding switch unit The first end of the switch unit receives the first reference voltage, the control end of the switch unit receives the first control signal, and the shift register and the switch unit simultaneously pull the potential of the scan line to a low potential; the plurality of shift registers
  • the utility model comprises a plurality of odd-numbered shift registers and a plurality of even-numbered shift registers, wherein the plurality of odd-level shift registers are disposed on the left side of the display area of the array substrate, and the plurality of even-numbered shift
  • the plurality of switch units include a plurality of first switch units and a plurality of second switch units, the plurality of first switch units are disposed on a right side of the display area, and the plurality of second switch units are disposed on a left side of the display area
  • the plurality of first switching units are respectively connected to the other end of the odd-numbered scanning lines, and the plurality of second switching units are respectively connected to the other end of the even-numbered scanning lines
  • the plurality of shift registers are disposed on the left of the display area of the array substrate On the side, a plurality of switch units are set to the right of the display area.
  • an array substrate including a plurality of scan lines, a plurality of data lines, a plurality of shift registers, and a plurality of switch units, the plurality of scans a line and the plurality of data lines are disposed to intersect to form a plurality of pixel units; each of the shift registers is configured to input a scan signal to one end of the corresponding scan line, and the other end of each of the scan lines is connected Corresponding to the first end of the switch unit, the second end of the switch unit receives a first reference voltage, the control end of the switch unit receives a first control signal, and the shift register and the switch unit simultaneously The potential of the scan line is pulled to a low potential.
  • a display device including an array substrate including a plurality of scan lines, a plurality of data lines, a plurality of shift registers, and a plurality of switches a unit, a plurality of scan lines and a plurality of data lines are intersected to form a plurality of pixel units; each shift register is configured to input a scan signal to one end of the corresponding scan line, and the other end of each scan line is connected to the corresponding switch The first end of the unit, the second end of the switch unit receives the first reference voltage, the control end of the switch unit receives the first control signal, and the shift register and the switch unit simultaneously pull the potential of the scan line to a low potential.
  • each shift register of the present invention is used to input a scan signal to one end of a corresponding scan line, and the other end of each scan line is connected to the corresponding switch unit.
  • the second end of the switch unit receives the first reference voltage
  • the control end of the switch unit receives the first control signal
  • the shift register and the switch unit simultaneously pull the potential of the scan line to a low potential, wherein each scan line corresponds to one Shift register, thereby reducing the space occupied by multiple shift registers, achieving a narrow bezel and improving the user experience
  • the shift register and the switching unit simultaneously pull the potential of the scan line to a low potential, thereby ensuring that the scan line is pulled The time to the low potential is the same.
  • FIG. 1 is a schematic structural view of a prior art array substrate
  • FIG. 2 is a schematic structural view of an array substrate of the first embodiment
  • Figure 3 is a timing chart of Figure 2;
  • FIG. 4 is a schematic structural view of an array substrate of a second embodiment
  • Figure 5 is a timing chart of Figure 4.
  • FIG. 6 is a schematic structural view of a display panel of the first embodiment
  • Fig. 7 is a schematic structural view of a display device of the first embodiment.
  • FIG. 2 is a schematic structural view of the array substrate of the first embodiment.
  • the array substrate 20 of the present embodiment includes a plurality of scan lines 21, a plurality of data lines 22, a plurality of shift registers 23, and a plurality of switch units 24, wherein the number of the plurality of shift registers 23 and the number of the plurality of switch units 24 Each of them corresponds to the number of the plurality of scanning lines 21 in one-to-one correspondence.
  • the array substrate 20 includes 1080 scanning lines 21, correspondingly provided with 1080 shift registers 23 and 1080 switching units 24.
  • the plurality of scan lines 21 and the plurality of data lines 22 are disposed to intersect to form a plurality of pixel units 25.
  • Each shift register 23 is connected to one end of a corresponding scan line 21 for inputting a scan signal to the scan line 21.
  • the pixel unit 25 connected to the scan line 21 acquires a data signal from the corresponding data line 22.
  • the other end of the scan line 21 is connected to the first end of the corresponding switch unit 24, and the second end of the switch unit 24 receives the first reference voltage VSS (ie, the DC low voltage VSS below), and the control end of the switch unit 24 receives The first control signal, when the shift register 23 and the corresponding switch unit 24 are simultaneously operated, the shift register 23 and the switch unit 24 simultaneously pull the potential of the scan line 21 to a low potential, so that the pixels connected to both sides of the scan line 21 Unit 25 is turned off at the same time.
  • VSS the DC low voltage VSS below
  • the plurality of shift registers 23 of the present embodiment include a plurality of odd-numbered shift registers 231 and a plurality of even-numbered shift registers 232 disposed on the left side of the display area AA of the array substrate 20, A plurality of even-numbered shift registers 232 are disposed on the right side of the display area AA of the array substrate 20, and a plurality of odd-numbered shift registers 231 are respectively connected to one end of the odd-numbered scan lines 21, and the plurality of even-numbered shift registers 232 are respectively It is connected to one end of the even-numbered scanning line 21.
  • the plurality of switch units 24 include a plurality of first switch units 241 and a plurality of second switch units 242.
  • the plurality of first switch units 241 are disposed on the right side of the display area AA, and the plurality of second switch units 242 are disposed on the display. The left side of the area AA.
  • the plurality of first switching units 241 are respectively connected to the other end of the odd-numbered scanning lines 21, and the plurality of second switching units 242 are respectively connected to the other end of the even-numbered scanning lines 21.
  • a signal line 261 is disposed on a side of the plurality of odd-numbered shift registers 231 away from the display area AA, and the signal line 261 is configured to transmit the enable signal STV, the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and One of the high frequency clock signals CK1-CK4, the plurality of odd-numbered shift registers 231 are connected to the signal line 261, for example, the first odd-numbered shift register 231 receives the enable signal STV through the signal line 261, a low frequency clock signal LC1, a second low frequency clock signal LC2, a direct current low voltage VSS, and a high frequency clock signal CK1; the nth odd-numbered shift register 231 receives the first low frequency clock signal LC1, the second low frequency clock through the signal line 261 Signal LC2, DC low voltage VSS, and one of high frequency clock signals CK1-CK4, where n is greater than one.
  • a signal line 262 is disposed on a side of the plurality of even-numbered shift registers 232 away from the display area AA, and the signal line 262 is configured to transmit the enable signal STV, the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and One of the high frequency clock signals CK1-CK4, the plurality of even-numbered shift registers 232 are connected to the signal line 262, for example, the first even-stage shift register 232 receives the start signal STV through the signal line 262, a low frequency clock signal LC1, a second low frequency clock signal LC2, a direct current low voltage VSS, and a high frequency clock signal CK2; the nth even stage shift register 232 receives the first low frequency clock signal LC1 and the second low frequency clock through the signal line 262.
  • Each shift register 23 of this embodiment may include a GOA circuit, and the first control signal may be any one of a high frequency clock signal CK1, a high frequency clock signal CK2, a high frequency clock signal CK3, and a high frequency clock signal CK4.
  • Each of the shift registers 23 inputs a second control signal, and the second control signal may be any one of a high frequency clock signal CK1, a high frequency clock signal CK2, a high frequency clock signal CK3, and a high frequency clock signal CK4.
  • the shift register 23 generates a scan signal according to the second control signal, wherein the phase of the first control signal is opposite to the phase of the second control signal; for example, the second control signal connected to the odd-numbered shift register 231 is the high frequency clock signal CK1,
  • the first control signal connected to the corresponding first switch unit 241 is the high frequency clock signal CK3, or the second control signal connected to the even-numbered shift register 232 is the high frequency clock signal CK2, and the corresponding second switch unit 242 is connected.
  • the first control signal is the high frequency clock signal CK4.
  • the timings of the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, the high frequency clock signal CK1, the high frequency clock signal CK2, the high frequency clock signal CK3, and the high frequency clock signal CK4 are shown.
  • the graph, G(n) and G(n+1) are timing charts of the scan signal.
  • the plurality of first switching units 241 are used to pull the odd-numbered scan lines 21 to a low potential; specifically, in an odd number
  • the stage shift register 231 inputs the second control signal to a low level
  • the scan signal output from the odd-numbered shift register 231 is at a low level, so the plurality of odd-numbered shift registers 231 pull the odd-numbered scan lines 21 to a low potential.
  • the control terminal of the first switching unit 241 inputs the first control signal to a high level, and the first switching unit 241 operates to pull the level of the odd-numbered scanning lines 21 to the DC low voltage VSS, thus a plurality of odd-numbered stages.
  • the shift register 231 and the plurality of first switching units 241 simultaneously pull the levels across the odd-numbered scanning lines 21 to a low level.
  • the plurality of second switch units 242 are used to pull the even-numbered scan lines 21 to a low potential; specifically, in even-numbered shifts
  • the bit register 232 inputs the second control signal to a low level
  • the scan signal output by the even-numbered shift register 232 is at a low level, so the plurality of even-numbered shift registers 232 pull the even-numbered scan lines 21 to a low potential
  • the control terminal of the two switching unit 242 inputs the first control signal to a high level, and the second switching unit 242 operates to pull the level of the even-numbered scanning line 21 to a DC low voltage VSS, thus shifting multiple even orders
  • the register 232 and the plurality of second switching units 242 simultaneously pull the levels across the even-numbered scanning lines 21 to a low level.
  • the plurality of switching units 24 may each be a thin film transistor, the control end of the switching unit 24 is the gate of the thin film transistor, the first end of the switching unit 24 is the drain of the thin film transistor, and the second end of the switching unit 24 is a thin film transistor.
  • the source is the first end of the switching unit 24 .
  • the first control signal controls the switch unit 24 to operate normally, and at this time, the switch unit 24 simultaneously pulls the scan line 21 to a low potential, thereby ensuring the array.
  • the pixel unit 25 is simultaneously turned off at both the left and right sides of the substrate 20.
  • each scan line 21 of the present embodiment corresponds to one shift register 23, and the number of the plurality of shift registers 23 is reduced, thereby reducing the number of shift registers 23.
  • the space is occupied, the narrow bezel is realized, and the user's experience is improved.
  • the shift register 23 and the switching unit 24 simultaneously pull the potential of the scanning line 21 to a low potential, and the same time can be ensured that the scanning line 21 is pulled to the low potential.
  • control end of the switch unit 24 receives the second control signal
  • the other end of the scan line 21 is connected to the first end of the corresponding switch unit 24, and the second end of the switch unit 24 receives the high level.
  • the switching unit 24 and the shift register 23 operate simultaneously, at which time the scan signal output from the shift register 23 is at a high level, and the switching unit 24 pulls the level of the scan line 21 to a high level.
  • Flat so that the pixel units 25 connected to both sides of the scanning line 21 are simultaneously turned on.
  • the array substrate 40 of the second embodiment is different from the array substrate 20 disclosed in the first embodiment in that a plurality of shift registers 43 are disposed on the left side of the display area AA of the array substrate 40.
  • a plurality of switching units 44 are disposed on the right side of the display area AA, a signal line 461 is disposed on a side of the plurality of shift registers 43 away from the display area AA, and a signal line 462 is disposed on a side of the plurality of switching units 44 away from the display area AA.
  • the signal line 461 is used to transmit one of the start signal STV, the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and the high frequency clock signal CK1-CK4.
  • the signal line 462 is for transmitting one of the DC low voltage VSS and the high frequency clock signals CK1-CK4.
  • the timing chart corresponding to the shift register 43 of this embodiment is as shown in FIG.
  • each scan line 41 of the present embodiment corresponds to one shift register 43, and a plurality of shift registers 43 are disposed on the left side of the display area AA of the array substrate 40. Further, the space occupied by the plurality of shift registers 43 is reduced, a narrow bezel is realized, and the user experience is improved. Further, the shift register 43 and the switching unit 44 simultaneously pull the potential of the scan line 41 to a low potential, thereby ensuring that the scan line is The time to pull to the low potential is the same.
  • one of ordinary skill in the art can fully place a plurality of shift registers on the right side of the display area of the array substrate, and a plurality of switch units are disposed on the left side of the display area.
  • the display panel 60 of the present embodiment includes an array substrate 61 , a color filter substrate 62 , and a liquid crystal layer 63 .
  • the color filter substrate 62 is disposed opposite to the array substrate 61
  • the liquid crystal layer 63 is disposed on the color filter substrate 62 and the array substrate.
  • the array substrate 61 is the array substrate disclosed in the above embodiments, and will not be described herein.
  • the display device 70 of the present embodiment includes a display panel 71 and a backlight module 72.
  • the display panel 71 is disposed in the light emitting direction of the backlight module 72.
  • the display panel 71 includes an array substrate 711, a color filter substrate 712, and a liquid crystal.
  • the color filter substrate 712 is disposed opposite to the array substrate 711, and the liquid crystal layer 713 is disposed between the color filter substrate 712 and the array substrate 711.
  • the array substrate 711 is the array substrate disclosed in the above embodiments, and details are not described herein.
  • each shift register is configured to input a scan signal to one end of the corresponding scan line, and the other end of each scan line is connected to the first end of the corresponding switch unit, and the second end of the switch unit receives the first reference.
  • Voltage the control end of the switch unit receives the first control signal, and the shift register and the switch unit simultaneously pull the potential of the scan line to a low potential, wherein each scan line corresponds to a shift register, thereby reducing the occupation of multiple shift registers Space, achieve a narrow border, improve the user experience; in addition, the shift register and the switching unit simultaneously pull the potential of the scan line to a low potential, which can ensure that the scan line is pulled to the low potential for the same time.

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Abstract

一种阵列基板(20)、显示面板(60)以及显示装置(70)。阵列基板(20)包括多条扫描线(21)、多条数据线(22)、多个移位寄存器(23)和多个开关单元(24)，每个移位寄存器(23)用于向对应的扫描线(21)的一端输入扫描信号，每条扫描线(21)的另一端连接对应的开关单元(24)的第一端，开关单元(24)的第二端接收第一参考电压(VSS)，开关单元(24)的控制端接收第一控制信号，移位寄存器(23)和开关单元(24)同时将扫描线(21)的电位拉到低电位。能够实现窄边框，提高用户的体验效果，并且保证扫描线(21)被拉到低电位的时间相同。

Description

阵列基板、显示面板以及显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板、显示面板以及显示装置。
【背景技术】
液晶显示器以其高显示品质、价格低廉、携带方便等优点，应用在移动通讯设备、PC（Personal Compute，电脑）、TV（Television，电视）等的显示终端。目前普遍采用的TV液晶显示器的面板驱动技术逐渐趋向于采用GOA（Gate Driver on Array，阵列基板栅极驱动）技术，其运用平板显示面板的原有制程将面板水平扫描线的驱动电路制作在显示区周围的基板上，GOA技术能简化平板显示面板的制作工序，省去水平扫描线方向的bonding（焊接）工艺，可提升产能并降低产品成本。
如图1所示，现有的液晶显示装置的多个移位寄存器10用于为阵列基板的多条扫描线Gn提供扫描信号，其包括多个第一移位寄存器11和多个第二移位寄存器12。多个第一移位寄存器11设置在阵列基板的显示区域AA的左侧，分别与多条扫描线Gn的一端连接。多个第二移位寄存器12设置在阵列基板的显示区域AA的右侧，分别与多条扫描线Gn的另一端连接。
其中，第一级的第一移位寄存器11和第一级的第二移位寄存器12均与启动信号STV连接，多个第一移位寄存器11和多个第二移位寄存器12分别与第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1-CK4中的一个高频时钟信号连接。在显示区域AA的两侧均需要设置至少四条信号线用于传输第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1-CK4中的一个高频时钟信号，因此多个移位寄存器10需要占用阵列基板的空间大，无法实现窄边框。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板、显示面板以及显示装置，能够减低移位寄存器所占用的空间，实现窄边框，提高用户的体验效果。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示面板，其包括阵列基板，该阵列基板包括多条扫描线、多条数据线、多个移位寄存器和多个开关单元，多条扫描线和多条数据线相交设置，以形成多个像素单元；每个移位寄存器用于向对应的扫描线的一端输入扫描信号，每条扫描线的另一端连接对应的开关单元的第一端，开关单元的第二端接收第一参考电压，开关单元的控制端接收第一控制信号，移位寄存器和开关单元同时将扫描线的电位拉到低电位；多个移位寄存器包括多个奇数级移位寄存器和多个偶数级移位寄存器，多个奇数级移位寄存器设置在阵列基板的显示区域的左侧，多个偶数级移位寄存器设置在显示区域的右侧，多个奇数级移位寄存器分别与奇数级的扫描线的一端连接，多个偶数级移位寄存器分别与偶数级的扫描线的一端连接；多个开关单元包括多个第一开关单元和多个第二开关单元，多个第一开关单元设置在显示区域的右侧，多个第二开关单元设置在显示区域的左侧，多个第一开关单元分别与奇数级的扫描线的另一端连接，多个第二开关单元分别与偶数级的扫描线的另一端连接；多个移位寄存器设置在阵列基板的显示区域的左侧，多个开关单元设置显示区域的右侧。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，其包括多条扫描线、多条数据线、多个移位寄存器和多个开关单元，所述多条扫描线和所述多条数据线相交设置，以形成多个像素单元；每个所述移位寄存器用于向对应的所述扫描线的一端输入扫描信号，每条所述扫描线的另一端连接对应的所述开关单元的第一端，所述开关单元的第二端接收第一参考电压，所述开关单元的控制端接收第一控制信号，所述移位寄存器和所述开关单元同时将所述扫描线的电位拉到低电位。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，其包括阵列基板，该阵列基板包括多条扫描线、多条数据线、多个移位寄存器和多个开关单元，多条扫描线和多条数据线相交设置，以形成多个像素单元；每个移位寄存器用于向对应的扫描线的一端输入扫描信号，每条扫描线的另一端连接对应的开关单元的第一端，开关单元的第二端接收第一参考电压，开关单元的控制端接收第一控制信号，移位寄存器和开关单元同时将扫描线的电位拉到低电位。
本发明的有益效果是：区别于现有技术的情况，本发明的每个移位寄存器用于向对应的扫描线的一端输入扫描信号，每条扫描线的另一端连接对应的开关单元的第一端，开关单元的第二端接收第一参考电压，开关单元的控制端接收第一控制信号，移位寄存器和开关单元同时将扫描线的电位拉到低电位，其中每条扫描线对应一个移位寄存器，进而减少多个移位寄存器所占用空间，实现窄边框，提高用户的体验效果；此外，移位寄存器和开关单元同时将扫描线的电位拉到低电位，能够保证扫描线被拉到低电位的时间相同。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要采用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术的阵列基板的结构示意图；
图2是第一实施例的阵列基板的结构示意图；
图3是图2中的时序图；
图4是第二实施例的阵列基板的结构示意图；
图5是图4中的时序图；
图6是第一实施例的显示面板的结构示意图；
图7是第一实施例的显示装置的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图2所示，图2是第一实施例的阵列基板的结构示意图。本实施例的阵列基板20包括多条扫描线21、多条数据线22、多个移位寄存器23以及多个开关单元24，其中多个移位寄存器23的数量和多个开关单元24的数量均与多条扫描线21的数量一一对应。例如，阵列基板20包括1080条扫描线21，对应设置有1080个移位寄存器23和1080个开关单元24。
其中，多条扫描线21和多条数据线22相交设置，以形成多个像素单元25。每个移位寄存器23与对应的扫描线21的一端连接，用于向该扫描线21输入扫描信号。在扫描线21输入扫描信号时，与该扫描线21连接的像素单元25从对应的数据线22获取数据信号。该扫描线21的另一端连接对应的开关单元24的第一端，该开关单元24的第二端接收第一参考电压VSS（即下文的直流低电压VSS），该开关单元24的控制端接收第一控制信号，在移位寄存器23和对应的开关单元24同时工作时，移位寄存器23和该开关单元24同时将扫描线21的电位拉到低电位，使得扫描线21两侧连接的像素单元25的同时关闭。
本实施例的多个移位寄存器23包括多个奇数级移位寄存器231和多个偶数级移位寄存器232，多个奇数级移位寄存器231设置在阵列基板20的显示区域AA的左侧，多个偶数级移位寄存器232设置在阵列基板20的显示区域AA的右侧，多个奇数级移位寄存器231分别与奇数级的扫描线21的一端连接，多个偶数级移位寄存器232分别与偶数级的扫描线21的一端连接。
其中，多个开关单元24包括多个第一开关单元241和多个第二开关单元242，多个第一开关单元241设置在显示区域AA的右侧，多个第二开关单元242设置在显示区域AA的左侧。其中，多个第一开关单元241分别与奇数级的扫描线21的另一端连接，多个第二开关单元242分别与偶数级的扫描线21的另一端连接。
多个奇数级移位寄存器231远离显示区域AA的一侧设置有信号线261，信号线261用于传输启动信号STV、第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1-CK4中的一个高频时钟信号，多个奇数级移位寄存器231与信号线261连接，例如第一个的奇数级移位寄存器231通过信号线261接收启动信号STV、第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1；第n个的奇数级移位寄存器231通过信号线261接收第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1-CK4中的一个高频时钟信号，其中n大于1。
多个偶数级移位寄存器232远离显示区域AA的一侧设置有信号线262，信号线262用于传输启动信号STV、第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1-CK4中的一个高频时钟信号，多个偶数级移位寄存器232与信号线262连接，例如第一个的偶数级移位寄存器232通过信号线262接收启动信号STV、第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK2；第n个的偶数级移位寄存器232通过信号线262接收第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1-CK4中的一个高频时钟信号。
本实施例的每个移位寄存器23均可以包括GOA电路，第一控制信号可以为高频时钟信号CK1、高频时钟信号CK2、高频时钟信号CK3以及高频时钟信号CK4中的任意一个。
其中，每个移位寄存器23输入第二控制信号，第二控制信号可以为高频时钟信号CK1、高频时钟信号CK2、高频时钟信号CK3以及高频时钟信号CK4中的任意一个。移位寄存器23根据第二控制信号产生扫描信号，其中第一控制信号的相位与第二控制信号的相位相反；例如奇数级移位寄存器231连接的第二控制信号为高频时钟信号CK1，则对应的第一开关单元241连接的第一控制信号为高频时钟信号CK3，或者偶数级移位寄存器232连接的第二控制信号为高频时钟信号CK2，则对应的第二开关单元242连接的第一控制信号为高频时钟信号CK4。
如图3所示，第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、高频时钟信号CK1、高频时钟信号CK2、高频时钟信号CK3以及高频时钟信号CK4的时序图，G（n）和G（n+1）为扫描信号的时序图。在多个奇数级移位寄存器231将奇数级的扫描线21拉到低电位时，多个第一开关单元241用于将所述奇数级的扫描线21拉到低电位；具体地，在奇数级移位寄存器231输入第二控制信号为低电平时，奇数级移位寄存器231输出的扫描信号为低电平，因此多个奇数级移位寄存器231将奇数级的扫描线21拉到低电位；第一开关单元241的控制端输入第一控制信号为高电平，第一开关单元241工作，以将奇数级的扫描线21的电平拉低至直流低电压VSS，因此多个奇数级移位寄存器231和多个第一开关单元241同时将奇数级的扫描线21两端的电平拉到低电平。在多个偶数级移位寄存器232将偶数级的扫描线21拉到低电位时，多个第二开关单元242用于将偶数级的扫描线21拉到低电位；具体地，在偶数级移位寄存器232输入第二控制信号为低电平时，偶数级移位寄存器232输出的扫描信号为低电平，因此多个偶数级移位寄存器232将偶数级的扫描线21拉到低电位；第二开关单元242的控制端输入第一控制信号为高电平，第二开关单元242工作，以将偶数级的扫描线21的电平拉低至直流低电压VSS，因此多个偶数级移位寄存器232和多个第二开关单元242同时将偶数级的扫描线21两端的电平拉到低电平。
其中，多个开关单元24均可以为薄膜晶体管，开关单元24的控制端为薄膜晶体管的栅极，开关单元24的第一端为薄膜晶体管的漏极，开关单元24的第二端为薄膜晶体管的源极。
因此，本实施例的扫描线21在被移位寄存器23下拉到低电位时，第一控制信号控制开关单元24正常工作，此时开关单元24同时将扫描线21下拉到低电位，进而保证阵列基板20的左右两侧同时关闭像素单元25。
与图1所示的多个移位寄存器10相比较，本实施例的每条扫描线21对应一个移位寄存器23，多个移位寄存器23的数量减少，进而减少多个移位寄存器23所占用空间，实现窄边框，提高用户的体验效果；此外，移位寄存器23和开关单元24同时将扫描线21的电位拉到低电位，能够保证扫描线21被拉到低电位的时间相同。
更进一步，在其他实施例中，开关单元24的控制端接收第二控制信号，扫描线21的另一端连接对应的开关单元24的第一端，该开关单元24的第二端接收高电平。在第二控制信号为高电平时，开关单元24和移位寄存器23同时工作，此时移位寄存器23输出的扫描信号为高电平，并且开关单元24将扫描线21的电平拉至高电平，以使扫描线21两侧连接的像素单元25的同时开启。
如图4所示，第二实施例的阵列基板40与第一实施例所揭示的阵列基板20的不同之处在于：多个移位寄存器43设置在阵列基板40的显示区域AA的左侧，多个开关单元44设置在显示区域AA的右侧，多个移位寄存器43远离显示区域AA的一侧设置有信号线461，多个开关单元44远离显示区域AA的一侧设置有信号线462。
其中，信号线461用于传输启动信号STV、第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS以及高频时钟信号CK1-CK4中的一个高频时钟信号。信号线462用于传输直流低电压VSS、高频时钟信号CK1-CK4中的一个高频时钟信号。本实施例的移位寄存器43对应的时序图，如图5所示。
与图1所示的多个移位寄存器10相比较，本实施例的每条扫描线41对应一个移位寄存器43，且多个移位寄存器43设置在阵列基板40的显示区域AA的左侧，进而减少多个移位寄存器43所占用空间，实现窄边框，提高用户的体验效果；此外，移位寄存器43和开关单元44同时将扫描线41的电位拉到低电位，能够保证扫描线被拉到低电位的时间相同。
在其他实施例中，本领域的普通技术人员完全可以将多个移位寄存器设置在阵列基板的显示区域的右侧，多个开关单元设置在显示区域的左侧。
如图6所示，本实施例的显示面板60包括阵列基板61、彩膜基板62以及液晶层63，彩膜基板62与阵列基板61相对设置，液晶层63设置在彩膜基板62与阵列基板61之间，该阵列基板61为上述实施例所揭示的阵列基板，在此不再赘述。
如图7所示，本实施例的显示装置70包括显示面板71和背光模组72，显示面板71设置在背光模组72的出光方向，显示面板71包括阵列基板711、彩膜基板712以及液晶层713，彩膜基板712与阵列基板711相对设置，液晶层713设置在彩膜基板712与阵列基板711之间，该阵列基板711为上述实施例所揭示的阵列基板，在此不再赘述。
综上所述，每个移位寄存器用于向对应的扫描线的一端输入扫描信号，每条扫描线的另一端连接对应的开关单元的第一端，开关单元的第二端接收第一参考电压，开关单元的控制端接收第一控制信号，移位寄存器和开关单元同时将扫描线的电位拉到低电位，其中每条扫描线对应一个移位寄存器，进而减少多个移位寄存器所占用空间，实现窄边框，提高用户的体验效果；此外，移位寄存器和开关单元同时将扫描线的电位拉到低电位，能够保证扫描线被拉到低电位的时间相同。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括多条扫描线、多条数据线、多个移位寄存器和多个开关单元，所述多条扫描线和所述多条数据线相交设置，以形成多个像素单元；每个所述移位寄存器用于向对应的所述扫描线的一端输入扫描信号，每条所述扫描线的另一端连接对应的所述开关单元的第一端，所述开关单元的第二端接收第一参考电压，所述开关单元的控制端接收第一控制信号，所述移位寄存器和所述开关单元同时将所述扫描线的电位拉到低电位；
    所述多个移位寄存器包括多个奇数级移位寄存器和多个偶数级移位寄存器，所述多个奇数级移位寄存器设置在所述阵列基板的显示区域的左侧，所述多个偶数级移位寄存器设置在所述显示区域的右侧，所述多个奇数级移位寄存器分别与奇数级的扫描线的一端连接，所述多个偶数级移位寄存器分别与偶数级的扫描线的一端连接；
    所述多个开关单元包括多个第一开关单元和多个第二开关单元，所述多个第一开关单元设置在所述显示区域的右侧，所述多个第二开关单元设置在所述显示区域的左侧，所述多个第一开关单元分别与所述奇数级的扫描线的另一端连接，所述多个第二开关单元分别与所述偶数级的扫描线的另一端连接；
    所述多个移位寄存器设置在所述阵列基板的显示区域的左侧，所述多个开关单元设置所述显示区域的右侧。
  2. 根据权利要求1所述的显示面板，其中，在所述多个奇数级移位寄存器将所述奇数级的扫描线拉到低电位时，所述多个第一开关单元用于将所述奇数级的扫描线拉到低电位；在所述多个偶数级移位寄存器将所述偶数级的扫描线拉到低电位时，所述多个第二开关单元用于将所述偶数级的扫描线拉到低电位。
  3. 根据权利要求1所述的显示面板，其中，所述移位寄存器输入第二控制信号，所述移位寄存器根据所述第二控制信号产生扫描信号，所述第一控制信号的相位与所述第二控制信号的相位相反。
  4. 根据权利要求1所述的显示面板，其中，所述开关单元包括薄膜晶体管，所述开关单元的控制端为所述薄膜晶体管的栅极，所述开关单元的第一端为所述薄膜晶体管的漏极，所述开关单元的第二端为所述薄膜晶体管的源极。
  5. 一种阵列基板，其中，所述阵列基板包括多条扫描线、多条数据线、多个移位寄存器和多个开关单元，所述多条扫描线和所述多条数据线相交设置，以形成多个像素单元；每个所述移位寄存器用于向对应的所述扫描线的一端输入扫描信号，每条所述扫描线的另一端连接对应的所述开关单元的第一端，所述开关单元的第二端接收第一参考电压，所述开关单元的控制端接收第一控制信号，所述移位寄存器和所述开关单元同时将所述扫描线的电位拉到低电位。
  6. 根据权利要求5所述的阵列基板，其中，所述多个移位寄存器包括多个奇数级移位寄存器和多个偶数级移位寄存器，所述多个奇数级移位寄存器设置在所述阵列基板的显示区域的左侧，所述多个偶数级移位寄存器设置在所述显示区域的右侧，所述多个奇数级移位寄存器分别与奇数级的扫描线的一端连接，所述多个偶数级移位寄存器分别与偶数级的扫描线的一端连接。
  7. 根据权利要求6所述的阵列基板，其中，所述多个开关单元包括多个第一开关单元和多个第二开关单元，所述多个第一开关单元设置在所述显示区域的右侧，所述多个第二开关单元设置在所述显示区域的左侧，所述多个第一开关单元分别与所述奇数级的扫描线的另一端连接，所述多个第二开关单元分别与所述偶数级的扫描线的另一端连接。
  8. 根据权利要求7所述的阵列基板，其中，在所述多个奇数级移位寄存器将所述奇数级的扫描线拉到低电位时，所述多个第一开关单元用于将所述奇数级的扫描线拉到低电位；在所述多个偶数级移位寄存器将所述偶数级的扫描线拉到低电位时，所述多个第二开关单元用于将所述偶数级的扫描线拉到低电位。
  9. 根据权利要求5所述的阵列基板，其中，所述多个移位寄存器设置在所述阵列基板的显示区域的左侧，所述多个开关单元设置所述显示区域的右侧。
  10. 根据权利要求5所述的阵列基板，其中，所述多个移位寄存器设置在所述阵列基板的显示区域的右侧，所述多个开关单元设置所述显示区域的左侧。
  11. 根据权利要求5所述的阵列基板，其中，所述移位寄存器输入第二控制信号，所述移位寄存器根据所述第二控制信号产生扫描信号，所述第一控制信号的相位与所述第二控制信号的相位相反。
  12. 根据权利要求5所述的阵列基板，其中，所述开关单元包括薄膜晶体管，所述开关单元的控制端为所述薄膜晶体管的栅极，所述开关单元的第一端为所述薄膜晶体管的漏极，所述开关单元的第二端为所述薄膜晶体管的源极。
  13. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括多条扫描线、多条数据线、多个移位寄存器和多个开关单元，所述多条扫描线和所述多条数据线相交设置，以形成多个像素单元；每个所述移位寄存器用于向对应的所述扫描线的一端输入扫描信号，每条所述扫描线的另一端连接对应的所述开关单元的第一端，所述开关单元的第二端接收第一参考电压，所述开关单元的控制端接收第一控制信号，所述移位寄存器和所述开关单元同时将所述扫描线的电位拉到低电位。
  14. 根据权利要求13所述的显示装置，其中，所述多个移位寄存器包括多个奇数级移位寄存器和多个偶数级移位寄存器，所述多个奇数级移位寄存器设置在所述阵列基板的显示区域的左侧，所述多个偶数级移位寄存器设置在所述显示区域的右侧，所述多个奇数级移位寄存器分别与奇数级的扫描线的一端连接，所述多个偶数级移位寄存器分别与偶数级的扫描线的一端连接。
  15. 根据权利要求14所述的显示装置，其中，所述多个开关单元包括多个第一开关单元和多个第二开关单元，所述多个第一开关单元设置在所述显示区域的右侧，所述多个第二开关单元设置在所述显示区域的左侧，所述多个第一开关单元分别与所述奇数级的扫描线的另一端连接，所述多个第二开关单元分别与所述偶数级的扫描线的另一端连接。
  16. 根据权利要求15所述的显示装置，其中，在所述多个奇数级移位寄存器将所述奇数级的扫描线拉到低电位时，所述多个第一开关单元用于将所述奇数级的扫描线拉到低电位；在所述多个偶数级移位寄存器将所述偶数级的扫描线拉到低电位时，所述多个第二开关单元用于将所述偶数级的扫描线拉到低电位。
  17. 根据权利要求13所述的显示装置，其中，所述多个移位寄存器设置在所述阵列基板的显示区域的左侧，所述多个开关单元设置所述显示区域的右侧。
  18. 根据权利要求13所述的显示装置，其中，所述多个移位寄存器设置在所述阵列基板的显示区域的右侧，所述多个开关单元设置所述显示区域的左侧。
  19. 根据权利要求13所述的显示装置，其中，所述移位寄存器输入第二控制信号，所述移位寄存器根据所述第二控制信号产生扫描信号，所述第一控制信号的相位与所述第二控制信号的相位相反。
  20. 根据权利要求13所述的显示装置，其中，所述开关单元包括薄膜晶体管，所述开关单元的控制端为所述薄膜晶体管的栅极，所述开关单元的第一端为所述薄膜晶体管的漏极，所述开关单元的第二端为所述薄膜晶体管的源极。
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