WO2019052583A1 - 极化码的速率匹配的方法和装置 - Google Patents

极化码的速率匹配的方法和装置 Download PDF

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Publication number
WO2019052583A1
WO2019052583A1 PCT/CN2018/106299 CN2018106299W WO2019052583A1 WO 2019052583 A1 WO2019052583 A1 WO 2019052583A1 CN 2018106299 W CN2018106299 W CN 2018106299W WO 2019052583 A1 WO2019052583 A1 WO 2019052583A1
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Prior art keywords
index
codeword
bit sequence
bit
index set
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PCT/CN2018/106299
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English (en)
French (fr)
Inventor
王坚
黄凌晨
乔云飞
李榕
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华为技术有限公司
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Priority to EP18856028.8A priority Critical patent/EP3667927A4/en
Publication of WO2019052583A1 publication Critical patent/WO2019052583A1/zh
Priority to US16/822,712 priority patent/US10958374B2/en
Priority to US17/189,834 priority patent/US11362760B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols

Definitions

  • the present application relates to the field of channel coding, and more particularly to a method and apparatus for rate matching of a polarization code.
  • Polar code is the first good code that theoretically proves that it can achieve Shannon capacity and has low coding and decoding complexity, so it is widely used.
  • the length of the codeword obtained after the bit to be encoded is Polar-coded is an integer power of 2.
  • the coded codeword needs to be rate matched to obtain a codeword of a desired length, and then transmitted on the channel.
  • the bit space to be coded before encoding may be referred to as a U field
  • the coded code word space may be referred to as an X field.
  • Existing rate matching schemes include both shorting and puncture. Whether shortening or punching, the shortening position or the punching position is first determined in the X domain, and the subchannel in which the forced freeze bit is placed is determined in the U domain according to the shortened position or the punched position, and finally the information bit set and the fixed bit set are selected. .
  • the position or punch position is the shortened position or punched position selected for the X field. Practice has found that when the X-domain search shortens the position or the punching position, the search space is large, and the performance obtained by a plurality of different shortened positions or punched positions is basically equivalent, and the search efficiency is low.
  • Polar code is the first good code that theoretically proves that it can achieve Shannon capacity and has low coding and decoding complexity, so it is widely used.
  • the length of the codeword obtained after the bit to be encoded is Polar-coded is an integer power of 2.
  • the coded codeword needs to be rate matched to obtain a codeword of a desired length, and then transmitted on the channel.
  • the bit space to be coded before encoding may be referred to as a U field
  • the coded code word space may be referred to as an X field.
  • Existing rate matching schemes include both shorting and puncture. Whether shortening or punching, the shortening position or the punching position is first determined in the X domain, and the subchannel in which the forced freeze bit is placed is determined in the U domain according to the shortened position or the punched position, and finally the information bit set and the fixed bit set are selected. .
  • the position or punch position is the shortened position or punched position selected for the X field. Practice has found that when the X-domain search shortens the position or the punching position, the search space is large, and the performance obtained by a plurality of different shortened positions or punched positions is basically equivalent, and the search efficiency is low.
  • FIG. 1 is a schematic structural diagram of a wireless communication system applicable to an embodiment of the present application.
  • Figure 2 is a basic flow diagram for communicating using wireless technology.
  • FIG. 3 is a flowchart of a method for rate matching of a polarization code according to an embodiment of the present application.
  • FIG. 4 is an interaction diagram of an encoding end and a decoding end according to an embodiment of the present application.
  • FIG. 5 is a shortening process of a Polar code provided by an embodiment of the present application.
  • FIG. 6 is a puncturing process of a Polar code according to an embodiment of the present application.
  • Figure 7 is a schematic diagram of a bit swapping process.
  • FIG. 8 is a schematic diagram of an apparatus 600 for rate matching of a polarization code provided by the present application.
  • FIG. 9 is a schematic structural diagram of a device 700 for rate matching of a polarization code provided by the present application.
  • FIG. 10 is a schematic structural diagram of a terminal device 800 according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a wireless communication system applicable to an embodiment of the present application.
  • the wireless communication system can include at least one network device in communication with one or more terminal devices.
  • the network device may be a base station, or may be a device integrated with a base station controller, or may be another device having similar communication functions.
  • the wireless communication system mentioned in the embodiments of the present application includes, but is not limited to, a narrow band-internet of things (NB-IoT), a global system for mobile communications (GSM), and an enhanced data rate.
  • GSM evolution EDGE
  • WCDMA wideband code division multiple access
  • CDMA2000 code division multiple access
  • TD-SCDMA time division synchronization code
  • LTE long term evolution
  • 5G mobile communication systems namely enhanced mobile broadband (eMBB) ), ultra reliable low latency communication (URLLC) and enhanced mass machine type communication (eMTC) or new communication systems that will emerge in the future.
  • eMBB enhanced mobile broadband
  • URLLC ultra reliable low latency communication
  • eMTC enhanced mass machine type communication
  • the terminal devices involved in the embodiments of the present application may include various handheld devices having wireless communication functions, in-vehicle devices, wearable devices, computing devices, or other processing devices connected to the wireless modem.
  • the terminal may be a mobile station (MS), a subscriber unit, a cellular phone, a smart phone, a wireless data card, a personal digital assistant (PDA) computer, a tablet.
  • MS mobile station
  • PDA personal digital assistant
  • a computer a wireless modem, a handset, a laptop computer, a machine type communication (MTC) terminal, and the like.
  • MTC machine type communication
  • FIG. 1 only illustrates a network device and two terminal devices (such as the network device 101, the terminal device 102, and the terminal device 103 shown in FIG. 1) in the communication system as an example. Obviously, the communication system can also Includes more network devices or more terminal devices.
  • the network device in FIG. 1 communicates with the terminal device using wireless technology.
  • the network device sends a signal, it is the encoding end.
  • the network device receives the signal, it is the decoding end.
  • the terminal device is also the same.
  • the terminal device sends a signal, it is the encoding end.
  • the terminal device receives the signal, it is the decoding end.
  • the encoding end can also be considered as the transmitting end, and the decoding end can also be regarded as the receiving end.
  • Figure 2 is a basic flow diagram for communicating using wireless technology.
  • the source of the transmitting end is sequentially sent on the channel after source coding, channel coding, rate matching and modulation. After receiving the signal, the receiving end receives demodulation, de-rate matching, channel decoding and source decoding to obtain the sink.
  • Channel codec is one of the core technologies in the field of wireless communication, and its performance improvement will directly improve network coverage and user transmission rate.
  • the polarization code is a channel coding technology that can theoretically prove to reach the Shannon limit and has practical linear complexity coding and decoding capabilities.
  • the core of the polarization code structure is the processing of "channel polarization".
  • the coding method is used to make each subchannel exhibit different reliability.
  • the no-noise channel of 1 and the other part of the channel tend to be a full-noise channel with a capacity close to zero.
  • the transmission of information directly on a channel having a capacity close to 1 is selected to approximate the channel capacity.
  • the encoding strategy of the Polar code is the characteristic that applies this phenomenon.
  • the non-noise channel is used to transmit the useful information of the user, and the full-noise channel transmits the agreed information or does not transmit the information.
  • G N is an N ⁇ N matrix, and Defined as the Kronecker product of log2 N matrices F 2 .
  • the addition and multiplication operations involved in the above equations are addition and multiplication operations on the binary Galois field.
  • a part of the bits are used to carry information, called a set of information bits.
  • the set of indices for these bits is denoted A.
  • the other part of the bits is set to a fixed value pre-agreed by the receiving end and the transmitting end, which is called a fixed bit set or a set of frozen bits, and the set of indexes is represented by the complement A c of A.
  • the encoding process of the Polar code is equivalent to Here, F N (A) is a sub-matrix obtained by the row corresponding to the index in the set A in F N .
  • F N (A C ) is a sub-matrix obtained from the row corresponding to the index in the set A C in F N .
  • u A is The set of information bits in the number is K. for A fixed set of bits in the number (NK) that is a known bit. These fixed bits are usually set to 0, but the fixed bits can be arbitrarily set as long as the receiving end and the transmitting end pre-agreed.
  • u A is In the information bit set, u A is the row vector of length K, ie
  • K, the symbol
  • the construction process of the Polar code determines the performance of the Polar code.
  • the construction process of the Polar code is usually such that a total of N polarization channels are determined according to the mother code length N. Obtaining the reliability of the N polarized channels, taking the sequence number (or index) of the top K polarized channels with the highest reliability as the elements of the set A, and the sequence numbers of the remaining (NK) polarized channels as the fixed bit numbers.
  • Set A determines the position of the information bits, and set A C determines the position of the fixed bits.
  • Common construction methods include density evolution (DE) and Gaussian approximation (GA).
  • the length of the mother code output by the encoder is an integer power of 2.
  • the rate matching of the mother code is required to obtain the required The length of the code.
  • the method of rate matching of the Polar code includes shortening, punching, and the like.
  • the principle of shortening the operation is that by adjusting the vector to be encoded, some bits in the encoded mother code code word are fixed values (generally 0), and other bits in the code word are unaffected as much as possible. In this way, the transmitting end can not transmit these bits having a fixed value (for example, 0), and the receiving end can still know their values (generally 0), which serves to shorten the codeword.
  • the receiving end decodes the bit rate ratio (LLR) of these positions by positive infinity because the known shortened bit position is 0.
  • the principle and shortening of the puncturing are different. It can be known from the principle of shortening that the bit of the shortened position in the coded code word must be 0, and the code word bit punctured in the puncturing is not necessarily 0. Therefore, when the receiving end matches the rate, the LLR of the position that needs to be punctured is filled with 0 for decoding.
  • LLR refers to a log likelihood ratio (LLR).
  • LLR log likelihood ratio
  • the LLR represents the ratio of the probability that a bit is judged to 0 to the probability of being judged by 1, and the logarithm of the ratio is taken.
  • the decoding end decodes the shortened position LLRs into positive infinity.
  • the decoding end decodes the LLR of the puncturing position into 0, and decodes the bits of the puncturing positions.
  • the probability of being 0 or 1 is 50% each.
  • the present application proposes a method for rate matching of a polarization code, first determining a position where a U-domain places a forced freeze bit, and then determining a shortened position or a punched position of the X-domain according to a position at which the U-domain places a forced freeze bit, which can be selected at the pole.
  • the rate matching scheme of the code is used, the search space of the codeword domain is reduced.
  • FIG. 3 is a schematic flowchart of rate matching provided by the embodiment of the present application.
  • the rate matching and de-rate matching scheme of the Polar code involved in the embodiment of the present application is implemented in a network element that performs Polar code encoding and decoding, respectively. Specifically, for uplink transmission, rate matching is completed at the terminal, and de-rate matching is performed at the base station. Conversely, for downlink transmission, rate matching is done at the base station, and rate resolution matching is done at the terminal.
  • FIG. 4 is an interaction diagram of an encoding end and a decoding end according to an embodiment of the present application.
  • the encoding end determines a first index set corresponding to the N to-be-coded bits.
  • the N bits to be encoded correspond to N polarized channels.
  • the first index set in the embodiment of the present application refers to an index (or a serial number) of Z polarized channels that are determined by the encoding end to be forced to freeze bits from the N polarized channels.
  • the first index set can be determined in a variety of ways, whether for shortening or puncturing. For example, bit reverse order, grouping, and the like.
  • the first index set is ⁇ 0, 1, 2 ⁇ ; if the natural order shortening mode is adopted, the first index set is ⁇ 5, 6, 7 ⁇ .
  • the encoding end acquires a first codeword of length N, where the first codeword is obtained by performing polarization coding on the N to-be-coded bits.
  • the encoding end performs rate matching on the first codeword according to the first index set to obtain a second codeword whose length is equal to M.
  • M ⁇ N and M is a positive integer greater than zero.
  • the encoding end is based on first determining, in the U domain, a set of indexes of the subchannels for which the forced freeze bits are placed (ie, the first index set), and then determining, by the first index set, the shortened position or punching of the X domain. The location is rate matched.
  • the encoding end sends the second codeword.
  • the receiving end receives the demodulated information.
  • modulation and mapping can refer to the prior art and will not be described in detail herein.
  • the decoding end performs de-rate matching on the demodulated information, and decodes the bit sequence after the de-rate matching, to obtain a decoded sequence.
  • the demodulated LLR is input at the decoding end, that is, the demodulated information mentioned here.
  • the decoding process at the decoding end is the inverse process of the polarization encoding and rate matching of the N bits to be encoded by the encoding end. Therefore, the decoding end first performs de-rate matching on the demodulated information, and then decodes the bits after the de-rate matching to obtain a decoded sequence.
  • Steps 310-350 shown in Figure 4 are by way of example only.
  • the rate matching at the encoding end and the de-rate matching at the decoding end are all based on the same Pattern.
  • the Pattern is first determined.
  • the encoding end performs rate matching based on the Pattern
  • the decoding end performs rate matching based on the Pattern. Therefore, when performing rate matching, the encoding end may not need to perform steps 310 and 320.
  • the encoding end can perform rate matching directly based on the Pattern that is pre-determined.
  • the method for determining the pattern may be the method for determining the second index set described in the embodiment of the present application.
  • the second index set is determined according to the first index set. The following is a detailed description of how to determine the second index set cooperation based on the first index set.
  • step 330 if the first codeword is rate matched according to the first index set, a detailed description will be given.
  • the shortened position of the X domain is determined according to the index of the subchannel in which the U domain places the forced freeze bit.
  • the set of indexes of the sub-channels in which the U-domain is placed with the forced freeze bits is recorded as the first index set, and the set of the shortened positions of the X-domain or the set of the punched positions is recorded as the second index set.
  • the position where the U-domain places the forced freeze bit is the same as the shortened position of the X-domain.
  • FIG. 5 is a shortening process of a Polar code according to an embodiment of the present application.
  • the set of index components of the subchannels in which the U field is placed with the forced freeze bits is denoted as F S .
  • the encoder determines a set of U places the field force F S subchannel index bits freezing.
  • the selection of the index of the subchannel in which the U domain places the forced freeze bit may be based on the performance of the Polar code.
  • the coding result of the X field corresponding to the subchannel in which the forced freeze bit is placed must be 0, and the F S satisfying this condition is not unique and can be determined in various ways. For example, bit reverse order or grouping, and the like.
  • the encoding end acquires reliability of the remaining subchannels except the subchannel indicated by the index in the set F S .
  • the encoding end can determine the reliability of the remaining subchannels by formula calculation or table lookup.
  • the remaining subchannels referred to herein refer to subchannels other than the subchannels indicated by the index included in the F S among the N polarized channels corresponding to the N to-be-coded bits.
  • the coding end selects the K subchannels with the highest reliability among the remaining subchannels to carry information bits, and the remaining subchannels are used to carry the freeze bits.
  • the encoding end selects the K most polarized channels with the highest reliability to carry the information bits according to the reliability of the remaining subchannels obtained in step 402, and the remaining subchannels are used to carry the frozen bits.
  • the encoding end performs polarization coding on the N bits to be encoded to obtain a first codeword.
  • the length of the mother code codeword (i.e., the first codeword) subjected to polarization coding of the coded bits is equal to an integer power of two.
  • the encoding end determines the shortened position X S of the X domain according to the F S of the U domain.
  • the shortened position X S of the X domain is the same as the position where the forced freeze bit is placed in the U domain.
  • the encoding end shortens the bit of the shortened position X S in the first codeword to obtain a second codeword of length M.
  • FIG. 6 is a punching process according to an embodiment of the present application.
  • the encoding end determines a set F P of indexes of the subchannels in which the U domain places the forced freeze bits.
  • the reliability of the encoder acquire the remaining subchannels except F P subchannel index indicated.
  • the coding end selects the K subchannels with the highest reliability among the remaining subchannels to carry information bits, and the remaining subchannels are used to carry the freeze bits.
  • the encoding end performs Polar coding on the N to-be-coded bits to obtain a first codeword.
  • the encoding end determines the punching position X P of the X domain according to the F P of the U domain.
  • the encoding end punches a bit of the punching position X P in the first codeword to obtain a second codeword whose required code length is equal to M.
  • step 505 how to determine the puncturing position X P of the X domain according to the set F P of the index of the subchannel in which the forced freeze bit is placed in the U domain.
  • the first bit sequence is determined according to the set F P of the indices of the subchannels for which the forced freeze bits are placed in the U domain.
  • bit 0 is placed at the position indicated by the index in F P
  • bit 1 is placed at other positions.
  • the first bit sequence may be the bit sequence F itself of length N, or may be a bit sequence obtained after inverting the bit sequence F.
  • P 1 [f 1 , f 2 , f 3 , ..., f N ].
  • the bit-aligning process is to reverse the bit placed at the position indicated by the ith index of one bit sequence and the bit placed at the position indicated by the N/2+i index, i traverse ⁇ 0, 1, ..., N / 2-1 ⁇ , the L second bit sequences are different from each other.
  • each second index set can be used as a collection of puncturing locations of the X domain.
  • F P ⁇ 0,1,2 ⁇
  • the i-th position in the first bit sequence and the bit in the 4+ith position are reversed, i traversing ⁇ 0, 1, 2, 3 ⁇ .
  • bit of the i-th position and the bit of the 4+ith position are referred to as a pair of bits, in the process of reconciliation, one or more groups can be selected each time to obtain one.
  • the second bit sequence if the bit of the i-th position and the bit of the 4+ith position are referred to as a pair of bits, in the process of reconciliation, one or more groups can be selected each time to obtain one.
  • the second bit sequence if the bit of the i-th position and the bit of the 4+ith position are referred to as a pair of bits, in the process of reconciliation, one or more groups can be selected each time to obtain one.
  • the second bit sequence is if the bit of the i-th position and the bit of the 4+ith position are referred to as a pair of bits, in the process of reconciliation, one or more groups can be selected each time to obtain one. The second bit sequence.
  • an index of a position having a bit value of 0 is read from each of the second bit sequences, respectively, to obtain a second index set. It can be seen that the plurality of second bit sequences are read to obtain a plurality of second index sets. In other words, each time a second bit sequence is read, a second set of indices is obtained.
  • Reading the 8 second bit sequences obtained by P 1 results in the following 8 second index sets: ⁇ 0, 1, 2 ⁇ , ⁇ 1, 2, 4 ⁇ , ⁇ 0, 2, 5 ⁇ , ⁇ 0, 1,6 ⁇ , ⁇ 2,4,5 ⁇ , ⁇ 0,5,6 ⁇ , ⁇ 1,4,6 ⁇ , ⁇ 4,5,6 ⁇ .
  • Reading the 8 second bit sequences obtained by P 2 yields the following 8 second index sets: ⁇ 1, 2, 3 ⁇ , ⁇ 2, 3, 5 ⁇ , ⁇ 1, 3, 6 ⁇ , ⁇ 1, 2,7 ⁇ , ⁇ 3,5,6 ⁇ , ⁇ 1,6,7 ⁇ , ⁇ 2,5,7 ⁇ , ⁇ 5,6,7 ⁇ .
  • One of the 16 second index sets is arbitrarily selected as a set of puncturing positions of the X domain. For example, if ⁇ 0, 1, 2 ⁇ is selected for rate matching, the position of the index position of 0, 1, and 2 in the first code word is determined as the punch position. For another example, if ⁇ 1, 4, 6 ⁇ is selected for rate matching, the positions of the index positions of 1, 4, and 6 in the first code word are determined as the punch positions.
  • bit-aligning the bit sequence P 1 if the bit of the i-th position is the same as the The bits of the positions are the same (same as 0 or the same as 1), and the bit sequence obtained after the call is the same as P 1 . At this time, the sequence after the reconciliation should not be calculated within the second bit sequence.
  • Figure 7 is a schematic diagram of a bit swapping process.
  • N 8
  • F P ⁇ 0, 1, 2 ⁇
  • P 2 [1 1 1 1 1 0 0 0].
  • P 1 to the bit reversed bit sequence obtained includes a process P 11, P 12, ..., P 18,
  • P 2 to the bit reversed bit sequence obtained includes a process P 21, P 22, ..., P 28 .
  • the indexes of the positions where the bits 0 are placed in P 11 , P 12 , . . . , P 18 are respectively read to obtain a plurality of second index sets.
  • the indexes of the positions where the bits 0 are placed in P 21 , P 22 , ..., P 28 are respectively read to obtain a plurality of second bit index sets.
  • a second index set is arbitrarily selected from the plurality of second index sets, and the index included in the selected second index set is selected as a rate matching puncture position.
  • rate matching and de-rate matching are based on one Pattern.
  • the encoding end that is, the transmitting end
  • the decoding end ie, the receiving end
  • the method for determining the second index set described in the embodiment of the present application is a method for determining a Pattern.
  • the encoding end Based on the Pattern, the encoding end performs rate matching on the first codeword having a length equal to N to obtain a second codeword of a desired length (for example, a length equal to M), where M ⁇ N, M is a positive integer greater than zero.
  • the encoding end modulates, maps, and sends the second codeword to the decoding end.
  • the decoding end performs de-rate matching based on the same Pattern.
  • the coding end first determines the index of the subchannel in which the U domain places the forced freeze bit, and then determines the shortened position or the punched position of the X domain to achieve rate matching of the polarization code, which can control the rate more directly. Matching performance.
  • FIG. 8 is a schematic diagram of an apparatus 600 for rate matching of a polarization code provided by the present application. As shown in FIG. 8, the apparatus 600 includes a processing unit 610 and a transmitting unit 620.
  • the processing unit 610 is configured to:
  • the sending unit 620 is configured to send the second codeword of length M.
  • processing unit is specifically configured to:
  • each of the second index sets is an index of the determined punched position or the shortened position in the first codeword
  • the processing unit is configured to read an index that is the same as an index in the first index set from the N indexes corresponding to the first codeword, to obtain one of the second index sets.
  • processing unit is specifically configured to:
  • bit-pairing processing on the first bit sequence to obtain at least one second bit sequence wherein the bit-pitched processing is a bit placed at a position indicated by an ith index in the first bit sequence
  • the bits placed at the position indicated by the N/2+i index are reversed, i traversing ⁇ 0, 1, ..., N/2-1 ⁇ , wherein the at least one third bit sequence is different from each other;
  • an index of a position in which the bit 0 is placed in the first bit sequence is the same as an index in the first index set.
  • processing unit is specifically configured to:
  • the third bit sequence is flipped to obtain the first bit sequence.
  • processing unit is specifically configured to: use, as a shortened position or a punched position of the first codeword, a position indicated by an index in any one of the second index sets in the first codeword And performing rate matching on the first codeword to obtain the second codeword.
  • the encoding end is based on first determining, in the U domain, a set of indexes of the subchannels for which the forced freeze bits are placed (ie, the first index set), and then determining, by the first index set, the shortened position or punching of the X domain. Rate matching of the location, which can reduce the search space of the codeword domain when selecting the rate matching scheme of the polarization code
  • FIG. 9 is a schematic structural diagram of a device 700 for rate matching of a polarization code provided by the present application.
  • device 700 includes one or more processors 701, one or more memories 702, and one or more transceivers 703.
  • the processor 701 is configured to control the transceiver 703 to send and receive signals
  • the memory 702 is used to store a computer program
  • the processor 701 is configured to call and run the computer program from the memory 702, such that the device 700 performs the corresponding flow of the embodiments of the interleaving method and/or Or operation.
  • the device 700 performs the corresponding flow of the embodiments of the interleaving method and/or Or operation.
  • processing unit 610 can be implemented by processor 701
  • transmitting unit 620 can be implemented by transceiver 703, and the like.
  • the present application provides a computer readable storage medium having stored therein instructions for causing a computer to perform rate matching of polarization codes in various embodiments of the present application when it is run on a computer .
  • the present application also provides a computer program product comprising computer program code for causing a computer to perform a rate matching method of a polarization code as described in any one of the above embodiments when the computer program code is run on a computer.
  • the present application also provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted performs A method of rate matching of polarization codes in various method embodiments of the present application.
  • the communication device on which the chip is mounted may be a device that performs rate matching of a polarization code.
  • the terminal device in uplink transmission, the terminal device is equipped with the chip to perform the rate matching method provided by the present application, such as the terminal device 102 shown in FIG. 1, and the network device 101 performs de-rate matching.
  • the network device 101 is installed with the chip to perform the rate matching method provided by the present application, and the terminal device 103 performs de-rate matching.
  • the present application also provides an encoding apparatus having a function of a method of realizing rate matching of a polarization code in the above embodiment.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding apparatus has other functions of performing the process related to the polarization code encoding, such as Polar encoding, modulation, etc., in addition to the method of rate matching provided by the present application.
  • the encoding device when performing uplink transmission, may specifically be a terminal device, such as the terminal device 102 shown in FIG. 1.
  • the encoding device when performing downlink transmission, may specifically be a network device, such as the network device 101 shown in FIG.
  • the encoding device comprises: an input interface circuit for acquiring a first index set and a first codeword; and a logic circuit for using the first index The set performs rate matching on the first codeword of length N to obtain a second codeword of length M; and an output interface circuit for outputting the second codeword.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, when the program When executed, the encoding device can implement the interleaving method described in any of the possible designs of the above embodiments.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • the foregoing memory and the memory may be physically independent units, or the memory may be integrated with the processor.
  • FIG. 10 is a schematic structural diagram of a terminal device 800 according to an embodiment of the present application.
  • the terminal device 800 includes a transceiver 808 and a processor 804.
  • Terminal device 800 can also include a memory 819 that stores computer-executed instructions.
  • the transceiver 808 is configured to output a second codeword of length M according to the indication of the processor 804.
  • the processor 804 can obtain the first codeword of length N through the internal communication interface of the terminal device.
  • the processor 804 can be used to perform actions implemented internally by the rate matching device in the method embodiment, and the transceiver 808 can be used to perform receiving or transmitting actions in the method embodiments.
  • the processor 804 can be used to perform actions implemented internally by the rate matching device in the method embodiment
  • the transceiver 808 can be used to perform receiving or transmitting actions in the method embodiments.
  • the processor 804 and the memory 819 described above may be integrated into one processing device, and the processor 804 is configured to execute program code stored in the memory 819 to implement the above functions.
  • the memory 819 can also be integrated in the processor 804 when implemented.
  • the terminal device 800 described above may also include a power source 812 for providing power to various devices or circuits in the terminal device 800.
  • the terminal device 800 described above may include an antenna 810 for transmitting data or information output by the transceiver 808 through a wireless signal.
  • the terminal device 800 may further include one or more of an input unit 814, a display unit 816, an audio circuit 818, a camera 820, a sensor 822, and the like.
  • the audio circuit may also include a speaker 8182, a microphone 8184, and the like.
  • rate matching and de-rate matching are based on one Pattern. After determining the Pattern, the sender performs rate matching based on the Pattern, and the receiving end performs rate matching based on the Pattern.
  • a method for determining a second index set is a method for determining a Pattern.
  • the present application also provides an apparatus for de-rate matching that has the functionality to implement a method of de-rate matching.
  • These functions can be implemented in hardware or implemented in hardware by executing the corresponding software.
  • the apparatus for de-rate matching may be a chip, and a communication device on which the chip is mounted may perform a method of de-rate matching.
  • the chip When performing uplink transmission, the chip can be installed on a network device, so that the network device has a function of realizing a method of de-rate matching.
  • the device for de-rate matching may be the network device 101 as shown in FIG.
  • the chip When performing downlink transmission, the chip can be installed on the terminal device, so that the terminal device has a function of realizing a method of de-rate matching.
  • the present application provides a de-rate matching device that includes one or more processors, one or more memories, and one or more transceivers (each transceiver including a transmitter and a receiver).
  • the transmitter or receiver transmits and receives signals through the antenna.
  • the memory is used to store computer program instructions (or code).
  • the processor is configured to execute instructions stored in the memory, and when the instructions are executed, the processor performs a method of de-rate matching.
  • the present application also provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted performs The method of decoding rate matching.
  • the present application provides a computer readable storage medium having stored therein instructions that, when run on a computer, cause the computer to perform the method of de-rate matching in the above embodiments.
  • the application also provides a computer program product comprising: computer program code for causing a computer to perform the method of de-rate matching as described in any one of the above embodiments when the computer program code is run on a computer.
  • the present application also provides a decoding apparatus having a function of implementing the method of de-rate matching in the above-described embodiments of the present application.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the decoding device also has associated functions for implementing Polar code decoding, such as demodulation, decoding, and the like.
  • the processor may be a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more programs for controlling the program of the present application.
  • the processor can include a digital signal processor device, a microprocessor device, an analog to digital converter, a digital to analog converter, and the like.
  • the processor can distribute the control and signal processing functions of the mobile device among the devices according to their respective functions.
  • the processor can include functionality to operate one or more software programs, which can be stored in memory.
  • the functions of the processor may be implemented by hardware or by software executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of information and instructions that can be stored. Dynamic storage device. It can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, and a disc storage (including a compact disc, a laser disc, a compact disc, a digital versatile disc, a Blu-ray disc, etc.), a disk storage medium or other magnetic storage device, or any other device that can be used to carry or store desired program code in the form of an instruction or data structure and accessible by a computer. Medium, but not limited to this.
  • EEPROM electrically erasable programmable read-only memory
  • CD-ROM compact disc read-only memory
  • disc storage including a compact disc, a laser disc, a compact disc, a digital versatile disc, a Blu-ray disc, etc.
  • the above functions are implemented in the form of software and sold or used as stand-alone products, they can be stored in a computer readable storage medium.
  • the part of the technical solution of the present application which contributes in essence or to the prior art, or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program code. .

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Abstract

本申请提供一种极化码的速率匹配的方法和装置，能够在选择极化码的速率匹配方案时，减小码字域的搜索空间。该方法包括：确定N个待编码比特对应的第一索引集合，第一索引集合包括放置强制冻结比特的Z个极化信道的索引，该Z个极化信道为该N个待编码比特对应的N个极化信道的子集，N＝2n，Z<N，n和Z为正整数；获取长度为N的第一码字，第一码字是对所述N个待编码比特进行极化编码得到的；根据第一索引集合，对第一码字进行速率匹配，得到长度为M的第二码字，其中，M<N且M为正整数；发送长度为M的第二码字。

Description

极化码的速率匹配的方法和装置
本申请要求于2017年09月18日提交中国国家知识产权局、申请号为201710843301.4、申请名称为“极化码的速率匹配的方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信道编码领域，更具体地，涉及一种极化码的速率匹配的方法和装置。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，保证通信的质量。极化码(即，Polar码)是第一个理论上证明可以取得香农容量且具有低编、译码复杂度的好码，因此得到了广泛应用。
在采用Polar码进行信道编码时，根据Polar的编码原理，待编码比特经过Polar编码后得到的码字的长度都是2的整数次幂。当信道的实际能够传输的码长非2的整数次幂时，则需要对编码后的码字进行速率匹配，得到所需长度的码字，进而在信道上进行传输。通常，可以将编码前的待编码比特空间称作U域，将编码后的码字空间称作X域。
现有的速率匹配方案包括缩短(shorten)和打孔(puncture)两种方式。不论是缩短或打孔，都是首先在X域确定缩短位置或打孔位置，再根据缩短位置或打孔位置在U域确定放置强制冻结比特的子信道，最后选择信息比特集合和固定比特集合。而在X域确定缩短位置或打孔位置时，一般都需要搜索大量的缩短位置或打孔位置，通过比较以这些缩短位置或打孔位置进行速率匹配而取得的性能，将性能较好的缩短位置或打孔位置作为X域选择的缩短位置或打孔位置。实践发现，在X域搜索缩短位置或打孔位置时，搜索空间较大，并且，可能多种不同的缩短位置或打孔位置取得的性能基本相当，搜索效率较低。
发明内容
通信系统通常采用信道编码提高数据传输的可靠性，保证通信的质量。极化码(即，Polar码)是第一个理论上证明可以取得香农容量且具有低编、译码复杂度的好码，因此得到了广泛应用。
在采用Polar码进行信道编码时，根据Polar的编码原理，待编码比特经过Polar编码后得到的码字的长度都是2的整数次幂。当信道的实际能够传输的码长非2的整数次幂时，则需要对编码后的码字进行速率匹配，得到所需长度的码字，进而在信道上进行传输。通常，可以将编码前的待编码比特空间称作U域，将编码后的码字空间称作X域。
现有的速率匹配方案包括缩短(shorten)和打孔(puncture)两种方式。不论是缩短或打孔，都是首先在X域确定缩短位置或打孔位置，再根据缩短位置或打孔位置在U域确定放置强制冻结比特的子信道，最后选择信息比特集合和固定比特集合。而在X域确定 缩短位置或打孔位置时，一般都需要搜索大量的缩短位置或打孔位置，通过比较以这些缩短位置或打孔位置进行速率匹配而取得的性能，将性能较好的缩短位置或打孔位置作为X域选择的缩短位置或打孔位置。实践发现，在X域搜索缩短位置或打孔位置时，搜索空间较大，并且，可能多种不同的缩短位置或打孔位置取得的性能基本相当，搜索效率较低。
附图说明
图1为适用于本申请实施例的无线通信系统的结构示意图。
图2是采用无线技术进行通信的基本流程图。
图3为本申请实施例提供的极化码的速率匹配的方法流程图。
图4为本申请实施例提供的编码端和译码端的交互图。
图5为本申请实施例提供的Polar码的缩短流程。
图6为本申请实施例提供的Polar码的打孔流程。
图7为比特对调过程的示意图。
图8为本申请提供的极化码的速率匹配的装置600的示意图。
图9为本申请提供的极化码的速率匹配的设备700的示意性结构图。
图10为本申请实施例提供的终端设备800的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
图1为适用于本申请实施例的无线通信系统的结构示意图。该无线通信系统中可以包括至少一个网络设备，该网络设备与一个或多个终端设备进行通信。该网络设备可以是基站，也可以是基站与基站控制器集成后的设备，还可以是具有类似通信功能的其它设备。
本申请实施例提及的无线通信系统包括但不限于：窄带物联网系统(narrow band-internet of things，NB-IoT)、全球移动通信系统(global system for mobile communications，GSM)、增强型数据速率GSM演进系统(enhanced data rate for GSM evolution，EDGE)、宽带码分多址系统(wideband code division multiple access，WCDMA)、码分多址2000系统(code division multiple access,CDMA2000)、时分同步码分多址系统(time division-synchronization code division multiple access，TD-SCDMA)，长期演进系统(long term evolution，LTE)、下一代5G移动通信系统的三大应用场景，即增强移动带宽(enhanced mobile broadband,eMBB)，高可靠性低延迟通信(ultra reliable low latency communication，URLLC)和增强海量机器连接通信(massive machine type communication，eMTC)或者将来出现的新的通信系统。
本申请实施例中所涉及到的终端设备可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。终端可以是移动台(mobile station，MS)、用户单元(subscriber unit)、蜂窝电话(cellular phone)、智能电话(smart phone)、无线数据卡、个人数字助理(personal digital assistant，PDA)电脑、平板型电脑、无线调制解调器(modem)、手持设备(handset)、膝上型电脑(laptop computer)、机器类型通信(machine type communication，MTC)终端等。
应理解，图1仅以通信系统中包括一个网络设备和两个终端设备(如图1中所示的网 络设备101、终端设备102和终端设备103)为例进行说明，显然，通信系统还可以包括更多的网络设备或更多的终端设备。
图1中的网络设备与终端设备之间采用无线技术进行通信。当网络设备发送信号时，其为编码端，当网络设备接收信号时，其为译码端。终端设备也是一样的，当终端设备发送信号时，其为编码端，当终端设备接收信号时，其为译码端。
另外，编码端也可以认为是发送端，译码端也可以认为是接收端。
图2是采用无线技术进行通信的基本流程图。发送端的信源依次经过信源编码、信道编码、速率匹配和调制后在信道上发出，接收端接收到信号后依次经过解调、解速率匹配、信道解码和信源解码后获得信宿。
为了便于理解和说明，首先对本申请实施例中涉及的相关概念作简单介绍。
信道编解码是无线通信领域的核心技术之一，其性能的改进将直接提升网络覆盖及用户传输速率。目前，极化码是可理论证明达到香农极限，并且具有可实用的线性复杂度编译码能力的信道编码技术。极化码构造的核心是通过“信道极化”的处理，在编码侧，采用编码的方法使各个子信道呈现出不同的可靠性，当码长持续增加时，一部分信道将趋向于容量接近于1的无噪信道，另一部分信道趋向于容量接近于0的全噪信道。选择在容量接近于1的信道上直接传输信息以逼近信道容量。
Polar码的编码策略正是应用了这种现象的特性，利用无噪信道传输用户有用的信息，全噪信道传输约定的信息或者不传信息。Polar码也是一种线性块码，其编码矩阵(也称为生成矩阵)为G N，编码过程为
Figure PCTCN2018106299-appb-000001
其中，
Figure PCTCN2018106299-appb-000002
是一个二进制的行矢量，长度为N(即，码长)，也称作待编码向量，且N＝2 n，n为正整数。
Figure PCTCN2018106299-appb-000003
为编码后的母码码字。G N是一个N×N的矩阵，且
Figure PCTCN2018106299-appb-000004
Figure PCTCN2018106299-appb-000005
定义为log2 N个矩阵F 2的克罗内克(Kronecker)乘积。
其中，
Figure PCTCN2018106299-appb-000006
以上各式中涉及的加法、乘法操作均为二进制伽罗华域上的加法、乘法操作。
Polar码的编码过程中，
Figure PCTCN2018106299-appb-000007
中的一部分比特用来携带信息，称为信息比特集合。这些比特的索引的集合记作A。另外的一部分比特设置为接收端和发送端预先约定的固定值，称之为固定比特集合或冻结比特(frozen bits)集合，其索引的集合用A的补集A c表示。Polar码的编码过程相当于
Figure PCTCN2018106299-appb-000008
这里，F N(A)是F N中由集合A中的索引对应的行得到的子矩阵。F N(A C)是F N中由集合A C中的索引对应的行得到的子矩阵。u A为
Figure PCTCN2018106299-appb-000009
中的信息比特集合，数量为K。
Figure PCTCN2018106299-appb-000010
为
Figure PCTCN2018106299-appb-000011
中的固定比特集合，其数量为(N-K)，是已知比特。这些固定比特通常被设置为0，但是只要接收端和发送端预先约定，固定比特可以被任意设置。从而，Polar码的编码输出可简化为
Figure PCTCN2018106299-appb-000012
这里的u A为
Figure PCTCN2018106299-appb-000013
中的信息比特集合，u A为长度K的行矢量，即|A|＝K,符号||表示集合中元素的个数，K为信息块大小，F N(A)是矩阵F N中由集合A中的索引对应的那些行得到的子矩阵，F N(A)是一个N×N的矩阵。
Polar码的构造过程即集合A的选取过程，决定了Polar码的性能。Polar码的构造过程通常是，根据母码码长N确定共存在N个极化信道。获取这N个极化信道的可靠度， 将可靠度最高的前K个极化信道的序号(或者说，索引)作为集合A的元素，剩余(N-K)个极化信道的序号作为固定比特序号集合A C的元素。集合A决定了信息比特的位置，集合A C决定了固定比特的位置。常见的构造方法有密度进化(density evolution,DE)、高斯近似(Gaussian approximation,GA)等。
在Polar码的编码过程中，编码器输出的母码长度都是2的整数次幂，当实际所需的长度非2的整数次幂的情况下，需要对母码进行速率匹配，得到所需的码长。Polar码的速率匹配的方法包括缩短(shorten)、打孔(Puncture)等。
下面对缩短和打孔的原理作简单介绍。
(一)缩短
缩短操作的原理是，通过调整待编码向量，使得编码后的母码码字中某些比特为固定值(一般为0)，而码字中的其它比特尽量不受影响。这样，发送端就可以不发送这些拥有固定值(例如为0)的比特，而接收端仍然可以知道它们的值(一般为0)，起到码字缩短的作用。接收端由于已知被缩短的比特位置为0，解速率匹配时将这些位置的对数似然比(likelihood rate,LLR)填为正无穷进行译码。
(二)打孔
打孔的原理和缩短不同，从缩短的原理中可以知道，编码后的码字中被缩短的位置的比特一定为0，而打孔中打掉的码字比特不一定为0。因此，接收端在解速率匹配时，会将需要打孔的位置的LLR填为0进行译码。
需要说明的是，LLR是指对数似然比(likelihood Rate，LLR)。在Polar译码中，LLR表示，将一个比特判为0的概率与判为1的概率的比值，再对这个比值取对数的结果。
由此可以理解的是，在缩短方式中，由于X域缩短位置的比特一定为0，因此在解速率匹配时，译码端将这些缩短位置的LLR填为正无穷进行译码。而在打孔方式中，由于X域打掉的比特不一定是0，因此，在解速率匹配时，译码端将打孔位置的LLR填为0进行译码，表示这些打孔位置的比特为0或者为1的概率各占50％。
本申请提出一种极化码的速率匹配的方法，先确定U域放置强制冻结比特的位置，再根据U域放置强制冻结比特的位置确定X域的缩短位置或打孔位置，可以在选择极化码的速率匹配方案时，减小码字域的搜索空间。
本申请实施例提供的速率匹配的流程参见图3，图3为本申请实施例提供的速率匹配的示意性流程图。
本申请实施例涉及的Polar码的速率匹配及解速率匹配方案，分别在执行Polar码编码和译码的网元中实现。具体的，对于上行传输，速率匹配在终端完成，解速率匹配在基站完成。反之，对于下行传输，速率匹配在基站完成，解速率匹配在终端完成。
下面结合图4，对本申请实施例的极化码的速率匹配的方法的作详细说明。图4为本申请实施例提供的编码端和译码端的交互图。
310、编码端确定N个待编码比特对应的第一索引集合。
其中，第一索引集合包括放置强制冻结比特的Z个极化信道的索引，该Z个极化信道为该N个待编码比特对应的N个极化信道的子集，N＝2 n，Z<N，n和Z为正整数。
根据Polar码的基本理论可以知道，N个待编码比特对应N个极化信道。而本申请实施例中所说的第一索引集合是指编码端从这N个极化信道中确定的放置强制冻结比特的Z 个极化信道的索引(或者说，序号)。
具体地，无论对于缩短或是打孔，都可以通过多种方式确定第一索引集合。例如，比特逆序、分组等。以母码长度为N＝8，速率匹配后的码长为5，极化信道序号为{0,1,2,…,6,7}为例。可知，对母码码字进行速率匹配，需要去掉3个比特。
如果采用自然顺序的打孔方式，则第一索引集合为{0,1,2}；如果采用自然顺序的缩短方式，则第一索引集合为{5,6,7}。
如果采用比特逆序打孔，操作过程为：
将{0,1,2}展开为长度为log 2(8)＝3的二进制表示，即为{000,001,010}。对该二进制表示作翻转，得到{000,100,010}，翻转后二进制数值对应的十进制数值为{0,4,2}，即得到第一索引集合为{0,4,2}。
如果采用比特逆序缩短方式，操作过程为：
将{5,6,7}展开为长度为3的二进制表示{101,110,111}，作翻转得到{101,011,111}。十进制表示为{5,3,7}，即第一索引集合为{5,3,7}。
320、编码端获取长度为N的第一码字，第一码字是对该N个待编码比特进行极化编码得到的。
330、编码端根据第一索引集合，对第一码字进行速率匹配，得到长度等于M的第二码字。其中，M<N，且M为大于0的正整数。
本申请实施例中，编码端是基于首先在U域确定放置强制冻结比特的子信道的索引的集合(即，第一索引集合)，再由第一索引集合确定X域的缩短位置或打孔位置进行速率匹配的。
340、编码端发送第二码字。
接收端接收解调后的信息。
可以理解的是，编码端发送第二码字需要经过调制、映射过程。调制、映射的过程可以参考现有技术，此处不作详述。
350、译码端对解调后的信息进行解速率匹配，并对解速率匹配之后的比特序列进行译码，得到译码后序列。
应理解，译码端输入的是解调后的LLR，即这里所说的解调后的信息。
译码端的译码过程正是编码端对N个待编码比特进行极化编码、速率匹配的逆过程。因此，译码端先对解调后的信息进行解速率匹配，再对解速率匹配之后的比特进行译码，得到译码后序列。
图4中所示的步骤310-350仅是作为示例。实际上，在进行信道编解码时，编码端进行速率匹配和译码端进行解速率匹配都是基于同一个Pattern的。换句话说，首先确定Pattern，确定Pattern之后，编码端基于这个Pattern进行速率匹配，译码端基于这个Pattern进行解速率匹配。因此，在进行速率匹配时，编码端可能不需要执行步骤310和320。在步骤330，编码端可以直接基于预先确定采用的Pattern进行速率匹配。而确定pattern的方法可以是本申请实施例中描述的确定第二索引集合的方法。第二索引集合是根据第一索引集合确定的。下文会对如何根据第一索引集合确定第二索引集合作详细说明。
下面对于步骤330中，如果根据第一索引集合，对第一码字进行速率匹配作详细说明。
下文针对缩短方式和打孔方式，分别进行描述。
(一)缩短方式
根据U域放置强制冻比特的子信道的索引，确定X域的缩短位置。
在本申请实施例中，将U域放置强制冻结比特的子信道的索引的集合记作第一索引集合，将X域的缩短位置的集合或打孔位置的集合记作第二索引集合。
根据Polar码的编码理论，在缩短方式下，U域放置强制冻结比特的位置与X域的缩短位置相同。
参见图5，图5为本申请实施例提供的Polar码的缩短流程。
在图5中，将U域放置强制冻结比特的子信道的索引组成的集合记作F S。
401、编码端确定U域放置强制冻结比特的子信道的索引的集合F S。
其中，U域放置强制冻结比特的子信道的索引的选择可以以Polar码的性能为依据。而根据Polar码的编码理论可以知道，放置强制冻结比特的子信道对应的X域的编码结果一定为0，满足这个条件的F S并不唯一，可以通过多种方式确定。例如，比特逆序或者分组等。
402、编码端获取除了集合F S中的索引指示的子信道之外的其余子信道的可靠度。
编码端可以通过公式计算或者查表等方式，确定其余子信道的可靠度。这里所说的其余的子信道，是指N个待编码比特对应的N个极化信道中除了F S中包括的索引指示的子信道之外的子信道。
403、编码端在所述其余子信道中选出可靠度最高的K个子信道用来承载信息比特，剩下的子信道用来承载冻结比特。
编码端根据步骤402中获取的其余子信道的可靠度的大小，从中选择可靠度最高的K个极化信道用来承载信息比特，剩下的子信道用来承载冻结比特。
404、编码端对N个待编码比特进行极化编码，得到第一码字。
应理解，对待编码比特进行极化编码后的母码码字(即，第一码字)的长度等于2的整数次幂。
405、编码端根据U域的F S，确定X域的缩短位置X S。
其中，X域的缩短位置X S与U域放置强制冻结比特的位置相同。
406、编码端将第一码字中的缩短位置X S的比特缩短，得到长度为M的第二码字。
其中，M<N，且M和N为正整数。需要注意的是，经过速率匹配之后的第二码字的长度M不再受限于2的整数次幂的取值，M的取值可以为小于N的任意一个正整数。例如，N＝16，如果F S中包括3个元素，则M＝13。又例如，N＝8，如果F S中包括3个元素，则M＝5。
(二)打孔方式
参见图6，图6为本申请实施例提供的打孔流程。
501、编码端确定U域放置强制冻结比特的子信道的索引的集合F P。
502、编码端获取除了F P中的索引指示的子信道之外的其余子信道的可靠度。
503、编码端在所述其余子信道中选出可靠度最高的K个子信道用于承载信息比特，剩下的子信道用于承载冻结比特。
504、编码端对N个待编码比特进行Polar编码，得到第一码字。
505、编码端根据U域的F P，确定X域的打孔位置X P。
506、编码端将第一码字中的打孔位置X P的比特打孔，得到所需码长等于M的第二码字。
在缩短模式下，U域放置强制冻结比特的位置与X域的缩短位置相同。而在打孔模式下却并不是如此。下面详细说明步骤505中，根据U域放置强制冻结比特的子信道的索引的集合F P，如何确定X域的打孔位置X P。
(1)根据U域放置强制冻结比特的子信道的索引的集合F P，确定第一比特序列。
根据U域放置强制冻结比特的索引的集合F P，可以得到一个长为N的比特序列F＝[f 1,f 2,f 3,…,f N]。其中，在这个比特序列中，F P中的索引指示的位置上放置比特0，其它位置上放置比特1。
在本申请实施例中，第一比特序列可以是这个长度为N的比特序列F本身，或者，也可以是对这个比特序列F进行翻转之后得到的比特序列。
为了便于描述，下文将比特序列F记作P 1，则P 1＝[f 1,f 2,f 3,…,f N]。对比特序列F进行翻转，得到的比特序列记作P 2，P 2＝[f N,f N-1,f N-2,…,f 1]。
(2)对比特序列P 1和/或比特序列P 2进行比特对调处理，得到L个第二比特序列。
在本申请实施例中，比特对调处理是将一个比特序列第i个索引指示的位置上放置的比特和第N/2+i个索引指示的位置上放置的比特进行对调，i遍历{0,1,…,N/2-1}，该L个第二比特序列互不相同。
(3)从该L个第二比特序列中的每个第二比特序列中读取放置比特0的位置的索引，得到至少一个第二索引集合，其中，每个第二比特序列对应一个第二索引集合。
后续，每个第二索引集合都可以作为X域的打孔位置的集合。
下面以N＝8，F P＝{0,1,2}为例进行说明。
根据F P＝{0,1,2}，可以得到一个长度为N＝8的比特序列F＝[f 1,f 2,f 3,…,f 8]。其中，F中索引位置为0,1和2的位置上放置比特0，其余位置上放置比特1。即，F＝[00011111]。由此，可以得到P 1＝F＝[00011111]，P 2＝[11111000]。
将P 1中的第i个索引指示的位置上放置的比特和第
Figure PCTCN2018106299-appb-000014
个索引指示的位置上放置的比特进行对调，i遍历
Figure PCTCN2018106299-appb-000015
对于这个例子而言，即是将第一比特序列中的第i个位置和第4+i个位置的比特进行对调，i遍历{0,1,2,3}。
这里需要说明的是，如果将第i个位置的比特和第4+i个位置的比特称作一组比特的对调，在对调的过程中，可以每次选择对调一组或多组，得到一个第二比特序列。
对P 1＝F＝[0 0 0 1 1 1 1 1]进行比特对调处理，得到如下8个第二比特序列：
[0 0 0 1 1 1 1 1]、[1 0 0 1 0 1 1 1]、[0 1 0 1 1 0 1 1]、[0 0 1 1 1 1 0 1]、
[1 1 0 1 0 0 1 1]、[0 1 1 1 1 0 0 1]、[1 0 1 1 0 1 0 1]、[1 1 1 1 0 0 0 1]。
此外，也可以对P 2＝[1 1 1 1 1 0 0 0]执行比特对调处理，同样地，也可以得到如下8个第二比特序列：
[1 0 0 0 1 1 1 1]、[1 1 0 0 1 0 1 1]、[1 0 1 0 1 1 0 1]、[1 0 0 1 1 1 1 0]
[1 1 1 0 1 0 0 1]、[1 0 1 1 1 1 0 0]、[1 1 0 1 1 0 1 0]、[1 1 1 1 1 0 0 0]
接下来，分别从每一个第二比特序列中读取比特值为0的位置的索引，得到一个第二索引集合。由此可知，读取这多个第二比特序列，得到多个第二索引集合。换句话说，每读取一个第二比特序列，即可得到一个第二索引集合。
读取由P 1得到的8个第二比特序列，得到如下8个第二索引集合：{0,1,2}，{1,2,4}，{0,2,5}，{0,1,6}，{2,4,5}，{0,5,6}，{1,4,6}，{4,5,6}。
读取由P 2得到的8个第二比特序列，得到如下8个第二索引集合：{1,2,3}，{2,3,5}，{1,3,6}，{1,2,7}，{3,5,6}，{1,6,7}，{2,5,7}，{5,6,7}。
从上述16个第二索引集合中任意选取一个作为X域的打孔位置的集合。例如，如果选取{0,1,2}进行速率匹配，则将第一码字中索引位置为0、1和2的位置确定为打孔位置。又例如，如果选取{1,4,6}进行速率匹配，则将第一码字中索引位置为1、4和6的位置确定为打孔位置。
可以理解的是，在对比特序列P 1进行比特对调的过程中，如果第i个位置的比特与第
Figure PCTCN2018106299-appb-000016
个位置的比特相同(同为0或同为1)，则对调之后得到的比特序列与P 1相同。此时，对调之后的序列不应该计算在第二比特序列之内。
参见图7，图7为比特对调过程的示意图。图7中N＝8，F P＝{0,1,2}，由F P确定的比特序列为F＝[0 0 0 1 1 1 1 1]，并由此确定P 1＝F＝[0 0 0 1 1 1 1 1]，P 2＝[1 1 1 1 1 0 0 0]。
如7所示，对P 1进行比特对调处理得到的比特序列包括P 11,P 12,…,P 18，对P 2进行比特对调处理得到的比特序列包括P 21,P 22,…,P 28。分别读取P 11,P 12,…,P 18中放置比特0的位置的索引，得到多个第二索引集合。分别读取P 21,P 22,…,P 28中放置比特0的位置的索引，得到多个第二比特索引集合。
从这多个第二索引集合种任意选择一个第二索引集合，选择的这个第二索引集合中包括的索引作为速率匹配的打孔位置。
需要说明的是，在信道编码时，速率匹配和解速率匹配都是基于一个Pattern(模式)的。通常是确定Pattern之后，编码端(也即发送端)基于这个Pattern进行速率匹配，而解码端(也即接收端)基于这个Pattern进行解速率匹配。
本申请实施例中描述的确定第二索引集合的方法，即是确定Pattern的方法。
编码端基于这个Pattern，对长度等于N的第一码字进行速率匹配，得到所需长度(例如，长度等于M)的第二码字，其中，M<N，M为大于0的正整数。
后续，编码端将第二码字经过调制、映射，发送给译码端。
译码端基于相同的Pattern，进行解速率匹配。
以上对本申请提供的极化码的速率匹配的方法作了详细说明。在本申请的技术方案中，编码端先确定U域放置强制冻结比特的子信道的索引，再确定X域的缩短位置或打孔位置来实现极化码的速率匹配，可以更直接的控制速率匹配的性能。
从上面描述的确定X域的打孔位置的过程可以看出，在X域搜索性能较好的打孔位置时，许多打孔方案的效果是等效的。而直接在U域选择放置强制冻结比特的的子信道的索引，可以减小搜索空间。
下文结合图8和图9，详细说明本申请实施例提供的极化码的速率匹配的装置。
图8为本申请提供的极化码的速率匹配的装置600的示意图。如图8所示，装置600 包括处理单元610和发送单元620。
其中，处理单元610用于：
确定N个待编码比特对应的第一索引集合，第一索引集合包括放置强制冻结比特的Z个极化信道的索引，该所述Z个极化信道为该N个待编码比特对应的N个极化信道的子集，N＝2 n，Z<N，n和Z为正整数；
获取长度为N的第一码字，第一码字是对该N个待编码比特进行极化编码得到的；
根据第一索引集合，对第一码字进行速率匹配，得到长度为M的第二码字，其中，M<N且M为正整数；以及，
发送单元620，用于发送该长度为M的第二码字。
进一步地，所述处理单元具体用于：
根据所述第一索引集合，确定至少一个第二索引集合，每个第二索引集合中为确定的所述第一码字中被打孔位置或被缩短位置的索引；
根据所述至少一个第二索引集合中的任意一个第二索引集合，对所述第一码字进行速率匹配。
所述处理单元具体用于从所述第一码字对应的N个索引中，读取与所述第一索引集合中的索引相同的索引，得到一个所述第二索引集合。
进一步地，所述处理单元具体用于：
根据所述第一索引集合，确定第一比特序列，所述第一比特序列的长度等于N；
对所述第一比特序列进行比特对调处理，得到至少一个第二比特序列，其中，所述比特对调处理是将所述第一比特序列中的第i个索引指示的位置上放置的比特和第N/2+i个索引指示的位置上放置的比特进行对调，i遍历{0,1,…,N/2-1}，其中，所述至少一个第三比特序列互不相同；
从所述至少一个第二比特序列中的每个第二比特序列中读取放置比特0的位置的索引，得到至少一个所述第二索引集合，其中，每个第二比特序列对应一个第二索引集合。
进一步地，所述第一比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同。
进一步地，所述处理单元具体用于：
根据所述第一索引集合，确定第三比特序列，所述第三比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同；
对所述第三比特序列进行翻转，得到所述第一比特序列。
进一步地，所述处理单元具体用于，将任意一个所述第二索引集合中的索引在所述第一码字中指示的位置作为所述第一码字的被缩短位置或被打孔位置，对所述第一码字进行速率匹配，得到所述第二码字。
本申请实施例的装置600中的各单元和上述其它操作或功能分别为了实现本申请提供的各实施例中的极化码的速率匹配的方法。为了简洁，此处不再赘述。
本申请实施例中，编码端是基于首先在U域确定放置强制冻结比特的子信道的索引的集合(即，第一索引集合)，再由第一索引集合确定X域的缩短位置或打孔位置进行速率匹配，可以在选择极化码的速率匹配方案时，减小码字域的搜索空间
图9为本申请提供的极化码的速率匹配的设备700的示意性结构图。如图9所示，设 备700包括：一个或多个处理器701，一个或多个存储器702，一个或多个收发器703。处理器701用于控制收发器703收发信号，存储器702用于存储计算机程序，处理器701用于从存储器702中调用并运行该计算机程序，使得设备700执行交织方法各实施例的相应流程和/或操作。为了简洁，此处不再赘述。
需要说明的是，图8中所示的装置600可以通过图9中所示的设备700实现。例如，处理单元610可以由处理器701实现，发送单元620可以由收发器703实现等。
此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行本申请各实施例中的极化码的速率匹配的方法。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行上述任意一个实施例中描述的极化码的速率匹配的方法。
本申请还提供一种芯片(或者说，芯片系统)，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行本申请各方法实施例中的极化码的速率匹配的方法。
这里，安装有该芯片的通信设备可以是进行极化码的速率匹配的设备。例如，在上行传输时，终端设备安装有该芯片，以执行本申请提供的速率匹配的方法，例如图1中所示的终端设备102，网络设备101进行解速率匹配。在下行传输时，网络设备101安装有该芯片，以执行本申请提供的速率匹配的方法，终端设备103进行解速率匹配。
本申请还提供一种编码装置，该编码装置具有实现上述实施例中的极化码的速率匹配的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
此外，编码装置除了可以执行本申请提供的速率匹配的方法，还具备执行和极化码编码相关流程的其它功能，例如，Polar编码、调制等。
应理解，在进行上行传输时，编码装置具体可以为终端设备，例如图1中所示的终端设备102。在进行下行传输时，编码装置具体可以为网络设备，例如图1中所示的网络设备101。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，编码装置包括：输入接口电路，用于获取第一索引集合和第一码字；逻辑电路，用于根据第一索引集合对长度为N的第一码字进行速率匹配，得到长度为M的第二码字；输出接口电路，用于输出第二码字。其中，M<N，且M和N为正整数，N＝2 n，n为大于0的整数。
可选的，编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，编码装置可以实现上述实施例中任意一种可能的设计中所述的交织方法。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
可选的，上述的存储器与存储器可以是物理上相互独立的单元，或者，存储器也可以和处理器集成在一起。
在本申请实施例中，当执行速率匹配的方法的装置为终端设备时，终端设备的结构可以如图10所示。图10为本申请实施例的终端设备800的示意性结构图。
如图10所示，终端设备800包括：收发器808和处理器804。终端设备800还可以包括存储器819，其存储计算机执行指令。
处理器804，用于确定N个待编码比特对应的第一索引集合，所述第一索引集合包括放置强制冻结比特的Z个极化信道的索引，所述Z个极化信道为所述N个待编码比特对应的N个极化信道的子集，N＝2 n，Z<N，n和Z为正整数；获取长度为N的第一码字，所述第一码字是对所述N个待编码比特进行极化编码得到的；根据所述第一索引集合，对所述第一码字进行速率匹配，得到长度为M的第二码字，其中，M<N且M为正整数；
收发器808，用于根据处理器804的指示，输出长度为M的第二码字。
其中，处理器804可以通过终端设备的内部通信接口获取长度为N的第一码字。
进一步地，上述处理器804可以用于执行方法实施例中由速率匹配的装置内部实现的动作，而收发器808可以用于执行方法实施例中的接收或发送动作。具体请见前面方法实施例中的描述，此处不再赘述。
上述处理器804和存储器819可以集成为一个处理装置，处理器804用于执行存储器819中存储的程序代码来实现上述功能。具体实现时，该存储器819也可以集成在处理器804中。
上述终端设备800还可以包括电源812，用于给终端设备800中的各种器件或电路提供电源。上述终端设备800可以包括天线810，用于将收发器808输出的数据或信息通过无线信号发送出去。
除此之外，为了使得终端设备800的功能更加完善，该终端设备800还可以包括输入单元814，显示单元816，音频电路818，摄像头820和传感器822等中的一个或多个。音频电路还可以包括扬声器8182，麦克风8184等。
需要说明的是，在信道编码时，速率匹配和解速率匹配都是基于一个Pattern(模式)的。确定Pattern之后，发送端基于这个Pattern进行速率匹配，而接收端基于这个Pattern进行解速率匹配。
在本申请实施例中，确定第二索引集合的方法，即是确定Pattern的方法。
因此，本申请还提供一种解速率匹配的装置，该装置具有实现解速率匹配的方法的功能。这些功能可以通过硬件实现，或者通过硬件执行相应的软件实现。
此外，解速率匹配的装置可以为芯片，安装有该芯片的通信设备可以执行解速率匹配的方法。在进行上行传输时，该芯片可以安装在网络设备上，使得网络设备具有实现解速率匹配的方法的功能。此时，解速率匹配的装置可以如图1中所示的网络设备101。在进行下行传输时，该芯片可以安装在终端设备上，使得终端设备具有实现解速率匹配的方法的功能。如图1中所示的终端设备103。
此外，本申请提供一种解速率匹配的设备，该设备包括一个或多个处理器，一个或多个存储器，一个或多个收发器(每个收发器包括发射机和接收机)。发射机或接收机通过天线收发信号。存储器用于存储计算机程序指令(或者说，代码)。处理器用于执行存储器中存储的指令，当指令被执行时，处理器执行解速率匹配的方法。
本申请还提供一种芯片(或者说，芯片系统)，包括存储器和处理器，存储器用于存 储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行解速率匹配的方法。
此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述实施例中的解速率匹配的方法。
本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行上述任意一个实施例中描述的解速率匹配的方法。
本申请还提供一种译码装置，该译码装置具有实现上述本申请实施例中的解速率匹配的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。除此之外，译码装置还具有实现Polar码译码的相关功能，例如，解调、译码等。
以上实施例中，处理器可以为中央处理器(central processing unit，CPU)、微处理器、特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路等。例如，处理器可以包括数字信号处理器设备、微处理器设备、模数转换器、数模转换器等。处理器可以根据这些设备各自的功能而在这些设备之间分配移动设备的控制和信号处理的功能。此外，处理器可以包括操作一个或多个软件程序的功能，软件程序可以存储在存储器中。
处理器的所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
存储器可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备。也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。
结合前面的描述，本领域的技术人员可以意识到，本文实施例的方法，可以通过硬件(例如，逻辑电路)，或者软件，或者硬件与软件的结合来实现。这些方法究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
当上述功能通过软件的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。在这种情况下，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟 悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种极化码的速率匹配的方法，其特征在于，包括：
    确定N个待编码比特对应的第一索引集合，所述第一索引集合包括放置强制冻结比特的Z个极化信道的索引，所述Z个极化信道为所述N个待编码比特对应的N个极化信道的子集，N＝2 n，Z<N，n和Z为正整数；
    获取长度为N的第一码字，所述第一码字是对所述N个待编码比特进行极化编码得到的；
    根据所述第一索引集合，对所述第一码字进行速率匹配，得到长度为M的第二码字，其中，M<N且M为正整数；
    发送长度为M的第二码字。
  2. 根据权利要求1所述的方法，其特征在于，根据所述第一索引集合，对所述第一码字进行速率匹配，包括：
    根据所述第一索引集合，确定至少一个第二索引集合，每个第二索引集合中为确定的所述第一码字中被打孔位置或被缩短位置的索引；
    根据所述至少一个第二索引集合中的任意一个第二索引集合，对所述第一码字进行速率匹配。
  3. 根据权利要求1或2所述的方法，其特征在于，根据所述第一索引集合，确定至少一个第二索引集合，包括：
    从所述第一码字对应的N个索引中，读取与所述第一索引集合中的索引相同的索引，得到一个所述第二索引集合。
  4. 根据权利要求1或2所述的方法，其特征在于，根据第一索引集合，确定至少一个第二索引集合，包括：
    根据所述第一索引集合，确定第一比特序列，所述第一比特序列的长度等于N；
    对所述第一比特序列进行比特对调处理，得到至少一个第二比特序列，其中，所述比特对调处理是将所述第一比特序列中的第i个索引指示的位置上放置的比特和第N/2+i个索引指示的位置上放置的比特进行对调，i遍历{0,1,…,N/2-1}，其中，所述至少一个第三比特序列互不相同；
    从所述至少一个第二比特序列中的每个第二比特序列中读取放置比特0的位置的索引，得到至少一个所述第二索引集合，其中，每个第二比特序列对应一个第二索引集合。
  5. 根据权利要求4所述的方法，其特征在于，所述第一比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同。
  6. 根据权利要求4所述的方法，其特征在于，所述根据所述第一索引集合，确定第一比特序列，包括：
    根据所述第一索引集合，确定第三比特序列，所述第三比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同；
    对所述第三比特序列进行翻转，得到所述第一比特序列。
  7. 根据权利要求2至6中任一项所述的方法，其特征在于，所述根据所述至少一个 第二索引集合中的任意一个第二索引集合，对所述第一码字进行速率匹配，包括：
    将任意一个所述第二索引集合中的索引在所述第一码字中指示的位置作为所述第一码字的被缩短位置或被打孔位置，对所述第一码字进行速率匹配。
  8. 一种极化码的速率匹配的装置，其特征在于，包括：
    处理单元，用于确定N个待编码比特对应的第一索引集合，所述第一索引集合包括放置强制冻结比特的Z个极化信道的索引，所述Z个极化信道为所述N个待编码比特对应的N个极化信道的子集，N＝2 n，Z<N，n和Z为正整数；
    所述处理单元，还用于获取长度为N的第一码字，所述第一码字是对所述N个待编码比特进行极化编码得到的；
    所述处理单元，还用于根据所述第一索引集合，对所述第一码字进行速率匹配，得到长度为M的第二码字，其中，M<N且M为正整数；
    发送单元，用于发送所述长度为M的第二码字。
  9. 根据权利要求8所述的装置，其特征在于，所述处理单元具体用于：
    根据所述第一索引集合，确定至少一个第二索引集合，每个第二索引集合中为确定的所述第一码字中被打孔位置或被缩短位置的索引；
    根据所述至少一个第二索引集合中的任意一个第二索引集合，对所述第一码字进行速率匹配。
  10. 根据权利要求8或9所述的装置，其特征在于，所述处理单元具体用于从所述第一码字对应的N个索引中，读取与所述第一索引集合中的索引相同的索引，得到一个所述第二索引集合。
  11. 根据权利要求8或9所述的装置，其特征在于，所述处理单元具体用于：
    根据所述第一索引集合，确定第一比特序列，所述第一比特序列的长度等于N；
    对所述第一比特序列进行比特对调处理，得到至少一个第二比特序列，其中，所述比特对调处理是将所述第一比特序列中的第i个索引指示的位置上放置的比特和第N/2+i个索引指示的位置上放置的比特进行对调，i遍历{0,1,…,N/2-1}，其中，所述至少一个第三比特序列互不相同；
    从所述至少一个第二比特序列中的每个第二比特序列中读取放置比特0的位置的索引，得到至少一个所述第二索引集合，其中，每个第二比特序列对应一个第二索引集合。
  12. 根据权利要求11所述的装置，其特征在于，所述第一比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同。
  13. 根据权利要求11所述的装置，其特征在于，所述处理单元具体用于：
    根据所述第一索引集合，确定第三比特序列，所述第三比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同；
    对所述第三比特序列进行翻转，得到所述第一比特序列。
  14. 根据权利要求9至13中任一项所述的装置，其特征在于，所述处理单元具体用于，将任意一个所述第二索引集合中的索引在所述第一码字中指示的位置作为所述第一码字的被缩短位置或被打孔位置，对所述第一码字进行速率匹配，得到所述第二码字。
  15. 一种极化码的速率匹配的设备，其特征在于，包括：
    处理器，用于确定N个待编码比特对应的第一索引集合，所述第一索引集合包括放置 强制冻结比特的Z个极化信道的索引，所述Z个极化信道为所述N个待编码比特对应的N个极化信道的子集，N＝2 n，Z<N，n和Z为正整数；获取长度为N的第一码字，所述第一码字是对所述N个待编码比特进行极化编码得到的；根据所述第一索引集合，对所述第一码字进行速率匹配，得到长度为M的第二码字，其中，M<N且M为正整数；
    收发器，用于发送所述长度M的第二码字。
  16. 根据权利要求15所述的设备，其特征在于，所述处理器具体用于：
    根据所述第一索引集合，确定至少一个第二索引集合，每个第二索引集合中为确定的所述第一码字中被打孔位置或被缩短位置的索引；
    根据所述至少一个第二索引集合中的任意一个第二索引集合，对所述第一码字进行速率匹配。
  17. 根据权利要求15或16所述的设备，其特征在于，所述处理器具体用于：从所述第一码字对应的N个索引中，读取与所述第一索引集合中的索引相同的索引，得到一个所述第二索引集合。
  18. 根据权利要求15或16所述的设备，其特征在于，所述处理器具体用于：
    根据所述第一索引集合，确定第一比特序列，所述第一比特序列的长度等于N；
    对所述第一比特序列进行比特对调处理，得到至少一个第二比特序列，其中，所述比特对调处理是将所述第一比特序列中的第i个索引指示的位置上放置的比特和第N/2+i个索引指示的位置上放置的比特进行对调，i遍历{0,1,…,N/2-1}，其中，所述至少一个第三比特序列互不相同；
    从所述至少一个第二比特序列中的每个第二比特序列中读取放置比特0的位置的索引，得到至少一个所述第二索引集合，其中，每个第二比特序列对应一个第二索引集合。
  19. 根据权利要求18所述的设备，其特征在于，所述第一比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同。
  20. 根据权利要求18所述的设备，其特征在于，所述根据所述第一索引集合，确定第一比特序列，包括：
    根据所述第一索引集合，确定第三比特序列，所述第三比特序列中放置比特0的位置的索引与所述第一索引集合中的索引相同；
    对所述第三比特序列进行翻转，得到所述第一比特序列。
  21. 根据权利要求16至20中任一项所述的设备，其特征在于，所述处理器具体用于：将任意一个所述第二索引集合中的索引在所述第一码字中指示的位置作为所述第一码字的被缩短位置或被打孔位置，对所述第一码字进行速率匹配。
  22. 一种芯片，其特征在于，包括存储器和处理器，所述存储器用于存储计算机程序，所述处理器用于从所述存储器中调用并运行所述计算机程序，使得安装有所述芯片的通信设备执行权利要求1至7中任一项所述的方法。
  23. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，所述计算机程序在计算机上执行时，使得计算机执行权利要求1至7中任一项所述的方法。
  24. 一种计算机程序产品，该计算机程序产品包括计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行上述权利要求1至7中任一项所述的方法。
  25. 一种极化码的速率匹配的设备，其特征在于，所述设备用于执行权利要求1-7任意一项所述的方法。
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