WO2019091444A1 - 交织方法和交织装置 - Google Patents

交织方法和交织装置 Download PDF

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Publication number
WO2019091444A1
WO2019091444A1 PCT/CN2018/114712 CN2018114712W WO2019091444A1 WO 2019091444 A1 WO2019091444 A1 WO 2019091444A1 CN 2018114712 W CN2018114712 W CN 2018114712W WO 2019091444 A1 WO2019091444 A1 WO 2019091444A1
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Prior art keywords
bit
bit sequence
bits
read
interleaving
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PCT/CN2018/114712
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English (en)
French (fr)
Inventor
王桂杰
张公正
童佳杰
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华为技术有限公司
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Publication of WO2019091444A1 publication Critical patent/WO2019091444A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of channel coding, and in particular, to an interleaving method and an interleaving apparatus.
  • Digital communication systems usually use channel coding to improve the reliability of data transmission.
  • Some channel coding uses interleaving technology to further improve the anti-interference performance during data transmission.
  • interleaving technology to further improve the anti-interference performance during data transmission.
  • On many composite channels where random errors and burst errors occur simultaneously if an error occurs, a string of data is often transmitted, resulting in burst errors exceeding the channel error correction capability and error correction capability. If the burst error is first discretized into random errors and random error correction is performed, the anti-interference performance of the system will be further improved.
  • the interleaving method is mainly divided into random interleaving and row-column interleaving.
  • Random Interleaving When calculating the interleaving sequence offline, it is necessary to store the permutation sequence for interleaving and deinterleaving. In the case of a long code length, the storage resources required for random interleaving are very large or even unacceptable. However, the interleaving of rows and columns is weak for the error correction and the error correction performance is poor.
  • the present application provides an interleaving method and an interleaving apparatus, which can improve error correction performance without increasing interlacing complexity.
  • the present application provides an interleaving method, the method comprising: acquiring a first bit sequence, where the first bit sequence includes N bits, N ⁇ 2 and being an integer; and from the first bit sequence according to at least one read interval Reading bits, obtaining L bit sets, each bit set includes at least one bit in the first bit sequence, and the bits included in any two bit sets are different in index in the first bit sequence, the L bit sets The sum of the number of bits in the middle is equal to N, where L ⁇ 2 and is an integer; according to the L bit sets, a second bit sequence is obtained; and a second bit sequence is transmitted.
  • the interleaving method in the embodiment of the present application has low interlacing complexity, but the interleaving performance is equivalent to or even better than the random interleaving performance. Therefore, the error correction performance can be improved without increasing the complexity of the interleaving.
  • the L sets of bits are sequentially arranged in a read order.
  • the reading the bits from the first bit sequence according to the at least one read interval to obtain the L bit sets comprises: according to the ith read interval, Reading at least one bit from the first bit set to the remaining bits after the (i-1)th bit set in the first bit sequence, to obtain an i-th bit set, where 1 ⁇ i ⁇ L, and i is Integer.
  • the first bit set can be directly read from the first bit sequence according to the determined read interval.
  • the ith read interval and the (i-1)th read interval are the same or different.
  • any one of the at least one read interval is determined based on a modulation order or a predetermined function.
  • an interleaving apparatus for performing the method of the first aspect or any possible implementation of the first aspect.
  • the apparatus comprises means for performing the method of the first aspect or any of the possible implementations of the first aspect.
  • the present application provides an interleaving device that includes one or more processors, one or more memories, and one or more transceivers (each transceiver including a transmitter and a receiver).
  • the transceiver is used to transmit and receive signals through the antenna.
  • the memory is used to store computer program instructions (or code).
  • the processor is operative to execute instructions stored in the memory, and when the instructions are executed, the processor performs the method of the first aspect or any of the possible implementations of the first aspect.
  • the present application provides a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform any of the above first aspects or any possible implementation of the first aspect The method in the way.
  • the present application provides a chip (or a chip system) including a memory and a processor, the memory is used to store a computer program, and the processor is configured to call and run the computer program from the memory so that the chip is installed.
  • the communication device performs the method of the first aspect described above and any one of its possible implementations.
  • the application provides a computer program product, comprising: computer program code, when the computer program code is run on a computer, causing the computer to perform the first aspect and any one of the possible The method in the implementation.
  • the present application provides an encoding apparatus having a function of implementing the method of any of the above-described first aspects and any one of the possible implementations of the first aspect. These functions can be implemented in hardware or in software by executing the corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device should also have encoding-related capabilities such as encoding, rate matching, and the like.
  • the encoding device when part or all of the functions are implemented by hardware, the encoding device comprises: an input interface circuit for acquiring a first bit sequence; and a logic circuit for performing the first aspect and the first aspect thereof An interleaving method in any of the possible designs; an output interface circuit for outputting a second bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when some or all of these functions are implemented by software, includes: a memory for storing a computer program; a processor, a computer program for executing the memory storage, when the computer program When executed, the encoding device can implement the interleaving method described in the first aspect above and any one of the possible designs of the first aspect.
  • the encoding device when some or all of these functions are implemented by software, the encoding device includes a processor, the memory for storing the computer program is located outside the encoding device, and the processor is connected to the memory through the circuit/wire for the The computer program stored in the memory is read and executed.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the interleaving method described in the implementation of the present application is performed by the transmitting end of data and/or information. At the receiving end of the data and/or information, the received bit sequence needs to be deinterleaved. It is well known to those skilled in the art that deinterleaving is the inverse of interleaving. Based on the interleaving method described in the above first aspect and any of its possible implementation manners, those skilled in the art can easily obtain a method of deinterleaving, which is not described in detail herein.
  • the present application provides an apparatus for deinterleaving, and in particular, the apparatus for deinterleaving includes means for performing a method of deinterleaving.
  • the present application also provides a deinterleaved device that includes one or more processors, one or more memories, and one or more transceivers (the transceiver includes a transmitter and a receiver).
  • the transmitter or receiver transmits and receives signals through the antenna.
  • the memory is used to store computer program instructions (or code).
  • the processor is configured to execute instructions stored in the memory, and when the instructions are executed, the processor performs a method of deinterleaving.
  • the present application provides a computer readable storage medium having stored therein computer instructions that, when run on a computer, cause the computer to perform a method of deinterleaving.
  • the application also provides a computer program product comprising: computer program code, a method of causing a computer to perform deinterleaving when the computer program code is run on a computer.
  • the present application also provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted performs The interleaving method in the method embodiments of the present application.
  • the present application also provides a decoding apparatus having a function of implementing the method of deinterleaving as described in the embodiments of the present application. These functions can be implemented in hardware or in software by executing the corresponding software.
  • the decoding device also has associated functions for implementing decoding, such as de-rate matching, decoding, and the like.
  • FIG. 1 is a wireless communication system 100 suitable for use in an embodiment of the present application.
  • Figure 2 is a basic flow diagram for communicating using wireless technology.
  • FIG. 3 is a flowchart of an interleaving method in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a process of reading L bit sets from a first bit sequence according to an embodiment of the present application.
  • FIG. 5 is an example of an interleaving method in an embodiment of the present application.
  • FIG. 6 is another example of an interleaving method of an embodiment of the present application.
  • FIG. 7 is still another example of the interleaving method of the embodiment of the present application.
  • FIG. 8 is a schematic diagram of an interleaving apparatus 500 according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an interleaving device 700 according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a terminal device 800 according to an embodiment of the present application.
  • FIG. 1 is a wireless communication system 100 suitable for use in an embodiment of the present application.
  • the wireless communication system can include at least one network device 101 in communication with one or more terminal devices (e.g., terminal device 102 and terminal device 102 shown in FIG. 1).
  • the network device 101 may be a base station, or may be a device integrated with a base station controller, or may be another device having similar communication functions.
  • the wireless communication system mentioned in the embodiments of the present application includes, but is not limited to, a narrow band-internet of things (NB-IoT), a global system for mobile communications (GSM), and an enhanced data rate.
  • GSM evolution EDGE
  • WCDMA wideband code division multiple access
  • CDMA2000 code division multiple access
  • TD-SCDMA time division synchronization code
  • LTE long term evolution
  • 5G mobile communication systems namely enhanced mobile broadband (eMBB) ), ultra reliable low latency communications (URLLC) and enhanced machine type of communication (eMTC) or new communication systems that will emerge in the future.
  • eMBB enhanced mobile broadband
  • URLLC ultra reliable low latency communications
  • eMTC enhanced machine type of communication
  • the terminal devices involved in the embodiments of the present application may include various handheld devices having wireless communication functions, in-vehicle devices, wearable devices, computing devices, or other processing devices connected to the wireless modem.
  • the terminal device may be a mobile station (MS), a subscriber unit, a cellular phone, a smart phone, a wireless data card, a personal digital assistant (PDA) computer, A tablet computer, a wireless modem, a handset, a laptop computer, a machine type communication (MTC) terminal, and the like.
  • MS mobile station
  • PDA personal digital assistant
  • MTC machine type communication
  • the network device 101 and the terminal device in FIG. 1 communicate using wireless technology.
  • the network device sends a signal, it is the transmitting end, and the terminal device is the receiving end.
  • the network device receives the signal, it is the receiving end, and the terminal device is the transmitting end.
  • Figure 2 is a basic flow diagram for communicating using wireless technology.
  • the source of the transmitting end is sequentially transmitted on the channel after source coding, channel coding, rate matching and modulation. After receiving the signal, the receiving end obtains the sink after demodulation, de-rate matching, channel decoding, and source decoding.
  • Channel coding is one of the core technologies of wireless communication systems, and its performance improvement will directly improve network coverage and user transmission rate.
  • an interleaving technique can be further introduced. The idea of interleaving technology is to separate symbols in time and convert a memory channel into a memoryless channel, so that the code for correcting random errors can also be applied to the noise burst channel.
  • Random interleaving is superior in average performance, but due to the randomness of interleaving, there is no guarantee that each interleaving will have superior performance. And in the case of offline interleaving, it is necessary to store a large number of permutation sequences for interleaving and deinterleaving. When the code length is long, the storage resources required for random interleaving are large, causing a large hardware load to the encoder, and is even unacceptable. In addition, the complexity of random interleaving is higher. The scheme of interlacing is simple, but the randomization of data is weak, and the interleaving performance is not ideal.
  • the present application proposes an interleaving method, which can improve error correction performance without increasing the complexity of interleaving.
  • the interleaving method of the embodiment of the present application will be described in detail below.
  • FIG. 3 is a flowchart of an interleaving method in an embodiment of the present application.
  • the first bit sequence includes N bits, where N ⁇ 2 and is an integer.
  • the L bit sets are obtained by reading bits from the first bit sequence.
  • the sum of the number of bits in the L bit sets is equal to N.
  • the bits included in any two bit sets are different in index in the first bit sequence.
  • the N bits included in the first bit sequence are placed in L bit sets, respectively.
  • a second bit sequence can be obtained according to the L bit sets, thereby completing interleaving.
  • the first bit sequence is a bit sequence to be interleaved
  • the interleaved bit sequence is a second bit sequence
  • the second bit sequence can be generated in various ways.
  • L bit sets are combined and sorted to obtain a second bit sequence.
  • the L bit sets are sequentially arranged in order of reading the L bit sets from the first bit sequence to obtain a second bit sequence.
  • the second bit sequence is mapped, modulated, and transmitted.
  • FIG. 4 is a schematic diagram of a process of reading L bit sets from a first bit sequence according to an embodiment of the present application.
  • the interleaving process can be described as: first acquiring a first bit sequence.
  • the bits are read from the first bit sequence at the first reading interval to obtain a first bit set (hereinafter referred to as bit set 1).
  • bit set 2 bits are read from the remaining bits other than the bits in the first bit set from the first bit sequence, and a second bit set (hereinafter referred to as bit set 2) is obtained.
  • bit set 2 a second bit set
  • bit set 3 the bits are read from the first bit sequence except the bits in the first bit set and the second bit set, and the third bit set is obtained (hereinafter referred to as bit set 3).
  • the first bit set is removed from the first bit sequence to the remaining bits other than the bits in the (i-1)th bit set, and the bit is read to obtain the ith. Bit set. And so on until all the bits in the first bit sequence are read.
  • the bit set 1 the bit set 2, ..., the bit set L, the second bit sequence can be obtained.
  • i ⁇ 2 the i-th bit set is read from the remaining bits other than the bits in the first bit set to the (i-1)th bit set in the first bit sequence.
  • the second bit sequence is obtained according to the L bit sets, and there may be multiple ways.
  • bit set 1 bit set 2
  • bit set L bit set L in the order of reading the L bit sets from the first bit sequence.
  • the L bit sets are sequentially arranged to obtain a second bit sequence.
  • the order of the L bit sets read out in sequence is scrambled and reordered to form a second bit sequence.
  • the ith read interval corresponds to the ith bit set, where the ith read interval is a read used when the bit is read from the first bit sequence to form the ith bit set. interval.
  • the ith read interval refers to an interval in a bit sequence composed of the first bit set and the remaining bits of the (i-1)th bit set removed from the first bit sequence.
  • the first bit sequence ⁇ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,23,24,25,26,27,28,29,30,31 ⁇ .
  • the bit set 1 ⁇ 1, 6, 11, 16 ⁇ read from the first bit sequence.
  • the ith read interval and the (i-1)th read interval may be the same or different, i ⁇ 1 and an integer.
  • the second bit sequence obtained from the first bit sequence is the process of interleaving. Before and after interleaving, the number of bits included in the bit sequence does not change. That is, if the first bit sequence includes N bits, the second bit sequence obtained after the interleaving also includes N bits, N ⁇ 1 and is an integer.
  • the ordering of the N bits in the second bit sequence in the second bit sequence is different from the ordering of the N bits in the first bit sequence.
  • the method of determining the reading interval will be described below. In particular, there may be multiple ways to determine the read interval.
  • the read interval can be determined based on the modulation order.
  • the reading interval can be set to different values.
  • the read interval is a function of the modulation order M.
  • the read interval is equal to the modulation order +1.
  • the example is illustrated by taking the length of the first bit sequence equal to 31 and the modulation order to be 4 as an example.
  • FIG. 5 is an example of an interleaving method in an embodiment of the present application.
  • bit set 1 ⁇ 1, 6, 11, 16, 21, 26, 31 ⁇ .
  • bit set 2 ⁇ 2, 8, 14, 20, 27 ⁇ .
  • the bit sequence 1, the bit set 2, ..., the sequence of the bit order in the bit set L is the interleaved bit sequence, that is, the second bit sequence.
  • the interleaved bit sequence ⁇ 1,6,11,16,21,26,31,2,8,14,20,27,3,10,18,25,4,13,23,5,17 , 29, 7, 22, 9, 28, 12, 15, 19, 24, 30 ⁇ .
  • the length of the first bit sequence is equal to 31, and the modulation order is 6 as an example.
  • FIG. 6 is another example of the interleaving method of the embodiment of the present application.
  • the read bits Starting from the first bit in the first bit sequence, one bit is read every 7 bits, and from left to right, the read bits form a bit set of 1. Similarly, from the remaining bits in the first bit sequence, one bit is read every 7 bits, and from left to right, the read bits make up the bit set 2.
  • bits in the bit set 1, the bit set 2, ... and the bit set L are sequentially arranged to obtain an interleaved bit sequence (i.e., a second bit sequence).
  • the interleaved bit sequence ⁇ 1, 8, 15, 22, 29, 2, 10, 18, 26, 3, 12, 21, 31, 4, 18, 25, 4, 14, 25, 5, 17 , 30, 6, 20, 7, 24, 9, 28, 11, 13, 16, 19, 23, 27 ⁇ .
  • this read interval is used in each round of reading.
  • the i-th read interval and the (i-1)th read interval are equal, i ⁇ 2.
  • the read interval can be determined according to a preset function.
  • the preset function is denoted as f(M), and f(M) produces M 1 values between 1 and M, and the M 1 values correspond to M 1 position indices.
  • the remaining bits After reading the bits of the position indicated by the M 1 position index from the bit sequence to be interleaved, the remaining bits generate M 2 position indexes according to f(NM), and then read the M 2 position indexes to indicate The bit of the location. The remaining bits are deduced by analog until all the bits in the bit sequence to be interleaved are read.
  • Preset functions can take many forms.
  • the default function f mod(i, 5), i ⁇ ⁇ 1, 2, ..., M ⁇ .
  • the reading interval is determined according to a preset function. Also, as the number of remaining bits in the first bit sequence continues to decrease, the calculated read intervals for each calculation may be unequal. Of course, it is also possible that the read intervals obtained a certain number of times are equal.
  • the default function is Ceil(N/4). Where N is the length of the sequence to be read.
  • the function of the function Ceil() is to return the smallest integer greater than or equal to the specified expression.
  • the current position index is skipped, and the bit corresponding to the next position index is read.
  • the index sequence obtained by the bit reverse order operation is reordered from large to small or from small to large, and then the bits of the corresponding positions in the index sequence are read.
  • index sequence #1 For example, if the sequence of the current sequence to be read is subjected to bit reverse order operation, the sequence consists of ⁇ 1, 5, 3, 7, 2, 6 ⁇ (for the sake of distinction, it is referred to as index sequence #1). It can be seen that the index "7" in the index sequence #1 is larger than the length 6 of the current sequence to be read. At this time, the index values in the index sequence #1 are reordered from small to large to obtain a new index sequence ⁇ 1, 2, 3, 5, 6, 7 ⁇ (referred to as index sequence #2). The bits in the index sequence #2 are read as [1, 5, 3, 2, 6, 4] from the current sequence to be read.
  • the read intervals of adjacent sets of bits may be the same or different, and the bits in each set of bits are read at the same read interval.
  • FIG. 7 is still another example of the interleaving method in the embodiment of the present application.
  • the first bit sequence length is equal to 18, the first read interval is equal to 5, and the second read interval is equal to 5.
  • the third read interval and the fourth read interval are equal to 3, and the fifth read interval is equal to 2. Until the number of remaining bits in the first bit sequence is not enough to read through the read interval.
  • the resulting interleaved bit sequence ⁇ 1, 6, 11, 16, 2, 8, 14, 3, 7, 12, 17, 4, 10, 18, 5, 13, 9, 15 ⁇ .
  • the read interval can be determined according to the length N of the sequence to be read currently.
  • the length N of the current sequence to be read refers to the number of remaining bits in the first bit sequence at each reading.
  • the length of the sequence to be read is equal to 32 for the first reading. If 8 bits are read out for the first time, then (32-8) bits remain in the first bit sequence, and the length of the sequence to be read is equal to 24 in the second reading.
  • the read interval when N ⁇ N 1 , the read interval is equal to M 1 .
  • the read interval is equal to M 2 .
  • the read interval is equal to M 3 , and so on.
  • the value of N i may be equal to the length of the mother code or a certain length preset, i ⁇ 1 and an integer.
  • the value of N i may be 1024, 2048, 1000, 2000, 500, and the like.
  • N 1 1024 is set in advance
  • N 2 512
  • the read interval is equal to M 1
  • M 1 may be a set value
  • the length N of the bit sequence to be interleaved is equal to 500 ⁇ 512
  • the read interval is equal to M 2 .
  • M 1 and M 2 may be preset values, and M 1 and M 2 are not equal.
  • the read interval can be determined according to the length N of the sequence to be read currently and the modulation order.
  • the read interval (hereinafter referred to as the initial read interval) employed at the time of the first reading can be determined based on the preset function in which the argument is the modulation order.
  • the read interval used in subsequent reads can be incremented or decremented based on the initial read interval.
  • the speed and magnitude of the increment or decrement can be related to the length N of the sequence to be read.
  • the modulation order is equal to 4
  • the read interval at the first reading is equal to 5.
  • the read interval is 6. If the length of the sequence to be read currently is greater than 600 and less than 800, the read interval is taken as 7, and so on.
  • the read interval may be determined according to the length Q of the mother code corresponding to the length K i of the sequence to be read, i ⁇ 1 and is an integer.
  • the read interval when Q ⁇ N 1 , the read interval is equal to M 1 .
  • the read interval is equal to M 2 .
  • the read interval is equal to M 3 .
  • the value of N i may be the length of the mother code or a preset length.
  • the value of N i may be 1024, 2048, 1000, 2000, 500, or the like.
  • the interleaving method in the embodiment of the present application can improve the error correction performance without increasing the complexity of interleaving.
  • FIG. 8 is a schematic diagram of an interleaving apparatus 500 according to an embodiment of the present application.
  • the apparatus 500 includes a receiving unit 510, a processing unit 520, and a transmitting unit 530. among them,
  • the receiving unit 510 is configured to acquire a first bit sequence, where the first bit sequence includes N bits, N ⁇ 2 and is an integer;
  • the processing unit 520 is configured to read the bit from the first bit sequence according to the at least one read interval, to obtain L bit sets, where each bit set includes at least one bit in the first bit sequence, and any two bit sets The included bits are different in the index of the first bit sequence, the sum of the number of bits in the L bit sets being equal to N, where N ⁇ 2, L ⁇ 2, and N and L are integers;
  • the sending unit 530 is configured to send a second bit sequence.
  • the interleaving apparatus of the embodiment of the present application can improve error correction performance without increasing the complexity of interleaving.
  • FIG. 9 is a schematic structural diagram of an interleaving device 700 according to an embodiment of the present application.
  • device 700 includes one or more processors 701, one or more memories 702, and one or more transceivers 703.
  • the processor 701 is configured to control the transceiver 703 to transmit and receive signals
  • the memory 702 is configured to store a computer program
  • the processor 701 is configured to call and run the computer program from the memory 702, such that the interleaving device 700 performs the corresponding processes of the embodiments of the interleaving method and / or operation.
  • the interleaving device 700 performs the corresponding processes of the embodiments of the interleaving method and / or operation.
  • interleaving apparatus 500 shown in FIG. 8 can be implemented by the interleaving apparatus 700 shown in FIG.
  • the receiving unit 510 and the transmitting unit 530 can be implemented by the transceiver 703 in FIG.
  • Processing unit 520 can be implemented by processor 701, and the like.
  • the interleaving device may be the network device or the terminal device shown in FIG. 1.
  • the interleaving device is specifically a terminal device, and the terminal device has a function of implementing the interleaving method described in the above embodiments.
  • These functions can be implemented in hardware or in software by executing the corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the interleaving device is specifically a network device (for example, a base station), and the network device has a function of implementing the interleaving method described in the above embodiments.
  • these functions can be implemented in hardware or in software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • FIG. 10 is a schematic structural diagram of a terminal device 800 according to an embodiment of the present application.
  • the terminal device 800 includes a transceiver 808 and a processing device 804.
  • Terminal device 800 can also include a memory 819 for storing computer instructions.
  • the transceiver 808 is configured to acquire a first bit sequence, where the first bit sequence includes N bits, N ⁇ 2 and is an integer;
  • the processor 804 is configured to read the bit from the first bit sequence according to the at least one read interval, to obtain L bit sets, where each bit set includes at least one bit in the first bit sequence, and any two bit sets The included bits are different in the index of the first bit sequence, the sum of the number of bits in the L bit sets being equal to N, where N ⁇ 2, L ⁇ 2, and N and L are integers;
  • the transceiver 808 is configured to send a second bit sequence according to the indication of the processing device 804.
  • processing device 804 can be used to perform the actions implemented by the interleaving device described in the foregoing method embodiments
  • the transceiver 808 can be used to perform the receiving or transmitting action of the interleaving device described in the foregoing method embodiments.
  • the description in the previous method embodiments please refer to the description in the previous method embodiments, and details are not described herein again.
  • the processing device 804 and the memory 819 described above may be integrated into a processor for executing program code stored in the memory 819 to implement the above functions.
  • the memory 819 can also be integrated in the processor.
  • the terminal device 800 described above may also include a power source 812 for providing power to various devices or circuits in the terminal device 800.
  • the terminal device 800 described above may include an antenna 810 for transmitting data or information output by the transceiver 808 through a wireless signal.
  • the terminal device 800 may further include one or more of an input unit 814, a display unit 816, an audio circuit 818, a camera 820, and a sensor 822.
  • the audio circuit may also include a speaker 8182, a microphone 8184, and the like.
  • interleaving method may be applicable to various channel coding, for example, an LDPC code, a Turbo code, a Polar code, and the like. This embodiment of the present application does not limit this.
  • the interleaving method provided by the present application can be used as a separate interleaving module for implementing interleaving processing. It can also be used as a way to read bits during rate matching, so that interleaving and rate matching can be integrated. It is not necessary to design an interleaving module separately, and the same error correction performance as random interleaving can be achieved.
  • interleaving method in the embodiment of the present application is also applicable to the interleaving of the symbol sequence.
  • the method for interleaving the bit sequence according to the above description may also be applied to the interleaving of the symbol sequence. No longer detailed.
  • the present application provides a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the interleaving method of the various embodiments described above.
  • the application also provides a computer program product comprising: computer program code for causing a computer to perform the interleaving method described in the above embodiments when the computer program code is run on a computer.
  • the present application also provides a chip comprising a memory for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted performs the interleaving described in the above embodiments method.
  • the communication device mentioned herein may be a network device or a terminal device.
  • the present application also provides an encoding apparatus having a function of implementing the interleaving method described in the above embodiments. These functions can be implemented in hardware or in software by executing the corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device also has a related function for implementing encoding. After the encoding apparatus encodes the encoded sequence, the encoded sequence is interleaved by using the interleaving method of the embodiment of the present application. Alternatively, the encoding apparatus may also apply the interleaving method of the embodiment of the present application to rate matching, so that the interleaving module may be omitted, but the effect of improving error correction performance is also improved.
  • the encoding device when some or all of these functions are implemented by hardware, the encoding device includes:
  • An input interface circuit configured to acquire a first bit sequence
  • a logic circuit configured to perform the interleaving method described in the foregoing embodiment, performing interleaving on the first bit sequence to obtain a second bit sequence;
  • An output interface circuit for outputting a second bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when some or all of these functions are implemented by software, includes: a memory for storing a computer program; a processor, a computer program for executing memory storage, when the computer program is executed
  • the encoding apparatus may implement the interleaving method described in any of the possible designs of the above embodiments.
  • the encoding device when some or all of these functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a computer program is located outside of the encoding device, and the processor is coupled to the memory through a circuit/wire for reading and executing a computer program stored in the memory.
  • the interleaving method described in the implementation of the present application is performed by the transmitting end of data and/or information. At the receiving end of the data and/or information, the received bit sequence needs to be deinterleaved. It is well known to those skilled in the art that deinterleaving is the inverse of interleaving. Based on the interleaving method described in the above first aspect and any of its possible implementation manners, those skilled in the art can easily obtain a method of deinterleaving, which is not described in detail herein.
  • the present application provides a deinterleaving device for implementing corresponding functions in the method of deinterleaving. These functions can be implemented in hardware or in software by executing the corresponding software.
  • the present application provides a computer readable storage medium having stored therein computer instructions that, when run on a computer, cause the computer to perform a method of deinterleaving.
  • the application also provides a computer program product comprising: computer program code, a method of causing a computer to perform deinterleaving when the computer program code is run on a computer.
  • the present application also provides a chip (or a chip system) including a memory and a processor for storing a computer program, the processor for calling and running the computer program from the memory, such that the communication device on which the chip is mounted performs The interleaving method in the method embodiments of the present application.
  • the application provides a deinterleaved device that includes one or more processors, one or more memories, and one or more transceivers (each transceiver including a transmitter and a receiver).
  • the transmitter or receiver transmits and receives signals through the antenna.
  • the memory is used to store computer program instructions (or code).
  • the processor is configured to execute instructions stored in the memory, and when the instructions are executed, the processor performs a method of deinterleaving.
  • the present application also provides a decoding apparatus having a function of implementing the method of deinterleaving as described in the embodiments of the present application. These functions can be implemented in hardware or in software by executing the corresponding software.
  • the decoding device also has associated functions for implementing decoding, such as de-rate matching, decoding, and the like.
  • the memory and the memory described in the foregoing embodiments may be physically independent units, or the memory may be integrated with the processor.
  • the processor may be a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more programs for controlling the program of the present application.
  • the processor can include a digital signal processor device, a microprocessor device, an analog to digital converter, a digital to analog converter, and the like.
  • the processor can distribute the control and signal processing functions of the mobile device among the devices according to their respective functions.
  • the processor can include functionality to operate one or more software programs, which can be stored in memory.
  • the functions of the processor may be implemented by hardware or by software executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of information and instructions that can be stored. Dynamic storage device. It can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, and a disc storage (including a compact disc, a laser disc, a compact disc, a digital versatile disc, a Blu-ray disc, etc.), a disk storage medium or other magnetic storage device, or any other device that can be used to carry or store desired program code in the form of an instruction or data structure and accessible by a computer. Medium, but not limited to this.
  • EEPROM electrically erasable programmable read-only memory
  • CD-ROM compact disc read-only memory
  • disc storage including a compact disc, a laser disc, a compact disc, a digital versatile disc, a Blu-ray disc, etc.
  • the above functions are implemented in the form of software and sold or used as stand-alone products, they can be stored in a computer readable storage medium.
  • the part of the technical solution of the present application which contributes in essence or to the prior art, or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program code. .

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Abstract

本申请提供了一种交织方法，能够在不增加交织复杂度的情况下，提升纠错性能。该方法包括：获取第一比特序列，所述第一比特序列包括N个比特；根据至少一个读取间隔从所述第一比特序列中读取比特，得到L个比特集合，每个比特集合中包括所述第一比特序列中的至少一个比特，任意两个比特集合中包括的比特在所述第一比特序列中的索引不同，所述L个比特集合中比特数目之和等于所述N，其中，N≥2，L≥2，且N和L为整数；根据所述L个比特集合，得到第二比特序列；发送所述第二比特序列。

Description

交织方法和交织装置
本申请要求于2017年11月10日提交中国专利局、申请号为201711105339.8、申请名称为“交织方法和交织装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信道编码领域，尤其涉及一种交织方法和交织装置。
背景技术
数字通信系统通常采用信道编码提高数据传输的可靠性，其中，一些信道编码采用了交织技术，以进一步提升数据传输过程中的抗干扰性能。在许多同时出现随机错误和突发错误的复合信道上，如果发生一个错误，往往会波及一串数据，导致突发错误超过信道纠错能力，纠错能力下降。而如果首先把突发错误离散成随机错误，再进行随机错误纠错，则系统的抗干扰性能将进一步得到提高。
现阶段，根据交织方法的不同，交织方法主要分为随机交织和行列交织。随机交织在离线计算交织序列时，需要存储置换序列供交织和解交织使用，在码长较长的情况下，随机交织所需的存储资源非常大，甚至不可接受。而行列交织对于所及错误的纠错能力较弱，纠错性能较差。
发明内容
本申请提供一种交织方法和交织装置，可以在不增加交织复杂度的情况下提升纠错性能。
第一方面，本申请提供一种交织方法，该方法包括：获取第一比特序列，第一比特序列包括N个比特，N≥2且为整数；根据至少一个读取间隔从第一比特序列中读取比特，得到L个比特集合，每个比特集合中包括第一比特序列中的至少一个比特，任意两个比特集合中包括的比特在第一比特序列中的索引不同，该L个比特集合中比特数目之和等于N，其中，L≥2且为整数；根据该L个比特集合，得到第二比特序列；发送第二比特序列。
本申请实施例的交织方法，与随机交织相比，交织复杂度低，但是交织性能却与随机交织性能相当甚至更优。因此，在不增加交织复杂度的情况下可以提升纠错性能。
结合第一方面，在第一方面的某些实现方式中，该L个比特集合按照读取顺序依序排列。
结合第一方面，在第一方面的某些实现方式中，该根据至少一个读取间隔从第一比特序列中读取比特，得到L个比特集合，包括：根据第i个读取间隔，从第一比特序列中除去第1个比特集合至第(i-1)个比特集合后的剩余比特中读取至少一个比特，得到第i个比特集合，其中，1≤i≤L，且i为整数。
这里需要说明的是，第1个比特集合可以根据确定的读取间隔，直接从第一比特序列中读取。
结合第一方面，在第一方面的某些实现方式中，第i个读取间隔和第(i-1)个读取间隔相同或不同。
结合第一方面，在第一方面的某些实现方式中，该至少一个读取间隔中的任意一个读取间隔是根据调制阶数或预设函数确定的。
第二方面，提供了一种交织装置，用于执行第一方面或第一方面的任意可能的实现方式中的方法。具体地，该装置包括执行第一方面或第一方面的任意可能的实现方式中的方法的单元。
第三方面，本申请提供一种交织设备，该交织设备包括一个或多个处理器，一个或多个存储器，一个或多个收发器(每个收发器包括发射机和接收机)。收发器用于通过天线收发信号。存储器用于存储计算机程序指令(或者说，代码)。处理器用于执行存储器中存储的指令，当指令被执行时，处理器执行第一方面或第一方面的任意可能的实现方式中的方法。
第四方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面或第一方面的任意可能的实现方式中的方法。
第五方面，本申请提供一种芯片(或者说，芯片系统)，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行上述第一方面及其任意一种可能的实现方式中的方法。
第六方面，本申请提供一种计算机程序产品，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述第一方面及其任意一种可能的实现方式中的方法。
第七方面，本申请提供一种编码装置，该编码装置具有实现上述第一方面及其第一方面任意一种可能的实现方式中的方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。此外，该编码装置还应具有和编码相关的性能，例如，编码、速率匹配等。
在一个可能的设计中，当这些功能的部分或全部通过硬件实现时，编码装置包括：输入接口电路，用于获取第一比特序列；逻辑电路，用于执行上述第一方面及其第一方面的任意一种可能的设计中的交织方法；输出接口电路，用于输出第二比特序列。
可选的，编码装置可以是芯片或者集成电路。
在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括：存储器，用于存储计算机程序；处理器，用于执行所述存储器存储的计算机程序，当所述计算机程序被执行时，编码装置可以实现上述第一方面及其第一方面的任意一种可能的设计中所述的交织方法。
在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括处理器，用于存储计算机程序的存储器位于编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的计算机程序。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
需要说明的是，本申请实施了中描述的交织方法是由数据和/或信息的发送端来执行的。在数据和/或信息的接收端，需要对接收到的比特序列进行解交织。本领域技术人员公知，解交织是交织的逆过程。在上述第一方面及其任意一种可能的实现方式中描述的交织方法的基础上，本领域技术人员容易得到解交织的方法，本文中不作详述。
此外，本申请提供一种解交织的装置，具体地，解交织的装置包括执行解交织的方法的单元。
此外，本申请还提供一种解交织的设备，该设备包括一个或多个处理器，一个或多个存储器，一个或多个收发器(收发器包括发射机和接收机)。发射机或接收机通过天线收发信号。存储器用于存储计算机程序指令(或者，代码)。处理器用于执行存储器中存储的指令，当指令被执行时，处理器执行解交织的方法。
此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当其在计算机上运行时，使得计算机执行解交织的方法。
本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行解交织的方法。
本申请还提供一种芯片(或者说，芯片系统)，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行本申请各方法实施例中的交织方法。
本申请还提供一种译码装置，该译码装置具有实现本申请实施例中所说的解交织的方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。除此之外，译码装置还具有实现译码的相关功能，例如，解速率匹配、译码等。
在本申请实施例中，提出了一种简单易操作的交织方法，能够在不增加交织复杂度的情况下提升纠错性能。
附图说明
图1为适用于本申请实施例的无线通信系统100。
图2是采用无线技术进行通信的基本流程图。
图3是本申请实施例的交织方法的流程图。
图4是本申请实施例的从第一比特序列中读取L个比特集合的过程示意图。
图5是本申请实施例的交织方法的一个示例。
图6是本申请实施例的交织方法的另一个示例。
图7是本申请实施例的交织方法的又一个示例。
图8为本申请实施例的交织装置500的示意图。
图9为本申请实施例的交织设备700的示意性结构图。
图10为本申请实施例的终端设备800的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
图1为适用于本申请实施例的无线通信系统100。该无线通信系统中可以包括至少一个网络设备101，该网络设备与一个或多个终端设备(例如，图1中所示的终端设备102 和终端设备102)进行通信。网络设备101可以是基站，也可以是基站与基站控制器集成后的设备，还可以是具有类似通信功能的其它设备。
本申请实施例提及的无线通信系统包括但不限于：窄带物联网系统(narrow band-internet of things，NB-IoT)、全球移动通信系统(global system for mobile communications，GSM)、增强型数据速率GSM演进系统(enhanced data rate for GSM evolution，EDGE)、宽带码分多址系统(wideband code division multiple access，WCDMA)、码分多址2000系统(code division multiple access,CDMA2000)、时分同步码分多址系统(time division-synchronization code division multiple access，TD-SCDMA)，长期演进系统(long term evolution，LTE)、下一代5G移动通信系统的三大应用场景，即增强移动宽带(enhanced mobile broadband，eMBB)，低时延高可靠性(ultra reliable low latency communications,URLLC)和增强机器类通信(enhanced machine type of communication,eMTC)或者将来出现的新的通信系统。
本申请实施例中所涉及到的终端设备可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。终端设备可以是移动台(mobile station，MS)、用户单元(subscriber unit)、蜂窝电话(cellular phone)、智能电话(smart phone)、无线数据卡、个人数字助理(personal digital assistant，PDA)电脑、平板型电脑、无线调制解调器(modem)、手持设备(handset)、膝上型电脑(laptop computer)、机器类型通信(machine type communication，MTC)终端等。
图1中的网络设备101与终端设备之间采用无线技术进行通信。当网络设备发送信号时，其为发送端，终端设备为接收端。当网络设备接收信号时，其为接收端，终端设备为发送端。
图2是采用无线技术进行通信的基本流程图。发送端的信源依次经过信源编码、信道编码、速率匹配和调制后在信道上发出。接收端接收到信号后依次经过解调、解速率匹配、信道解码和信源解码后获得信宿。
信道编码是无线通信系统的核心技术之一，其性能的改进将直接提升网络覆盖及用户传输速率。为了提高信号的抗干扰性，可以进一步地可以引入交织技术。交织技术的思想是在时间上分离码元，将一个有记忆信道转变为无记忆信道，从而使得纠随机错误的编码也能适用于噪声突发信道。
常用的交织方法包括随机交织和行列交织。随机交织在平均性能上较优，但是由于交织的随机性，无法保证每次交织都具有较优的性能。并且在离线交织的情况下，需要存储大量的置换序列供交织和解交织使用。当码长较长时，随机交织所需的存储资源较大，给编码器造成很大的硬件负荷，甚至不可接受。此外，随机交织的复杂度较高。而行列交织的方案比较简单，但是对于数据的随机化处理较弱，交织性能不太理想。
为此，本申请提出一种交织方法，可以在不增加交织复杂度的情况下，提升纠错性能。下面对本申请实施例的交织方法进行详细说明。
参见图3，图3是本申请实施例的交织方法的流程图。
310、获取第一比特序列。
其中，第一比特序列包括N个比特，其中，N≥2且为整数。
320、根据至少一个读取间隔，从第一比特序列中读取比特，得到L个比特集合。
在本申请实施例中，L个比特集合是从第一比特序列中读取比特得到的。L个比特集合中比特的数目之和等于N。并且，任意两个比特集合中包括的比特在第一比特序列中的索引不同。换句话说，将第一比特序列中包括的N个比特分别放置在L个比特集合中。
330、根据该L个比特集合，得到第二比特序列。
得到L个比特集合之后，根据该L个比特集合可以得到第二比特序列，从而完成交织。
在本申请实施例中，第一比特序列是待交织的比特序列，交织后的比特序列为第二比特序列。
具体地，得到L个比特集合之后，可以有多种方式生成第二比特序列。
例如，将L个比特集合进行组合排序，得到第二比特序列。
又例如，按照从第一比特序列中读取得到该L个比特集合的顺序，依序将该L个比特集合排列，得到第二比特序列。
340、发送第二比特序列。
对第一比特序列完成交织，得到第二比特序列后，对第二比特序列进行映射、调制、发送。这些过程可以与现有技术相同，这里不作详述。
下面结合图4，对本申请实施例中从第一比特序列中读取得到L个比特集合的过程作详细说明。
参见图4，图4是本申请实施例的从第一比特序列中读取L个比特集合的过程示意图。交织过程可以描述为：首先获取第一比特序列。按照第1个读取间隔从第一比特序列中读取比特，得到第1个比特集合(以下记作比特集合1)。按照第2个读取间隔，从第一比特序列中除去第一比特集合中的比特之外的剩余比特中读取比特，得到第2个比特集合(以下记作比特集合2)。按照第3个读取间隔，从第一比特序列中除去第一比特集合和第二比特集合中的比特之外的剩余比特中读取比特，得到第3个比特集合(以下记作比特集合3)。以此类推，按照第i个读取间隔，从第一比特序列中除去第1个比特集合至第(i-1)个比特集合中的比特之外的剩余比特中读取比特，得到第i个比特集合。以此类推，直至将第一比特序列中的比特全部读出。
再根据比特集合1，比特集合2，…，比特集合L，可以得到第二比特序列。
应理解，i＝1时可以看作一个特殊情况，即第1个比特集合可以按照第1个读取间隔，直接从第一比特序列中读出。i≥2时，第i个比特集合是从第一比特序列中除去第1个比特集合至第(i-1)个比特集合中的比特之外的剩余比特中读出的。
在本申请实施例中，根据L个比特集合得到第二比特序列，可以有多种方式。
为了便于说明，按照从第一比特序列中读出这L个比特集合的先后顺序，将这L个比特集合分别记作比特集合1,比特集合2，….,比特集合L。
例如，按照先后读出L个比特集合的顺序，依序将这L个比特集合顺序排列，得到第二比特序列。
又例如，将先后读出的L个比特集合的顺序打乱，重新排序组成第二比特序列。
在本申请实施例中，第i个读取间隔与第i个比特集合对应，其中，第i个读取间隔是从第一比特序列中读取比特组成第i个比特集合时采用的读取间隔。
需要注意的是，第i个读取间隔是指从第一比特序列中除去第1个比特集合至第(i-1)个比特集合的剩余比特组成的比特序列中的间隔。
例如，第一比特序列＝{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31}。
若按照第1个读取间隔等于5，则从第一比特序列中读取得到的比特集合1＝{1,6,11,16}。
除去比特集合1之后，按照第2个读取间隔等于5，从剩余比特组成的比特序列中读取比特，得到比特集合2＝{2,8,14}。
在本申请实施例中，第i个读取间隔和第(i-1)读取间隔可以相同或者不同，i≥1且为整数。
应理解，由第一比特序列得到第二比特序列，即是交织的过程。交织前后，比特序列中包括的比特数量是不会发生变化的。也就是说，如果第一比特序列包括N个比特，那么交织后得到的第二比特序列也包括N个比特，N≥1且为整数。
此外，第二比特序列中的N个比特在第二比特序列中的排序与该N个比特在第一比特序列中的排序不同。
下面对确定读取间隔的方法进行说明。具体地，读取间隔的可以有多种确定方式。
方式1
读取间隔可以根据调制阶数确定。
针对系统采用的调制阶数(以下将调制阶数的取值记作M)，读取间隔可以设置不同的取值。换句话说，读取间隔是调制阶数M的函数。例如，读取间隔等于调制阶数+1。
以第一比特序列的长度等于31，调制阶数为4作为示例进行举例说明。
参见图5，图5是本申请实施例的交织方法的一个示例。假定系统采用的调制阶数为4，第一比特序列＝{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31}，即第一比特序列的长度等于31。
假定，读取间隔为调制阶数+1，则读取间隔＝4+1＝5。
从第一比特序列中的第1个比特开始，从左至右，每间隔5个比特读取一个，读出的比特组成比特集合1。如图5，比特集合1＝{1,6,11,16,21,26,31}。
从第一比特序列中除去比特集合1之外的剩余比特中，从左至右，每间隔5个比特读取一个，读出的比特组成比特集合2。如图5，比特集合2＝{2,8,14,20,27}。
依次类推，按照读取间隔等于5，继续读取第一比特序列中的剩余比特，直至第一比特序列中的剩余比特不够通过读取间隔读出，此时，将剩余比特全部读出作为一个比特集合(记作比特集合L)。
比特集合1、比特集合2，…，比特集合L中的比特顺序组成的序列则为交织后的比特序列，即第二比特序列。
因此，交织后的比特序列＝{1,6,11,16,21,26,31,2,8,14,20,27,3,10,18,25,4,13,23,5,17,29,7,22,9,28,12,15,19,24,30}。
在图5所示的示例中，所有的读取间隔都相等。
再以第一比特序列的长度等于31，调制阶数为6作为示例作举例说明。
参见图6，图6本申请实施例的交织方法的另一个示例。如图6所示，系统采用的调制阶数为6，第一比特序列＝{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31}，即第一比特序列的长度等于31。
继续以读取间隔等于调制阶数+1为例，则读取间隔＝6+1＝7。
从第一比特序列中的第一个比特开始，每间隔7个比特读取一个，从左至右，读出的比特组成比特集合1。类似地，从第一比特序列中剩余的比特中，每间隔7个比特读取一个，从左至右，读出的比特组成比特集合2。
依次类推，直至第一比特序列中的比特的个数不足够通过读取间隔来读取。此时，将第一比特序列中的剩余比特一次全部读出，组成比特集合L。
将比特集合1、比特集合2，…和比特集合L中的比特顺序排列，得到交织后的比特序列(即第二比特序列)。
因此，交织后的比特序列＝{1,8,15,22,29,2,10,18,26,3,12,21,31,4,18,25,4,14,25,5,17,30,6,20,7,24,9,28,11,13,16,19,23,27}。
在方式1中，通过调制阶数确定一个读取间隔之后，在每一轮读取时，都采用这个读取间隔。或者说，第i个读取间隔和第(i-1)个读取间隔是相等的，i≥2。
方式2
读取间隔可以根据预设函数确定。
在方式2中，假定待交织的比特序列的长度等于N。
将预设函数记作f(M)，f(M)产生1至M之间的M 1个数值，将这M 1个数值对应M 1个位置索引。从待交织的比特序列中，读出这M 1个位置索引所指示的位置的比特后，剩余比特再按照f(N-M)产生M 2个位置索引，再读取这M 2个位置索引所指示的位置的比特。剩余比特以此类推，直至将待交织的比特序列中的全部比特读出。
预设函数可以有多种形式。
例如，预设函数f＝mod(i,5)，i∈{1,2,…,M}。
在方式2中，与方式1不同的是，读取间隔是根据预设函数确定的。并且，随着第一比特序列中剩余比特的数量的不断减少，每次计算得到的读取间隔可能是不相等的。当然，也有可能某几次计算得到的读取间隔是相等的。
又例如，预设函数是Ceil(N/4)。其中，N是待读取序列的长度。函数Ceil()的功能是返回大于或者等于指定表达式的最小整数。
交织的过程可以使用比特逆序函数。以一个长度N＝16的比特序列为例，若对该比特序列执行比特逆序操作后，得到的比特序列为{1,9,5,13,3,11,7,15,2,10,6,14,4,12,8,16}，读取位置索引为[1,9,5,13]的比特。剩余的12个比特继续执行比特逆序操作，得到序列＝{1 9 5 13 3 11 7 15 2 10 6 14}，读取位置索引为[1,9,5]的比特。剩余9个比特继续执行比特逆序操作，得到序列＝{1,9,5,13,3,11,7,15,2}，读取位置索引为[1 9 5]的比特。剩余6个比特继续执行比特逆序操作，得到的序列为＝{1,5,3,7,2,6}，读取位置索引为[15]的比特。最后剩余的4个比特一次读出。
在读取的过程中，若读取的位置索引大于当前待读取序列的长度，则跳过当前的位置索引，并读取后面一个位置索引对应的比特。
或者，将比特逆序操作获得的索引序列按照从大到小或从小到大重新排序，然后再读取索引序列中对应位置的比特。
例如，若当前待读取序列执行比特逆序操作后的索引构成的序列为{1,5,3,7,2,6}(为了便于区分，记作索引序列#1)。可以看到，索引序列#1中的索引“7”大于当前待读取序 列的长度6。此时，将索引序列#1中的索引值按照从小到大重新进行排序，得到新的索引序列{1,2,3,5,6,7}(记作索引序列#2)。再从当前待读取序列中读取在索引序列#2中的位置为[1,5,3,2,6,4]的比特。
方式3
相邻比特集合的读取间隔可以相同或不同，每个比特集合中的比特是按照相同的读取间隔读取得到的。
参见图7，图7是本申请实施例的交织方法的又一个示例。
如图7所示，第一比特序列长度等于18，第一个读取间隔等于5，第二个读取间隔等于5。第三个读取间隔和第四个读取间隔等于3，第五个读取间隔等于2。直至第一比特序列中剩余比特的数目不够通过读取间隔来读取。最后，得到的交织后的比特序列＝{1,6,11,16,2,8,14,3,7,12,17,4,10,18,5,13,9,15}。
方式4
读取间隔可以根据当前待读取序列的长度N确定。
在方式4中，给定待交织的第一比特序列之后，随着从第一比特序列中不断读出比特，第一比特序列中的剩余比特越来越少。这里，当前待读取序列的长度N是指每次读取时第一比特序列中剩余比特的个数。
例如，若第一比特序列中包括32个比特，那么第一次读取时，待读取序列的长度等于32。若第一次读出8个比特，则第一比特序列中剩余(32-8)个比特，第二次读取时，待读取序列的长度等于24。
作为一个实施例，当N<N 1时，读取间隔等于M 1。当N<N 2时，读取间隔等于M 2。当N<N 3时，读取间隔等于M 3，以此类推。N i的取值可以等于母码长度或是预先设定的某个长度，i≥1且为整数。例如，N i的取值可以为1024,2048,1000,2000,500等。
例如，若预先设定N 1＝1024，N 2＝512，如果待交织的比特序列的长度N＝800<1024，则读取间隔等于M 1，M 1可以为一个设定值。如果待交织的比特序列的长度N等于500<512，则读取间隔等于M 2。其中，M 1和M 2可以为预设值，M 1和M 2不相等。
方式5
读取间隔可以根据当前待读取序列的长度N和调制阶数确定。
在方式5中，首次读取时采用的读取间隔(以下称作初始读取间隔)可以根据自变量为调制阶数的预设函数确定。后续读取时采用的读取间隔可以在初始读取间隔的基础上递增或者递减。递增或者递减的速度与幅度可以和待读取的序列长度N相关。
例如，第一比特序列长度N＝1000，调制阶数等于4，首次读取时的读取间隔等于5。后续读取时，若当前待读取的序列长度大于800，读取间隔取6。若当前待读取的序列长度大于600且小于800，读取间隔取7，以此类推。
方式6
读取间隔可以根据当前待读取序列的长度K i对应的母码长度Q确定，i≥1且为整数。
在方式6中，当Q<N 1时，读取间隔等于M 1。当Q<N 2时，读取间隔等于M 2。当Q<N 3时，读取间隔等于M 3。以此类推，N i的取值可以是母码长度或预先设定的长度，例如，N i的取值可以为1024,2048,1000,2000,500等。
例如，若预先设定N 1＝128，N 2＝64，如果待交织的比特序列的长度等于50，对于第一 次读取来说，待读取序列的长度K 1＝50，而长度等于50的比特序列对应的母码长度Q＝64<128，则第一次读取时的读取间隔可以取M 1。若第一次读出20个比特，对于第二次读取来说，当前待读取序列的长度变为(50-20)，即K 2＝30，而长度等于30的比特序列对应的母码长度Q＝32<64，则第二次读取时的读取间隔可以取M 2。其中，M 1和M 2可以为预设值，M 1和M 2不相等。
本申请实施例的交织方法，能够在不增加交织复杂度的情况下提升纠错性能。
以上结合图1至图7，对本申请实施例的交织方法的过程作了详细说明，以下对本申请实施例的交织装置作介绍。
图8为本申请实施例的交织装置500的示意图。如图8所示，装置500包括接收单元510、处理单元520和发送单元530。其中，
接收单元510，用于获取第一比特序列，第一比特序列包括N个比特，N≥2且为整数；
处理单元520，用于根据至少一个读取间隔从第一比特序列中读取比特，得到L个比特集合，每个比特集合中包括第一比特序列中的至少一个比特，任意两个比特集合中包括的比特在第一比特序列中的索引不同，该L个比特集合中比特数目之和等于N，其中，N≥2，L≥2，且N和L为整数；
发送单元530，用于发送第二比特序列。
本申请实施例的装置500中的各单元和上述其它操作或功能分别为了实现本申请各实施例中的交织方法。为了简洁，此处不再赘述。
本申请实施例的交织装置，能够在不增加交织复杂度的情况下提升纠错性能。
图9为本申请实施例的交织设备700的示意性结构图。如图9所示，设备700包括：一个或多个处理器701，一个或多个存储器702，一个或多个收发器703。处理器701用于控制收发器703收发信号，存储器702用于存储计算机程序，处理器701用于从存储器702中调用并运行该计算机程序，使得交织设备700执行交织方法各实施例的相应流程和/或操作。为了简洁，此处不再赘述。
需要说明的是，图8中所示的交织装置500可以通过图9中所示的交织设备700实现。例如，接收单元510、发送单元530可以由图9中的收发器703实现。处理单元520可以由处理器701实现等。
交织设备可以为图1中所示的网络设备或终端设备。在上行传输时，交织设备具体为终端设备，终端设备具有实现上述各实施例中描述的交织方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。在下行传输时，交织设备具体为网络设备(例如，基站)，网络设备具有实现上述各实施例中描述的交织方法的功能。同样地，这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
当交织设备700具体为终端设备时，终端设备的结构可以如图10所示。图10为本申请实施例的终端设备800的示意性结构图。
如图10所示，终端设备800包括：收发器808和处理装置804。终端设备800还可以包括存储器819，存储器819用于存储计算机指令。
收发器808，用于获取第一比特序列，第一比特序列包括N个比特，N≥2且为整数；
处理器804，用于根据至少一个读取间隔从第一比特序列中读取比特，得到L个比特集合，每个比特集合中包括第一比特序列中的至少一个比特，任意两个比特集合中包括的比特在第一比特序列中的索引不同，该L个比特集合中比特数目之和等于N，其中，N≥2，L≥2，且N和L为整数；
收发器808，用于根据处理装置804的指示，发送第二比特序列。
进一步地，上述处理装置804可以用于执行前面方法实施例中描述的由交织设备内部实现的动作，而收发器808可以用于执行前面方法实施例中描述的交织设备的接收或发送动作。具体请见前面方法实施例中的描述，此处不再赘述。
上述处理装置804和存储器819可以集成为一个处理器，处理器用于执行存储器819中存储的程序代码来实现上述功能。具体实现时，该存储器819也可以集成在处理器中。
上述终端设备800还可以包括电源812，用于给终端设备800中的各种器件或电路提供电源。上述终端设备800可以包括天线810，用于将收发器808输出的数据或信息通过无线信号发送出去。
除此之外，为了使终端设备800的功能更加完善，终端设备800还可以包括输入单元814，显示单元816，音频电路818，摄像头820和传感器822等中的一个或多个。音频电路还可以包括扬声器8182，麦克风8184等。
需要说明的是，本申请实施例中提供的交织方法可以适用于各种信道编码，例如，LDPC码、Turbo码码、极化(Polar)码等。本申请实施例对此不作限定。
此外，本申请提供的交织方法可以作为一个单独的交织模块，用于实现交织处理。也可以作为速率匹配时读取比特的方式，这样就可以将交织和速率匹配集成在一起实现，不需要单独设计交织模块，同样也可以达到与随机交织相同的纠错性能。
另外，本申请实施例的交织方法，对于符号(symbol)序列的交织也是适用的，本领域技术人员根据上面描述的对比特序列进行交织的方法，也可以将其应用于符号序列的交织，本文中不再详述。
此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各实施例中的交织方法。
本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行上述实施例中描述的交织方法。
本申请还提供一种芯片，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行上述实施例中描述的交织方法。
其中，这里所说的通信设备可以为网络设备或终端设备。
本申请还提供一种编码装置，该编码装置具有实现上述实施例中描述的交织方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。除此之外，编码装置还具有实现编码的相关功能。编码装置对待编码序列进行编码后，采用本申请实施例的交织方法，对编码后的序列进行交织。或者，该编码装置也可以将本申请实施例的交织方法应用在速率匹配，这样可以省掉交织模块，但是同样会起到提高纠错性能的作用。
在一个可能的设计中，当这些功能的部分或全部通过硬件实现时，编码装置包括：
输入接口电路，用于获取第一比特序列；
逻辑电路，用于执行上述实施例中描述的交织方法，对第一比特序列进行交织，得到第二比特序列；
输出接口电路，用于输出第二比特序列。
可选的，编码装置可以是芯片或者集成电路。
在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括：存储器，用于存储计算机程序；处理器，用于执行存储器存储的计算机程序，当所述计算机程序被执行时，编码装置可以实现上述实施例中任意一种可能的设计中所述的交织方法。
在一个可能的设计中，当这些功能的部分或全部通过软件实现时，编码装置包括处理器。用于存储计算机程序的存储器位于编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行存储器中存储的计算机程序。
需要说明的是，本申请实施了中描述的交织方法是由数据和/或信息的发送端来执行的。在数据和/或信息的接收端，需要对接收到的比特序列进行解交织。本领域技术人员公知，解交织是交织的逆过程。在上述第一方面及其任意一种可能的实现方式中描述的交织方法的基础上，本领域技术人员容易得到解交织的方法，本文中不作详述。
相对应地，本申请提供一种解交织的装置，用于实现解交织的方法中的相应功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。
此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当其在计算机上运行时，使得计算机执行解交织的方法。
本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行解交织的方法。
本申请还提供一种芯片(或者说，芯片系统)，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行该计算机程序，使得安装有该芯片的通信设备执行本申请各方法实施例中的交织方法。
本申请提供一种解交织的设备，该设备包括一个或多个处理器，一个或多个存储器，一个或多个收发器(每个收发器包括发射机和接收机)。发射机或接收机通过天线收发信号。存储器用于存储计算机程序指令(或者，代码)。处理器用于执行存储器中存储的指令，当指令被执行时，处理器执行解交织的方法。
本申请还提供一种译码装置，该译码装置具有实现本申请实施例中所说的解交织的方法的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。除此之外，译码装置还具有实现译码的相关功能，例如，解速率匹配、译码等。
可选的，以上实施例中所述的存储器与存储器可以是物理上相互独立的单元，或者，存储器也可以和处理器集成在一起。
以上实施例中，处理器可以为中央处理器(central processing unit，CPU)、微处理器、特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路等。例如，处理器可以包括数字信号处理器设备、微处理器设备、模数转换器、数模转换器等。处理器可以根据这些设备各自的功能而在这些设备之间分配移动设备的控制和信号处理的功能。此外，处理器可以包括操作一个或多个软件 程序的功能，软件程序可以存储在存储器中。
处理器的所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
存储器可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备。也可以是电可擦可编程只读存储器(Electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。
结合前面的描述，本领域的技术人员可以意识到，本文实施例的方法，可以通过硬件(例如，逻辑电路)，或者软件，或者硬件与软件的结合来实现。这些方法究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
当上述功能通过软件的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。在这种情况下，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种交织方法，其特征在于，包括：
    获取第一比特序列，所述第一比特序列包括N个比特，N≥2且为整数；
    根据至少一个读取间隔从所述第一比特序列中读取比特，得到L个比特集合，每个比特集合中包括所述第一比特序列中的至少一个比特，任意两个比特集合中包括的比特在所述第一比特序列中的索引不同，所述L个比特集合中比特数目之和等于所述N，其中，L≥2且为整数；
    根据所述L个比特集合，得到第二比特序列；
    发送所述第二比特序列。
  2. 根据权利要求1所述的方法，其特征在于，所述L个比特集合按照读取顺序依序排列。
  3. 根据权利要求2所述的方法，其特征在于，所述根据至少一个读取间隔从所述第一比特序列中读取比特，得到L个比特集合，包括：
    根据第i个读取间隔，从所述第一比特序列中除去第1个比特集合至第(i-1)个比特集合后的剩余比特中读取至少一个比特，得到第i个比特集合，其中，1≤i≤L，且i为整数。
  4. 根据权利要求3所述的方法，其特征在于，所述第i个读取间隔和第(i-1)个读取间隔相同或不同。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述至少一个读取间隔中的任意一个读取间隔是根据调制阶数或预设函数确定的。
  6. 一种交织装置，其特征在于，包括：
    接收单元，用于获取第一比特序列，所述第一比特序列包括N个比特，N≥2且为整数；
    处理单元，用于根据至少一个读取间隔从所述第一比特序列中读取比特，得到L个比特集合，每个比特集合中包括所述第一比特序列中的至少一个比特，任意两个比特集合中包括的比特在所述第一比特序列中的索引不同，所述L个比特集合中比特数目之和等于所述N，其中，L≥2且为整数；
    所述处理单元，还用于根据所述L个比特集合，得到第二比特序列；
    发送单元，用于发送所述第二比特序列。
  7. 根据权利要求6所述的装置，其特征在于，所述L个比特集合按照读取顺序依序排列。
  8. 根据权利要求6或7所述的装置，其特征在于，所述处理单元具体用于：
    根据第i个读取间隔，从所述第一比特序列中除去第1个比特集合至第(i-1)个比特集合后的剩余比特中读取至少一个比特，得到第i个比特集合，其中，1≤i≤L，且i为整数。
  9. 根据权利要求8所述的装置，其特征在于，所述第i个读取间隔和第(i-1)个读取间隔相同或不同。
  10. 根据权利要求6至9中任一项所述的装置，其特征在于，所述至少一个读取间隔中的任意一个读取间隔是根据调制阶数或预设函数确定的。
  11. 一种计算机可读存储介质，其特征在于，包括计算机指令，当所述计算机指令在计算机上运行时，使得所述计算机执行权利要求1至5中任一项所述的方法。
  12. 一种计算机程序产品，其特征在于，当所述计算机程序产品在计算机上运行时，使得所述计算机执行权利要求1至5中任一项所述的方法。
  13. 一种芯片，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于从所述存储器中调用并运行所述计算机程序，使得安装有所述芯片的通信设备执行权利要求1至5中任一项所述的方法。
  14. 一种交织装置，其特征在于，所述装置用于执行权利要求1-5任意一项所述的方法。
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