WO2019051838A1 - 芯片开短路测试装置、方法及系统 - Google Patents

芯片开短路测试装置、方法及系统 Download PDF

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Publication number
WO2019051838A1
WO2019051838A1 PCT/CN2017/102103 CN2017102103W WO2019051838A1 WO 2019051838 A1 WO2019051838 A1 WO 2019051838A1 CN 2017102103 W CN2017102103 W CN 2017102103W WO 2019051838 A1 WO2019051838 A1 WO 2019051838A1
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WIPO (PCT)
Prior art keywords
point
measured
tested
chip
protection
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PCT/CN2017/102103
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English (en)
French (fr)
Inventor
沈丹禹
杨卓豪
宋海宏
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/102103 priority Critical patent/WO2019051838A1/zh
Publication of WO2019051838A1 publication Critical patent/WO2019051838A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • Embodiments of the present invention relate to the field of chip detection technologies, and in particular, to a chip open short test device, method, and system.
  • the IC (Integrated Circuit) test in the prior art uses the IC to be sent to the test factory after being packaged by the packaging factory, and the test factory utilizes a large ATE (Automatic Test Equipment) for testing.
  • ATE Automatic Test Equipment
  • packaging factories are paying more and more attention to problems in advance.
  • the packaging factory samples the chips in advance of the chip package, and strives to solve the problem at the front end.
  • the open-short test of the chip is one of the most important tests.
  • the cost is higher, in addition to the part used in the open circuit test in ATE, most of the other resources are redundant. This has resulted in a high cost of testing the IC using the ATE in the packaging factory, and most of the functions of the ATE are wasted.
  • one of the technical problems to be solved by the embodiments of the present invention is to provide a chip open-circuit test device, method and system, which overcome the defects of high chip open-circuit test cost in the prior art, and achieve chip open circuit short circuit. Test the effect of lower cost.
  • the embodiment of the invention provides a chip open short test device, which is used for testing an open short circuit of a chip to be tested.
  • the chip to be tested includes a pin protection circuit, and the pin protection circuit has a first point to be tested and a second point to be tested, and the chip
  • the open short test device includes an integrated circuit board, a first protection unit and a second protection unit, the integrated circuit board including a control unit, a first voltage output unit, and a second voltage output unit; wherein the first voltage output unit passes the first protection unit Connected to a first point to be tested in the chip to be tested; the second voltage output unit is connected to the second point to be tested in the chip to be tested through the second protection unit; the control unit passes the first voltage output unit and the second voltage output unit Adjust and measure the first point to be measured and the first The voltage of the two points to be measured, and determining whether the pin protection circuit is short-circuited according to the voltage difference between the first point to be measured and the second point to be measured.
  • the integrated circuit board is an integrated MCU circuit board
  • the integrated MCU circuit board includes a VDD module, a GND module, and an IO module
  • the first voltage output unit is a VDD module, a GND module, or an IO module.
  • the second voltage output unit is an IO module integrated with the MCU circuit board.
  • the pin protection circuit includes a plurality of protection branches, each protection branch includes two protection diodes;
  • the IO module of the second voltage output unit includes an IO interface and a An ADC interface, the IO interface is connected in series with the second point to be tested of the chip to be tested through the second protection unit, and the second point to be measured is located between the two protection diodes of one of the plurality of protection branches, The first ADC interface is connected to the second point to be tested.
  • the VDD module when the first voltage output unit is a VDD module of the integrated MCU circuit board, the VDD module includes a first DAC interface, a second ADC interface, and a third ADC interface, and the first DAC The interface is connected in series with the first to-be-measured point of the chip to be tested by the first protection unit, where the first to-be-measured point is the VDD end of the chip to be tested, the second ADC interface is connected to the first end of the first protection unit, and the third ADC interface is connected. Connected between the second end of the first protection unit and the first point to be tested.
  • the GND module when the first voltage output unit is a GND module of the integrated MCU circuit board, the GND module includes a second DAC interface, a fourth ADC interface, and a fifth ADC interface, and the second DAC The interface is connected in series with the first point to be tested of the chip to be tested by the first protection unit, the first point to be tested is the GND end of the chip to be tested, and the fourth ADC interface is connected to the first end of the first protection unit, the fifth ADC The interface is connected between the second end of the first protection unit and the first point to be tested.
  • the pin protection circuit includes a plurality of protection branches, each protection branch includes two protection diodes; when the first voltage output unit is an integrated MCU circuit board IO
  • the IO module includes an IO interface and a first ADC interface, and the IO interface of the first voltage output unit is connected in series with the first to-be-measured point of the chip to be tested through the first protection unit, and the first to-be-measured point is located in multiple protection branches
  • the first ADC interface of the first voltage output unit is connected to the first point to be tested;
  • the second voltage output unit is the IO module, and the second voltage output unit
  • the IO module includes an IO interface and a first ADC interface, the IO interface is connected in series with the second to-be-measured point of the chip to be tested through the second protection unit, and the second to-be-measured point is located in the other of the plurality of protection branches.
  • control unit determines that the pressure difference between the first to-be-measured point and the second to-be-measured point is less than a minimum value of the predetermined voltage drop range, determining the first to-be-measured point and the second A short circuit between the points to be measured; if it is determined that the pressure difference between the first to-be-measured point and the second to-be-measured point is greater than a maximum value of the predetermined pressure drop range, determining an open circuit between the first to-be-measured point and the second to-be-measured point.
  • control unit determines that the voltage of the first to-be-measured point is equal to the voltage of the second to-be-measured point, determining the first to-be-measured point and the second to-be-tested of the pin protection circuit Short circuit between points.
  • a chip open-circuit test method comprising: adjusting a chip to be tested by controlling a first voltage output unit and a second voltage output unit by a control unit in the chip open-circuit test device described above a voltage of the first to-be-measured point and the second to-be-measured point; the first unit to be tested and the first to be tested by the control unit in the chip open-circuit test device described above through the first voltage output unit and the second voltage output unit
  • the voltage of the two points to be measured is calculated, and the pressure difference between the first point to be measured and the second point to be measured is calculated, and whether a short circuit is opened between the first point to be tested and the second point to be measured is determined according to the pressure difference.
  • the control unit passes the first voltage output unit and the second voltage output unit.
  • Measuring a voltage of the first to-be-measured point and the second to-be-measured point of the chip to be tested, and calculating a pressure difference between the first to-be-measured point and the second to-be-measured point, determining the first to-be-measured point and the second according to the pressure difference Whether the short circuit is to be opened between the points to be measured includes: measuring the voltages of the first end and the second end of the first protection unit, and calculating the voltage drop on the first protection unit, and calculating the current according to the voltage drop and the resistance of the first protection unit a value; measuring a voltage of the first point to be measured and a second point to be measured, and calculating an actual voltage drop between the first point to be measured and the second point to be measured, and
  • measuring voltages of the first to-be-measured point and the second to-be-measured point and calculating a voltage drop between the first to-be-measured point and the second to-be-measured point, according to the current value
  • determining, by the voltage drop, whether there is an open circuit between the first to-be-measured point and the second to-be-measured point comprising: obtaining a predetermined voltage drop range between the first to-be-measured point and the second to-be-measured point corresponding to the current value; If the pressure drop is less than the minimum value of the predetermined pressure drop range, determining a short circuit between the first point to be tested and the second point to be measured; if the actual pressure drop is greater than the maximum value of the predetermined pressure drop range, determining the first point to be measured and the first Open the road between the two points to be measured.
  • the pin protection circuit of the chip to be tested includes multiple a protection branch, each protection branch comprising two protection diodes; if the first point to be measured is located between two protection diodes of one of the plurality of protection branches, the control unit passes the first voltage
  • the output unit and the second voltage output unit measure the voltages of the first to-be-measured point and the second to-be-measured point of the chip to be tested, and calculate a pressure difference between the first to-be-measured point and the second to-be-measured point, and determine according to the pressure difference Whether the short circuit between the first to-be-measured point and the second to-be-measured point includes: if the voltage of the first to-be-measured point is equal to the voltage of the second to-be-measured point, determining between the first to-be-measured point and the second to-be-measured point Short circuit.
  • a chip open short test system comprising an instruction transmitting device, such as the chip open short test device and the chip to be tested, wherein the command transmitting device is connected to the chip open short test device, and receives And sending a test command to the chip open short test device, the chip open short test device is connected with the chip to be tested, and testing the chip to be tested according to the test command.
  • the chip open short test device of the embodiment of the present invention uses the first voltage output unit, the second voltage output unit, the control unit, and the resistor and the chip to be tested on the integrated circuit board to form a test loop, and is tested in an open short circuit.
  • the circuit is simple and compact, the test scheme is flexible, the efficiency is high, the measurement is accurate, and the cost is extremely low.
  • FIG. 1 is a schematic structural view showing a chip open short test device connected to a chip to be tested according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram showing a test circuit of a first voltage output unit of a chip open short test device as a VDD module according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing a test circuit of a first voltage output unit of the chip open short test device as a GND module according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram showing a test circuit of a first voltage output unit of the chip open short test device as an IO module according to an embodiment of the present invention
  • FIG. 5 is a flow chart showing a chip open short test method according to an embodiment of the present invention.
  • FIG. 6 shows a schematic structural view of a chip open short test system in accordance with an embodiment of the present invention.
  • a chip open short test device is used for performing an open short test on a chip 2 to be tested.
  • the chip under test 2 includes a pin protection circuit, and the pin protection circuit has a first to-be-measured point and The second point to be tested.
  • the chip open short test device includes an integrated circuit board 1, a first protection unit and a second protection unit, and the integrated circuit board 1 includes a control unit, a first voltage output unit, and a second voltage output unit.
  • the first voltage output unit is connected to the first point to be tested in the chip to be tested 2 through the first protection unit.
  • the second voltage output unit is connected to the second point to be tested in the chip 2 to be tested through the second protection unit.
  • the control unit adjusts and measures the voltages of the first to-be-measured point and the second to-be-measured point through the first voltage output unit and the second voltage output unit, and determines the pin according to the pressure difference between the first to-be-measured point and the second to-be-measured point. Whether the protection circuit is short-circuited.
  • the integrated circuit board 1 of the chip open-circuit test device is connected to the chip to be tested 2 through the first protection unit and the second protection unit, and utilizes the control unit of the integrated circuit board 1 , the first voltage output unit and the second voltage output.
  • the unit realizes the output and detection of the voltage, and the control unit can determine whether the pin protection circuit is open or shorted according to the voltage difference between the first to-be-measured point and the second to-be-measured point, thereby realizing the test of the open-circuit of the chip 2 to be tested.
  • the chip open-circuit test device can realize open-short test by using the integrated circuit board and the resistor, the circuit is simple and compact, the test plan is flexible, the efficiency is high, the measurement is accurate, the cost is extremely low, and the test can be applied to various chips.
  • the first protection unit and the second protection unit are mainly used to protect the chip 2 to be tested, and form a constant current source with the integrated circuit board 1, and the chip to be tested 2 is tested.
  • the first protection unit and the second protection unit may be resistors, or any structure, circuit, unit, or the like capable of forming an equivalent resistance.
  • the open-short test of the chip is also called open/short test (OS test).
  • the principle of the open short test is based on the principle of the forward voltage drop of the diode in the ESD (Electro-Static discharge) antistatic protection circuit of the chip itself.
  • the pins of the device that normally need to be tested for open-circuit such as IO pins, ground (GND), or power-side (VDD), have ESD protection diodes. By using the principle of diode forward conduction, the pin can be identified. On and off.
  • the pin protection circuit of the chip 2 to be tested includes a plurality of protection branches, and each protection branch includes two protection diodes connected in series.
  • the structure of the pin protection circuit of the chip 2 to be tested may be a different structure.
  • the chip open short test device of this embodiment can realize the open short circuit test of the chip of any structure pin protection circuit.
  • the structure of the first voltage output unit may be the same as or different from the structure of the second voltage output unit, as long as voltage can be applied to the first to-be-measured point and the second to-be-measured point, and a voltage difference can be generated.
  • the first voltage output unit and the second voltage output unit may further have a voltage detecting function or the like.
  • the control unit may determine whether the pin protection circuit is short-circuited according to a voltage difference between the first to-be-measured point and the second to-be-measured point.
  • the first voltage output unit includes a voltage output interface and at least one voltage detection interface.
  • the first voltage output unit is used for outputting a voltage
  • the voltage detecting interface is used for detecting the voltage value.
  • the first voltage output unit may include any number of voltage detection interfaces depending on the structure of the integrated circuit board.
  • the second voltage output unit also includes a voltage output interface and at least one voltage detection interface.
  • the voltage output interface of the second voltage output unit is used for outputting a voltage
  • the voltage detection interface is used for detecting a voltage value.
  • the voltage output from the voltage output interface of the first voltage output unit should be different from the voltage output from the voltage output interface of the second voltage output unit to form a voltage difference.
  • the control unit controls the voltage output interface output voltage and can adjust the voltage value output by the voltage output interface.
  • the control unit can receive the voltage values detected by the voltage detection interface and judge according to the voltage values.
  • the voltage output interface of the first voltage output unit is connected to the first to-be-measured point through the first protection unit, and the at least one voltage detection interface of the first voltage output unit is connected to the first to-be-measured point to detect the first to-be-tested The voltage at the measuring point.
  • the voltage output interface of the second voltage output unit is connected to the second point to be tested through the second protection unit, and the at least one voltage detection interface of the second voltage output unit is connected to the second The points to be measured are connected, and the voltage of the second point to be measured is detected.
  • the first to-be-measured point may be the VDD terminal, the GND terminal, or the IO terminal of the chip 2 to be tested, where the IO terminal is located between two protection diodes connected in series of the protection branch.
  • the second point to be tested may be the IO terminal of the chip 2 to be tested, wherein the IO terminal is located between the two protection diodes in series of the protection branch. If both the first to-be-measured point and the second to-be-measured point are IO terminals, they should be on two different protection branches.
  • the integrated circuit board 1 is an integrated MCU (Microcontroller Unit) circuit board.
  • the integrated MCU circuit board also known as the Single Chip Microcomputer or single-chip microcomputer, appropriately reduces the frequency and specifications of the Central Processing Unit (CPU), and uses memory, counter, and USB, A/D conversion, UART, PLC, DMA and other peripheral interfaces, even LCD driver circuits are integrated on a single chip, forming a chip-level computer, for different combinations of different applications.
  • the control unit can be a self-contained processor or a single-chip microcomputer on the integrated MCU circuit board, or can be other structures.
  • the integrated MCU circuit board includes a VDD module 11, a GND module 12, and an IO module 13.
  • the resources of the integrated MCU board can be used to test the open and short of the pins of the chip 2 to be tested.
  • ADCs Analog-to-Digital Converters, which are devices that convert continuously changing analog signals into discrete digital signals, real-world analog signals, may be utilized, For example, temperature, pressure, sound or image, etc., need to be converted into digital form that is easier to store, process and transmit.
  • Analog to digital converter can convert analog signals into digital signals.
  • Function and DAC Digital to analog converter Converted to an analog signal, a device that converts a digital signal into an analog signal (in the form of current, voltage, or charge) functions to test the chip under test.
  • the VDD end of the chip 2 to be tested is connected to the VDD end of the integrated circuit board 1 , and the GND end of the chip 2 to be tested and the GND end of the integrated circuit board.
  • the IO end of the chip 2 to be tested is connected to the IO end of the integrated circuit board. That is, when the detection loop is formed, the first voltage output unit may be the VDD module 11, the GND module 12, or the IO module 13 of the integrated MCU board.
  • the second voltage output unit is an IO module 13 that integrates the MCU circuit board.
  • the connected circuit can be divided into three types: a normal Pin unit, a power supply Pin unit, and a ground Pin unit.
  • the power supply Pin unit refers to the VDD terminal connected to the VDD module 11 of the integrated MCU circuit board through the protection resistor. The resulting circuit structure.
  • the ground Pin unit refers to the chip to be tested 2
  • the GND terminal is formed by a protection resistor connected to the GND module 12 of the integrated MCU board.
  • the ordinary Pin unit is a circuit structure formed when the normal IO end of the chip 2 to be tested is connected to the IO module 13 of the integrated MCU board through a protection resistor.
  • the first voltage output unit is the VDD module 11 of the integrated MCU circuit board
  • the second voltage output unit is any one of the IO modules 13 of the integrated MCU circuit board.
  • the VDD module 11 includes a first DAC interface 111, a second ADC interface 112, and a third ADC interface 113.
  • the first DAC interface 111 is used to output a voltage.
  • the second ADC interface 112 and the third ADC interface 113 are used to detect voltage.
  • the IO module 13 includes an IO interface 131 and a first ADC interface 132.
  • the IO interface 131 is used for outputting a voltage.
  • the first ADC interface 132 is used to detect voltage.
  • the first DAC interface 111 is connected in series with the first point to be tested of the chip 2 to be tested through the first protection unit 3 (for example, the first resistor), and the first point to be tested is the VDD end of the chip 2 to be tested.
  • the second ADC interface 112 is connected to the first end of the first protection unit 3, and the third ADC interface 113 is connected between the second end of the first protection unit 3 and the first point to be tested.
  • the IO interface 131 is connected in series with the second point to be tested of the chip 2 to be tested by the second protection unit 4 (for example, the second resistor), and the second point to be tested is located in the protection branch of the protection branch. Between the tubes, the first ADC interface 132 is connected to the second point to be tested.
  • the control unit acquires a predetermined pressure drop range between the first to-be-measured point and the second to-be-measured point, and a pressure difference between the first to-be-measured point and the second to-be-measured point.
  • the voltage of the first point to be measured is detected by the third ADC interface 113
  • the voltage of the second point to be measured is detected by the first ADC interface 132.
  • the pressure difference between the first to-be-measured point and the second to-be-measured point is less than a minimum value of the predetermined pressure drop range, determining a short circuit between the first to-be-measured point and the second to-be-measured point. If the pressure difference between the first to-be-measured point and the second to-be-measured point is greater than a maximum value of the predetermined pressure drop range, determining an open circuit between the first to-be-measured point and the second to-be-measured point.
  • the predetermined voltage drop range may be a predetermined voltage drop range, for example, a reasonable voltage drop range is determined based on the characteristics of the protection diode.
  • the integrated MCU board passes the IO module 13 (second voltage output unit) through the control unit
  • the level of the IO interface 131 is pulled high, and the voltage of the IO interface 131 is usually adjusted to about 3.3V.
  • the branch current can be adjusted to a suitable range, for example, about 300 ⁇ A (microamperes).
  • the branch current Cur is calculated as follows:
  • V 113 is a voltage of the second end of the first protection unit 3 (the end connected to the VDD end of the chip 2 to be tested);
  • V 112 is a voltage of a first end of the first protection unit 3 (an end connected to the first DAC interface 111 of the VDD module 11);
  • R 1 is the resistance of the first protection unit 3.
  • the magnitude of the appropriate branch current can be determined according to the characteristics of the protection diode, for example, it can be between 100 ⁇ A and 300 ⁇ A.
  • the voltage drop of the protection diode can be determined and the voltage drop can be judged to be reasonable to determine whether there is an open circuit condition.
  • the voltage at the second point to be measured connected thereto is detected by the first ADC interface 132 of the IO module 13, in combination with the voltage at the first point to be detected detected by the third ADC interface 113 and the first ADC interface 132.
  • the detected voltage at the second point to be measured can determine the voltage drop across the protection diode.
  • the pressure drop on the protection diode is calculated as follows:
  • V V 132 -V 113
  • V is the voltage drop across the protection diode
  • V 132 is a voltage value of a second point to be detected detected by the first ADC interface 132;
  • V 113 is the voltage value of the first point to be detected detected by the third ADC interface 113.
  • the reasonable voltage drop range of the protection diode is 200-900mV. If the voltage drop across the protection diode is greater than 900mV, it is considered to be open to the power supply. If the voltage drop across the protection diode is less than 200mV, it is considered to be a short circuit.
  • the first voltage output unit is a GND module 12 of the integrated MCU circuit board
  • the second voltage output unit is any one of the IO modules 13 of the integrated MCU circuit board.
  • the GND module 12 includes a second DAC interface 121, a fourth ADC interface 122, and a fifth ADC interface 123.
  • the second DAC interface 121 is used for outputting a voltage.
  • the fourth ADC interface 122 and the fifth ADC interface 123 are used to detect voltage.
  • the IO module 13 includes an IO interface 131 and a first ADC interface 132.
  • the IO interface 131 is used for outputting a voltage.
  • the first ADC interface 132 is used to detect voltage.
  • the second DAC interface 121 is connected in series with the first point to be tested of the chip 2 to be tested through the first protection unit 3, and the first point to be tested is the GND end of the chip 2 to be tested, and the fourth ADC interface 122 is connected to the first end of the first protection unit 3, and the fifth ADC interface 123 is connected between the second end of the first protection unit 3 and the first point to be tested.
  • the IO interface 131 is connected in series with the second point to be tested through the second protection unit 4, and the second measurement point is located between the two protection diodes of one of the plurality of protection branches, the first ADC interface 132 and the first The two points to be tested are connected.
  • the integrated MCU board pulls down the level of the IO interface 131 in the IO module 13 (second voltage output unit) through the control unit, and typically adjusts the voltage of the IO interface 131 to 0V.
  • the magnitude of the branch current Cur can be adjusted to an appropriate range.
  • the formula for calculating the branch current Cur is as follows:
  • V 122 is a voltage value of the first end of the first protection unit 3 detected by the fourth ADC interface 122;
  • V 123 is a voltage value of the second end of the first protection unit 3 detected by the fifth ADC interface 123, and the voltage value may also be equivalent to the voltage value of the first point to be tested of the chip 2 to be tested;
  • R 1 is the resistance of the first protection unit 3.
  • the magnitude of the appropriate branch current can be determined according to the characteristics of the protection diode, for example, it can be between 100 ⁇ A and 300 ⁇ A.
  • the voltage drop across the protection diode can be sensed and it is reasonable to determine if there is an open-circuit condition based on this voltage drop value. For example, the voltage at the second point to be measured connected to the first ADC interface 132 of the IO module 13 is detected, and the voltage at the first point to be detected detected by the fifth ADC interface 123 can be determined on the protection diode. Pressure drop. The pressure drop on the protection diode is calculated as follows:
  • V V 123 -V 132
  • V is the voltage drop across the protection diode
  • V 123 is a voltage value of the first point to be detected detected by the fifth ADC interface 123;
  • V 132 is the voltage value of the second point to be detected detected by the first ADC interface 132.
  • the reasonable voltage drop range of the protection diode is 200-900mV. If the voltage drop across the protection diode is greater than 900mV, it is considered to be open to the power supply. If the voltage drop across the protection diode is less than 200mV, it is considered to be a short circuit.
  • the first voltage output unit is an IO module 13
  • the second voltage output unit is another IO module 13 of the integrated MCU circuit board.
  • the IO modules 13 of the first voltage output unit and the second voltage output unit each include an IO interface 131 and a first ADC interface 132.
  • the IO interface 131 is for outputting voltage
  • the first ADC interface 132 is for detecting voltage.
  • the IO interface 131 of the first voltage output unit is connected in series with the first point to be tested of the chip 2 to be tested through the first protection unit 3, and the first point to be measured is located in the protection of one of the plurality of protection branches. Between the diodes, the first ADC interface 132 of the first voltage output unit is connected to the first point to be measured.
  • the IO interface 131 of the second voltage output unit is connected to the second point to be tested of the chip to be tested 2 through the second protection unit 4, and the second protection point is located at the other protection branch of the plurality of protection branches. Between the diodes, the first ADC interface 132 of the second voltage output voltage is connected to the second point to be tested of the chip 2 to be tested.
  • the control unit determines whether the pin protection circuit is short-circuited according to the voltage difference between the first to-be-measured point and the second to-be-measured point. If the voltage of the first to-be-measured point is equal to the voltage of the second to-be-measured point, the pin protection circuit is A short circuit between the point to be measured and the second point to be measured.
  • the level of the IO interface 131 of the second voltage output unit can be raised to form a circuit as shown in FIG.
  • the voltage of the first point to be measured is detected by the first ADC interface 132 of the first voltage output unit, and the voltage of the second point to be measured is detected by the first ADC interface 132 of the second voltage output unit, according to the first point to be measured and the first The voltage of the two points to be measured determines whether the two ordinary Pins are short-circuited.
  • the resistance between the first to-be-measured point and the second to-be-measured point of the chip 2 to be tested is 0, and the voltage value at the first to-be-measured point is equal to or very close to the voltage value at the second to-be-measured point.
  • the integrated circuit board and the resistor are connected to the chip to be tested 2, and the open-circuit test of the chip to be tested 2 is realized.
  • the circuit of the test device is simple to implement, and the constant current source module is replaced by adjusting the branch current, and only one integrated DAC function is needed.
  • the integrated MCU board of the ADC function and the feedback resistor (the first protection unit and the second protection unit can be called feedback resistors) can complete the OS test, so that the test circuit basically has no additional peripheral circuits, and the basic functions can be passed through the software.
  • on-chip resource implementation of the integrated MCU board instead of packaging test equipment (such as WAT machine).
  • the circuit is very simple and compact. When applied, the unit module can be flexibly attached to the test interface board to complete the package failure detection.
  • the chip open-circuit test device module is compact, the measurement scheme is flexible, and can be independently tested, or can be easily integrated into an existing interface board or test board.
  • the first protection unit is mainly used to provide a feedback voltage drop calculation current during testing
  • the second protection unit is mainly used to protect the chip 2 to be tested.
  • the feedback resistor of the first protection unit mainly functions to calculate the current by the voltage across the feedback resistor, thereby adjusting the current.
  • a chip open short test method is provided, and the method includes:
  • Step S502 The control unit in the chip open short test device described above outputs a high voltage by controlling one of the first voltage output unit and the second voltage output unit, and the other of the first voltage output unit and the second voltage output unit The low voltage is output, and the voltages of the first to-be-measured point and the second to-be-measured point of the chip 2 to be tested are adjusted.
  • a voltage is applied to the chip 2 to be tested by the first voltage output unit and the second voltage output unit, thereby testing whether the chip under test 2 has an open short circuit according to the diode forward conduction principle in the protection branch of the chip 2 to be tested.
  • the voltage output interface of the second voltage output unit is controlled to output a low voltage, thereby adjusting the first to-be-measured point and the second to-be-measured point of the chip 2 to be tested.
  • the voltage is used to form a voltage difference on the chip 2 to be tested. Since the voltage outputted by the voltage output interface can be conveniently and flexibly adjusted, the branch current can be more conveniently and accurately controlled, and the current is within a reasonable range to better reflect the test.
  • the characteristics of the protection diode of the chip 2 ensure the detection accuracy.
  • the voltage output interface of the first voltage output unit may be controlled to output a low voltage
  • the voltage output interface of the second voltage output unit may be controlled to output a high voltage
  • Step S504 The control unit in the chip open-circuit test device detects the voltages of the first to-be-measured point and the second-to-be-measured point of the chip 2 to be tested through the first voltage output unit and the second voltage output unit, and calculates the first A pressure difference between the point to be measured and the second point to be measured determines whether a short circuit is opened between the first point to be tested and the second point to be measured according to the pressure difference.
  • the first to-be-measured point is the VDD terminal or the GND terminal of the pin protection circuit of the chip 2 to be tested
  • measure the voltage of the first to-be-measured point and the second to-be-measured point of the chip 2 to be tested and calculate the first
  • the pressure difference between the point to be measured and the second point to be measured determines whether the short circuit between the first point to be tested and the second point to be tested is determined according to the pressure difference:
  • the voltages at the first end and the second end of the first protection unit 3 are measured, and the voltage drop across the first protection unit 3 is calculated, and the current value is calculated based on the voltage drop and the resistance of the first protection unit 3. This current value is used to determine the appropriate current range to better characterize the protection diode to ensure test accuracy.
  • the predetermined voltage drop range may be a predetermined voltage drop range that meets the protection diode characteristics. For example, when the current value is 300 ⁇ A, the reasonable predetermined voltage drop of the protection diode ranges from 200 mV to 900 mV.
  • the actual pressure drop is less than the minimum of the predetermined pressure drop range, a short circuit between the first point to be tested and the second point to be measured is determined. If the actual pressure drop is greater than the maximum value of the predetermined pressure drop range, it is determined that an open circuit is between the first point to be tested and the second point to be measured.
  • the first point to be measured is located between two protection diodes of one of the plurality of protection branches of the pin protection circuit
  • the second point to be measured is located at two of the other protection branches
  • the voltages of the first to-be-measured point and the second to-be-measured point of the chip 2 to be tested are measured, and the voltage difference between the first to-be-measured point and the second to-be-measured point is calculated, and the difference is determined according to the pressure difference.
  • Whether a short circuit is between a point to be measured and a second point to be tested includes:
  • the voltage of the first point to be measured is equal to the voltage of the second point to be measured, it is determined that the first point to be measured is short-circuited with the second point to be measured.
  • the above chip open short test method changes the flow direction of the branch current and adjusts the branch current by changing the voltage output of the integrated MCU board (for example, by adjusting the voltage level of the IO interface 131 and the DAC interface to change the current flow direction, by adjusting the DAC)
  • the voltage of the interface adjusts the current).
  • the chip open-short test method includes the detection of whether the ordinary Pin detects the open or short circuit of VDD, the detection of whether the ordinary Pin is open-circuited to GND, and the detection of whether the ordinary Pin is short-circuited to the ordinary Pin, and the first voltage output unit on the integrated circuit board is used.
  • the second voltage output unit can serve as a constant current source, and the detection circuit is simple.
  • a chip open short test system comprising an instruction transmitting device, such as the chip open short test device and the chip under test 2, wherein the command transmitting device is connected to the chip open short test device, The test command is received and sent to the chip open short test device, and the chip open short test device is connected to the chip to be tested 2, and the test chip 2 is tested according to the test command.
  • the instruction transmitting device may be any device capable of receiving and transmitting an instruction, including but not limited to a computer, an industrial computer, or the like.
  • the chip open-circuit test device can be STM32 (STM32 is based on STMicroelectronics' MCU family based on the ARM Cortex-M3 core specifically designed for embedded applications requiring high performance, low cost, low power consumption).
  • STM32 is based on STMicroelectronics' MCU family based on the ARM Cortex-M3 core specifically designed for embedded applications requiring high performance, low cost, low power consumption.
  • As an integrated MCU circuit board an ADC interface, a DAC interface, and a general IO interface are provided, and the chip to be tested can be tested for opening and shorting according to the above circuit connection method.
  • the chip open short test device can be other integrated circuit boards that can achieve the same function.
  • the chip under test 2 is connected to the chip open short test device.
  • the command sending device can be used to send a test command and save the test log.
  • the chip open short test system may further include an LCD (Liquid Crystal Display) for displaying the test result.
  • LCD Liquid Crystal Display
  • the LCD is an optional module, and the LCD is removed without affecting the test.
  • the chip open short test device, method and system can test the open and short circuit of the test chip, adapt to the IO impedance test for the IC, the circuit is simple to implement, the module is compact, the measurement scheme is flexible, the measurement precision is high, and the OS test requirement can be met. Adjustable current sources with DAC and ADC resources on the integrated MCU board simplify test circuits, reduce test costs, and increase test flexibility. Compared with the previous OS test, the integrated MCU board's own combination of ADC, DAC and feedback resistors replaces the original constant current source. Only an integrated MCU board with sufficient ADC and DAC and resistors can be used. Short circuit test. The circuit is simple and compact, the test scheme is flexible, the efficiency is high, the measurement is accurate, and the cost is extremely low.

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Abstract

一种芯片开短路测试装置、方法及系统，属于芯片测试技术领域。芯片开短路测试装置包括集成电路板（1）、第一保护单元（3）和第二保护单元（4），集成电路板（1）包括控制单元、第一电压输出单元和第二电压输出单元；其中，第一电压输出单元通过第一保护单元（3）与待测芯片（2）中的第一待测点连接；第二电压输出单元通过第二保护单元（4）与待测芯片（2）中的第二待测点连接；控制单元通过第一电压输出单元和第二电压输出单元调节并测量第一待测点和第二待测点的电压，并根据第一待测点和第二待测点的压差确定管脚保护电路是否开短路。该芯片开短路测试装置结构简单，测试效果好。

Description

芯片开短路测试装置、方法及系统 技术领域
本发明实施例涉及芯片检测技术领域，尤其涉及一种芯片开短路测试装置、方法及系统。
背景技术
现有技术中的IC(Integrated Circuit，集成电路)测试采用的是IC在封装厂封装完之后，送到测试厂，由测厂利用大型的ATE(Automatic Test Equipment，自动化测试设备)进行测试。在IC测试领域存在一个十倍法则，即坏品在后道工序被发现，比在前道工序被发现所付出的成本是十倍之多。因此，若测试后发现芯片存在封装或加工问题，需要将芯片再反馈到封装厂，由封装厂改善，由此造成芯片修正成本急剧增加。
为了降低成本，保证生产质量，封装厂也越来越注重提前发现问题。为此，封装厂在芯片封装之前提前进行抽样，力争把问题在前端解决掉。对于封装厂的前端IC测试来说，对芯片进行开短路测试是最为主要的测试之一。但对于封装厂而言，利用大型ATE来测试，成本较高，ATE中除用于开短路测试的部分之外，其它大部分资源是冗余的。这就造成了封装厂采用ATE对IC进行测试成本高,且ATE的大部分功能被闲置浪费。
发明内容
有鉴于此，本发明实施例所解决的技术问题之一在于提供一种芯片开短路测试装置、方法及系统，用以克服现有技术中的芯片开短路测试成本高的缺陷，达到芯片开短路测试成本较低的效果。
本发明实施例提供一种芯片开短路测试装置，用于对待测芯片进行开短路测试，待测芯片包括管脚保护电路，管脚保护电路具有第一待测点和第二待测点，芯片开短路测试装置包括集成电路板、第一保护单元和第二保护单元，集成电路板包括控制单元、第一电压输出单元和第二电压输出单元；其中，第一电压输出单元通过第一保护单元与待测芯片中的第一待测点连接；第二电压输出单元通过第二保护单元与待测芯片中的第二待测点连接；控制单元通过第一电压输出单元和第二电压输出单元调节并测量第一待测点和第 二待测点的电压，并根据第一待测点和第二待测点的压差确定管脚保护电路是否开短路。
可选地，在本发明一具体实施例中，集成电路板为集成MCU电路板，集成MCU电路板包括VDD模块、GND模块和IO模块，第一电压输出单元为VDD模块、GND模块或IO模块。
可选地，在本发明一具体实施例中，第二电压输出单元为集成MCU电路板的IO模块。
可选地，在本发明一具体实施例中，管脚保护电路包括多个保护支路，每个保护支路包括两个保护二级管；第二电压输出单元的IO模块包括IO接口和第一ADC接口，IO接口通过第二保护单元与待测芯片的第二待测点串联，第二待测点位于多个保护支路中的一个保护支路的两个保护二级管之间，第一ADC接口与第二待测点连接。
可选地，在本发明一具体实施例中，当第一电压输出单元为集成MCU电路板的VDD模块时，VDD模块包括第一DAC接口、第二ADC接口和第三ADC接口，第一DAC接口通过第一保护单元与待测芯片的第一待测点串联，第一待测点为待测芯片的VDD端，第二ADC接口与第一保护单元的第一端连接，第三ADC接口连接在第一保护单元的第二端和第一待测点之间。
可选地，在本发明一具体实施例中，当第一电压输出单元为集成MCU电路板的GND模块时，GND模块包括第二DAC接口、第四ADC接口和第五ADC接口，第二DAC接口通过第一保护单元与待测芯片的第一待测点串联，第一待测点为待测芯片的GND端，第四ADC接口连接在第一保护单元的第一端上，第五ADC接口连接在第一保护单元的第二端和第一待测点之间。
可选地，在本发明一具体实施例中，管脚保护电路包括多个保护支路，每个保护支路包括两个保护二级管；当第一电压输出单元为集成MCU电路板的IO模块时，IO模块包括IO接口和第一ADC接口，第一电压输出单元的IO接口通过第一保护单元与待测芯片的第一待测点串联，第一待测点位于多个保护支路中的一个保护支路的两个保护二级管之间，第一电压输出单元的第一ADC接口连接在第一待测点上；第二电压输出单元为IO模块，第二电压输出单元的IO模块包括IO接口和第一ADC接口，IO接口通过第二保护单元与待测芯片的第二待测点串联，第二待测点位于多个保护支路中的另 一个保护支路的两个保护二级管之间，第一ADC接口与第二待测点连接。
可选地，在本发明一具体实施例中，控制单元若确定第一待测点和第二待测点的压差小于预定压降范围的最小值，则确定第一待测点和第二待测点之间短路；若确定第一待测点和第二待测点的压差大于预定压降范围的最大值，则确定第一待测点和第二待测点之间开路。
可选地，在本发明一具体实施例中，控制单元若确定第一待测点的电压等于第二待测点的电压，则确定管脚保护电路的第一待测点和第二待测点之间短路。
根据本发明的另一方面，提供一种芯片开短路测试方法，方法包括：由上述的芯片开短路测试装置中的控制单元通过控制第一电压输出单元和第二电压输出单元调节待测芯片的第一待测点和第二待测点的电压；由上述的芯片开短路测试装置中的控制单元通过第一电压输出单元和第二电压输出单元测量待测芯片的第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的压差，根据压差确定第一待测点和第二待测点之间是否开短路。
可选地，在本发明一具体实施例中，若第一待测点为待测芯片的管脚保护电路的VDD端或GND端，则控制单元通过第一电压输出单元和第二电压输出单元测量待测芯片的第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的压差，根据压差确定第一待测点和第二待测点之间是否开短路包括：测量第一保护单元的第一端和第二端的电压，并计算第一保护单元上的压降，根据压降和第一保护单元的阻值，计算电流值；测量第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的实际压降，根据电流值和实际压降判断第一待测点和第二待测点之间是否存在开短路。
可选地，在本发明一具体实施例中，测量第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的压降，根据电流值和压降判断第一待测点和第二待测点之间是否存在开短路包括：获取与电流值对应的第一待测点和第二待测点之间的预定压降范围；若实际压降小于预定压降范围的最小值，则确定第一待测点和第二待测点之间短路；若实际压降大于预定压降范围的最大值，则确定第一待测点和第二待测点之间开路。
可选地，在本发明一具体实施例中，待测芯片的管脚保护电路包括多个 保护支路，每个保护支路包括两个保护二极管；若第一待测点位于多个保护支路中的一个保护支路的两个保护二级管之间，则控制单元通过第一电压输出单元和第二电压输出单元测量待测芯片的第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的压差，根据压差确定第一待测点和第二待测点之间是否开短路包括：若第一待测点的电压等于第二待测点的电压，则确定第一待测点与第二待测点之间短路。
根据本发明的另一方面，提供一种芯片开短路测试系统，其包括指令发送装置、如上述的芯片开短路测试装置和待测芯片，其中，指令发送装置与芯片开短路测试装置连接，接收并发送测试指令到芯片开短路测试装置，芯片开短路测试装置与待测芯片连接，并根据测试指令测试待测芯片。
由以上技术方案可见，本发明实施例的芯片开短路测试装置利用集成电路板上的第一电压输出单元、第二电压输出单元、控制单元和电阻与待测芯片组成测试回路，在开短路测试时没有额外电路，电路简单小巧，测试方案灵活，效率高，测量准确，成本极低。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本发明的实施例的芯片开短路测试装置与待测芯片连接的结构示意图；
图2示出了根据本发明的实施例的芯片开短路测试装置的第一电压输出单元为VDD模块的测试电路原理图；
图3示出了根据本发明的实施例的芯片开短路测试装置的第一电压输出单元为GND模块的测试电路原理图；
图4示出了根据本发明的实施例的芯片开短路测试装置的第一电压输出单元为IO模块的测试电路原理图；
图5示出了根据本发明的实施例的芯片开短路测试方法的流程示意图；
图6示出了根据本发明的实施例的芯片开短路测试系统的结构示意图。
附图标记说明：
1、集成电路板；11、VDD模块；111、第一DAC接口；112、第二ADC接口；113、第三ADC接口；12、GND模块；121、第二DAC接口；122、第四ADC接口；123、第五ADC接口；13、IO模块；131、IO接口；132、第一ADC接口；2、待测芯片；3、第一保护单元；4、第二保护单元。
具体实施方式
为使得本发明实施例的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明实施例一部分实施例，而非全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明实施例保护的范围。
下面结合本发明实施例附图进一步说明本发明实施例具体实现。
如图1所示，根据本发明的实施例，芯片开短路测试装置用于对待测芯片2进行开短路测试，待测芯片2包括管脚保护电路，管脚保护电路具有第一待测点和第二待测点。芯片开短路测试装置包括集成电路板1、第一保护单元和第二保护单元，集成电路板1包括控制单元、第一电压输出单元和第二电压输出单元。其中，第一电压输出单元通过第一保护单元与待测芯片2中的第一待测点连接。第二电压输出单元通过第二保护单元与待测芯片2中的第二待测点连接。控制单元通过第一电压输出单元和第二电压输出单元调节并测量第一待测点和第二待测点的电压，并根据第一待测点和第二待测点的压差确定管脚保护电路是否开短路。
该芯片开短路测试装置的集成电路板1通过第一保护单元和第二保护单元与待测芯片2实现连接，利用集成电路板1自有的控制单元、第一电压输出单元和第二电压输出单元实现电压的输出和检测，控制单元根据第一待测点和第二待测点的压差就可以确定管脚保护电路是否开短路，从而实现对待测芯片2的开短路的测试。该芯片开短路测试装置利用集成电路板和电阻就可以实现开短路测试，电路简单小巧，测试方案灵活，效率高，测量准确，成本极低，可以适用于各种芯片的测试。
第一保护单元和第二保护单元主要用于保护待测芯片2，与集成电路板1组成恒流源，对待测芯片2进行测试。第一保护单元和第二保护单元可以是电阻，也可以是任何能够形成等效电阻的结构、电路和单元等。
芯片的开短路测试又称open/short test(OS测试)。开短路测试的原理是基于芯片本身管脚(pin)的ESD(Electro-Static discharge)防静电保护电路中的二极管的正向导通压降的原理进行测试。通常需要进行开短路测试的器件的管脚，如IO管脚、对地(GND)或者对电源端(VDD)都有ESD保护二极管，利用二极管正向导通的原理，就可以判别该管脚的通断情况。
在本实施例中，待测芯片2的管脚保护电路包括多个保护支路，每个保护支路包括两个串联的保护二极管。当然，在其他实施例中，待测芯片2的管脚保护电路的结构可以是不同结构。本实施例的芯片开短路测试装置能够实现对任意结构管脚保护电路的芯片的开短路测试。
可选地，第一电压输出单元的结构可以与第二电压输出单元的结构相同，也可以不同，只要能够实现对第一待测点和第二待测点施加电压，并产生压差即可。第一电压输出单元和第二电压输出单元还可以具有电压检测功能等。控制单元可以根据第一待测点和第二待测点之间的压差确定管脚保护电路是否开短路。
例如，第一电压输出单元包括电压输出接口和至少一个电压检测接口。其中，第一电压输出单元用于输出电压，电压检测接口用于检测的电压值。根据集成电路板的结构的不同，第一电压输出单元可以包含任意数量的电压检测接口。第二电压输出单元也包括电压输出接口和至少一个电压检测接口。其中，第二电压输出单元的电压输出接口用于输出电压，电压检测接口用于检测电压值。第一电压输出单元的电压输出接口输出的电压应与第二电压输出单元的电压输出接口输出的电压不同，以形成压差。控制单元控制电压输出接口输出电压，并能够调节电压输出接口输出的电压值。控制单元可以接收电压检测接口检测的电压值，并根据这些电压值进行判断。
可选地，第一电压输出单元的电压输出接口通过第一保护单元与第一待测点连接，第一电压输出单元的至少一个电压检测接口与第一待测点连接，以检测第一待测点的电压。第二电压输出单元的电压输出接口通过第二保护单元与第二待测点连接，第二电压输出单元的至少一个电压检测接口与第二 待测点连接，并检测第二待测点的电压。
如图1所示，在本实施例中，第一待测点可以是待测芯片2的VDD端、GND端或者IO端，其中，IO端位于保护支路的串联的两个保护二极管之间。第二待测点可以是待测芯片2的IO端，其中IO端位于保护支路的串联的两个保护二极管之间。若第一待测点和第二待测点均为IO端，则它们应位于两个不同的保护支路上。
在本实施例中，集成电路板1为集成MCU(Microcontroller Unit，微控制单元)电路板。集成MCU电路板又称单片微型计算机(Single Chip Microcomputer)或者单片机，是把中央处理器(Central Process Unit；CPU)的频率与规格做适当缩减，并将内存(memory)、计数器(Timer)、USB、A/D转换、UART、PLC、DMA等周边接口，甚至LCD驱动电路都整合在单一芯片上，形成芯片级的计算机，为不同的应用场合做不同组合控制。控制单元可以是集成MCU电路板上自有的处理器或单片机等，也可以是其他结构。
参考图1-4，该集成MCU电路板包括VDD模块11、GND模块12和IO模块13。利用该集成MCU电路板的资源就能够对待测芯片2的管脚的开短路进行测试。当然，在其他实施例中，可以利用其他具有ADC(Analog-to-Digital Converter，模拟/数字转换器，是指将连续变化的模拟信号转换为离散的数字信号的器件，真实世界的模拟信号，例如温度、压力、声音或者图像等，需要转换成更容易储存、处理和发射的数字形式。通过模/数转换器可以将模拟信号转换为数字信号)功能和DAC(Digital to analog converter，数字信号转换为模拟信号，是一种将数字信号转换为模拟信号(以电流、电压或电荷的形式)的设备)功能的电路板实现对待测芯片的测试。
如图1所示，在待测芯片2与集成电路板1连接时，待测芯片2的VDD端与集成电路板1的VDD端连接，待测芯片2的GND端与集成电路板的GND端连接，待测芯片2的IO端与集成电路板的IO端连接。即，形成检测回路时，第一电压输出单元可以为集成MCU电路板的VDD模块11、GND模块12或IO模块13。第二电压输出单元为集成MCU电路板的IO模块13。
这样连接后的电路从结构上看，可以分为普通Pin单元、电源Pin单元和地Pin单元三种，其中，电源Pin单元是指VDD端通过保护电阻与集成MCU电路板的VDD模块11连接时形成的电路结构。地Pin单元是指待测芯片2 的GND端通过一个保护电阻与集成MCU电路板的GND模块12连接时形成的电路结构。普通Pin单元是指待测芯片2的普通IO端通过一个保护电阻与集成MCU电路板的IO模块13连接时形成的电路结构。
下面对不同组合的测试过程进行说明：
如图2所示，进行VDD端与普通Pin之间的测试时，以管脚保护电路的一个保护支路的测试为例，其他保护支路的测试方法和过程与之一致：
第一电压输出单元为集成MCU电路板的VDD模块11，第二电压输出单元为集成MCU电路板的任意一个IO模块13。
VDD模块11包括第一DAC接口111、第二ADC接口112和第三ADC接口113。其中，第一DAC接口111用于输出电压。第二ADC接口112和第三ADC接口113用于检测电压。
IO模块13包括IO接口131和第一ADC接口132。其中，IO接口131用于输出电压。第一ADC接口132用于检测电压。
结合参见图1和2，第一DAC接口111通过第一保护单元3(例如第一电阻)与待测芯片2的第一待测点串联，第一待测点为待测芯片2的VDD端，第二ADC接口112与第一保护单元3的第一端连接，第三ADC接口113连接在第一保护单元3的第二端和第一待测点之间。
IO接口131通过第二保护单元4(例如第二电阻)与待测芯片2的第二待测点串联，第二待测点位于多个保护支路中的一个保护支路的两个保护二级管之间，第一ADC接口132与第二待测点连接。
控制单元获取第一待测点和第二待测点之间的预定压降范围以及第一待测点和第二待测点的压差。例如，通过第三ADC接口113检测第一待测点的电压，通过第一ADC接口132检测第二待测点的电压。
若第一待测点和第二待测点的压差小于预定压降范围的最小值，则确定第一待测点和第二待测点之间短路。若第一待测点和第二待测点的压差大于预定压降范围的最大值，则确定第一待测点和第二待测点之间开路。
预定压降范围可以是预先设定的压降范围，例如根据保护二极管的特性确定一个合理的压降范围。
测试时：
集成MCU电路板通过控制单元将IO模块13(第二电压输出单元)中的 IO接口131的电平拉高，通常将IO接口131的电压调整到3.3V左右。
调节VDD模块11中的第一DAC接口111的输出电压，形成如图2所示的电流支路，通过第二ADC接口112检测第一保护单元3的第一端的电压，通过第三ADC接口113检测第一保护单元3的第二端的电压，从而计算出第一保护单元3上的压降，进而结合第一保护单元3的阻值可以求得支路电流Cur的大小。通过调节第一DAC接口111的电压，可以调节支路电流大小到合适的范围，例如300μA(微安)左右。支路电流Cur计算公式如下：
Cur＝(V113–V112)/R1
其中，Cur为支路电流；
V113为第一保护单元3的第二端(与待测芯片2的VDD端连接的一端)的电压；
V112为第一保护单元3的第一端(与VDD模块11的第一DAC接口111连接的一端)的电压；
R1为第一保护单元3的阻值。
需要说明的是，合适的支路电流的大小可以根据保护二极管的特性确定，例如，其可以在100μA到300μA之间。
支路电流调节到合适范围之后，可以确定保护二极管的压降，并判断压降是否合理，从而确定是否存在开短路情况。例如，通过IO模块13的第一ADC接口132检测与之相连接的第二待测点处的电压，结合第三ADC接口113检测到的第一待测点处的电压和第一ADC接口132检测到的第二待测点处的电压，可以确定保护二极管上的压降。保护二极管上的压降计算公式如下：
V＝V132-V113
其中，V为保护二极管上的压降；
V132为第一ADC接口132检测的第二待测点的电压值；
V113为第三ADC接口113检测的第一待测点的电压值。
以合理支路电流为300μA为例，保护二极管的合理压降范围为200-900mV，若保护二极管上的压降大于900mV认为对电源开路，若保护二极管上的压降小于200mV认为是短路。
通过上述方式，可以进行待测芯片2的VDD端与普通Pin之间的开短路 测试。
如图3所示，进行GND端与普通Pin之间的测试时，以对管脚保护电路的一个保护支路的测试为例，其他保护支路的测试方法和过程与之一致：
第一电压输出单元为集成MCU电路板的GND模块12，第二电压输出单元为集成MCU电路板的任意一个IO模块13。
GND模块12包括第二DAC接口121、第四ADC接口122和第五ADC接口123。其中，第二DAC接口121用于输出电压。第四ADC接口122和第五ADC接口123用于检测电压。
IO模块13包括IO接口131和第一ADC接口132。其中，IO接口131用于输出电压。第一ADC接口132用于检测电压。
结合参见图1和图3，第二DAC接口121通过第一保护单元3与待测芯片2的第一待测点串联，第一待测点为待测芯片2的GND端，第四ADC接口122连接在第一保护单元3的第一端上，第五ADC接口123连接在第一保护单元3的第二端和第一待测点之间。
IO接口131通过第二保护单元4与第二待测点串联，第二测点位于多个保护支路中的一个保护支路的两个保护二级管之间，第一ADC接口132与第二待测点连接。
测试时：
集成MCU电路板通过控制单元将IO模块13(第二电压输出单元)中的IO接口131的电平拉低，通常将IO接口131的电压调整到0V。
调节GND模块12中的第二DAC接口121的输出电压，形成如图3所示的电流支路，通过第四ADC接口122检测第一保护单元3的第一端的电压，通过第五ADC接口123检测第一保护单元3的第二端的电压(此电压值同时也是第一待测点的电压)，从而计算出第一保护单元3上的压降，进而可以求得支路电流Cur的大小。通过调节GND模块12中的第二DAC接口121的输出电压，可以调节支路电流Cur的大小到合适的范围。支路电流Cur的计算公式如下：
Cur＝(V122–V123)/R1
其中，Cur为支路电流；
V122为第四ADC接口122检测的第一保护单元3的第一端的电压值；
V123为第五ADC接口123检测的第一保护单元3的第二端的电压值，这一电压值同时也可以等价于待测芯片2的第一待测点的电压值；
R1为第一保护单元3的阻值。
需要说明的是，合适的支路电流的大小可以根据保护二极管的特性确定，例如，其可以在100μA到300μA之间。
支路电流调节到合适范围之后，可以检测保护二极管上的压降，并根据这一压降值是否合理确定是否存在开短路情况。例如，通过IO模块13的第一ADC接口132检测与之相连接的第二待测点处的电压，结合第五ADC接口123检测的第一待测点处的电压，可以确定保护二极管上的压降。保护二极管上的压降计算公式如下：
V＝V123-V132
其中，V为保护二极管上的压降；
V123为第五ADC接口123检测的第一待测点的电压值；
V132为第一ADC接口132检测的第二待测点的电压值。
以合理支路电流为300μA为例，保护二极管的合理压降范围为200-900mV，若保护二极管上的压降大于900mV认为对电源开路，若保护二极管上的压降小于200mV认为是短路。
通过上述方式，可以进行待测芯片2的GND端与普通Pin之间的开短路测试。
如图4所示，进行普通Pin与普通Pin之间的测试时，以对管脚保护电路的相邻两个保护支路的测试为例，其他保护支路的测试方法和过程与之一致：
第一电压输出单元为IO模块13，第二电压输出单元为集成MCU电路板的另一IO模块13。
第一电压输出单元和第二电压输出单元的IO模块13均包括IO接口131和第一ADC接口132。其中，IO接口131用于输出电压，第一ADC接口132用于检测电压。
第一电压输出单元的IO接口131通过第一保护单元3与待测芯片2的第一待测点串联，第一待测点位于多个保护支路中的一个保护支路的两个保护 二级管之间，第一电压输出单元的第一ADC接口132连接在第一待测点上。
第二电压输出单元的IO接口131通过第二保护单元4与待测芯片2的第二待测点连接，第二待测点位于多个保护支路中的另一个保护支路的两个保护二级管之间，第二电压输出电压的第一ADC接口132连接在待测芯片2的第二待测点上。
控制单元根据第一待测点和第二待测点的压差确定管脚保护电路是否开短路，若第一待测点的电压等于第二待测点的电压，则管脚保护电路的第一待测点和第二待测点之间短路。
测试时：
将第一电压输出单元的IO接口131的电平拉高，将第二电压输出单元的IO接口131的电平拉低，或将第一电压输出单元的IO接口131的电平拉低，将第二电压输出单元的IO接口131的电平拉高均可形成如图4所示电路。
通过第一电压输出单元的第一ADC接口132检测第一待测点的电压，通过第二电压输出单元的第一ADC接口132检测第二待测点的电压，根据第一待测点和第二待测点的电压，判断这两个普通Pin是否短路。短路时，待测芯片2的第一待测点和第二待测点之间的电阻为0，第一待测点处的电压值与第二待测点处的电压值相等或很接近。
通过集成电路板和电阻与待测芯片2连接，实现对待测芯片2的开短路测试，这种测试装置电路实现简单，通过调节支路电流来代替恒流源模块，只需要一个集成了DAC功能、ADC功能的集成MCU电路板和反馈电阻(第一保护单元和第二保护单元均可称为反馈电阻)就可以完成OS测试，这样测试电路基本没有额外的外围电路，基本功能都可以通过软件和集成MCU电路板的片上资源实现，代替封装测试设备(例如WAT机台)。电路非常简单小巧。应用时做成单元模块，灵活附加到测试接口板上就能够完成封装不良检测。
该芯片开短路测试装置模块小巧，测量方案灵活，可以独立测试，也可以很方便地集成到封装现有的接口板或者测试板。上述测试过程中，第一保护单元主要用于测试时提供反馈压降计算电流，第二保护单元主要用于保护待测芯片2。第一保护单元的反馈电阻主要作用是反馈电阻两端电压计算电流，从而调节电流。
如图5所示，根据本发明的另一方面，提供一种芯片开短路测试方法，方法包括：
步骤S502：由上述的芯片开短路测试装置中的控制单元通过控制第一电压输出单元和第二电压输出单元中的一个输出高电压，第一电压输出单元和第二电压输出单元中的另一个输出低电压，调整待测芯片2的第一待测点和第二待测点的电压。
通过第一电压输出单元和第二电压输出单元对待测芯片2施加电压，从而根据待测芯片2的保护支路中的二极管正向导通原理测试待测芯片2是否存在开短路。
例如，通过控制第一电压输出单元的电压输出接口输出高电压，控制第二电压输出单元的电压输出接口输出低电压，从而调整待测芯片2的第一待测点和第二待测点的电压，以在待测芯片2上形成压差，由于电压输出接口输出的电压可以方便灵活地调节，因此可以更加方便准确地控制支路电流，使电流在合理范围内，更好地体现待测芯片2的保护二极管的特性，从而保证检测准确性。
当然为了满足保护二极管的正向导通特性，也可以控制第一电压输出单元的电压输出接口输出低电压，控制第二电压输出单元的电压输出接口输出高电压。
步骤S504：上述的芯片开短路测试装置中的控制单元通过第一电压输出单元和第二电压输出单元测量待测芯片2的第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的压差，根据压差确定第一待测点和第二待测点之间是否开短路。
例如，若第一待测点为待测芯片2的管脚保护电路的VDD端或GND端，则测量待测芯片2的第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的压差，根据压差确定第一待测点和第二待测点之间是否开短路包括：
测量第一保护单元3的第一端和第二端的电压，并计算第一保护单元3上的压降，根据压降和第一保护单元3的阻值，计算电流值。该电流值用于确定合适的电流范围，以较好地体现保护二极管的特性，从而确保测试准确性。
测量第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的实际压降，根据电流值和实际压降判断第一待测点和第二待测点之间是否存在开短路。
其具体包括：
获取与电流值对应的第一待测点和第二待测点之间的预定压降范围。该预定压降范围可以是预先设定的，符合保护二极管特性的合理压降范围，例如当电流值为300μA时，保护二极管的合理的预定压降范围为200mV-900mV。
若实际压降小于预定压降范围的最小值，则确定第一待测点和第二待测点之间短路。若实际压降大于预定压降范围的最大值，则确定第一待测点和第二待测点之间开路。
又例如，若第一待测点位于管脚保护电路的多个保护支路中的一个保护支路的两个保护二级管之间，第二待测点位于另一个保护支路的两个保护二极管之间，则测量待测芯片2的第一待测点和第二待测点的电压，并计算第一待测点和第二待测点之间的压差，根据压差确定第一待测点和第二待测点之间是否开短路包括：
若第一待测点的电压等于第二待测点的电压，则确定第一待测点与第二待测点之间短路。
上述芯片开短路测试方法通过改变集成MCU电路板的电压输出，来改变支路电流的流向和调节支路电流的大小(如通过调节IO接口131和DAC接口的电压高低改变电流流向，通过调节DAC接口的电压调节电流大小)，通过集成MCU电路板可以得到各节点(第一待测点、第二待测点)的电压，从而得到需要的压降，从而根据压降确定是否存在开短路。该芯片开短路测试方法包括了普通Pin对VDD是否开短路的检测、普通Pin对GND是否开短路的检测、和普通Pin对普通Pin是否短路的检测，利用集成电路板上的第一电压输出单元和第二电压输出单元即可充当恒流源，检测电路简单。
根据本发明的另一方面，提供一种芯片开短路测试系统，其包括指令发送装置、如上述的芯片开短路测试装置和待测芯片2，其中，指令发送装置与芯片开短路测试装置连接，接收并发送测试指令到芯片开短路测试装置，芯片开短路测试装置与待测芯片2连接，并根据测试指令测试待测芯片2。
如图6所示，指令发送装置可以是任何能够接收并发送指令的设备，包括但不限于计算机、工控机等。芯片开短路测试装置可以是STM32(STM32是使用意法半导体(STMicroelectronics)基于专为要求高性能、低成本、低功耗的嵌入式应用专门设计的ARM Cortex-M3内核的MCU系列。)，其作为集成MCU电路板提供ADC接口、DAC接口及普通IO接口，根据上述电路连接方法可以对待测芯片进行开短路测试。当然芯片开短路测试装置可以是其他能够实现同样功能的集成电路板。待测芯片2与芯片开短路测试装置连接。
指令发送装置可以用于发送测试命令及保存测试Log。
可选地，芯片开短路测试系统还可以包括LCD(Liquid Crystal Display，液晶显示屏)，用于显示测试结果，需要说明的是LCD属于可选模块，去掉LCD也不影响测试。
芯片开短路测试装置、方法和系统能够对待测芯片的开短路进行测试，适应用于IC的IO阻抗测试，电路实现简单，模块小巧，测量方案灵活，测量精度高，可以满足OS测试需求。利用集成MCU电路板上的DAC和ADC资源实现可调电流源，简化测试电路，降低测试成本，提高测试灵活性。和以往的OS测试相比，利用集成MCU电路板自带的ADC、DAC与反馈电阻组合，代替原本的恒流源，只需要一个有足够ADC、DAC的集成MCU电路板及电阻就可以完成开短路测试。电路简单小巧，测试方案灵活，效率高，测量准确，成本极低。解决了现有技术中OS测试都是使用大型的ATE测试，但是如果封装厂使用ATE测试，ATE的大部分资源是冗余的，造成的测试成本高的问题。与以往大型的ATE测试机相比能够实现开短路测试，且电路简单小巧，成本极低，可以满足封装厂对OS测试的需求。
最后应说明的是：以上实施例仅用以说明本发明实施例的技术方案，而非对其限制；尽管参照前述实施例对本发明实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (14)

  1. 一种芯片开短路测试装置，用于对待测芯片(2)进行开短路测试，所述待测芯片(2)包括管脚保护电路，所述管脚保护电路具有第一待测点和第二待测点，其特征在于，所述芯片开短路测试装置包括集成电路板(1)、第一保护单元(3)和第二保护单元(4)，所述集成电路板(1)包括控制单元、第一电压输出单元和第二电压输出单元；
    其中，
    所述第一电压输出单元通过第一保护单元(3)与所述待测芯片(2)中的第一待测点连接；
    所述第二电压输出单元通过第二保护单元(4)与所述待测芯片(2)中的第二待测点连接；
    所述控制单元通过所述第一电压输出单元和所述第二电压输出单元调节并测量所述第一待测点和所述第二待测点的电压，并根据所述第一待测点和所述第二待测点的压差确定所述管脚保护电路是否开短路。
  2. 根据权利要求1所述的芯片开短路测试装置，其特征在于，所述集成电路板(1)为集成MCU电路板，所述集成MCU电路板包括VDD模块(11)、GND模块(12)和IO模块(13)，所述第一电压输出单元为所述VDD模块(11)、所述GND模块(12)或所述IO模块(13)。
  3. 根据权利要求2所述的芯片开短路测试装置，其特征在于，所述第二电压输出单元为所述集成MCU电路板的IO模块(13)。
  4. 根据权利要求3所述的芯片开短路测试装置，其特征在于，所述管脚保护电路包括多个保护支路，每个保护支路包括两个保护二级管；所述第二电压输出单元的所述IO模块(13)包括IO接口(131)和第一ADC接口(132)，所述IO接口(131)通过所述第二保护单元(4)与所述待测芯片(2)的第二待测点串联，所述第二待测点位于多个保护支路中的一个保护支路的两个保护二级管之间，所述第一ADC接口(132)与所述第二待测点连接。
  5. 根据权利要求2或4所述的芯片开短路测试装置，其特征在于，当所述第一电压输出单元为所述集成MCU电路板的VDD模块(11)时，
    所述VDD模块(11)包括第一DAC接口(111)、第二ADC接口(112) 和第三ADC接口(113)，所述第一DAC接口(111)通过所述第一保护单元(3)与所述待测芯片(2)的第一待测点串联，所述第一待测点为所述待测芯片(2)的VDD端，所述第二ADC接口(112)与所述第一保护单元(3)的第一端连接，所述第三ADC接口(113)连接在所述第一保护单元(3)的第二端和所述第一待测点之间。
  6. 根据权利要求2或4所述的芯片开短路测试装置，其特征在于，当所述第一电压输出单元为所述集成MCU电路板的GND模块(12)时，
    所述GND模块(12)包括第二DAC接口(121)、第四ADC接口(122)和第五ADC接口(123)，所述第二DAC接口(121)通过第一保护单元(3)与所述待测芯片(2)的第一待测点串联，所述第一待测点为所述待测芯片(2)的GND端，所述第四ADC接口(122)连接在所述第一保护单元(3)的第一端上，所述第五ADC接口(123)连接在所述第一保护单元(3)的第二端和所述第一待测点之间。
  7. 根据权利要求2所述的芯片开短路测试装置，其特征在于，所述管脚保护电路包括多个保护支路，每个保护支路包括两个保护二级管；当所述第一电压输出单元为所述集成MCU电路板的IO模块(13)时，
    所述IO模块(13)包括IO接口(131)和第一ADC接口(132)，所述第一电压输出单元的IO接口(131)通过第一保护单元(3)与所述待测芯片(2)的第一待测点串联，所述第一待测点位于多个所述保护支路中的一个保护支路的两个保护二级管之间，所述第一电压输出单元的第一ADC接口(132)连接在所述第一待测点上；
    所述第二电压输出单元为IO模块(13)，所述第二电压输出单元的所述IO模块(13)包括IO接口(131)和第一ADC接口(132)，所述IO接口(131)通过所述第二保护单元(4)与所述待测芯片(2)的第二待测点串联，所述第二待测点位于多个保护支路中的另一个保护支路的两个保护二级管之间，所述第一ADC接口(132)与所述第二待测点连接。
  8. 根据权利要求1所述的芯片开短路测试装置，其特征在于，所述控制单元若确定所述第一待测点和所述第二待测点的压差小于预定压降范围的最小值，则确定所述第一待测点和所述第二待测点之间短路；
    若确定所述第一待测点和所述第二待测点的压差大于所述预定压降范围 的最大值，则确定所述第一待测点和所述第二待测点之间开路。
  9. 根据权利要求1所述的芯片开短路测试装置，其特征在于，所述控制单元若确定所述第一待测点的电压等于第二待测点的电压，则确定管脚保护电路的第一待测点和第二待测点之间短路。
  10. 一种芯片开短路测试方法，其特征在于，所述方法包括：
    由权利要求1-9中任一项所述的芯片开短路测试装置中的控制单元通过控制第一电压输出单元和第二电压输出单元调节待测芯片(2)的第一待测点和第二待测点的电压；
    由权利要求1-9中任一项所述的芯片开短路测试装置中的控制单元通过所述第一电压输出单元和所述第二电压输出单元测量所述待测芯片(2)的第一待测点和所述第二待测点的电压，并计算所述第一待测点和所述第二待测点之间的压差，根据所述压差确定所述第一待测点和所述第二待测点之间是否开短路。
  11. 根据权利要求10所述的方法，其特征在于，若所述第一待测点为待测芯片(2)的管脚保护电路的VDD端或GND端，则控制单元通过所述第一电压输出单元和所述第二电压输出单元测量所述待测芯片(2)的第一待测点和所述第二待测点的电压，并计算所述第一待测点和所述第二待测点之间的压差，根据所述压差确定所述第一待测点和所述第二待测点之间是否开短路包括：
    测量所述第一保护单元(3)的第一端和第二端的电压，并计算所述第一保护单元(3)上的压降，根据所述压降和所述第一保护单元(3)的阻值，计算电流值；
    测量所述第一待测点和所述第二待测点的电压，并计算所述第一待测点和所述第二待测点之间的实际压降，根据所述电流值和所述实际压降判断所述第一待测点和所述第二待测点之间是否存在开短路。
  12. 根据权利要求11所述的方法，其特征在于，测量所述第一待测点和所述第二待测点的电压，并计算所述第一待测点和所述第二待测点之间的压降，根据所述电流值和所述压降判断所述第一待测点和所述第二待测点之间是否存在开短路包括：
    获取与所述电流值对应的所述第一待测点和所述第二待测点之间的预定 压降范围；
    若所述实际压降小于所述预定压降范围的最小值，则确定所述第一待测点和所述第二待测点之间短路；
    若所述实际压降大于所述预定压降范围的最大值，则确定所述第一待测点和所述第二待测点之间开路。
  13. 根据权利要求10所述的方法，其特征在于，所述待测芯片(2)的管脚保护电路包括多个保护支路，每个所述保护支路包括两个保护二极管；若所述第一待测点位于多个所述保护支路中的一个保护支路的两个保护二级管之间，则控制单元通过所述第一电压输出单元和所述第二电压输出单元测量所述待测芯片(2)的第一待测点和所述第二待测点的电压，并计算所述第一待测点和所述第二待测点之间的压差，根据所述压差确定所述第一待测点和所述第二待测点之间是否开短路包括：
    若所述第一待测点的电压等于所述第二待测点的电压，则确定所述第一待测点与所述第二待测点之间短路。
  14. 一种芯片开短路测试系统，其特征在于，包括指令发送装置、如权利要求1-9中任一项所述的芯片开短路测试装置和待测芯片(2)，其中，所述指令发送装置与所述芯片开短路测试装置连接，接收并发送测试指令到所述芯片开短路测试装置，所述芯片开短路测试装置与所述待测芯片(2)连接，并根据所述测试指令测试所述待测芯片(2)。
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CN112698240A (zh) * 2020-11-23 2021-04-23 苏州华兴源创科技股份有限公司 开短路测试装置
CN114859210A (zh) * 2022-04-22 2022-08-05 上海研鼎信息技术有限公司 一种cmos芯片开短路测试系统及测试方法
CN115436777A (zh) * 2022-08-11 2022-12-06 江西晶浩光学有限公司 一种开短路测试装置
CN116256618A (zh) * 2023-03-01 2023-06-13 中船重工安谱（湖北）仪器有限公司 一种短路测试装置、短路测试电路及短路测试方法
CN117420419A (zh) * 2023-11-20 2024-01-19 深圳市微特精密科技股份有限公司 一种用于芯片管脚间的开路或短路测试方法、系统及平台
CN118245311A (zh) * 2023-11-24 2024-06-25 浙江正泰仪器仪表有限责任公司 芯片检测方法、芯片检测装置
CN117970079A (zh) * 2024-03-27 2024-05-03 深圳市晶凯电子技术有限公司 具有管脚开短路定位功能的芯片测试装置及其测试方法
CN117970079B (zh) * 2024-03-27 2024-06-04 深圳市晶凯电子技术有限公司 具有管脚开短路定位功能的芯片测试装置及其测试方法

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