WO2019041818A1 - 像素电路及其驱动方法、显示基板及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2019041818A1
WO2019041818A1 PCT/CN2018/082503 CN2018082503W WO2019041818A1 WO 2019041818 A1 WO2019041818 A1 WO 2019041818A1 CN 2018082503 W CN2018082503 W CN 2018082503W WO 2019041818 A1 WO2019041818 A1 WO 2019041818A1
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Prior art keywords
circuit
sub
driving
transistor
reset
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PCT/CN2018/082503
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English (en)
French (fr)
Inventor
高雪岭
羊振中
彭宽军
秦纬
邹祥祥
杨洋
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京东方科技集团股份有限公司
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Priority to US16/332,783 priority Critical patent/US10803806B2/en
Publication of WO2019041818A1 publication Critical patent/WO2019041818A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, a display substrate, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • Embodiments of the present application provide a pixel circuit and a driving method thereof, a display substrate, a driving method thereof, and a display device, which can at least improve a short-term afterimage problem.
  • a pixel circuit including: a driving reset sub-circuit, a write compensation sub-circuit, a light-emitting reset sub-circuit, a light-emitting enable sub-circuit, a driving sub-circuit, and a light-emitting device;
  • the driving sub-circuit includes a driving a transistor, a source of the driving transistor is connected to the write compensation sub-circuit;
  • the driving reset sub-circuit is respectively connected to the first reset signal terminal, the first initial voltage terminal, and the driving sub-circuit for Controlling, by the first reset signal terminal, inputting a voltage provided by the first initial voltage terminal to a gate of the driving transistor in the driving sub-circuit, resetting a driving sub-circuit; writing a compensation sub-circuit Connecting a scan signal end, a data voltage end, and the driving sub-circuit, respectively, for inputting a data voltage output by the data voltage terminal to the driving sub-circuit under the control of the scanning signal end, and Driving the sub
  • the driving sub-circuit is further connected to the first power voltage terminal; the driving sub-circuit further includes a storage capacitor; a gate of the driving transistor and the driving reset sub-circuit and the writing The compensation sub-circuit is electrically connected, and the first pole and the second pole of the driving transistor are electrically connected to the light-emitting enable sub-circuit and the write compensation sub-circuit; one end of the storage capacitor and the driving transistor The gate is electrically connected, and the other end is electrically connected to the first power voltage terminal.
  • the driving reset sub-circuit includes a first transistor; a gate of the first transistor is electrically connected to the first reset signal end, and a first pole is electrically connected to a gate of the driving transistor, The second pole is electrically connected to the first initial voltage terminal.
  • the write compensation sub-circuit includes a second transistor and a third transistor; a gate of the second transistor is electrically connected to the scan signal end, and a first pole is electrically connected to a gate of the drive transistor a second pole is electrically connected to a drain of the driving transistor; a gate of the third transistor is electrically connected to the scan signal end, a first pole is electrically connected to the data voltage terminal, and a second pole is The drain of the drive transistor is electrically connected.
  • the illuminating reset sub-circuit includes a fourth transistor; a gate of the fourth transistor is electrically connected to the scan signal end, and a first pole is electrically connected to the first initial voltage end, and a second pole Electrically connected to the light emitting device.
  • the illuminating enable sub-circuit includes a fifth transistor and a sixth transistor; a gate of the fifth transistor is electrically connected to the enable signal end, and the first pole and the first power voltage terminal are electrically connected Connected, the second pole is electrically connected to the source of the driving transistor; the gate of the sixth transistor is electrically connected to the enable signal terminal, the first pole is electrically connected to the drain of the driving transistor, and the second The pole is electrically connected to the light emitting device.
  • the light emitting device comprises a light emitting diode; an anode of the light emitting diode is electrically connected to the light emitting enable subcircuit and the light emitting reset subcircuit, and a cathode is electrically connected to the second power voltage terminal.
  • a display substrate comprising an array of sub-pixels, each of the sub-pixels comprising the pixel circuit of the first aspect described above.
  • the scanning signal ends of the pixel circuits in the row of sub-pixels are all connected to one gate line;
  • the display substrate further includes at least one switch sub-circuit, and each of the switch sub-circuits respectively a gate line connection, all of the switch sub-circuits are connected to the second reset signal end and the second initial voltage end;
  • the switch sub-circuit is configured to be under the control of the second reset signal end A voltage supplied from the second initial voltage terminal is input to the gate line, so that the write compensation sub-circuit inputs the data voltage output from the data voltage terminal to the driving sub-circuit in the erasing phase.
  • each of the switch sub-circuits includes a seventh transistor; a gate of the seventh transistor is electrically connected to the second reset signal terminal, and the first pole is electrically connected to the gate line The second pole is electrically connected to the second initial voltage terminal.
  • a display device comprising the display substrate of the second aspect.
  • a fourth aspect provides a driving method of a pixel circuit according to the first aspect, comprising: a reset phase of an image frame, under the control of the first reset signal terminal, driving the reset sub-circuit through the first initial voltage terminal weight a driving sub-circuit; a write compensation phase of an image frame, under the control of the scanning signal end, the write compensation sub-circuit supplies a data voltage to the driving sub-circuit through the data voltage end, and performs data compensation on the driving sub-circuit
  • the illuminating reset sub-circuit resets the illuminating device through the first initial voltage terminal;
  • the illuminating phase of an image frame under the control of the enable signal terminal, the illuminating enable sub-circuit Supplying a voltage supplied from a first power voltage terminal to the driving subcircuit and connecting the driving subcircuit to the light emitting device, the driving sub circuit providing a driving current to the light emitting device; adjacent image frames During the erasing phase, under the control of the
  • a driving method of a display substrate includes sub-pixels, each of the sub-pixels includes the pixel circuit described in the first aspect, and the display substrate further includes at least one switch sub-circuit.
  • Each of the switch sub-circuits is connected to a gate line, and all of the switch sub-circuits are connected to the second reset signal terminal and the second initial voltage terminal.
  • the driving method of the display substrate comprises: a reset phase of an image frame, under the control of the first reset signal end, driving the reset sub-circuit to reset the driving sub-circuit through the first initial voltage end; writing compensation of an image frame
  • the write compensation sub-circuit supplies a data voltage to the driving sub-circuit through the data voltage end, and performs data compensation on the driving sub-circuit; meanwhile, under the control of the scanning signal end, the luminous weight
  • the set sub-circuit resets the light-emitting device through the first initial voltage terminal; in the light-emitting phase of an image frame, under the control of the enable signal terminal, the light-emission enable sub-circuit provides the voltage provided by the first power supply voltage terminal to the Driving the sub-circuit, and connecting the driving sub-circuit to the light-emitting device, the driving sub-circuit providing a driving current to the light-emitting device; a shadowing stage between adjacent image frames, at the first weight Under the control of the signal terminal
  • FIG. 1 is a schematic diagram of a hysteresis effect provided by the related art
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by the present application.
  • FIG. 3 is a schematic diagram of a hysteresis-based effect provided by the present application.
  • FIG. 4 is a schematic diagram showing a specific structure of each sub-circuit of the pixel circuit shown in FIG. 2;
  • 5a-5d are equivalent circuit diagrams of the pixel circuit shown in FIG. 4 corresponding to different situations;
  • FIG. 6 is a schematic view 1 of a display substrate provided by the present application.
  • FIG. 7 is a schematic diagram 2 of a display substrate provided by the present application.
  • FIG. 8 is a schematic flow chart 1 of a driving method for driving a display substrate provided by the present application.
  • FIG. 10 is a schematic flow chart 2 of a driving method for driving a display substrate provided by the present application.
  • Fig. 11 is a timing chart 2 of each signal used when driving the pixel circuit.
  • the short-term afterimage phenomenon is related to the hysteresis effect of the driving transistor in the OLED display.
  • the process of the hysteresis effect is as shown in FIG. 1 , wherein the dotted line in FIG. 1 is the current Ids and the gate of the driving transistor when the source/drain voltage of the driving transistor in the sub-pixel is Vds1 when the maximum gray scale is displayed in the OLED display.
  • the driving current Ids in the sub-pixel needs to be reduced when the maximum gray level is displayed, so the semiconductor layer and the gate insulating layer interface of the driving transistor in the sub-pixel need to perform charge release (Hole Detrapping) ), from A1 point to A2 point, the Vgs value changes from V_w to V_g at this time; when switching from the minimum gray level to the intermediate gray level picture, the driving current Ids of the driving transistor in the sub-pixel needs to be increased when the minimum gray level is displayed, Therefore, the semiconductor layer and the gate insulating layer interface of the TFT in the sub-pixel need to perform charge trapping (Hole Trapping) from A3 to A4, and the Vgs value changes from V_b to V_g.
  • Hole Trapping charge trapping
  • the embodiment of the present application provides a pixel circuit, as shown in FIG. 2, including: a drive reset sub-circuit 10, a write compensation sub-circuit 20, a light-emitting reset sub-circuit 30, a light-emission enable sub-circuit 40, and a drive sub-circuit 50.
  • the light emitting device L; the driving sub circuit 50 includes a driving transistor Td (hereinafter, an example is shown in conjunction with FIG. 4), and the source of the driving transistor Td is connected to the write compensation sub circuit 20.
  • the reset sub-circuit 10 is connected to the first reset signal terminal RST1, the first initial voltage terminal V int1 and the driving sub-circuit 50 for controlling the first reset signal terminal RST1.
  • the voltage supplied from the initial voltage terminal V int1 is input to the driving sub-circuit 50 to reset the driving sub-circuit 50.
  • Writing compensation sub-circuit 20 respectively connected to the scanning signal terminal S, the data voltage terminal D and the driving sub-circuit 50 for inputting the reference voltage outputted by the data voltage terminal D in the erasing phase under the control of the scanning signal terminal S
  • the driving transistor Td is turned on in the erasing phase; in the write compensation phase, the data voltage output from the data voltage terminal D is input to the driving sub-circuit 50, and the driving sub-circuit 50 is subjected to data compensation. .
  • the illuminating reset sub-circuit 30 is connected to the scanning signal terminal S, the first initial voltage terminal V int1 and the anode of the illuminating device L respectively for supplying the voltage of the first initial voltage terminal V int1 under the control of the scanning signal terminal S
  • the light-emitting device L is input to the light-emitting device L, and the cathode of the light-emitting device L is connected to the second power supply voltage terminal ELVSS.
  • the light-emitting enable sub-circuit 40 is respectively connected to the enable signal terminal EM, the first power supply voltage terminal ELVDD, the driving sub-circuit 50 and the light-emitting device L for controlling the first power supply voltage terminal ELVDD under the control of the enable signal terminal EM.
  • the voltage is supplied to the driving sub-circuit 50, and the driving sub-circuit 50 is connected to the light emitting device L.
  • the driving sub-circuit 50 is for supplying a driving current to the light emitting device L.
  • the P-type driving transistor Td will be described as an example. It should be noted that the size of the driving transistor Td is relatively large and has a certain driving capability. Therefore, the driving transistor Td can provide the light emitting device L under the action of the output voltage of the first power supply voltage terminal ELVDD provided by the light-emitting enable sub-circuit 40. A driving current is driven to drive the light emitting device L to emit light.
  • the erasing phase is a time period between adjacent image frames, in which the residual image of the previous frame is eliminated. For any image frame, it goes through the progressive scan from the first row of gate lines to the last row of gate lines. Therefore, the erasing phase occurs when the last row of the previous image frame is scanned and the last row of sub-pixels After the display is completed, before the first line of the next image frame begins scanning.
  • the embodiment of the present application provides a pixel circuit that inputs a data voltage outputted by the data voltage terminal D to the driving transistor Td in the driving sub-circuit 50 in the write compensation phase by the write compensation sub-circuit 20, and performs data on the driving transistor Td.
  • the driving transistor Td emits the light-emitting device L
  • the current flowing through the light-emitting device L is independent of the threshold voltage of the driving transistor Td, thereby eliminating the influence of the threshold voltage on the luminance of the light-emitting, and improving display uniformity.
  • a voltage supplied from the first initial voltage terminal V int1 is input to the gate of the driving transistor Td, and at the same time, a reference voltage (referred to as V D ) output from the data voltage terminal D is input to the driving transistor.
  • the source can cause the Vgs of all the driving transistors Td of the display panel to be simultaneously reset (all equal to V int1 - V D ), so that the driving transistor Td is in an ON state (ON-Bias), that is, all the driving transistors Td at this time
  • the trapping state of the charges is the same, and therefore, regardless of the data voltage of the previous frame, the driving transistor Td performs data voltage writing and compensation from the same state, thereby improving the short-term afterimage problem caused by the hysteresis effect.
  • the maximum gray scale picture and the minimum gray scale picture are switched to the intermediate gray level picture, as shown in FIG. 3, in the pixel stage of each sub-pixel of the display panel, all the driving transistors Td All of them are in an ON state (ON-Bias).
  • the Vgs of the driving transistor Td are the same, and both are located at the uppermost end of the characteristic curve, and the corresponding current Ids is the same (corresponding to point A5 in FIG. 3), and the current Ids is large.
  • the sub-pixel displaying the maximum gray level it reaches the A5 point from the A1 point, and for the sub-pixel displaying the minimum gray level, it reaches the A5 point from the A3 point, and the charge trapping of the driving transistor Td in all the sub-pixels
  • the status is the same. Based on this, when the next image frame is displayed, the current Ids of the driving transistor in each sub-pixel needs to be reduced, so that the semiconductor layer and the gate insulating layer interface of the driving transistor Td in each sub-pixel need to perform charge detrapping.
  • the charge release paths of the respective driving transistors Td are the same, so that the short-term afterimage problem caused by the hysteresis effect can be improved, and the light-emitting luminance can reach the light-emitting luminance corresponding to the B point, which is consistent with the brightness corresponding to the actual gray level.
  • the driving sub-circuit 50 is also connected to the first power supply voltage terminal ELVDD.
  • the driving sub-circuit 50 includes a storage capacitor C st in addition to the driving transistor Td.
  • the gate of the driving transistor Td is electrically connected to the driving reset sub-circuit 10 and the write compensation sub-circuit 20, and both the source and the drain are electrically connected to the light-emission enable sub-circuit 40 and the write compensation sub-circuit 20.
  • One end of the storage capacitor C st is electrically connected to the gate of the driving transistor Td, and the other end is electrically connected to the first power supply voltage terminal ELVDD.
  • the driving sub-circuit 50 may further include a plurality of driving transistors Td connected in parallel.
  • Td driving transistors
  • the above is only an example of the driving sub-circuit 50.
  • Other structures having the same function as the driving sub-circuit 50 are not described herein again, but all should fall within the protection scope of the present application.
  • a P-type transistor will be described as an example in which a transistor other than the driving transistor is turned on, and the P-type transistor is turned on when the gate is input with a low level.
  • One of the first extreme source and the drain, and the second one of the source and the drain is different from the other pole of the first pole.
  • the transistors other than the driving transistors may be other types of transistors, such as N-type transistors, wherein the N-type transistors are turned on when the gate input is high. This application does not limit this.
  • the drive reset sub-circuit 10 includes a first transistor T1.
  • the gate of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode is electrically connected to the gate of the driving transistor Td, and the second electrode is electrically connected to the first initial voltage terminal V int1 .
  • the driving reset sub-circuit 10 may further include a plurality of switching transistors connected in parallel with the first transistor T1.
  • the above is only an example of the drive reset sub-circuit 10.
  • the other structures that are the same as those of the drive reset sub-circuit 10 are not described herein again, but all should fall within the scope of protection of the present application.
  • the write compensation sub-circuit 20 includes a second transistor T2 and a third transistor T3.
  • the gate of the second transistor T2 is electrically connected to the scanning signal terminal S, the first electrode is electrically connected to the gate of the driving transistor Td, and the second electrode is electrically connected to the drain of the driving transistor Td.
  • the gate of the third transistor T3 is electrically connected to the scanning signal terminal S, the first electrode is electrically connected to the data voltage terminal D, and the second electrode is electrically connected to the source of the driving transistor Td.
  • the write compensation sub-circuit 20 may further include a plurality of switching transistors connected in parallel with the second transistor T2, and/or a plurality of switching transistors connected in parallel with the third transistor T3.
  • the foregoing is merely an illustration of the write compensation sub-circuit 20.
  • Other structures having the same functions as those of the write compensation sub-circuit 20 are not described herein again, but are all within the scope of protection of the present application.
  • the light-emitting reset sub-circuit 30 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is electrically connected to the scanning signal terminal S, the first electrode is electrically connected to the first initial voltage terminal V int1 , and the second electrode is electrically connected to the light emitting device L.
  • the light emitting device L includes a light emitting diode, and the light emitting diode may be a semiconductor light emitting diode or an organic light emitting diode.
  • the second electrode of the fourth transistor T4 is electrically connected to the anode of the light emitting diode.
  • the light-emitting reset sub-circuit 30 may further include a plurality of switching transistors connected in parallel with the fourth transistor T4.
  • the foregoing is only an example of the illuminating reset sub-circuit 30.
  • Other structures having the same functions as those of the illuminating reset sub-circuit 30 are not described herein again, but all should fall within the protection scope of the present application.
  • the light-emission enable sub-circuit 40 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is electrically connected to the enable signal terminal EM, the first electrode is electrically connected to the first power supply voltage terminal ELVDD, and the second electrode is electrically connected to the source of the driving transistor Td.
  • the gate of the sixth transistor T6 is electrically connected to the enable signal terminal EM, the first electrode is electrically connected to the drain of the driving transistor Td, and the second electrode is electrically connected to the light emitting device L.
  • the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting diode.
  • the cathode of the light emitting diode is electrically connected to the second power supply voltage terminal ELVSS.
  • the first power voltage terminal ELVDD outputs a constant high voltage
  • the second power voltage terminal ELVSS outputs a constant low voltage.
  • the light-emitting enable sub-circuit 40 may further include a plurality of switching transistors connected in parallel with the fifth transistor T5 and/or a plurality of switching transistors connected in parallel with the sixth transistor T6.
  • the foregoing is merely an illustration of the light-emission enable sub-circuit 40.
  • Other structures having the same function as the light-emission enable sub-circuit 40 are not described herein again, but are all within the scope of the present application.
  • the enable signal terminal EM outputs a high-level signal
  • the data voltage terminal D When the reference voltage of the high level is output (the voltage is recorded as V D at this time), the equivalent circuit diagram of the pixel circuit shown in FIG. 4 is as shown in FIG. 5a, and the first transistor T1, the second transistor T2, and the third transistor T3, The fourth transistor T4 is turned on (the transistor in the off state is indicated by "x").
  • the first transistor T1 and the second transistor T2 are turned on such that the voltage of the first initial voltage terminal V int1 is input to the gate and the drain of the driving transistor Td; and the third transistor T3 is turned on, so that the data voltage terminal D is output.
  • all the driving transistors Td are in an on state, and the driving transistor Td performs data voltage writing and threshold voltage compensation from the same state regardless of the data voltage of the previous frame, thereby improving Short-term afterimage problems due to hysteresis effects.
  • the reference voltage V D data voltage terminal D output should satisfy V int1 -V D ⁇ -
  • the embodiment of the present application further provides a display substrate, as shown in FIG. 6, including sub-pixels arranged in an array, each of the sub-pixels including the above-mentioned pixel circuit.
  • the rectangular frame represents a pixel circuit.
  • a plurality of pixel circuits are arranged in an array on the display substrate, wherein the scanning signal terminal S of the pixel circuit located in each row of sub-pixels can be electrically connected to one scanning signal line CL.
  • the first reset signal terminal RST1 can be electrically connected to the scan signal line CL of the previous row.
  • all the scanning signal lines CL are outputted with a low level signal by causing the first reset signal terminal RST1 in the pixel circuit of the first row of sub-pixels to output a low level signal, and the signal terminal EM is outputted.
  • a high-level signal causes the data voltage terminal D to output a high-level reference voltage (the voltage is recorded as V D ), so that the Vgs of the driving transistor in the pixel circuits of all sub-pixels can be simultaneously reset (all equal to V int1 ) -V D ).
  • the display substrate further includes a plurality of switch sub-circuits 60.
  • One switch sub-circuit 60 is electrically connected to one gate line CL, and all of the switch sub-circuits 60 are connected to the second reset signal end.
  • RST2 is electrically connected to the second initial voltage terminal V int2 ;
  • the switch sub-circuit 60 is configured to input the voltage provided by the second initial voltage terminal V int2 to the corresponding gate line CL under the control of the second reset signal terminal RST2 to
  • the write compensation sub-circuit 20 is caused to input the reference voltage output from the data voltage terminal D to the source of the drive transistor Td in the drive sub-circuit 50 in the erasing stage.
  • the voltage supplied from the second initial voltage terminal V int2 is input to all the gate lines CL, and under the voltage control of the second initial voltage terminal V int2 , the data voltage terminal D
  • the output reference voltage can be input to the sources of all the driving transistors Td; in this case, when the first reset signal terminal RST1 in one row of pixel circuits is electrically connected to the scanning signal line CL of the previous row, the first initial voltage terminal
  • the voltage of V int1 can be input to the gate of the driving transistor Td, so that the Vgs of the driving transistor in the pixel circuits of all the sub-pixels can be simultaneously reset.
  • the voltage of the second initial voltage terminal V int2 should be smaller with respect to the voltage of the first initial voltage terminal V int1 , under the voltage control of the second initial voltage terminal V int2 , It is ensured that the reference voltage output from the data voltage terminal D can be input to the sources of all the driving transistors Td.
  • the reference voltage output from the data voltage terminal D can be input to the source of the driving transistor Td, making the control process simpler.
  • the switch sub-circuit 60 includes a seventh transistor T7.
  • the gate of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode is electrically connected to the gate line CL, and the second electrode is electrically connected to the second initial voltage terminal V int2 .
  • the embodiment of the present application further provides a display device including the above display substrate.
  • the embodiment of the present application further provides a driving method of the foregoing pixel circuit. As shown in FIG. 8, the driving method includes:
  • FIG. 5b an equivalent circuit diagram of a pixel circuit shown in FIG. 4 is as shown in FIG. 5b. It is shown that the first transistor T1 is turned on.
  • the first transistor T1 is turned on, the voltage of the first initial voltage terminal V int1 is input to the gate of the driving transistor Td, and the gate of the driving transistor Td is reset, so that the gate voltage is equal to the first initial voltage terminal V int1
  • the voltage is charged and the storage capacitor Cst is charged to reset the storage capacitor Cst.
  • the first reset signal terminal RST1 is electrically connected to the scan signal line CL connected to the previous row of sub-pixels in the pixel circuit of one row of sub-pixels
  • the scan signal line is connected to the previous row of sub-pixels
  • the first reset signal terminal RST1 of the pixel circuit of the current row of sub-pixels outputs a low level signal.
  • the write compensation sub-circuit 20 supplies the data voltage to the drive sub-circuit 50 through the data voltage terminal D, and The driving sub-circuit 50 performs data compensation; meanwhile, under the control of the scanning signal terminal S, the light-emitting reset sub-circuit 30 resets the light-emitting device L through the first initial voltage terminal V int1 .
  • the equivalent circuit diagram of a pixel circuit shown in FIG. 4 is as shown in FIG. 5c.
  • the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on.
  • V data data voltage
  • Vgs V int1 -V Data ⁇ -
  • is turned on, and when the gate voltage of the driving transistor Td reaches V data -
  • the conduction of the fourth transistor T4 inputs the voltage of the first initial voltage terminal V int1 to the anode of the light-emitting device L, thereby resetting the charge remaining on the anode of the light-emitting device L to protect the light-emitting device L.
  • the first reset signal terminal RST1 is electrically connected to the scan signal line CL connected to the previous row of sub-pixels in the pixel circuit of one row of sub-pixels
  • the scan signal line is connected to the previous row of sub-pixels
  • the first reset signal terminal RST1 of the pixel circuit outputs a high level signal.
  • the illumination enable sub-circuit 40 supplies the voltage provided by the first power supply voltage terminal ELVDD to the driving sub-circuit 50
  • the driving sub-circuit 50 is connected to the light-emitting device L, and the driving sub-circuit 50 supplies a driving current to the light-emitting device L.
  • the fifth transistor T5 is turned on so that the voltage supplied from the first power supply voltage terminal ELVDD can be input to the source of the driving transistor Td, and the sixth transistor T6 is turned on, so that the drain of the driving transistor Td and the anode of the light emitting device L Electrical connection.
  • Vgs V data ⁇
  • of the driving transistor Td the driving transistor Td is turned on, and the driving current of the driving transistor Td flows to the light emitting device L, causing the light emitting device L to emit light.
  • the current Is flowing through the light emitting device L is:
  • K W/L ⁇ C ⁇ u
  • W/L is the aspect ratio of the driving transistor Td
  • C is the channel insulating layer capacitance
  • u is the channel carrier mobility
  • the current flowing through the driving transistor Td is only related to the data voltage supplied from the data voltage terminal D for realizing the display and the voltage supplied from the first power supply voltage terminal ELVDD, irrespective of the threshold voltage Vth of the driving transistor Td, thereby eliminating The influence of the threshold voltage Vth of the driving transistor Td on the luminance of the light-emitting device L is improved, and the uniformity of the luminance of the light-emitting device L is improved.
  • the driving reset sub-circuit 10 is reset driven by the first initial voltage terminal V int1
  • the write compensating sub-circuit 20 supplies a reference voltage to the driving sub-circuit 50 through the data voltage terminal D, so that the driving transistor Td in the driving sub-circuit 50 is in an on state.
  • the equivalent circuit diagram of a pixel circuit shown in FIG. 4 is as shown in FIG. 5a. It is shown that the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on.
  • the first transistor T1 and the second transistor T2 are turned on such that the voltage of the first initial voltage terminal Vint1 is input to the gate and the drain of the driving transistor Td; and the third transistor T3 is turned on, so that the reference of the data voltage terminal D is output
  • the driving transistor Td performs data voltage writing and threshold voltage compensation from the same state, thereby improving the short-term afterimage problem caused by the hysteresis effect.
  • the data voltage V data output from the data terminal D voltage reference voltage and the data voltage V D output terminal D may be the same or different.
  • the gate of the driving transistor Td is reset, so that the Vgs of the driving transistor Td can remain V int1 - V D until the data voltage is written. .
  • the pixel circuit described above when the pixel circuit described above is applied to the display panel, the plurality of pixel circuits are arranged in an array on the display substrate.
  • the scanning signal line CL is turned on line by line to complete the image frame display.
  • all the pixel circuits enter the erasing phase P4.
  • a first transition phase P0 is further included between the erasing phase and the reset phase P1 phase of the next image frame; and between the image frame data writing phase P2 and the lighting phase P3
  • the second transition phase P2' can invert the signals of the scan signal terminal S, the first reset signal terminal RST1, the enable signal terminal EM, and the data voltage terminal D to ensure that the corresponding signal terminal outputs the active level according to the timing in the subsequent stage.
  • the effective level time of the enable signal terminal EM should be longer than the active level time of the scan signal terminal S and the active level time of the data voltage terminal D.
  • the second transition phase P2' is to ensure that the data voltage is written to the drive transistor, ensuring that the LED receives the correct drive current during the illumination phase.
  • the first reset signal terminal RST1 is scanned with the previous row.
  • the scanning signal line CL inputs the scanning signal row by row, and the data signal terminal D outputs the data voltage, so that the pixel circuit in each row of sub-pixels performs the above S10 and The driving process of S11, and under the control of the enable signal terminal EM, causes the pixel circuits in each row of sub-pixels to perform the driving process of S12.
  • the erasing phase is performed. In the erasing phase, all the scanning signal lines CL simultaneously input the scanning signals, and the data signal terminal D outputs the reference voltage to perform the driving process of the above S13.
  • the embodiment of the present application further provides a driving method of a display substrate, the display substrate includes at least one sub-pixel, each of the sub-pixels includes the pixel circuit described above, wherein the scanning signal terminal S and the pixel circuit in each row of sub-pixels
  • the root scan signal line CL is electrically connected
  • one switch sub-circuit 60 is electrically connected to one gate line CL, and all the switch sub-circuits 60 are electrically connected to the second reset signal terminal RST2 and the second initial voltage terminal Vint2 (refer to FIG. 7). Shown).
  • the driving method includes:
  • the write compensation sub-circuit 20 supplies the data voltage to the drive sub-circuit 50 through the data voltage terminal D, and The driving sub-circuit 50 performs data compensation; meanwhile, under the control of the scanning signal terminal S, the light-emitting reset sub-circuit 30 resets the light-emitting device L through the first initial voltage terminal V int1 .
  • an illumination phase P3 of an image frame (as shown in FIG. 11)
  • the illumination enable sub-circuit 40 supplies the voltage provided by the first power supply voltage terminal ELVDD to the driving sub-circuit 50
  • the driving sub-circuit 50 is connected to the light-emitting device L, and the driving sub-circuit 50 supplies a driving current to the light-emitting device L.
  • the scanning signal terminal connected to the gate line CL S outputs a low level signal, so that the scanning signal terminal S outputs a low level signal, and of course, the first reset signal terminal RST1 connected to the gate line CL also outputs a low level signal.
  • the first transition phase P0 is further included between the erasing phase P4 and the reset phase P1 phase of the next frame, and is also between an image frame data writing phase P2 and the lighting phase P3. Includes a second transition phase P2'.
  • the first transition phase P0 can invert the signals of the scan signal terminal S, the first reset signal terminal RST1, the enable signal terminal EM, and the data voltage terminal D to ensure that the corresponding signal terminal outputs the active level according to the timing in the subsequent stage.
  • the effective level time of the enable signal terminal EM should be longer than the active level time of the scan signal terminal S and the active level time of the data voltage terminal D.
  • the second transition phase P2' is to ensure that the data voltage is written to the drive transistor, ensuring that the LED receives the correct drive current during the illumination phase.

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Abstract

一种像素电路及其驱动方法、显示基板及其驱动方法、显示装置。像素电路包括：驱动重置子电路（10），用于在第一重置信号端（RST1）的控制下，将第一初始电压端（Vint1）的电压输入至驱动子电路（50）中驱动晶体管（Td）的栅极；写入补偿子电路（20），用于在扫描信号端（S）的控制下，在写入补偿阶段将数据电压输入至驱动子电路（50），并对驱动子电路（50）进行补偿；以及在消影阶段将数据电压端（D）输出的参考电压输入至驱动子电路（50），使驱动晶体管（Td）处于导通状态；发光重置子电路（30），用于在扫描信号端（S）的控制下，将第一初始电压端（Vint1）的电压输入至发光器件（L）进行重置；发光使能子电路（40），用于在使能信号端（EM）的控制下，将第一电源电压端（Vint1）的电压提供至驱动子电路（50），并使驱动子电路（50）与发光器件（L）连接；驱动子电路（50），用于向发光器件（L）提供驱动电流。

Description

像素电路及其驱动方法、显示基板及其驱动方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示基板及其驱动方法、显示装置。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)显示器是目前研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED具有低能耗、生产成本低、自发光、宽视角及相应速度快等优点。
分析表明，OLED在显示不同灰阶的画面时会出现短期残像现象。
发明内容
本申请的实施例提供一种像素电路及其驱动方法、显示基板及其驱动方法、显示装置，至少可改善短期残像问题。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种像素电路，包括：驱动重置子电路、写入补偿子电路、发光重置子电路、发光使能子电路、驱动子电路和发光器件；所述驱动子电路包括驱动晶体管，所述驱动晶体管的源极与所述写入补偿子电路连接；所述驱动重置子电路，分别连接第一重置信号端、第一初始电压端和驱动子电路，用于在所述第一重置信号端的控制下，将所述第一初始电压端提供的电压输入至所述驱动子电路中所述驱动晶体管的栅极，对驱动子电路进行重置；写入补偿子电路，分别连接扫描信号端、数据电压端和所述驱动子电路，用于在所述扫描信号端的控制下，将所述数据电压端输出的数据电压输入至所述驱动子电路，并对所述驱动子电路进行数据补偿；以及在所述扫描信号端的控制下，在所述驱动重置子电路在所述第一重置信号端的控制下将所述第一初始电压端提供的电压输入至所述驱动子电路中所述驱动晶体管的栅极以对所述驱动子电路进行重置时，将所述数据电压端输出的参考电压输入至所述驱动子电路，使所 述驱动晶体管处于导通状态；发光重置子电路，分别连接所述扫描信号端、所述第一初始电压端和所述发光器件的阳极，用于在所述扫描信号端的控制下，将所述第一初始电压端提供的电压输入至所述发光器件，对所述发光器件进行重置；所述发光器件的阴极连接第二电源电压端；发光使能子电路，分别连接使能信号端、第一电源电压端、所述驱动子电路和所述发光器件，用于在所述使能信号端的控制下，将所述第一电源电压端的电压提供至所述驱动子电路，并使所述驱动子电路与所述发光器件连接；所述驱动子电路，用于向所述发光器件提供驱动电流。
可选的，所述驱动子电路还与所述第一电源电压端连接；所述驱动子电路还包括存储电容；所述驱动晶体管的栅极与所述驱动重置子电路和所述写入补偿子电路电连接，所述驱动晶体管的第一极和第二极均与所述发光使能子电路和所述写入补偿子电路电连接；所述存储电容的一端与所述驱动晶体管的栅极电连接，另一端与所述第一电源电压端电连接。
可选的，所述驱动重置子电路包括第一晶体管；所述第一晶体管的栅极与所述第一重置信号端电连接，第一极与所述驱动晶体管的栅极电连接，第二极与所述第一初始电压端电连接。
可选的，所述写入补偿子电路包括第二晶体管和第三晶体管；所述第二晶体管的栅极与所述扫描信号端电连接，第一极与所述驱动晶体管的栅极电连接，第二极与所述驱动晶体管的漏极电连接；所述第三晶体管的栅极与所述扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述驱动晶体管的漏极电连接。
可选的，所述发光重置子电路包括第四晶体管；所述第四晶体管的栅极与所述扫描信号端电连接，第一极与所述第一初始电压端电连接，第二极与所述发光器件电连接。
可选的，所述发光使能子电路包括第五晶体管和第六晶体管；所述第五晶体管的栅极与所述使能信号端电连接，第一极与所述第一电源电压端电连接，第二极与所述驱动晶体管的源极电连接；所述第六晶体管的栅极与所述使能信号端电连接，第一极与所述驱动晶体管的漏极电连接，第二极与所述发光器件电连接。
可选的，所述发光器件包括发光二极管；所述发光二极管的阳极与所 述发光使能子电路和所述发光重置子电路电连接，阴极与所述第二电源电压端电连接。
第二方面，提供一种显示基板，包括阵列设置的子像素，每个所述子像素均包括上述第一方面所述的像素电路。
可选的，一行子像素中所述像素电路的扫描信号端均与一根栅线连接；所述显示基板还包括至少一个开关子电路，所述开关子电路中的每个开关子电路分别与一根栅线连接，所有所述开关子电路均与第二重置信号端和第二初始电压端连接；所述开关子电路用于在所述第二重置信号端的控制下，将所述第二初始电压端提供的电压输入至所述栅线，以使写入补偿子电路在消影阶段将数据电压端输出的数据电压输入至驱动子电路。
进一步的，所述开关子电路中的每个开关子电路包括第七晶体管；所述第七晶体管的栅极与所述第二重置信号端电连接，第一极与所述栅线电连接，第二极与所述第二初始电压端电连接。
第三方面，提供一种显示装置，包括第二方面所述的显示基板。
第四方面，提供一种第一方面所述像素电路的驱动方法，包括：一图像帧的重置阶段，在第一重置信号端的控制下，驱动重置子电路通过第一初始电压端重置驱动子电路；一图像帧的写入补偿阶段，在扫描信号端的控制下，写入补偿子电路通过数据电压端向所述驱动子电路提供数据电压，并对所述驱动子电路进行数据补偿；同时，在扫描信号端的控制下，发光重置子电路通过所述第一初始电压端重置发光器件；一图像帧的发光阶段，在使能信号端输的控制下，发光使能子电路将第一电源电压端提供的电压提供至所述驱动子电路，并使所述驱动子电路与所述发光器件连接，所述驱动子电路向所述发光器件提供驱动电流；相邻图像帧之间的消影阶段，在所述第一重置信号端的控制下，所述驱动重置子电路通过第一初始电压端重置驱动子电路，同时，在所述扫描信号端的控制下，所述写入补偿子电路通过数据电压端向所述驱动子电路提供参考电压，使所述驱动子电路中的驱动晶体管处于导通状态。
第五方面，提供一种显示基板的驱动方法，该显示基板包括子像素，每个所述子像素均包括上述第一方面所述的像素电路；所述显示基板还包括至少一个开关子电路，所述开关子电路中的每个开关子电路分别与一根 栅线连接，所有所述开关子电路均与第二重置信号端和第二初始电压端连接。
该显示基板的驱动方法包括：一图像帧的重置阶段，在第一重置信号端的控制下，驱动重置子电路通过第一初始电压端重置驱动子电路；一图像帧的写入补偿阶段，在扫描信号端的控制下，写入补偿子电路通过数据电压端向所述驱动子电路提供数据电压，并对所述驱动子电路进行数据补偿；同时，在扫描信号端的控制下，发光重置子电路通过所述第一初始电压端重置发光器件；一图像帧的发光阶段，在使能信号端输的控制下，发光使能子电路将第一电源电压端提供的电压提供至所述驱动子电路，并使所述驱动子电路与所述发光器件连接，所述驱动子电路向所述发光器件提供驱动电流；相邻图像帧之间的消影阶段，在所述第一重置信号端的控制下，所述驱动重置子电路通过第一初始电压端重置驱动子电路，同时，在第二重置信号端的控制下，第二初始电压端提供的电压通过开关子电路输入至栅线，以使所述写入补偿子电路通过数据电压端向所述驱动子电路提供参考电压，使所述驱动子电路中的驱动晶体管处于导通状态。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的一种迟滞效应的示意图；
图2为本申请提供的一种像素电路的结构示意图；
图3为本申请提供的一种基于迟滞效应的示意图；
图4为图2所示像素电路的各个子电路的一种具体结构示意图；
图5a-图5d为图4所示的像素电路对应不同情况时的等效电路图；
图6为本申请提供的一种显示基板的示意图一；
图7为本申请提供的一种显示基板的示意图二；
图8为本申请提供的一种驱动显示基板的驱动方法流程示意图一；
图9为驱动像素电路时采用的各个信号的时序图一；
图10为本申请提供的一种驱动显示基板的驱动方法流程示意图二；
图11为驱动像素电路时采用的各个信号的时序图二。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
短期残像现象和OLED显示器中驱动晶体管的迟滞效应有关。该迟滞效应的过程如图1所示，其中，图1中点划线为OLED显示器中显示最大灰阶时子像素中的驱动晶体管的源漏电压为Vds1时，该驱动晶体管的电流Ids与栅源电压(Vgs)的特性曲线；虚线为显示最小灰阶时子像素中的驱动晶体管的源漏电压为Vds3时，驱动晶体管的电流Ids与Vgs的特性曲线；实线为显示中间灰阶画面时子像素中的驱动晶体管的源漏电压为Vds2时，驱动晶体管的电流与Vgs的特性曲线。
当最大灰阶切换至中间灰阶画面时，显示最大灰阶时子像素内的驱动电流Ids需要减小，因此该子像素中驱动晶体管的半导体层和栅绝缘层界面需要进行电荷释放(Hole Detrapping)，由A1点到A2点，此时Vgs值由V_w变化为V_g；当从最小灰阶切换至中间灰阶画面时，显示最小灰阶时子像素中驱动晶体管的驱动电流Ids需要增大，因此该子像素内TFT的半导体层和栅绝缘层界面需要进行电荷捕获(Hole Trapping)，由A3点到A4点，此时Vgs值由V_b变化为V_g。由此可以看出，由于电荷俘获和释放过程中电压变化的路径不同，因此沿不同路径到达电压V_g的A2点和A4点分别对应的驱动电流Ids不同，因此使得由最大灰阶转换至中间灰阶画面的子像素和由最小灰阶转换至中间灰阶画面的子像素之间存在亮度差，从而出现短期残像现象。经过放置一段时间后，上述A2点和A4点均到达到B点，残像消失。
本申请实施例提供一种像素电路，如图2所示，包括：驱动重置 子电路10、写入补偿子电路20、发光重置子电路30、发光使能子电路40、驱动子电路50和发光器件L；驱动子电路50包括驱动晶体管Td(下面结合图4示出了一个示例)，驱动晶体管Td的源极与写入补偿子电路20连接。
具体的，驱动重置子电路10，分别连接第一重置信号端RST1、第一初始电压端V int1和驱动子电路50，用于在第一重置信号端RST1的控制下，将第一初始电压端V int1提供的电压输入至驱动子电路50，对驱动子电路50进行重置。
写入补偿子电路20，分别连接扫描信号端S、数据电压端D和驱动子电路50，用于在扫描信号端S的控制下，在消影阶段，将数据电压端D输出的参考电压输入至驱动子电路50，使驱动晶体管Td在消影阶段处于导通状态；在写入补偿阶段，将数据电压端D输出的数据电压输入至驱动子电路50，并对驱动子电路50进行数据补偿。
发光重置子电路30，分别连接扫描信号端S、第一初始电压端V int1和发光器件L的阳极，用于在扫描信号端S的控制下，将第一初始电压端V int1提供的电压输入至发光器件L，对发光器件L进行重置；发光器件L的阴极连接第二电源电压端ELVSS。
发光使能子电路40，分别连接使能信号端EM、第一电源电压端ELVDD、驱动子电路50和发光器件L，用于在使能信号端EM的控制下，将第一电源电压端ELVDD的电压提供至驱动子电路50，并使驱动子电路50与发光器件L连接。
驱动子电路50用于向发光器件L提供驱动电流。
下面，以P型驱动晶体管Td为例进行说明。需要说明的是，驱动晶体管Td的尺寸比较大，具有一定的驱动能力，因此，驱动晶体管Td能够在发光使能子电路40提供的第一电源电压端ELVDD输出电压的作用下向发光器件L提供驱动电流，以驱动该发光器件L发光。
可以理解的是，消影阶段为相邻图像帧之间的时间段，在该时间段，用于消除上一帧的残留图像。对于任一图像帧而言，其都经过从第一行栅线到最后一行栅线的逐行扫描，因而，消影阶段发生在前一图像帧的最后一行栅线扫描完且最后一行子像素完成显示之后到下一 图像帧的第一行栅线开始扫描之前。
本申请实施例提供一种像素电路，通过写入补偿子电路20在写入补偿阶段将数据电压端D输出的数据电压输入至驱动子电路50中的驱动晶体管Td，并对驱动晶体管Td进行数据补偿，可使驱动晶体管Td在驱动发光器件L发光时，流过发光器件L的电流与驱动晶体管Td的阈值电压无关，从而消除了阈值电压对发光亮度的影响，提高了显示均一性。此外，在消影阶段，通过将第一初始电压端V int1提供的电压输入至驱动晶体管Td的栅极，同时，将数据电压端D输出的参考电压(记为V D)输入至驱动晶体管的源极，可使显示面板的所有驱动晶体管Td的Vgs进行同时复位(都等于V int1-V D)，使驱动晶体管Td处于导通状态(ON-Bias)，即，此时所有驱动晶体管Td的电荷的捕获状态相同，因此，不论前一帧的数据电压如何，驱动晶体管Td皆由同一状态进行数据电压写入以及补偿，从而可改善因迟滞效应产生的短期残像问题。
以由最大灰阶画面和最小灰阶画面切换至中间灰阶画面为例，如图3所示，在消影阶段时，通过使显示面板的每个子像素的像素电路中，所有的驱动晶体管Td都处于导通状态(ON-Bias)，此时驱动晶体管Td的Vgs相同，均位于特性曲线的最上端，对应的电流Ids相同(对应图3中的A5点)，且该电流Ids很大。即：对于显示最大灰阶的子像素而言，其由A1点到达A5点，对于显示最小灰阶的子像素而言，其由A3点到达A5点，所有子像素中驱动晶体管Td的电荷捕获状态相同。基于此，当显示下一图像帧时，每个子像素内驱动晶体管的电流Ids需要减小，因此各个子像素内驱动晶体管Td的半导体层和栅绝缘层界面均需要进行电荷释放(Hole Detrapping)，且各个驱动晶体管Td的电荷释放路径相同，从而可改善因迟滞效应产生的短期残像问题，发光亮度可以达到B点对应的发光亮度，与实际灰阶对应的亮度一致。
如图4所示，驱动子电路50还与第一电源电压端ELVDD连接。其中，驱动子电路50除包括驱动晶体管Td外，还包括存储电容C st。
其中，驱动晶体管Td的栅极与驱动重置子电路10和写入补偿子 电路20电连接，源极和漏极均与发光使能子电路40和写入补偿子电路20电连接。
存储电容C st的一端与驱动晶体管Td的栅极电连接，另一端与第一电源电压端ELVDD电连接。
需要说明的是，驱动子电路50还可以包括并联的多个驱动晶体管Td。上述仅仅是对驱动子电路50的举例说明，其它与该驱动子电路50功能相同的结构在此不再一一赘述，但都应当属于本申请的保护范围。
下面以除驱动晶体管之外的晶体管为P型晶体管为例进行说明，P型晶体管在栅极输入低电平时导通。第一极为源极和漏极之一，第二极为源极和漏极中的不同于第一极的另一极。当然，除驱动晶体管之外的晶体管也可以是其他类型的晶体管，例如N型晶体管，其中N型晶体管在栅极输入高电平时导通。本申请对此不进行限制。
如图4所示，驱动重置子电路10包括第一晶体管T1。
第一晶体管T1的栅极与第一重置信号端RST1电连接，第一极与驱动晶体管Td的栅极电连接，第二极与第一初始电压端V int1电连接。
需要说明的是，驱动重置子电路10还可以包括与第一晶体管T1并联的多个开关晶体管。上述仅仅是对驱动重置子电路10的举例说明，其它与驱动重置子电路10功能相同的结构在此不再一一赘述，但都应当属于本申请的保护范围。
如图4所示，写入补偿子电路20包括第二晶体管T2和第三晶体管T3。
第二晶体管T2的栅极与扫描信号端S电连接，第一极与驱动晶体管Td的栅极电连接，第二极与驱动晶体管Td的漏极电连接。
第三晶体管T3的栅极与扫描信号端S电连接，第一极与数据电压端D电连接，第二极与驱动晶体管Td的源极电连接。
需要说明的是，写入补偿子电路20还可以包括与第二晶体管T2并联的多个开关晶体管、和/或与第三晶体管T3并联的多个开关晶体管。上述仅仅是对写入补偿子电路20的举例说明，其它与写入补偿子电路20功能相同的结构在此不再一一赘述，但都应当属于本申请的保 护范围。
如图4所示，发光重置子电路30包括第四晶体管T4。
第四晶体管T4的栅极与扫描信号端S电连接，第一极与第一初始电压端V int1电连接，第二极与发光器件L电连接。
其中，发光器件L包括发光二极管，该发光二极管可以为半导体发光二极管或有机发光二极管，第四晶体管T4的第二极与发光二极管的阳极电连接。
需要说明的是，发光重置子电路30还可以包括与第四晶体管T4并联的多个开关晶体管。上述仅仅是对发光重置子电路30的举例说明，其它与发光重置子电路30功能相同的结构在此不再一一赘述，但都应当属于本申请的保护范围。
如图4所示，发光使能子电路40包括第五晶体管T5和第六晶体管T6。
第五晶体管T5的栅极与使能信号端EM电连接，第一极与第一电源电压端ELVDD电连接，第二极与驱动晶体管Td的源极电连接。
第六晶体管T6的栅极与使能信号端EM电连接，第一极与驱动晶体管Td的漏极电连接，第二极与发光器件L电连接。
即，当发光器件L为发光二极管时，第六晶体管T6的第二极与发光二极管的阳极电连接。
发光二极管的阴极则与第二电源电压端ELVSS电连接。其中，本申请中第一电源电压端ELVDD输出恒定的高电压，而第二电源电压端ELVSS输出恒定的低电压。
需要说明的是，发光使能子电路40还可以包括与第五晶体管T5并联的多个开关晶体管、和/或与第六晶体管T6并联的多个开关晶体管。上述仅仅是对发光使能子电路40的举例说明，其它与发光使能子电路40功能相同的结构在此不再一一赘述，但都应当属于本申请的保护范围。
基于上述对各子电路具体电路的描述，在消影阶段，当扫描信号端S和第一重置信号端RST1输出低电平信号，使能信号端EM输出高电平信号，数据电压端D输出高电平的参考电压(此时电压记为V D) 时，图4所示的像素电路的等效电路图如图5a所示，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4均导通(处于截止状态的晶体管以打“×”表示)。
第一晶体管T1和第二晶体管T2的导通，使得第一初始电压端V int1的电压输入至驱动晶体管Td的栅极和漏极；第三晶体管T3的导通，使得数据电压端D输出的参考电压(此时电压记为V D)输入至驱动晶体管的源极，从而使得驱动晶体管Td的Vgs＝V int1-V D，驱动晶体管Td处于导通状态(ON-Bias)，这样，使显示面板的每个子像素的像素电路中，所有的驱动晶体管Td都处于导通状态，不论前一帧的数据电压如何，驱动晶体管Td皆由同一状态进行数据电压写入以及阈值电压补偿，从而可改善因迟滞效应产生的短期残像问题。在本申请中，数据电压端D输出的参考电压V D应满足V int1-V D＜-|Vth|(Vth为驱动晶体管Td的阈值电压)，以使得在V D输入至驱动晶体管的源极且V int1输入至驱动晶体管的栅极时驱动晶体管Td处于导通状态。
本申请实施例还提供一种显示基板，如图6所示，包括阵列设置的子像素，每个子像素均包括上述的像素电路。其中，图6中，矩形框代表像素电路。
例如，多个像素电路在显示基板上阵列排布，其中，位于每一行子像素中像素电路的扫描信号端S可与一根扫描信号线CL电连接。第一重置信号端RST1可与上一行的扫描信号线CL电连接，当上一行扫描信号线CL输入低电平信号时，下一行像素电路中的驱动重置子电路10对驱动晶体管Td的栅极进行重置。
基于此，在消影阶段，通过使第一行子像素的像素电路中第一重置信号端RST1输出低电平信号，使所有扫描信号线CL输出低电平信号，使能信号端EM输出高电平信号，并使数据电压端D输出高电平的参考电压(此时电压记为V D)，便可使所有子像素的像素电路中驱动晶体管的Vgs进行同时复位(都等于V int1-V D)。
可选的，如图7所示，所述显示基板还包括多个开关子电路60，一个开关子电路60与一根栅线CL电连接，所有开关子电路60均与第二重置信号端RST2和第二初始电压端V int2电连接；开关子电路60 用于在第二重置信号端RST2的控制下，将第二初始电压端V int2提供的电压输入至对应的栅线CL，以使写入补偿子电路20在消影阶段将数据电压端D输出的参考电压输入至驱动子电路50中驱动晶体管Td的源极。
即，在第二重置信号端RST2的控制下，将第二初始电压端V int2提供的电压输入至所有栅线CL，而在第二初始电压端V int2的电压控制下，数据电压端D输出的参考电压可输入至所有驱动晶体管Td的源极；在此情况下，当一行像素电路中的第一重置信号端RST1与上一行的扫描信号线CL电连接时，第一初始电压端V int1的电压可输入至驱动晶体管Td的栅极，从而可使所有子像素的像素电路中驱动晶体管的Vgs进行同时复位。
需要说明的是，具体地，对于第二初始电压端V int2的电压，其相对于第一初始电压端V int1的电压，应更小，以在第二初始电压端V int2的电压控制下，确保数据电压端D输出的参考电压能输入至所有驱动晶体管Td的源极。
这样，只需控制第二重置信号端RST2和第二初始电压端V int2的信号，便可使数据电压端D输出的参考电压输入至驱动晶体管Td的源极，使得控制过程更简单。
进一步的，如图7所示，开关子电路60包括第七晶体管T7。
第七晶体管T7的栅极与第二重置信号端RST2电连接，第一极与栅线CL电连接，第二极与第二初始电压端V int2电连接。
本申请实施例还提供一种显示装置，包括上述的显示基板。
本申请实施例还提供一种上述像素电路的驱动方法，如图8所示，该驱动方法包括：
S10、一图像帧的重置阶段P1(如图9所示)，在第一重置信号端RST1的控制下，驱动重置子电路10通过第一初始电压端V int1重置驱动子电路50。
具体的，当第一重置信号端RST1输出低电平信号，扫描信号端S和使能信号端EM输出高电平信号时，图4所示的一个像素电路的等效电路图如图5b所示，第一晶体管T1导通。
第一晶体管T1的导通，将第一初始电压端V int1的电压输入至驱动晶体管Td的栅极，对驱动晶体管Td的栅极进行重置，使栅极电压等于第一初始电压端V int1的电压，并对存储电容Cst进行充电，使存储电容Cst重置。
需要说明的是，在位于一行子像素的像素电路中第一重置信号端RST1和与上一行子像素连接的扫描信号线CL电连接的情况下，当与上一行子像素连接的扫描信号线CL输出低电平信号时，当前行子像素的像素电路中第一重置信号端RST1输出低电平信号。
S11、一图像帧的写入补偿阶段P2(如图9所示)，在扫描信号端S的控制下，写入补偿子电路20通过数据电压端D向驱动子电路50提供数据电压，并对驱动子电路50进行数据补偿；同时，在扫描信号端S的控制下，发光重置子电路30通过第一初始电压端V int1重置发光器件L。
具体的，当扫描信号端S输出低电平信号，第一重置信号端RST1和使能信号端EM输出高电平信号时，图4所示的一个像素电路的等效电路图如图5c所示，第二晶体管T2、第三晶体管T3和第四晶体管T4导通。
第三晶体管T3的导通，可使数据电压端D输出的数据电压(记为V data)输入至驱动晶体管Td的源极，此时第一极的电位为V data，Vgs＝V int1-V data＜-|Vth|，驱动晶体管Td导通；第二晶体管T2的导通，使得驱动晶体管Td的栅极与漏极电连接，从而对存储电容Cst进行充电，与此同时，存储电容Cst对驱动晶体管Td的栅极进行放电，直至栅极的电压达到V data-|Vth|，充电停止。以P型增强型晶体管为例，Vgs＜-|Vth|时打开，而当驱动晶体管Td的栅极电压达到V data-|Vth|，驱动晶体管Td关闭，此时数据写入以及补偿完成。
此外，第四晶体管T4的导通，将第一初始电压端V int1的电压输入至发光器件L的阳极，从而对发光器件L的阳极上残留的电荷进行重置，保护发光器件L。
需要说明的是，在位于一行子像素的像素电路中第一重置信号端RST1和与上一行子像素连接的扫描信号线CL电连接的情况下，当与 上一行子像素连接的扫描信号线CL输出高电平信号时，在与该扫描信号线CL连接的子像素中，像素电路的第一重置信号端RST1输出高电平信号。
S12、一图像帧的发光阶段P3(如图9所示)，在使能信号端EM的控制下，发光使能子电路40将第一电源电压端ELVDD提供的电压提供至驱动子电路50，并使驱动子电路50与发光器件L连接，驱动子电路50向发光器件L提供驱动电流。
当使能信号端EM输出低电平信号，第一重置信号端RST1和扫描信号端S输出高电平信号时，图4所示的一个像素电路的等效电路图如图5d所示，第五晶体管T5和第六晶体管T6导通。
第五晶体管T5的导通，使得第一电源电压端ELVDD提供的电压可输入至驱动晶体管Td的源极，而第六晶体管T6的导通，使得驱动晶体管Td的漏极与发光器件L的阳极电连接。其中，由于驱动晶体管Td的Vgs＝V data-|Vth|-ELVDD＜-|Vth|，因而，驱动晶体管Td导通，驱动晶体管Td的驱动电流流向发光器件L，使发光器件L发光。此时，流经发光器件L的电流Is为：
Is＝1/2×K×|(Vgs-(-|Vth|))| 2
＝1/2×K×|(V data-|Vth|-ELVDD-(-|Vth|))| 2
＝1/2×K×(ELVDD-V data) 2
其中，K＝W/L×C×u，W/L为驱动晶体管Td的宽长比，C为沟道绝缘层电容，u为沟道载流子迁移率。
由此可知，流过驱动晶体管Td的电流只与数据电压端D提供的用于实现显示的数据电压和第一电源电压端ELVDD提供的电压有关，与驱动晶体管Td的阈值电压Vth无关，从而消除了驱动晶体管Td的阈值电压Vth对发光器件L发光亮度的影响，提高了发光器件L亮度的均一性。
S13、相邻图像帧之间的消影阶段P4(如图9所示)，在第一重置信号端RST1的控制下，驱动重置子电路10通过第一初始电压端V int1重置驱动子电路50，同时，在扫描信号端S的控制下，写入补偿子电路20通过数据电压端D向驱动子电路50提供参考电压，使驱动 子电路50中驱动晶体管Td处于导通状态。
具体的，当扫描信号端S和第一重置信号端RST1输出低电平信号，使能信号端EM输出高电平信号时，图4所示的一个像素电路的等效电路图如图5a所示，第一晶体管T1、第二晶体管T2、第三晶体管T3均导通。
第一晶体管T1和第二晶体管T2的导通，使得第一初始电压端Vint1的电压输入至驱动晶体管Td的栅极和漏极；第三晶体管T3的导通，使得数据电压端D输出的参考电压(此时记为V D)输入至驱动晶体管Td的源极，从而使得所有驱动晶体管Td的Vgs＝V int1-V D，驱动晶体管Td导通，这样，不论前一帧的数据电压如何，驱动晶体管Td皆由同一状态进行数据电压写入以及阈值电压补偿，从而可改善因迟滞效应产生的短期残像问题。在本申请中，数据电压端D输出的参考电压V D和数据电压端D输出的数据电压V data可以相同，也可以不同。
需要说明的是，当位于一行子像素的像素电路中第一重置信号端RST1与上一行的扫描信号线CL电连接时，只需控制使所有栅线CL输出低电平信号，当然，第一行子像素的像素电路中第一重置信号端RST1也输出低电平信号，便可使所有驱动晶体管Td导通，且驱动晶体管Td的Vgs＝V int1-V D。
此外，在经过消影阶段后，在下一图像帧的重置阶段时，对驱动晶体管Td的栅极进行重置，可使驱动晶体管Td的Vgs仍然保持V int1-V D，直至数据电压写入。
需要说明的是，当上述的像素电路应用于显示面板时，多个像素电路在显示基板上阵列排布，在显示一图像帧的过程中，扫描信号线CL逐行开启，完成图像帧显示。在所有行子像素中的像素电路都完成P1-P3阶段后，所有像素电路均进入消影阶段P4。
此外，如图9所示，在消影阶段和下一图像帧的重置阶段P1阶段之间还包括第一过渡阶段P0；在图像帧数据写入阶段P2和发光阶段P3之间还包括第二过渡阶段P2’。例如，第一过渡阶段P0可以将扫描信号端S、第一重置信号端RST1、使能信号端EM、数据电压端D的 信号进行翻转，保证后续阶段相应的信号端按时序输出有效电平。可以理解的是，使能信号端EM的有效电平时间应当长于扫描信号端S的有效电平时间和数据电压端D的有效电平时间。第二过渡阶段P2’是为了确保数据电压写入驱动晶体管，保证在发光阶段发光二极管接收正确的驱动电流。
当上述的像素电路设置于显示基板的子像素中，且位于每一行子像素的像素电路中扫描信号端S与一根扫描信号线CL电连接，第一重置信号端RST1与上一行的扫描信号线CL电连接(参考图6所示)时，在一图像帧，扫描信号线CL逐行输入扫描信号，数据信号端D输出数据电压，使每行子像素中的像素电路进行上述S10和S11的驱动过程，并且在使能信号端EM的控制下，使每行子像素中的像素电路进行S12的驱动过程。在一图像帧显示完成之后，进行消影阶段，在消影阶段所有扫描信号线CL同时输入扫描信号，数据信号端D输出参考电压，进行上述S13的驱动过程。
本申请实施例还提供一种显示基板的驱动方法，该显示基板包括至少一个子像素，每个子像素均包括上述的像素电路；其中，位于每一行子像素的像素电路中扫描信号端S与一根扫描信号线CL电连接，且一个开关子电路60与一根栅线CL电连接，所有开关子电路60均与第二重置信号端RST2和第二初始电压端Vint2电连接(参考图7所示)。
如图10所示，该驱动方法包括：
S20、一图像帧的重置阶段P1(如图11所示)，在第一重置信号端RST1的控制下，驱动重置子电路10通过第一初始电压端V int1重置驱动子电路50。
具体可参考上述S10处的描述。
S21、一图像帧的写入补偿阶段P2(如图11所示)，在扫描信号端S的控制下，写入补偿子电路20通过数据电压端D向驱动子电路50提供数据电压，并对驱动子电路50进行数据补偿；同时，在扫描信号端S的控制下，发光重置子电路30通过第一初始电压端V int1重置发光器件L。
具体可参考上述S11处的描述。
S22、一图像帧的发光阶段P3(如图11所示)，在使能信号端EM的控制下，发光使能子电路40将第一电源电压端ELVDD提供的电压提供至驱动子电路50，并使驱动子电路50与发光器件L连接，驱动子电路50向发光器件L提供驱动电流。
具体可参考上述S12处的描述。
S23、相邻图像帧之间的消影阶段(如图11所示)，在第一重置信号端RST1的控制下，驱动重置子电路10通过第一初始电压端V int1重置驱动子电路50，同时，在第二重置信号端RST2的控制下，第二初始电压端V int2提供的电压通过开关子电路60输入至栅线CL，以使写入补偿子电路20通过数据电压端D向驱动子电路50提供参考电压，使驱动子电路50中驱动晶体管Td处于导通状态。
对于所有子像素的像素电路，在第二重置信号端RST2输出信号的控制下，当第二初始电压端V int2提供的电压输入至栅线CL时，与该栅线CL连接的扫描信号端S输出低电平信号，从而使扫描信号端S输出低电平信号，当然与栅线CL连接的第一重置信号端RST1也输出低电平信号。
具体可参考上述S13处的描述。
需要说明的是，针对图11，在消影阶段P4和下一帧的重置阶段P1阶段之间还包括第一过渡阶段P0，在一图像帧数据写入阶段P2和发光阶段P3之间还包括第二过渡阶段P2’。例如，第一过渡阶段P0可以将扫描信号端S、第一重置信号端RST1、使能信号端EM、数据电压端D的信号进行翻转，保证后续阶段相应的信号端按时序输出有效电平。可以理解的是，使能信号端EM的有效电平时间应当长于扫描信号端S的有效电平时间和数据电压端D的有效电平时间。第二过渡阶段P2’是为了确保数据电压写入驱动晶体管，保证在发光阶段发光二极管接收正确的驱动电流。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。 因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种像素电路，其特征在于，包括：驱动重置子电路、写入补偿子电路、发光重置子电路、发光使能子电路、驱动子电路和发光器件；所述驱动子电路包括驱动晶体管，所述驱动晶体管的源极与所述写入补偿子电路连接；
    所述驱动重置子电路，分别连接第一重置信号端、第一初始电压端和驱动子电路，用于在所述第一重置信号端的控制下，将所述第一初始电压端提供的电压输入至所述驱动子电路中所述驱动晶体管的栅极，对所述驱动子电路进行重置；
    写入补偿子电路，分别连接扫描信号端、数据电压端和所述驱动子电路，用于在所述扫描信号端的控制下，将所述数据电压端输出的数据电压输入至所述驱动子电路，并对所述驱动子电路进行数据补偿；以及在所述扫描信号端的控制下，在所述驱动重置子电路在所述第一重置信号端的控制下将所述第一初始电压端提供的电压输入至所述驱动子电路中所述驱动晶体管的栅极以对所述驱动子电路进行重置时，将所述数据电压端输出的参考电压输入至所述驱动子电路，使所述驱动晶体管处于导通状态；
    发光重置子电路，分别连接所述扫描信号端、所述第一初始电压端和所述发光器件，用于在所述扫描信号端的控制下，将所述第一初始电压端提供的电压输入至所述发光器件，对所述发光器件进行重置；
    发光使能子电路，分别连接使能信号端、第一电源电压端、所述驱动子电路和所述发光器件，用于在所述使能信号端的控制下，将所述第一电源电压端的电压提供至所述驱动子电路，并使所述驱动子电路与所述发光器件连接；
    所述驱动子电路，用于向所述发光器件提供驱动电流。
  2. 根据权利要求1所述的像素电路，其特征在于，所述驱动子电路还与所述第一电源电压端连接；
    所述驱动子电路还包括存储电容；
    所述驱动晶体管的栅极与所述驱动重置子电路和所述写入补偿子电路电连接，所述驱动晶体管的第一极和第二极均与所述发光使能子电路和所述写入补偿子电路电连接；
    所述存储电容的一端与所述驱动晶体管的栅极电连接，另一端与所述第一电源电压端电连接。
  3. 根据权利要求1所述的像素电路，其特征在于，所述驱动重置子电路包括第一晶体管；
    所述第一晶体管的栅极与所述第一重置信号端电连接，第一极与所述驱动晶体管的栅极电连接，第二极与所述第一初始电压端电连接。
  4. 根据权利要求1所述的像素电路，其特征在于，所述写入补偿子电路包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极与所述扫描信号端电连接，第一极与所述驱动晶体管的栅极电连接，第二极与所述驱动晶体管的漏极电连接；
    所述第三晶体管的栅极与所述扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述驱动晶体管的源极电连接。
  5. 根据权利要求1所述的像素电路，其特征在于，所述发光重置子电路包括第四晶体管；
    所述第四晶体管的栅极与所述扫描信号端电连接，第一极与所述第一初始电压端电连接，第二极与所述发光器件电连接。
  6. 根据权利要求1所述的像素电路，其特征在于，所述发光使能子电路包括第五晶体管和第六晶体管；
    所述第五晶体管的栅极与所述使能信号端电连接，第一极与所述第一电源电压端电连接，第二极与所述驱动晶体管的源极电连接；
    所述第六晶体管的栅极与所述使能信号端电连接，第一极与所述驱动晶体管的漏极电连接，第二极与所述发光器件电连接。
  7. 根据权利要求1-6任一项所述的像素电路，其特征在于，所述发光器件包括发光二极管；
    所述发光二极管的阳极与所述发光使能子电路和所述发光重置 子电路电连接，阴极与所述第二电源电压端电连接。
  8. 一种显示基板，包括阵列设置的子像素，其特征在于，每个所述子像素均包括权利要求1-7中任一项所述的像素电路。
  9. 根据权利要求8所述的显示基板，其特征在于，一行子像素中所述像素电路的扫描信号端均与一根栅线连接；
    所述显示基板还包括至少一个开关子电路，所述开关子电路中的每个开关子电路分别与一根栅线连接，所有所述开关子电路均与第二重置信号端和第二初始电压端连接；
    所述开关子电路用于在所述第二重置信号端的控制下，将所述第二初始电压端提供的电压输入至所述栅线，以使写入补偿子电路在消影阶段将数据电压端输出的参考电压输入至驱动子电路。
  10. 根据权利要求9所述的显示基板，其特征在于，所述开关子电路中的每个开关子电路包括第七晶体管；
    所述第七晶体管的栅极与所述第二重置信号端电连接，第一极与所述栅线电连接，第二极与所述第二初始电压端电连接。
  11. 一种显示装置，其特征在于，包括权利要求8-10中任一项所述的显示基板。
  12. 一种如权利要求1-7中任一项所述的像素电路的驱动方法，其特征在于，包括：
    一图像帧的重置阶段，在第一重置信号端的控制下，所述驱动重置子电路通过第一初始电压端重置所述驱动子电路；
    一图像帧的写入补偿阶段，在扫描信号端的控制下，所述写入补偿子电路通过数据电压端向所述驱动子电路提供数据电压，并对所述驱动子电路进行数据补偿；同时，在扫描信号端的控制下，所述发光重置子电路通过所述第一初始电压端重置所述发光器件；
    一图像帧的发光阶段，在使能信号端的控制下，发光使能子电路将第一电源电压端提供的电压提供至所述驱动子电路，并使所述驱动子电路与所述发光器件连接，所述驱动子电路向所述发光器件提供驱动电流；
    相邻图像帧之间的消影阶段，在所述第一重置信号端的控制下， 所述驱动重置子电路通过第一初始电压端重置驱动子电路，同时，在所述扫描信号端的控制下，所述写入补偿子电路通过数据电压端向所述驱动子电路提供参考电压，使所述驱动子电路中的驱动晶体管处于导通状态。
  13. 一种如权利要求9-10中任一项所述的显示基板的驱动方法，其特征在于，包括：
    一图像帧的重置阶段，在第一重置信号端的控制下，驱动重置子电路通过第一初始电压端重置驱动子电路；
    一图像帧的写入补偿阶段，在扫描信号端的控制下，写入补偿子电路通过数据电压端向所述驱动子电路提供数据电压，并对所述驱动子电路进行数据补偿；同时，在扫描信号端的控制下，发光重置子电路通过所述第一初始电压端重置发光器件；
    一图像帧的发光阶段，在使能信号端输的控制下，发光使能子电路将第一电源电压端提供的电压提供至所述驱动子电路，并使所述驱动子电路与所述发光器件连接，所述驱动子电路向所述发光器件提供驱动电流；
    相邻图像帧之间的消影阶段，在所述第一重置信号端的控制下，所述驱动重置子电路通过第一初始电压端重置驱动子电路，同时，在第二重置信号端的控制下，第二初始电压端提供的电压通过开关子电路输入至栅线，以使所述写入补偿子电路通过数据电压端向所述驱动子电路提供参考电压，使所述驱动子电路中的驱动晶体管处于导通状态。
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