WO2019033393A1 - 异质结遂穿场效应晶体管及其制备方法 - Google Patents

异质结遂穿场效应晶体管及其制备方法 Download PDF

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WO2019033393A1
WO2019033393A1 PCT/CN2017/098047 CN2017098047W WO2019033393A1 WO 2019033393 A1 WO2019033393 A1 WO 2019033393A1 CN 2017098047 W CN2017098047 W CN 2017098047W WO 2019033393 A1 WO2019033393 A1 WO 2019033393A1
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layer
heterojunction
insulating layer
substrate
heterojunction material
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PCT/CN2017/098047
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English (en)
French (fr)
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李伟
徐挽杰
徐慧龙
张臣雄
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华为技术有限公司
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Priority to PCT/CN2017/098047 priority Critical patent/WO2019033393A1/zh
Priority to CN201780005921.9A priority patent/CN109690786B/zh
Publication of WO2019033393A1 publication Critical patent/WO2019033393A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the embodiments of the present application relate to semiconductor technologies, and in particular, to a Tunnel Field-Effect Transistors (TFET) and a method for fabricating the same.
  • TFET Tunnel Field-Effect Transistors
  • the integrated circuit is continuously reduced according to Moore's Law, but when the size of the transistor enters the 14nm and 10nm nodes, the transistor size is further reduced, and the leakage current caused by the short channel effect is continuously increased, so that the power consumption of the integrated circuit becomes an increasingly serious problem.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the tunneling field effect transistor TFET uses a band-to-band tunneling mechanism with a subthreshold slope (Subthreshold Slope).
  • SS can be lower than 60mV / dec room temperature limit, which can effectively reduce the operating voltage, and dynamic power consumption is proportional to the square of the working voltage, so the integrated circuit fabricated with TFET device can significantly reduce power consumption.
  • TFET architectures are mainly homojunction TFETs with silicon as the channel material and heterojunction TFETs with the III-V material as the channel. Due to the large band gap and indirect bandgap semiconductor properties of silicon materials, the probability of tunneling between the bands is very low, resulting in a silicon-based TFET with an on-state current that is too low to meet the application requirements.
  • the III-V material has the characteristics of small band gap and low effective mass, which makes the heterojunction TFET based on III-V material can obtain a large on-state current, but the presence of a higher density interface state makes it difficult. Obtain an SS of less than 60 mV/dec.
  • Two-dimensional materials have excellent characteristics such as atomic thinness and no dangling bonds on the surface, and interface defects caused by lattice mismatch of heterojunctions based on two-dimensional materials. Therefore, heterojunction TFETs based on two-dimensional materials have advantages over conventional TFETs.
  • the surface of the two-dimensional material has no dangling bonds, but there are still dangling bonds at the boundary of the material, which will increase the leakage current of the two-dimensional material heterojunction TFET.
  • the embodiment of the present application provides a heterojunction tunneling effect transistor and a preparation method thereof, which are used to solve the problem that the surface of the two-dimensional material has no dangling bonds in the foregoing solution, but there is still a dangling bond at the boundary of the material, and the dangling key increases the two-dimensional The problem of the leakage current of the material heterojunction TFET.
  • a first aspect of the present application provides a heterojunction field effect transistor, including:
  • first insulating layer covering an upper surface of the substrate
  • first heterojunction material layer covering an end of the first insulating layer for arranging a source
  • the source is disposed at one end of the first heterojunction material layer, and the other end of the first heterojunction material layer a second insulating layer is disposed around;
  • isolation layer is disposed on the heterojunction layer, and the isolation layer covers an inner side of the source;
  • a second heterojunction material layer covering the other end of the first heterojunction material layer, the second insulating layer, and the second insulating layer, and the first The heterojunction material layer forms a heterojunction
  • drain being disposed on the second heterojunction layer opposite to the source
  • a gate dielectric layer covering a position between the source and the drain on the second heterojunction material layer
  • the gate being disposed on the gate dielectric layer.
  • the material of the first heterojunction material layer is tin selenide SnSe 2
  • the material of the second heterojunction material layer is tungsten selenide WSe 2 ;
  • the material of the first heterojunction material layer is SnSe 2
  • the material of the second heterojunction material layer is molybdenum selenide MoSe 2 ;
  • the material of the first heterojunction material layer is SnSe 2
  • the material of the second heterojunction material layer is molybdenum molybdenum MoTe 2 .
  • the first insulating layer and the second insulating layer are both oxide insulating layers.
  • the material of the first insulating layer is silicon oxide SiO 2 ; the material of the second insulating layer is yttrium oxide Y 2 O 3 or aluminum oxide Al 2 O 3 .
  • the heterojunction is formed by using a two-dimensional material, and interface defects due to lattice mismatch are avoided.
  • a second aspect of the present application provides a heterojunction field effect transistor, including:
  • the source being disposed at one end of an upper surface of the substrate
  • the first insulating layer is embedded in a position on the substrate for providing a drain;
  • the first layer of heterojunction material covering a portion of the first insulating layer and a portion of the substrate on which the source is not disposed, the heterojunction material layer a second insulating layer is disposed around the other end of the first insulating layer;
  • the drain is disposed on the first insulating layer, and the drain is in contact with an outer side of the heterojunction material layer;
  • the gate dielectric layer is located between the source and the drain, and the gate dielectric layer covers the substrate, the second insulating layer, and the heterojunction material layer;
  • the gate being disposed on the gate dielectric layer.
  • the isolation is performed by the second insulating layer, and the leakage current caused by the edge state is significantly reduced.
  • the heterojunction material layer is a tungsten selenide WSe 2 layer.
  • the first insulating layer and the second insulating layer are both oxide insulating layers.
  • the material of the second insulating layer is yttrium oxide Y 2 O 3 .
  • the use of two-dimensional materials to form heterojunctions avoids interface defects caused by lattice mismatch, while using a tunneling structure to increase the tunneling area, using a low barrier stagger-gap
  • the heterojunction increases the tunneling probability and increases the tunneling current.
  • the heterojunction is used and the tunneling barrier width is narrow.
  • a third aspect of the present application provides a method for fabricating a heterojunction field effect transistor, including:
  • a drain region is defined by photolithography, and a metal is vapor-deposited to form a drain;
  • a gate region is defined by photolithography, and a gate dielectric layer is formed by atomic layer deposition, and a gate is disposed on the gate dielectric layer.
  • the edge of the first heterojunction material layer is defined by exposure development. a region, and evaporating metal in the edge region for oxidation to form a second insulating layer, comprising:
  • the edge region is defined by exposure and development SnSe 2 layer, depositing a metal in the edge region of the yttrium SnSe 2 layer, and an oxidation treatment to form Y 2 O 3 insulating layer.
  • the second heterojunction material layer is a WSe 2 layer, and the second heterojunction material is transferred to the first heterojunction material layer, and the morphology is defined by optical exposure and etching is performed.
  • a second heterojunction material layer forming a heterojunction with the first heterojunction material layer comprising:
  • WSe 2 layer transferred onto SnSe 2 is defined by the form of optical exposure using RIE or ICP dry etching the exposed area is removed WSe 2, the resist is removed, WSe 2 layer is formed, and the SnSe 2 The layer forms a heterojunction.
  • the drain region is defined by photolithography, and the metal is vapor-deposited to form a drain, including:
  • a drain region is defined by photolithography on the WSe 2 layer, and a metal Cr/Pt/Au or MoO 3 /Pt is evaporated on the drain region to form a drain connected to the WSe 2 layer.
  • a gate region is defined by photolithography, and a gate dielectric layer is formed by atomic layer deposition, and a gate is disposed on the gate dielectric layer.
  • Photolithography is used to define a gate region on the WSe 2 layer, and a high-k gate dielectric yttrium oxide, aluminum oxide or zirconium oxide is grown by atomic layer deposition to form a gate dielectric layer, and a gate metal is evaporated on the gate dielectric layer. A gate is formed.
  • a fourth aspect of the present application provides a method for fabricating a heterojunction field effect transistor, including:
  • a gate region is defined by photolithography, and a gate dielectric layer is formed by atomic layer deposition, and is disposed on the gate dielectric layer Gate.
  • the recess is etched on the substrate by reactive ion etching RIE, and an oxide isolation layer is formed in the recess to form a first insulating layer, including:
  • An oxide isolation layer is defined on the substrate by photolithography, and a recess is etched on the substrate by reactive ion etching RIE, and an oxide isolation layer is formed in the recess by evaporation or ALD. Forming the first insulating layer.
  • the heterojunction material layer is a tungsten diselenide WSe 2 layer
  • the second insulating layer is made of yttrium oxide Y 2 O 3
  • the heterojunction material layer is defined by exposure development.
  • An edge region where WSe2 is in contact with the substrate is defined on the substrate by exposure development, and the metal ruthenium is vapor-deposited and oxidized to form a Y 2 O 3 layer.
  • the transferring the heterojunction material onto the substrate and etching to form a heterojunction material layer includes:
  • CVD-grown WSe2 was transferred onto the substrate, and the exposed WSe2 was removed by dry etching to form a WSe2 layer.
  • the source region is defined by photolithography on the substrate, and the source is formed by vapor deposition on the source region, including:
  • a source region is defined by photolithography in a section of the substrate, and a metal Ti/Pt/Au is evaporated in the source region to form a source.
  • the first insulating layer is formed by photolithography defining a drain region, and the metal is vapor-deposited in the drain region to form a drain, including:
  • a drain region is defined by photolithography on the first insulating layer, and a metal Cr/Pt/Au or MoO 3 /Pt is evaporated on the drain region to form a drain connected to the WSe 2 layer.
  • the gate region is defined by photolithography on the substrate, the second insulating layer, and the heterojunction material layer, and the gate dielectric layer is formed by atomic layer deposition. And providing a gate on the gate dielectric layer, comprising:
  • the gate metal is evaporated to form a gate.
  • the NMOS field effect tube includes: a first insulating layer covering an upper surface of the substrate, and a first heterojunction material layer covering the first insulating layer One end of the upper surface for arranging the source, the source is disposed at one end of the first heterojunction material layer, and the second insulating layer is disposed around the other end of the first heterojunction material layer, and the isolation layer is disposed on the heterojunction layer Upper, the isolation layer covers the inner side of the source; the second heterojunction material layer covers the other end of the first heterojunction material layer, the second insulating layer and the second insulating layer, and the first heterojunction material layer Forming a heterojunction, the drain is disposed on the other end of the second heterojunction layer opposite to the source; the gate dielectric layer covers the position between the source and the drain on the second heterojunction material layer, the gate It is placed on the gate dielectric layer.
  • Embodiment 1 is a schematic structural view of Embodiment 1 of a heterojunction field-effect transistor according to the present application;
  • FIG. 2 is a schematic structural view of a second embodiment of a heterojunction field-effect transistor according to the present application.
  • 3a is a schematic structural view of an example of a heterojunction field-effect transistor according to the present application.
  • 3b is a schematic structural view of another example of a heterojunction field-effect transistor of the present application.
  • Embodiment 4 is a flow chart of Embodiment 1 of a method for fabricating a heterojunction field-effect transistor according to the present application;
  • 5a-5g are schematic structural diagrams of an example of a method for preparing a heterojunction field-effect transistor of the present application.
  • FIG. 6 is a flow chart of a second embodiment of a method for fabricating a heterojunction field-effect transistor according to the present application.
  • FIGS. 7a-7i are schematic structural diagrams showing another example of a method for preparing a heterojunction field-effect transistor of the present application.
  • the present application proposes The dimension material is transferred to the bulk material to form a heterojunction or two two-dimensional materials are stacked to form a heterojunction, and an oxide layer is grown on the edge of the material at the heterojunction region (ie, the overlapping region of the two materials), and the edge is The isolation is opened, and the tunneling distance of carriers at the edges is increased to reduce the tunnel leakage current.
  • the structure and preparation method of the heterojunction field effect transistor provided by the present application will be described in detail below.
  • the heterojunction region of the heterojunction TFET in this scheme consists of a 2D material and a 2D material or a 2D material and a 3D material.
  • the heterojunction material composition is InAs-WSe2, SnSe2-Si, MoTe2-InAs, and the like.
  • the heterojunction material composition is WSe2-SnSe2, SnSe2-MoSe2, SnSe2-MoTe2, and the like.
  • FIG. 1 is a schematic structural diagram of Embodiment 1 of a heterojunction field-effect transistor according to the present application. As shown in FIG. 1 , the structure of a heterojunction field-effect transistor provided by the present application includes:
  • a substrate a first insulating layer, a first heterojunction material layer, a source, an isolation layer, a second heterojunction material layer, a drain, a gate dielectric layer, and a gate;
  • a first insulating layer covers an upper surface of the substrate, and the first heterojunction material layer covers an end of the first insulating layer for arranging a source, the source is disposed At one end of the first heterojunction material layer, a second insulating layer is disposed around the other end of the first heterojunction material layer; the isolation layer is disposed on the heterojunction layer, the isolation layer Covering the inner side of the source; the second heterojunction material layer overlying the other end of the first heterojunction material layer, the second insulating layer, and the second insulating layer, a heterojunction material layer forming a heterojunction, the drain being disposed on the other end of the second heterojunction layer opposite to the source; a gate dielectric layer overlying the gate dielectric layer a layer on the second heterojunction material layer between the source and the drain; a gate, the gate being disposed on the gate dielectric layer.
  • the insulating layer can be implemented by using an oxide material, that is, a first insulating layer and a second.
  • Each of the insulating layers may be an oxide insulating layer.
  • the first heterojunction material layer and the second heterojunction material layer constitute a heterojunction of the TFET, and at least include the following implementations:
  • the material of the first heterojunction material layer is tin selenide SnSe 2
  • the material of the second heterojunction material layer is tungsten disilicide WSe 2 (as shown in FIG. 3 a ); or, the a material of a heterojunction material layer is SnSe 2 , a material of the second heterojunction material layer is molybdenum selenide MoSe 2 ; or a material of the first heterojunction material layer is SnSe 2 , the first The material of the second heterojunction material layer is molybdenum molybdenum MoTe 2 . It can also be other heterojunction materials, and there is no restriction on this solution.
  • the material of the first insulating layer may be silicon oxide SiO 2 ; the material of the second insulating layer may be insulation such as yttrium oxide Y 2 O 3 or aluminum oxide Al 2 O 3 material.
  • the TFET device has a tunnel junction region, a source, a drain, and a gate.
  • the tunneling junction region is composed of two two-dimensional materials, one of which is located above the other material, and an oxide at the edge of the overlap region of the two materials is located between the two materials.
  • the source and the drain are respectively in contact with two kinds of 2D materials, the gate dielectric is located above the two-dimensional material of the junction region, the gate metal is located above the gate dielectric, and the source metal is electrically isolated from the insulating material of another 2D material.
  • the heterojunction field-effect transistor provided in this embodiment uses high-quality oxide as the second insulating layer to isolate the boundary of the two-dimensional material, effectively reducing the leakage current caused by the edge state, and adopting the local gate structure.
  • the atomic-scale thin two-dimensional material is used as a channel to enhance the gate control, so that the heterojunction junction field effect transistor has a smaller SS value, and the heterojunction structure can make the tunneling barrier width narrow, and at the same time
  • a thin oxide layer is grown at the edge of the tunneling junction region of the two-dimensional material to isolate the two-dimensional materials to increase the tunneling distance of the edge states.
  • the heterojunction field-effect transistor provided in this embodiment includes:
  • a substrate a source, a first insulating layer, a heterojunction material layer, a drain, a gate dielectric layer, and a gate.
  • a source is disposed at one end of the upper surface of the substrate; a first insulating layer is embedded in a position on the substrate for providing a drain, and the first layer of heterojunction material is covered in the portion An insulating layer and a portion of the upper surface of the substrate not provided with the source, the heterojunction material layer is provided with a second insulating layer around the other end of the first insulating layer, and the drain is disposed at On the first insulating layer, the drain is in contact with an outer side of the heterojunction material layer, the gate dielectric layer is located between a source and a drain, and the gate dielectric layer is covered On the substrate, the second insulating layer, and the heterojunction material layer, the gate is disposed on the gate dielectric layer.
  • the substrate is an n-doped substrate.
  • the isolation is performed by the second insulating layer, and the leakage current caused by the edge state is significantly reduced.
  • 3b is a schematic structural view of another example of a heterojunction field-effect transistor of the present application; as shown in FIG. 3b, in a specific implementation of the solution, the substrate is an n-type doped InAs substrate, and the heterogeneity
  • the junction material layer is a tungsten selenide WSe 2 layer.
  • Both the first insulating layer and the second insulating layer can be realized by an oxide, that is, both the first insulating layer and the second insulating layer can be an insulating oxide layer.
  • the material of the second insulating layer is yttrium oxide Y 2 O 3 .
  • the heterojunction field-effect transistor provided in this embodiment uses high-quality oxide as the second insulating layer to isolate the boundary of the two-dimensional material, effectively reducing the leakage current caused by the edge state, and adopting the local gate structure.
  • the atomic-scale thin two-dimensional material is used as a channel to enhance the gate control, so that the SS value of the heterojunction pass-through transistor is smaller, and the barrier structure can be narrowed by the heterojunction structure to avoid Interface defects caused by lattice mismatch, while using a tunneling structure, increasing the tunneling area, using a low barrier stagger-gap heterojunction, increasing the tunneling probability and increasing the tunneling current.
  • FIG. 4 is a flow chart of Embodiment 1 of a method for fabricating a heterojunction field-effect transistor according to the present application. As shown in FIG. 4, the preparation of the heterojunction field-effect transistor shown in FIG. 1 provided in this embodiment is provided. Method, specifically including the following steps Step:
  • S101 providing a substrate covered with a first insulating layer, and defining a source region in contact with the first heterojunction material on the substrate by optical exposure.
  • a substrate covered with an insulating layer as a target substrate, and the first insulating layer can be realized by an oxide such as silicon oxide or the like.
  • a first heterojunction material layer is formed on the substrate by using a two-dimensional material, and the first heterojunction material layer is etched into a strip shape and optically exposed in the first A source region is defined on a heterojunction material layer.
  • a source metal (which may be Cr/Pt) is vaporized in the source region to form a source of the heterojunction field effect transistor.
  • S103 defining an edge region of the first heterojunction material layer by exposure development, and depositing a metal in the edge region to oxidize to form a second insulating layer.
  • a photoresist is coated on the first heterojunction material layer, and an edge region of the first heterojunction material layer is defined by exposure and development, which is present in the first heterojunction material layer.
  • the edge region is vapor-deposited with a high quality metal, and the vaporized sample is oxidized to form the second insulating layer.
  • the second insulating layer is not in contact with the source.
  • S104 defining an isolation layer shape by optical exposure, and depositing an oxide on the inner side of the source to form an isolation layer.
  • the position and shape of the isolation layer are defined by optical exposure, and a thick oxide is deposited at a corresponding position to form an isolation layer, which is attached to the inner side of the source and located at the source and the second insulation. The position between the layers is not in contact with the second insulating layer. Finally the photoresist is removed.
  • S105 transferring the second heterojunction material to the first heterojunction material layer, defining the morphology by optical exposure and etching to form a second heterojunction material layer, forming a heterogeneity with the first heterojunction material layer Knot.
  • the implementation of the first heterojunction material layer and the second heterojunction material layer includes at least the following solutions:
  • the material of the first heterojunction material layer is tin selenide SnSe 2
  • the material of the second heterojunction material layer is tungsten disilicide WSe 2 .
  • the material of the first heterojunction material layer is SnSe 2
  • the material of the second heterojunction material layer is molybdenum selenide MoSe 2 .
  • a drain region is defined by photolithography, and a metal is vapor-deposited to form a drain.
  • a drain region is defined on the second heterojunction material layer, and a metal that can serve as a drain is evaporated to form a drain in contact with the second heterojunction material layer.
  • S107 on the second heterojunction material layer, define a gate region by photolithography, form a gate dielectric layer by atomic layer deposition, and set a gate on the gate dielectric layer.
  • the gate region is defined by photolithography, and a high-k gate dielectric oxide is deposited on the gate region to form a gate dielectric layer, and the gate metal is evaporated on the gate dielectric layer. A gate is formed.
  • the preparation scheme provided by the present embodiment is taken as an example in which the substrate is a silicon Si, a SnSe2-WSe2 heterojunction, the first insulating layer is SiO 2 , and the second insulating layer is yttrium oxide Y 2 O 3 .
  • Detailed instructions are given.
  • 5a-5g are schematic structural diagrams of an example of a method for preparing a heterojunction field-effect transistor of the present application. As shown in FIGS. 5a-5g, the specific implementation steps of the method for preparing the heterojunction field-effect transistor are as follows:
  • Step 1 providing a target substrate having SnSe2 (such as a silicon substrate grown with silicon dioxide (first insulating layer)), etching the heterojunction material tin selenide SnSe2 into strips as shown in FIG. 5a .
  • Step 2 the edge region defined by exposure and development SnSe 2 layer, depositing a metal in the edge region of the yttrium SnSe 2 layer, and an oxidation treatment to form Y 2 O 3 insulating layer (second insulating layer).
  • the photoresist was spin-coated on the sample in the step 1, and the SnSe2 edge region was defined by exposure development, and 2-3 nm metal ruthenium was evaporated, followed by a lift off process.
  • the sample was oxidized at 180-200 C (put on a hot plate or oven) for about 15 min to form Y 2 O 3 . As shown in Figure 5c.
  • Step 3 Form an isolation layer.
  • the optical exposure defines an isolation layer, an oxide of about 100 nm thick (e.g., silicon oxide) is evaporated, and the photoresist is removed using a lift off process to form an isolation layer, as shown in Figure 5d.
  • an oxide of about 100 nm thick e.g., silicon oxide
  • Step 4 Form a heterojunction.
  • the WSe 2 layer transferred onto SnSe 2, WSe 2 is defined by the form of optical exposure using reactive ion etching (Reactive Ion Etching, RIE) etching or inductively coupled plasma (Inductively Couple Plasma Etch, ICP) to scribe a dry etching the exposed area is removed WSe 2, the resist is removed, WSe 2 layer is formed, forming a heterojunction with the layer of SnSe 2, resulting in the structure shown in FIG. 5e.
  • reactive Ion Etching Reactive Ion Etching, RIE
  • ICP Inductively Couple Plasma Etch
  • Step 5 lithography is used to define a drain region on the WSe 2 layer, and a metal Cr/Pt/Au or MoO 3 /Pt is evaporated on the drain region to form a drain connected to the WSe 2 layer to prepare a drain. pole.
  • a photoresist is applied to the sample subjected to the step 4, and a drain region is defined by photolithography, and then a metal Cr/Pt/Au (about 2/60 nm) or MoO3/Pt (about 3/60 nm) is formed.
  • the drain contact connected to WSe2 was removed using a lift off process to obtain a sample as shown in Figure 5f.
  • Step 6 lithography is used to define a gate region on the WSe 2 layer, and a high-k gate dielectric yttrium oxide, aluminum oxide or zirconium oxide is grown by atomic layer deposition to form a gate dielectric layer, and a gate electrode is deposited on the gate dielectric layer.
  • a polar metal that forms a gate is used to define a gate region on the WSe 2 layer, and a high-k gate dielectric yttrium oxide, aluminum oxide or zirconium oxide is grown by atomic layer deposition to form a gate dielectric layer, and a gate electrode is deposited on the gate dielectric layer.
  • a polar metal that forms a gate is
  • a photoresist is applied to the sample in the step 5, a gate region is defined by photolithography, and a high-k gate dielectric yttrium oxide (or a high-k material such as alumina or zirconia) is grown by atomic layer deposition, and evaporation is performed.
  • the gate metal e.g., Ti/Au: 5/50 nm
  • high k materials include, but are not limited to, HfO 2 , Al 2 O 3 , ZrO 2 , Y 2 O 3 .
  • the atomic layer deposition may be a low-temperature atomic layer deposition technique or other methods of atomic layer deposition techniques, and the present scheme is not limited.
  • the gate dielectric and the gate electrode can be formed by using a long gate dielectric and a gate metal, and then masked by photoresist.
  • the film is obtained by wet etching;
  • the metal electrode of the source and drain electrodes and the gate electrode may also be made of other metals or semiconductor materials having good conductivity;
  • the covering of the edge region of the material may also adopt other oxides and adopt other processes, such as Atomic layer deposition grows alumina and then etches to obtain a similar structure.
  • FIG. 6 is a flow chart of a second embodiment of a method for fabricating a heterojunction field-effect transistor according to the present application. As shown in FIG. 6, the preparation of the heterojunction field-effect transistor shown in FIG. 2 is provided in this embodiment. Method, specifically including the following steps Step:
  • S202 etching a recess on the substrate by RIE, and forming an oxide isolation layer in the recess to form a first insulating layer.
  • an oxide isolation layer is defined by photolithography on the n-doped substrate, and a recess is etched on the substrate by RIE, using vapor deposition or atomic layer deposition (Atomic layer deposition, ALD) An oxide isolation layer is formed in the recess to form the first insulating layer.
  • the first insulating layer may be formed using an oxide.
  • S203 defining an edge region of the heterojunction material layer in contact with the substrate by exposure development, and depositing a metal in the edge region to oxidize to form a second insulating layer.
  • the edge region of the heterojunction material layer on the substrate is first defined by exposure and development, and then high-quality metal is evaporated and oxidized in the edge region to form the first Two insulation layers.
  • the heterojunction material layer is coated in the range of the second insulating layer.
  • S205 Defining a source region by photolithography on the substrate, and forming a source by vapor deposition on the source region.
  • a source region is defined by photolithography in a section of the substrate, and a source metal Ti/Pt/Au is evaporated in the source region to form a source.
  • the source is on the substrate and is not in contact with the second insulating layer and the layer of heterojunction material.
  • S206 forming a drain region by photolithography in the first insulating layer, and depositing a metal in the drain region to form a drain.
  • a drain region is defined by photolithography on the first insulating layer, and a metal that can serve as a drain, such as Cr/Pt/Au or MoO 3 /Pt, is formed on the drain region.
  • a metal that can serve as a drain such as Cr/Pt/Au or MoO 3 /Pt.
  • the drain of the heterojunction material layer is connected, and the drain is not in contact with the second insulating layer.
  • S207 on the substrate, the second insulating layer and the heterojunction material layer, define a gate region by photolithography, and form a gate dielectric layer by atomic layer deposition, and in the gate dielectric layer Set the gate on it.
  • the gate metal is vapor deposited to form a gate.
  • 7a-7i are schematic structural diagrams showing another example of a method for preparing a heterojunction field-effect transistor of the present application. As shown in FIG. 7a-7i, the specific implementation steps of the method for preparing the heterojunction field-effect transistor are as follows:
  • Step 1 Form an isolation layer.
  • An n-doped InAs substrate is provided, a photoresist is applied to the InAs sample, an Oxide isolation layer is defined by photolithography, and a recess is etched on the InAs substrate by RIE (Fig. 7a).
  • the oxide isolation layer is grown by evaporation or atomic layer deposition (ALD).
  • the isolation layer may be an insulating material such as silicon oxide or aluminum oxide, and the photoresist is removed by a lift off process. The surface is then smoothed using a CMP process to provide the structure of Figure 7b.
  • Step 2 The photoresist was spin-coated on the sample in the step 1, exposed and developed to define the edge region where WSe2 was in contact with the substrate, and 2-3 nm metal ruthenium was evaporated, followed by a lift off process.
  • the sample was oxidized for approximately 15 min at 180-200 C (put on a hot plate or oven). As shown in Figure 7c (left: cross-section; right: top view).
  • Step 3 Transfer the two-dimensional material layer.
  • CVD Chemical Vapor Deposition
  • Step 4 spin coating the photoresist on the sample in step 3, exposing and developing the photoresist, using a photoresist as a mask, removing the exposed WSe2 by dry etching, patterning the WSe2, and removing the photoresist. Mask. As shown in Figure 7e (left: cross-section; right: top view).
  • Step 5 Form the source. Applying a photoresist to the sample of step 4, defining the source region by photolithography, and then vapor-depositing the metal Ti/Pt/Au (about 5/20/30 nm) to form a source (electrode in contact with InAs). The photoresist is removed using a lift off process.
  • Figure 7f (left: cross-section; right: top view).
  • Step 6 Form the drain. Applying a photoresist to the sample of step 5, defining a drain region by photolithography, and then vapor-depositing metal Cr/Pt/Au (about 2/60 nm) or MoO3/Pt (about 3/60 nm) to form a drain ( The electrode in contact with WSe2 is contacted, and the photoresist is removed using a lift off process.
  • Figure 7g (left: cross-section; right: top view).
  • Step 7 Form a high-k gate dielectric.
  • a photoresist is applied to the sample from step 6, and the gate region is defined by photolithography.
  • Atomic layer deposition is used to grow high-k gate dielectric yttrium oxide (or high-k materials such as alumina and zirconia) (as shown in Figure 7h) (left: cross-section; right: top view), vapor-deposited gate metal (eg Ti/Au) : 5/50 nm), the photoresist was removed using a lift off process to obtain a sample as shown in Fig. 7i (left: sectional view; right: top view).
  • yttrium oxide or high-k materials such as alumina and zirconia
  • the structure realized by the steps in the preparation scheme can also be implemented by other similar processes.
  • the gate dielectric and the gate electrode can be formed by using a long gate dielectric and a gate metal, and then using photoresist.
  • the mask is obtained by a wet etching method.
  • the two-dimensional material-based heterojunction TFETs mentioned in this application are also applicable to heterojunction TFETs formed from bulk thinned (nanoscale) bulk materials.
  • the method for preparing a heterojunction field-effect transistor uses a high-quality oxide such as Y 2 O 3 for isolation during the preparation process, and significantly reduces the leakage current caused by the edge state, and adopts a local gate.
  • Structure-enhanced gate control makes it easier to achieve SS less than 60mV/dec, and uses a thin atomic two-dimensional material as the channel to further enhance the gate control.
  • the use of two-dimensional materials to form heterojunctions avoids interface defects caused by lattice mismatch; line tunneling structures are used to increase tunneling area.
  • a low barrier stagger-gap heterojunction is used to increase the tunneling probability and increase the tunneling current while making the tunneling barrier narrow.

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Abstract

本申请实施例提供一种异质结遂穿场效应晶体管及其制备方法，包括：第一绝缘层覆盖在衬底的上表面，第一异质结材料层覆盖在第一绝缘层的上表面上用于设置源极的一端，源极设置在第一异质结材料层的一端，第一异质结材料层另一端周围设置有第二绝缘层，隔离层设置在异质结层上，隔离层覆盖在源极的内侧；第二异质结材料层覆盖在第一异质结材料层的另一端、第二绝缘层以及第二绝缘层上，与第一异质结材料层形成异质结，漏极设置在第二异质结层上与源极相对的另一端；栅介质层覆盖在第二异质结材料层上位于源极和漏极之间的位置，栅极设置在栅介质层上。通过设置第二绝缘层进行隔离，显著减小边缘态导致的泄露电流，并利用二维材料形成异质结，避免了因晶格不匹配导致的界面缺陷。

Description

异质结遂穿场效应晶体管及其制备方法 技术领域
本申请实施例涉及半导体技术，尤其涉及一种异质结遂穿场效应晶体管(Tunnel Field-Effect Transistors，简称：TFET)及其制备方法。
背景技术
集成电路按照摩尔定律不断缩减，但当晶体管的尺寸进入14nm、10nm节点后，进一步的缩小晶体管尺寸，短沟道效应导致的泄漏电流不断增加，致使集成电路的功耗成为越来越严重的问题。与传统金属-氧化物半导体场效应晶体管，(Metal-Oxide-Semiconductor Field-Effect Transistor，简称：MOSFET)工作机制不同，隧穿场效应晶体管TFET采用带间隧穿机制，其亚阈值斜率(Subthreshold Slope，简称：SS)可低于60mV/dec的室温限制，从而可以有效降低工作电压，而动态功耗与工作电压的平方成正比，因此采用TFET器件制备的集成电路可以显著降低功耗。
常用的TFET架构主要是以硅为沟道材料的同质结TFET和以III-V族材料为沟道的异质结TFET。由于硅材料大带隙及间接带隙半导体特性，带间隧穿几率很低，导致硅基TFET开态电流太低，不能满足应用要求。III-V族材料具有带隙较小、有效质量小的特性，使得基于III-V族材料的异质结TFET能获得很大的开态电流，但较高密度的界面态的存在致使其难以获得小于60mV/dec的SS。二维材料具有原子级薄、表面无悬挂键等优异特点，且基于二维材料的异质结无晶格失配导致的界面缺陷。因此基于二维材料的异质结TFET相比于传统TFET更具优势。
然而，二维材料表面无悬挂键，但材料的边界仍存在悬挂键，该悬挂键会增加二维材料异质结TFET的泄漏电流。
发明内容
本申请实施例提供一种异质结遂穿场效应晶体管及其制备方法，用于解决前述方案中二维材料表面无悬挂键，但材料的边界仍存在悬挂键，该悬挂键会增加二维材料异质结TFET的泄漏电流的问题。
本申请第一方面提供一种异质结遂穿场效应晶体管，包括：
衬底；
第一绝缘层；所述第一绝缘层覆盖在所述衬底的上表面；
第一异质结材料层，所述第一异质结材料层覆盖在所述第一绝缘层的上表面上用于设置源极的一端；
源极，所述源极设置在所述第一异质结材料层的一端，所述第一异质结材料层另一端 周围设置有第二绝缘层；
隔离层，所述隔离层设置在所述异质结层上，所述隔离层覆盖在所述源极的内侧；
第二异质结材料层，所述第二异质结材料层覆盖在所述第一异质结材料层的另一端、第二绝缘层以及所述第二绝缘层上，与所述第一异质结材料层形成异质结；
漏极，所述漏极设置在所述第二异质结层上与所述源极相对的另一端；
栅介质层，所述栅介质层覆盖在所述第二异质结材料层上位于源极和漏极之间的位置；
栅极，所述栅极设置在所述栅介质层上。
本方案中，通过设置第二绝缘层进行隔离，显著减小边缘态导致的泄露电流。
可选的，所述第一异质结材料层的材料为二硒化锡SnSe2，所述第二异质结材料层的材料为二硒化钨WSe2；或者，
所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为硒化钼MoSe2；或者，
所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为碲化钼MoTe2。
可选的，所述第一绝缘层和所述第二绝缘层均为氧化物绝缘层。
可选的，所述第一绝缘层的材料为氧化硅SiO2；所述第二绝缘层的材料为氧化钇Y2O3或者氧化铝Al2O3。
上述方案中，利用二维材料形成异质结，避免了因晶格不匹配导致的界面缺陷。
本申请第二方面提供一种异质结遂穿场效应晶体管，包括：
衬底；
源极，所述源极设置在所述衬底上表面的一端；
第一绝缘层；所述第一绝缘层嵌入设置在所述衬底上用于设置漏极的位置；
异质结材料层，所述第一异质结材料层覆盖在部分所述第一绝缘层和未设置所述源极的部分所述衬底的上表面，所述异质结材料层所述第一绝缘层的另一端周围设置有第二绝缘层；
漏极，所述漏极设置在所述第一绝缘层上，且所述漏极与所述异质结材料层的外侧接触；
栅介质层，所述栅介质层位于源极和漏极之间的位置，且所述栅介质层覆盖在所述衬底、所述第二绝缘层、和所述异质结材料层上；
栅极，所述栅极设置在所述栅介质层上。
本方案中，通过第二绝缘层进行隔离，显著减小边缘态导致的泄露电流。
可选的，所述异质结材料层为二硒化钨WSe2层。
可选的，所述第一绝缘层和所述第二绝缘层均为氧化物绝缘层。
可选的，所述第二绝缘层的材料为氧化钇Y2O3。
在上述的几种具体实现中，利用二维材料形成异质结，避免了因晶格不匹配导致的界面缺陷，同时采用线隧穿结构，增加隧穿面积，采用低势垒的stagger-gap型异质结，增加隧穿几率，提高隧穿电流，采用异质结，隧穿势垒宽度窄。
本申请第三方面提供一种异质结遂穿场效应晶体管的制备方法，包括：
提供覆盖有第一绝缘层的衬底，并通过光学曝光在所述衬底上定义与第一异质结材料接触的源极区域；
在所述有源区域上通过蒸镀金属制作源极；
通过曝光显影定义第一异质结材料层的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层；
通过光学曝光定义隔离层形态，在所述源极内侧蒸镀氧化物形成隔离层；
将第二异质结材料转移至第一异质结材料层，通过光学曝光定义形态并进行刻蚀形成第二异质结材料层，与所述第一异质结材料层形成异质结；
在所述第二异质结材料层上，通过光刻定义漏极区域，并蒸镀金属形成漏极；
在所述第二异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极。
在一种具体实现中，当所述第一异质结材料层为SnSe2层，第二绝缘层为氧化钇Y2O3，则所述通过曝光显影定义第一异质结材料层的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层，包括：
通过曝光显影定义SnSe2层的边缘区域，在所述SnSe2层的边缘区域蒸镀金属钇，并进行氧化处理，形成Y2O3绝缘层。
在一种具体实现中，所述第二异质结材料层为WSe2层，所述将第二异质结材料转移至第一异质结材料层，通过光学曝光定义形态并进行刻蚀形成第二异质结材料层，与所述第一异质结材料层形成异质结，包括：
将WSe2转移至SnSe2层上，通过光学曝光定义WSe2的形态，采用RIE或者ICP进行干法刻蚀去除曝光区的WSe2，去除光刻胶，形成WSe2层，与所述SnSe2层形成异质结。
在一种具体实现中的，在所述第二异质结材料层上，通过光刻定义漏极区域，并蒸镀金属形成漏极，包括：
在WSe2层上采用光刻定义漏极区域，在所述漏极区域上蒸镀金属Cr/Pt/Au或MoO3/Pt，形成与WSe2层相连接的漏极。
在一种具体实现中，在所述第二异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极，包括：
在WSe2层上采用光刻定义栅极区域，采用原子层沉积生长高k栅介质氧化铪、氧化铝或氧化锆，形成栅介质层，并在所述栅介质层上蒸镀栅极金属，形成栅极。
本申请第四方面提供一种异质结遂穿场效应晶体管的制备方法，包括：
提供n型掺杂的衬底；
通过反应离子刻蚀RIE在所述衬底上刻蚀出一凹槽，在所述凹槽中生成氧化物隔离层，形成第一绝缘层；
通过曝光显影定义异质结材料层与所述衬底接触的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层；
将异质结材料转移至所述衬底上，并进行刻蚀形成异质结材料层；
在所述衬底上通过光刻定义源极区域，并在所述源极区域上通过蒸镀金属制作源极；
在所述第一绝缘层生采用光刻定义漏极区域，并在所述漏极区域蒸镀金属形成漏极；
在所述衬底、所述第二绝缘层和所述异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极。
在一种具体实现中，所述通过反应离子刻蚀RIE在所述衬底上刻蚀出一凹槽，在所述凹槽中生成氧化物隔离层，形成第一绝缘层，包括：
在所述衬底上采用光刻定义氧化物隔离层，再利用反应离子刻蚀RIE在所述衬底上刻蚀一凹槽，采用蒸镀或者ALD在所述凹槽中生成氧化物隔离层，形成所述第一绝缘层。
在一种具体实现中，所述异质结材料层为二硒化钨WSe2层，所述第二绝缘层的材料为氧化钇Y2O3，则通过曝光显影定义异质结材料层与所述衬底接触的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层，包括：
在所述衬底上采用曝光显影定义WSe2与衬底接触的边缘区域，蒸镀金属钇并进行氧化，形成Y2O3层。
在一种具体实现中，所述将异质结材料转移至所述衬底上，并进行刻蚀形成异质结材料层，包括：
将CVD生长的WSe2转移至所述衬底上，并利用干法刻蚀去除暴露的WSe2，形成WSe2层。
在一种具体实现中，所述在所述衬底上通过光刻定义源极区域，并在所述源极区域上通过蒸镀金属制作源极，包括：
在所述衬底的一段采用光刻定义源极区域，在所述源极区域蒸镀金属Ti/Pt/Au形成源极。
在一种具体实现中，所述在所述第一绝缘层生采用光刻定义漏极区域，并在所述漏极区域蒸镀金属形成漏极，包括：
在第一绝缘层上采用光刻定义漏极区域，在所述漏极区域上蒸镀金属Cr/Pt/Au或MoO3/Pt，形成与WSe2层相连接的漏极。
在一种具体实现中，所述在所述衬底、所述第二绝缘层和所述异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极，包括：
在WSe2层和Y2O3层上采用光刻定义栅极区域，采用原子层沉积生长高k栅介质氧化铪、氧化铝或氧化锆，形成栅介质层，并在所述栅介质层上蒸镀栅极金属，形成栅极。
本申请提供的异质结遂穿场效应晶体管和制备方法，该遂穿场效应管包括：第一绝缘层覆盖在衬底的上表面，第一异质结材料层覆盖在第一绝缘层的上表面上用于设置源极的一端，源极设置在第一异质结材料层的一端，第一异质结材料层另一端周围设置有第二绝缘层，隔离层设置在异质结层上，隔离层覆盖在源极的内侧；第二异质结材料层覆盖在第一异质结材料层的另一端、第二绝缘层以及第二绝缘层上，与第一异质结材料层形成异质结，漏极设置在第二异质结层上与源极相对的另一端；栅介质层覆盖在第二异质结材料层上位于源极和漏极之间的位置，栅极设置在栅介质层上。通过设置第二绝缘层进行隔离，显著减小边缘态导致的泄露电流，并利用二维材料形成异质结，避免了因晶格不匹配导致的界面缺陷。
附图说明
图1为本申请异质结遂穿场效应晶体管实施例一的结构示意图；
图2为本申请异质结遂穿场效应晶体管实施例二的结构示意图；
图3a为本申请异质结遂穿场效应晶体管一实例的结构示意图；
图3b为本申请异质结遂穿场效应晶体管另一实例的结构示意图；
图4为本申请异质结遂穿场效应晶体管的制备方法实施例一的流程图；
图5a-5g为本申请异质结遂穿场效应晶体管的制备方法一实例的过程结构示意图；
图6为本申请异质结遂穿场效应晶体管的制备方法实施例二的流程图；
图7a-7i为本申请异质结遂穿场效应晶体管的制备方法另一实例的过程结构示意图。
具体实施方式
为了克服常用的TFET中的二维材料表面无悬挂键，但材料的边界仍存在悬挂键，该悬挂键会增加二维材料异质结TFET的泄漏电流的问题，本申请提出一种通过将二维材料转移至块体材料形成异质结或将两种二维材料叠放形成异质结，异质结结区(即两材料的交叠区域)处的材料边缘上生长氧化层，将边缘处隔离开，增加边缘处载流子的隧穿距离，以降低隧穿泄漏电流的方案。下面对本申请提供的异质结遂穿场效应晶体管的结构和制备方法进行详细说明。
本方案中的异质结TFET的异质结区由2D材料和2D材料或2D材料和3D材料构成。对于2D-3D型异质结TFET，其异质结材料组成为InAs-WSe2、SnSe2-Si、MoTe2-InAs等。对于2D-2D型异质结TFET，其异质结材料组成为WSe2-SnSe2、SnSe2-MoSe2、SnSe2-MoTe2等。
图1为本申请异质结遂穿场效应晶体管实施例一的结构示意图，如图1所示，本申请提供的一种异质结遂穿场效应晶体管的结构包括：
衬底、第一绝缘层、第一异质结材料层、源极、隔离层、第二异质结材料层、漏极、栅介质层和栅极；
其中，第一绝缘层覆盖在所述衬底的上表面，所述第一异质结材料层覆盖在所述第一绝缘层的上表面上用于设置源极的一端，所述源极设置在所述第一异质结材料层的一端，所述第一异质结材料层另一端周围设置有第二绝缘层；所述隔离层设置在所述异质结层上，所述隔离层覆盖在所述源极的内侧；所述第二异质结材料层覆盖在所述第一异质结材料层的另一端、第二绝缘层以及所述第二绝缘层上，与所述第一异质结材料层形成异质结，所述漏极设置在所述第二异质结层上与所述源极相对的另一端；栅介质层，所述栅介质层覆盖在所述第二异质结材料层上位于源极和漏极之间的位置；栅极，所述栅极设置在所述栅介质层上。
图3a为本申请异质结遂穿场效应晶体管一实例的结构示意图，如图3a所示，在该结构的具体实现中，绝缘层可采用氧化物材料实现，即第一绝缘层和第二绝缘层均可以为氧化物绝缘层。
第一异质结材料层和第二异质结材料层构成该TFET的异质结，至少包括以下几种实现方案：
所述第一异质结材料层的材料为二硒化锡SnSe2，所述第二异质结材料层的材料为二 硒化钨WSe2(如图3a所示)；或者，所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为硒化钼MoSe2；或者，所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为碲化钼MoTe2。还可以是其他的异质结区材料，对此本方案不做限制。
可选的，在一种具体实现中，该第一绝缘层的材料可为氧化硅SiO2；所述第二绝缘层的材料可为氧化钇Y2O3或者氧化铝Al2O3等绝缘材料。
在该方案中，该具有隧穿结区，源极、漏极和栅极的TFET器件。隧穿结区由两种二维材料组成，其中一种材料位于另一材料的上方，两种材料交叠区的边缘处有氧化物位于两种材料间。源极和漏极分别与两种2D材料形成接触，栅介质位于结区二维材料之上，栅金属位于栅介质上方，源极金属与另一种2D材料有绝缘材料进行电隔离。
本实施例提供的异质结遂穿场效应晶体管，采用高质量的氧化物作为第二绝缘层对二维材料的边界进行隔离，有效减小边缘态导致的泄露电流，同时采用局域栅结构以及原子级薄的二维材料做沟道，可增强栅控，使得该异质结遂穿场效应晶体管的SS值更小，通过这种异质结结构可使遂穿势垒宽度窄，同时，二维材料隧穿结区的边缘处生长有薄层氧化层，将两二维材料隔离开，以增加边缘态的隧穿距离。
图2为本申请异质结遂穿场效应晶体管实施例二的结构示意图，如图2所示，本实施例提供的异质结遂穿场效应晶体管包括：
衬底、源极、第一绝缘层、异质结材料层、漏极、栅介质层和栅极。
其中，源极设置在所述衬底上表面的一端；第一绝缘层嵌入设置在所述衬底上用于设置漏极的位置，所述第一异质结材料层覆盖在部分所述第一绝缘层和未设置所述源极的部分所述衬底的上表面，所述异质结材料层所述第一绝缘层的另一端周围设置有第二绝缘层，所述漏极设置在所述第一绝缘层上，且所述漏极与所述异质结材料层的外侧接触，所述栅介质层位于源极和漏极之间的位置，且所述栅介质层覆盖在所述衬底、所述第二绝缘层、和所述异质结材料层上，所述栅极设置在所述栅介质层上。
该方案的一种具体实现中，衬底为n型掺杂的基底。
本方案中，通过第二绝缘层进行隔离，显著减小边缘态导致的泄露电流。
图3b为本申请异质结遂穿场效应晶体管另一实例的结构示意图；如图3b所示，该方案的一种具体实现中，衬底为n型掺杂的InAs基底，所述异质结材料层为二硒化钨WSe2层。
所述第一绝缘层和所述第二绝缘层均可通过氧化物实现，即第一绝缘层和第二绝缘层均可为绝缘的氧化物层。可选的，所述第二绝缘层的材料为氧化钇Y2O3。
本实施例提供的异质结遂穿场效应晶体管，采用高质量的氧化物作为第二绝缘层对二维材料的边界进行隔离，有效减小边缘态导致的泄露电流，同时采用局域栅结构以及原子级薄的二维材料做沟道，可增强栅控，使得该异质结遂穿场效应晶体管的SS值更小，通过这种异质结结构可使遂穿势垒宽度窄，避免了因晶格不匹配导致的界面缺陷，同时采用线隧穿结构，增加隧穿面积，采用低势垒的stagger-gap型异质结，增加隧穿几率，提高隧穿电流。
图4为本申请异质结遂穿场效应晶体管的制备方法实施例一的流程图，如图4所示，本实施例提供的上述图1所示的异质结遂穿场效应晶体管的制备方法，具体包括以下步 骤：
S101：提供覆盖有第一绝缘层的衬底，并通过光学曝光在所述衬底上定义与第一异质结材料接触的源极区域。
S102：在所述有源区域上通过蒸镀金属制作源极。
在上述步骤中，为制备该场效应晶体管，需要提供一覆盖有绝缘层的衬底作为目标基底，该第一绝缘层可通过氧化物实现，例如氧化硅等。为了在实现异质结，需要采用二维材料在该衬底上形成第一异质结材料层，并将该第一异质结材料层刻蚀成为条带状，并通过光学曝光在该第一异质结材料层上定义源极区域。
确定了该器件的源极区域之后，在该源极区域内蒸镀源极金属(可以是Cr/Pt)，形成该异质结遂穿场效应晶体管的源极。
S103：通过曝光显影定义第一异质结材料层的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层。
在本步骤中，将光刻胶涂布在第一异质结材料层上，进行曝光显影将该第一异质结材料层的边缘区域定义出来，本在该第一异质结材料层的边缘区域蒸镀高质量的金属，将蒸镀后的样品进行氧化形成该第二绝缘层，在本方案中，第二绝缘层与源极不接触。
S104：通过光学曝光定义隔离层形态，在所述源极内侧蒸镀氧化物形成隔离层。
在本步骤中，同样的通过光学曝光定义隔离层的位置和形态，并在对应的位置蒸镀厚氧化物形成隔离层，该隔离层贴付在源极内侧，并位于源极和第二绝缘层的之间的位置，与第二绝缘层不接触。最后将光刻胶除去。
S105：将第二异质结材料转移至第一异质结材料层，通过光学曝光定义形态并进行刻蚀形成第二异质结材料层，与所述第一异质结材料层形成异质结。
在本步骤中，在第一异质结材料层、第二绝缘层和周围的第一绝缘层上转移第二异质结材料，并通过光学曝光定义该第二异质结材料的形态，将曝光区域的第二异质结材料刻蚀掉，并去除光刻胶，得到该第二异质结材料层，该第二异质结材料层与源极不接触。
在该方案的具体实现中，第一异质结材料层和第二异质结材料层的实现至少包括以下几种方案：
第一种实现方案：所述第一异质结材料层的材料为二硒化锡SnSe2，所述第二异质结材料层的材料为二硒化钨WSe2。
第二种实现方案：所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为硒化钼MoSe2。
第三种实现方案：所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为碲化钼MoTe2。
S106：在所述第二异质结材料层上，通过光刻定义漏极区域，并蒸镀金属形成漏极。
在本步骤中，在第二异质结材料层上定义漏极区域，并蒸镀可作为漏极的金属，形成与第二异质结材料层接触的漏极。
S107：在所述第二异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极。
在上述步骤得到的样品的基础上，采用光刻定义栅极区域，并在该栅极区域上沉积生长高K栅介质氧化物，形成栅介质层，并在栅介质层上蒸镀栅极金属形成栅极。
在上述过程的基础上，以衬底为硅Si、SnSe2-WSe2异质结、第一绝缘层为SiO2、第二绝缘层为氧化钇Y2O3为例，对本实施例提供的制备方案进行详细说明。图5a-5g为本申请异质结遂穿场效应晶体管的制备方法一实例的过程结构示意图。如图5a-5g所示，该异质结遂穿场效应晶体管的制备方法具体的实现步骤为：
步骤1：提供具有SnSe2的目标基底(如生长有二氧化硅(第一绝缘层)的硅衬底)，将异质结材料二硒化锡SnSe2刻蚀成条带如图图5a所示结构。光学曝光定义与SnSe2接触的源极区域，然后蒸镀金属(例如Cr/Pt＝2/60nm),使用lift off工艺得到如图5b所示结构(截面图)。
步骤2：通过曝光显影定义SnSe2层的边缘区域，在所述SnSe2层的边缘区域蒸镀金属钇，并进行氧化处理，形成Y2O3绝缘层(第二绝缘层)。
具体的，将光刻胶旋涂于步骤1中的样品上，对其进行曝光显影定义SnSe2边缘区域，蒸镀2-3nm金属钇，然后进行lift off工艺。使样品在180-200C(放到热板上或烘箱里)氧化约15min，形成Y2O3。如图5c所示。
步骤3：形成隔离层。光学曝光定义隔离层，蒸镀约100nm厚氧化物(例如氧化硅)，使用lift off工艺去除光刻胶，形成隔离层，如图5d所示。
步骤4：形成异质结。将WSe2转移至SnSe2层上，通过光学曝光定义WSe2的形态，采用反应离子刻蚀(Reactive Ion Etching，RIE)或者感应耦合等离子体刻蚀(Inductively Couple Plasma Etch，ICP)进行干法刻蚀去除曝光区的WSe2，去除光刻胶，形成WSe2层，与所述SnSe2层形成异质结，得到如图5e所示的结构。
步骤5：在WSe2层上采用光刻定义漏极区域，在所述漏极区域上蒸镀金属Cr/Pt/Au或MoO3/Pt，形成与WSe2层相连接的漏极，制备漏极。
具体的，将光刻胶涂于经步骤4的样品上，采用光刻定义漏极区域，然后蒸镀金属Cr/Pt/Au(约2/60nm)或MoO3/Pt(约3/60nm)形成与WSe2相连接的漏极接触，使用lift off工艺去除光刻胶，得到如图5f所示样品。
步骤6：在WSe2层上采用光刻定义栅极区域，采用原子层沉积生长高k栅介质氧化铪、氧化铝或氧化锆，形成栅介质层，并在所述栅介质层上蒸镀栅极金属，形成栅极。
具体的，将光刻胶涂于经步骤5的样品上，采用光刻定义栅极区域，采用原子层沉积生长高k栅介质氧化铪(或氧化铝、氧化锆等高k材料)，蒸镀栅极金属(例如Ti/Au:5/50nm)，使用lift off工艺去除光刻胶得到如图5g所示的样品。在该方案中，应理解高k材料包括但不限于HfO2、Al2O3、ZrO2、Y2O3。
该原子层沉积可以是低温原子层沉积技术，也可以是其他方式的原子层沉积技术，对此本方案不做限制。
以上步骤所实现的结构亦可采用其它类似工艺来实现，相应的结构形态也会有些许不同，如栅介质与栅电极的形成可采用先生长栅介质和栅金属，然后用光刻胶做掩膜进行湿法刻蚀的方法获得；源漏和栅极的金属电极亦可采用其它金属或导电性良好的半导体材料；材料边缘区域的覆盖物亦可采用其它氧化物及采用其它工艺，比如采用原子层沉积生长氧化铝，然后再进行腐蚀获得类似的结构。
图6为本申请异质结遂穿场效应晶体管的制备方法实施例二的流程图，如图6所示，本实施例提供的上述图2所示的异质结遂穿场效应晶体管的制备方法，具体包括以下步 骤：
S201：提供n型掺杂的衬底。
S202：通过RIE在所述衬底上刻蚀出一凹槽，在所述凹槽中生成氧化物隔离层，形成第一绝缘层。
在上述步骤中，在n型掺杂的衬底上采用光刻定义氧化物隔离层，再利用RIE在所述衬底上刻蚀一凹槽，采用蒸镀或者原子层沉积(Atomic layer deposition，ALD)在凹槽中生成氧化物隔离层，形成所述第一绝缘层。该第一绝缘层可采用氧化物形成。
S203：通过曝光显影定义异质结材料层与所述衬底接触的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层。
在本步骤中，在异质结材料层之前，首先通过曝光显影定义异质结材料层在衬底上的边缘区域，然后在该边缘区域内蒸镀高质量的金属并进行氧化处理，形成第二绝缘层。
S204：将异质结材料转移至所述衬底上，并进行刻蚀形成异质结材料层。
在本步骤中，该异质结材料层涂布在第二绝缘层的范围内。
S205：在所述衬底上通过光刻定义源极区域，并在所述源极区域上通过蒸镀金属制作源极。
在本步骤中，在所述衬底的一段采用光刻定义源极区域，在所述源极区域蒸镀源极金属Ti/Pt/Au形成源极。源极位于衬底上，且与第二绝缘层和异质结材料层不接触。
S206：在所述第一绝缘层生采用光刻定义漏极区域，并在所述漏极区域蒸镀金属形成漏极。
在本步骤中，在第一绝缘层上采用光刻定义漏极区域，在所述漏极区域上蒸镀可作为漏极的金属，例如：Cr/Pt/Au或MoO3/Pt，形成与异质结材料层相连接的漏极，漏极与第二绝缘层不接触。
S207：在所述衬底、所述第二绝缘层和所述异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极。
在异质结材料层和第二绝缘层上采用光刻定义栅极区域，采用原子层沉积生长高k栅介质氧化铪、氧化铝或氧化锆，形成栅介质层，并在所述栅介质层上蒸镀栅极金属，形成栅极。
在上述过程的基础上，以衬底为InAs、WSe2异质结、第二绝缘层为氧化钇Y2O3为例，对本实施例提供的制备方案进行详细说明。图7a-7i为本申请异质结遂穿场效应晶体管的制备方法另一实例的过程结构示意图。如图7a-7i所示，该异质结遂穿场效应晶体管的制备方法具体的实现步骤为：
步骤1：形成隔离层。提供n型掺杂的InAs基底，将光刻胶涂于InAs样品上，采用光刻定义Oxide隔离层，然后利用RIE在InAs基底上刻蚀一凹槽(如图7a)。采用蒸镀或原子层沉积(Atomic layer deposition，ALD)生长氧化物隔离层，隔离层可以为氧化硅、氧化铝等绝缘材料，使用lift off工艺去除光刻胶。接着采用CMP工艺将表面磨平，得到如图7b的结构。
步骤2：将光刻胶旋涂于步骤1中的样品上，对其进行曝光显影定义WSe2与基底接触的边缘区域，蒸镀2-3nm金属钇，然后进行lift off工艺。使样品在180-200C(放到热板上或烘箱里)氧化约15min。如图7c(左：截面图；右：俯视图)所示。
步骤3：转移二维材料层。将基底放在35％HF：35％HCl＝1:1中约2分钟去除InAs基底氧化层，将化学气相沉积(Chemical Vapor Deposition，CVD)生长的WSe2转移至InAs基底上。得到如图7d(左：截面图；右：俯视图)所示结构。
步骤4：将光刻胶旋涂于步骤3中的样品上，对其进行曝光显影，以光刻胶做掩膜，利用干法刻蚀去除暴露的WSe2，将WSe2图案化，去除光刻胶掩膜。如图7e(左：截面图；右：俯视图)所示。
步骤5：形成源极。将光刻胶涂于经步骤4的样品上，采用光刻定义源极区域，然后蒸镀金属Ti/Pt/Au(约5/20/30nm)形成源极(与InAs接触的电极)接触，使用lift off工艺去除光刻胶。如图7f(左：截面图；右：俯视图)。
步骤6：形成漏极。将光刻胶涂于经步骤5的样品上，采用光刻定义漏极区域，然后蒸镀金属Cr/Pt/Au(约2/60nm)或MoO3/Pt(约3/60nm)形成漏极(与WSe2接触的电极)接触，使用lift off工艺去除光刻胶。如图7g(左：截面图；右：俯视图)。
步骤7：形成高k栅介质。将光刻胶涂于经步骤6的样品上，采用光刻定义栅极区域。采用原子层沉积生长高k栅介质氧化铪(或氧化铝、氧化锆等高k材料)(如图图7h)(左：截面图；右：俯视图)，蒸镀栅极金属(例如Ti/Au:5/50nm)，使用lift off工艺去除光刻胶得到如图7i(左：截面图；右：俯视图)所示的样品。
与上述实施例一类似，该制备方案中的步骤所实现的结构亦可采用其它类似工艺来实现，如栅介质与栅电极的形成可采用先生长栅介质和栅金属，然后用光刻胶做掩膜进行湿法刻蚀的方法获得。
本申请中提到的基于二维材料的异质结TFET也适用于厚度减薄(纳米尺度)的块体材料形成的异质结TFET。
上述实施例提供的异质结遂穿场效应晶体管的制备方法，在制备过程中采用高质量的氧化物例如Y2O3做隔离，显著减小边缘态导致的泄漏电流，并采用局域栅结构增强栅控，更易实现小于60mV/dec的SS，采用原子级薄的二维材料做沟道，能进一步增强栅控。利用二维材料形成异质结，避免了因晶格不匹配导致的界面缺陷；采用线隧穿结构，增加隧穿面积。采用低势垒的stagger-gap型异质结，增加隧穿几率，提高隧穿电流，同时使得隧穿势垒宽度窄。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制。

Claims (20)

  1. 一种异质结遂穿场效应晶体管，其特征在于，包括：
    衬底；
    第一绝缘层；所述第一绝缘层覆盖在所述衬底的上表面；
    第一异质结材料层，所述第一异质结材料层覆盖在所述第一绝缘层的上表面上用于设置源极的一端；
    源极，所述源极设置在所述第一异质结材料层的一端，所述第一异质结材料层另一端周围设置有第二绝缘层；
    隔离层，所述隔离层设置在所述异质结层上，所述隔离层覆盖在所述源极的内侧；
    第二异质结材料层，所述第二异质结材料层覆盖在所述第一异质结材料层的另一端、第二绝缘层以及所述第二绝缘层上，与所述第一异质结材料层形成异质结；
    漏极，所述漏极设置在所述第二异质结层上与所述源极相对的另一端；
    栅介质层，所述栅介质层覆盖在所述第二异质结材料层上位于源极和漏极之间的位置；
    栅极，所述栅极设置在所述栅介质层上。
  2. 根据权利要求1所述的异质结遂穿场效应晶体管，其特征在于，所述第一异质结材料层的材料为二硒化锡SnSe2，所述第二异质结材料层的材料为二硒化钨WSe2；或者，
    所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为硒化钼MoSe2；或者，
    所述第一异质结材料层的材料为SnSe2，所述第二异质结材料层的材料为碲化钼MoTe2。
  3. 根据权利要求1或2所述的异质结遂穿场效应晶体管，其特征在于，所述第一绝缘层和所述第二绝缘层均为氧化物绝缘层。
  4. 根据权利要求3所述的异质结遂穿场效应晶体管，其特征在于，所述第一绝缘层的材料为氧化硅SiO2；所述第二绝缘层的材料为氧化钇Y2O3或者氧化铝Al2O3。
  5. 一种异质结遂穿场效应晶体管，其特征在于，包括：
    衬底；
    源极，所述源极设置在所述衬底上表面的一端；
    第一绝缘层；所述第一绝缘层嵌入设置在所述衬底上用于设置漏极的位置；
    异质结材料层，所述第一异质结材料层覆盖在部分所述第一绝缘层和未设置所述源极的部分所述衬底的上表面，所述异质结材料层所述第一绝缘层的另一端周围设置有第二绝缘层；
    漏极，所述漏极设置在所述第一绝缘层上，且所述漏极与所述异质结材料层的外侧接触；
    栅介质层，所述栅介质层位于源极和漏极之间的位置，且所述栅介质层覆盖在所述衬底、所述第二绝缘层、和所述异质结材料层上；
    栅极，所述栅极设置在所述栅介质层上。
  6. 根据权利要求5所述的异质结遂穿场效应晶体管，其特征在于，所述异质结材料 层为二硒化钨WSe2层。
  7. 根据权利要求5或6所述的异质结遂穿场效应晶体管，其特征在于，所述第一绝缘层和所述第二绝缘层均为氧化物绝缘层。
  8. 根据权利要求7所述的异质结遂穿场效应晶体管，其特征在于，所述第二绝缘层的材料为氧化钇Y2O3。
  9. 一种异质结遂穿场效应晶体管的制备方法，其特征在于，包括：
    提供覆盖有第一绝缘层的衬底，并通过光学曝光在所述衬底上定义与第一异质结材料接触的源极区域；
    在所述有源区域上通过蒸镀金属制作源极；
    通过曝光显影定义第一异质结材料层的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层；
    通过光学曝光定义隔离层形态，在所述源极内侧蒸镀氧化物形成隔离层；
    将第二异质结材料转移至第一异质结材料层，通过光学曝光定义形态并进行刻蚀形成第二异质结材料层，与所述第一异质结材料层形成异质结；
    在所述第二异质结材料层上，通过光刻定义漏极区域，并蒸镀金属形成漏极；
    在所述第二异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极。
  10. 根据权利要求9所述的方法，其特征在于，当所述第一异质结材料层为SnSe2层，第二绝缘层为氧化钇Y2O3，则所述通过曝光显影定义第一异质结材料层的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层，包括：
    通过曝光显影定义SnSe2层的边缘区域，在所述SnSe2层的边缘区域蒸镀金属钇，并进行氧化处理，形成Y2O3绝缘层。
  11. 根据权利要求10所述的方法，其特征在于，所述第二异质结材料层为WSe2层，所述将第二异质结材料转移至第一异质结材料层，通过光学曝光定义形态并进行刻蚀形成第二异质结材料层，与所述第一异质结材料层形成异质结，包括：
    将WSe2转移至SnSe2层上，通过光学曝光定义WSe2的形态，采用反应离子刻蚀RIE或者感应耦合等离子体刻蚀ICP进行干法刻蚀去除曝光区的WSe2，去除光刻胶，形成WSe2层，与所述SnSe2层形成异质结。
  12. 根据权利要求11所述的方法，其特征在于，在所述第二异质结材料层上，通过光刻定义漏极区域，并蒸镀金属形成漏极，包括：
    在WSe2层上采用光刻定义漏极区域，在所述漏极区域上蒸镀金属Cr/Pt/Au或MoO3/Pt，形成与WSe2层相连接的漏极。
  13. 根据权利要求12所述的方法，其特征在于，在所述第二异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极，包括：
    在WSe2层上采用光刻定义栅极区域，采用原子层沉积生长高k栅介质氧化铪、氧化铝或氧化锆，形成栅介质层，并在所述栅介质层上蒸镀栅极金属，形成栅极。
  14. 一种异质结遂穿场效应晶体管的制备方法，其特征在于，包括：
    提供n型掺杂的衬底；
    通过反应离子刻蚀RIE在所述衬底上刻蚀出一凹槽，在所述凹槽中生成氧化物隔离层，形成第一绝缘层；
    通过曝光显影定义异质结材料层与所述衬底接触的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层；
    将异质结材料转移至所述衬底上，并进行刻蚀形成异质结材料层；
    在所述衬底上通过光刻定义源极区域，并在所述源极区域上通过蒸镀金属制作源极；
    在所述第一绝缘层生采用光刻定义漏极区域，并在所述漏极区域蒸镀金属形成漏极；
    在所述衬底、所述第二绝缘层和所述异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极。
  15. 根据权利要求14所述的方法，其特征在于，所述通过反应离子刻蚀RIE在所述衬底上刻蚀出一凹槽，在所述凹槽中生成氧化物隔离层，形成第一绝缘层，包括：
    在所述衬底上采用光刻定义氧化物隔离层，再利用反应离子刻蚀RIE在所述衬底上刻蚀一凹槽，采用蒸镀或者原子层沉积ALD在所述凹槽中生成氧化物隔离层，形成所述第一绝缘层。
  16. 根据权利要求14或15所述的方法，其特征在于，所述异质结材料层为二硒化钨WSe2层，所述第二绝缘层的材料为氧化钇Y2O3，则通过曝光显影定义异质结材料层与所述衬底接触的边缘区域，并在所述边缘区域蒸镀金属进行氧化，形成第二绝缘层，包括：
    在所述衬底上采用曝光显影定义WSe2与衬底接触的边缘区域，蒸镀金属钇并进行氧化，形成Y2O3层。
  17. 根据权利要求16所述的方法，其特征在于，所述将异质结材料转移至所述衬底上，并进行刻蚀形成异质结材料层，包括：
    将化学气相沉积CVD生长的WSe2转移至所述衬底上，并利用干法刻蚀去除暴露的WSe2，形成WSe2层。
  18. 根据权利要求17所述的方法，其特征在于，所述在所述衬底上通过光刻定义源极区域，并在所述源极区域上通过蒸镀金属制作源极，包括：
    在所述衬底的一段采用光刻定义源极区域，在所述源极区域蒸镀金属Ti/Pt/Au形成源极。
  19. 根据权利要求18所述的方法，其特征在于，所述在所述第一绝缘层生采用光刻定义漏极区域，并在所述漏极区域蒸镀金属形成漏极，包括：
    在第一绝缘层上采用光刻定义漏极区域，在所述漏极区域上蒸镀金属Cr/Pt/Au或MoO3/Pt，形成与WSe2层相连接的漏极。
  20. 根据权利要求19项所述的方法，其特征在于，所述在所述衬底、所述第二绝缘层和所述异质结材料层上，通过光刻定义栅极区域，并采用原子层沉积方式形成栅介质层，并在所述栅介质层上设置栅极，包括：
    在WSe2层和Y2O3层上采用光刻定义栅极区域，采用原子层沉积生长高k栅介质氧化铪、氧化铝或氧化锆，形成栅介质层，并在所述栅介质层上蒸镀栅极金属，形成栅极。
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