WO2019023824A1 - 一种比特块流处理、速率匹配、交换的方法和装置 - Google Patents

一种比特块流处理、速率匹配、交换的方法和装置 Download PDF

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Publication number
WO2019023824A1
WO2019023824A1 PCT/CN2017/095085 CN2017095085W WO2019023824A1 WO 2019023824 A1 WO2019023824 A1 WO 2019023824A1 CN 2017095085 W CN2017095085 W CN 2017095085W WO 2019023824 A1 WO2019023824 A1 WO 2019023824A1
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Prior art keywords
bit block
time slot
boundary
stream
slot
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PCT/CN2017/095085
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English (en)
French (fr)
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WO2019023824A8 (zh
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张xiao
肖帅
查敏
牛乐宏
陈兴耀
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华为技术有限公司
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Priority to PCT/CN2017/095085 priority Critical patent/WO2019023824A1/zh
Priority to JP2020504313A priority patent/JP6929436B2/ja
Priority to EP17919699.3A priority patent/EP3648400A4/en
Priority to KR1020207005039A priority patent/KR102337650B1/ko
Publication of WO2019023824A1 publication Critical patent/WO2019023824A1/zh
Priority to US16/775,338 priority patent/US11438091B2/en
Publication of WO2019023824A8 publication Critical patent/WO2019023824A8/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H04L49/352—Gigabit ethernet switching [GBPS]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1652—Optical Transport Network [OTN]
    • H04J3/1658—Optical Transport Network [OTN] carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H04L1/0003—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate by switching between different modulation schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
    • H04L1/0017—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy where the mode-switching is based on Quality of Service requirement
    • H04L1/0018—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy where the mode-switching is based on Quality of Service requirement based on latency requirement
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H04L1/0028—Formatting
    • H04L1/003—Adaptive formatting arrangements particular to signalling, e.g. variable amount of bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
    • H04J2203/0082—Interaction of SDH with non-ATM protocols
    • H04J2203/0085—Support of Ethernet

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a method and apparatus for bit block stream processing, rate matching, and switching.
  • the 802.3-based Ethernet defined by the Institute of Electrical and Electronics Engineers (IEEE) is used as a service interface in various applications and has achieved great success.
  • bandwidth particles are different. The larger the value, the more likely it is to deviate too much from the expectations of the actual application.
  • the mainstream application demand bandwidth may not belong to any kind of Ethernet standard rate. For example, if 50Gbps is used to transmit 100GE, there is no waste of resources, and 200Gbps does not currently have corresponding Ethernet standard particles to bear. It is expected that a flexible bandwidth port (virtual connection) can share one or several Ethernet physical interfaces, for example, two 40GE ports and two 10GE ports share one 100G physical interface.
  • Flexible Ethernet came into being by combining several Ethernet physical layer (PHY) devices into one FlexE group and physical layer channelization (sub-rate). , meet the flexible bandwidth port application needs. Therefore, the media access control (MAC) rate provided by FlexE can be greater than the rate of a single PHY (by binding) or less than the rate of a single PHY (through channelization).
  • PHY physical layer
  • MAC media access control
  • FlexE constructs a fixed frame format for physical interface transmission and performs time division multiplexing (TDM) slot division.
  • the FlexE TDM slot division is based on a 66B block, or a bit block.
  • the slot interleaving is implemented by 66B bit block interleaving.
  • the FlexE standard divides 20 slots for a 100G physical interface with 5G bandwidth per slot.
  • the slot interleaving period is 20 bit blocks, and slot positioning is implemented by overhead bit blocks, and a positioning overhead is inserted every 1023 slot cycles (ie, 1023 x 20 bit blocks). If the FlexE client signal bandwidth is 5G, it will occupy one time slot. If it is 5*n G, it will occupy n time slots.
  • the traffic of one FlexE client signal is mapped to one or more time slots of the physical interface for transmission, and the bitstream of the transmitted bits in multiple time slots cannot be rate adapted or exchanged separately.
  • the embodiments of the present invention provide a method and an apparatus for bit block stream processing, rate matching, and exchange, which are used to solve the problem that a bit block stream in a single time slot cannot be separately adapted or exchanged.
  • a bit block stream processing method includes: a source device obtains a first to-be-processed bit block stream; and a source device maps the first to-be-processed bit block stream to at least two slot-bit block streams, at least two The time slot bit block stream corresponds to at least two time slots on at least one physical interface, the different time slot bit block streams correspond to different time slots, and the at least two time slot bit block streams include the first time slot bit block stream and a second slot bit block stream, the first slot bit block stream includes a first boundary bit block and a second boundary bit block, and the second slot bit block stream includes a third boundary bit block and a fourth boundary bit block, first The boundary bit block corresponds to the third boundary bit block, and the second boundary bit block and the fourth boundary bit block correspond to each other, and the first boundary bit block and the second boundary bit block include N first bit blocks, and the third boundary bit block And N first bit blocks are included between the fourth boundary bit block, and the first bit block is a non-idle bit Block,
  • the number of non-idle bit blocks between the first boundary bit block and the second boundary bit block is equal to the number of non-idle bit blocks between the third boundary bit block and the fourth boundary bit block, so during transmission, a single time slot
  • the bit block stream can perform slot rate matching and time slot exchange separately. Different time slot bit block streams can also be transmitted to the receiving end device through different transmission paths or different intermediate nodes, and the receiving end device can delete all idle bits. The block is then aligned using the boundary bit block to recover the bit block stream to be received.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the method further includes: transmitting, by using a first time slot of the first physical interface, a first time slot bit block stream, and transmitting, by using a second time slot of the first physical interface, a second time slot bit block stream; or
  • the first time slot bit block stream is sent through the first time slot of the first physical interface, and the second time slot bit block stream is sent through the second time slot of the second physical interface.
  • obtaining the first to-be-processed bit block stream specifically includes: obtaining a first to-be-processed service; performing bit block coding on the first to-be-processed service to obtain a first to-be-processed bit-block stream.
  • the sending, by the first time slot of the first physical interface, the first time slot bit block stream specifically includes: adding or deleting an idle bit block between the first boundary bit block and the second boundary bit block, Obtaining a first time slot bit block stream after rate adaptation; transmitting a rate adapted first time slot bit block stream by using a first time slot of the first physical interface.
  • sending the second time slot bit block stream through the second time slot of the first physical interface or sending the second time slot bit block stream through the second time slot of the second physical interface includes: increasing or Deleting an idle bit block between the third boundary bit block and the fourth boundary bit block to obtain a rate-adjusted second slot bit block stream; and transmitting the rate adapted by the second time slot of the first physical interface A two-slot bit block stream, or a rate-adapted second slot bit block stream is transmitted through a second slot of the second physical interface.
  • the method further includes: switching a first slotted bitstream of the first slot of the first physical interface to a third slot of the third physical interface.
  • mapping the first to-be-processed bit block stream into the at least two time slot bit block streams specifically includes: mapping the first to-be-processed bit block stream into at least two time slots in a round-robin scheduling manner. Bit block stream.
  • a second aspect a bit block stream rate adaptation method, comprising: obtaining a first slot bit block stream, where the first slot bit block stream includes a first boundary bit block and a second boundary bit block, and the first boundary bit block And the first boundary block includes N first bit blocks, the first bit block is a non-idle bit block, and N is an integer greater than or equal to 1; adding or deleting between the first boundary bit block and the second boundary bit block
  • the idle bit block obtains the rate-adjusted first slot bit block stream; the rate-adapted first slot bit block stream is sent through the second slot of the second physical interface.
  • the single slot bit block stream includes a boundary bit block, and the boundary bit block includes non-idle bit blocks, so that the free bit block can be added or deleted between the boundary bit blocks, and the receiving end device can utilize after deleting all the free bit blocks.
  • the boundary bit blocks are aligned to recover the bit block stream to be received
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • a third aspect a bit block stream switching method, comprising: obtaining a first time slot through a first physical interface a time slot bit block stream, the first time slot bit block stream includes a first boundary bit block and a second boundary bit block, and the first boundary bit block and the second boundary bit block include N first bit blocks, the first bit The block is a non-idle bit block, N is an integer greater than or equal to 1; the first time slot bit block stream is switched to a second time slot of the second physical interface; and the first time slot is transmitted through the second time slot of the second physical interface Bit block stream.
  • the single slot bit block stream includes a boundary bit block, and the boundary bit block includes a non-idle bit block, so that the single slot bit block stream is separately time slot exchanged, and the receiving end device can delete all the idle bit blocks. Align with the boundary bit block to recover the bit block stream to be received
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the sending, by the second time slot of the second physical interface, the first time slot bit block stream specifically includes: adding or deleting an idle bit block between the first boundary bit block and the second boundary bit block, Obtaining a first time slot bit block stream after rate adaptation; transmitting a rate adapted first time slot bit block stream through a second time slot of the second physical interface.
  • the switching of the first time slot bit block stream to the second time slot of the second physical interface specifically includes: according to the first time slot of the first interface physical interface and the second interface physical interface The corresponding relationship of the time slots, the first time slot bit block stream is switched to the second time slot of the second interface physical interface.
  • a fourth aspect a method for processing a bit block stream, comprising: receiving, by a receiving device, at least two time slot bit block streams, where at least two time slot bit block streams correspond to at least two time slots on at least one physical interface, different The slotted bitstreams correspond to different time slots, and the at least two slotted bitstreams include a first slotted bitstream and a secondslotped blockstream, the first slotted bitstream comprising the first bounding bitblock And a second boundary bit block, the second slot bit block stream includes a third boundary bit block and a fourth boundary bit block, the first boundary bit block and the third boundary bit block, the second boundary bit block and the fourth boundary bit Corresponding to block, the first boundary bit block and the second boundary bit block include N first bit blocks, and the first boundary block includes a N first bit block, and the first bit block is a non-idle bit block; the receiving end device deletes the idle bit block between the first boundary bit block and the second boundary bit block, and deletes the idle bit block between the third boundary bit block and the fourth boundary
  • the number of non-idle bit blocks between the first boundary bit block and the second boundary bit block received by the receiving end device is equal to the number of non-idle bit blocks between the third boundary bit block and the fourth boundary bit block, and the receiving end device may After all the free bit blocks are deleted, the boundary bit blocks are used for alignment, thereby recovering the bit block stream to be received.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the method further includes: performing bit block decoding on the first to-be-received bit block stream to obtain a first to-be-received service.
  • the method further includes: performing IPG recovery on the first to-be-received bit block stream to obtain a first to-be-received service.
  • obtaining at least two time slot bit block streams specifically includes: obtaining, by using a first time slot of the first physical interface, a first time slot bit block stream, obtained by using a second time slot of the first physical interface Second time slot bit Block flow; or obtaining a first time slot bit block stream through a first time slot of the first physical interface, and obtaining a second time slot bit block stream by using a second time slot of the second physical interface.
  • a bit block stream processing apparatus includes a receiver, a processor, and a bit block stream processing apparatus for performing the method in any of the above first aspect or any possible implementation of the first aspect.
  • a bit block stream rate adaptation apparatus includes a receiver, a rate adapter, and a transmitter, where the bit block stream rate adaptation apparatus is used to perform the second aspect or any possible implementation of the second aspect. method.
  • a bit block stream switching apparatus includes a receiver, a switch, and a transmitter, and the bit block stream switching apparatus is configured to perform the method in any of the foregoing third aspect or the third aspect.
  • a bit block stream processing apparatus includes a receiver, a processor, and a bit block stream processing apparatus for performing the method in any of the possible implementations of the fourth aspect or the fourth aspect.
  • FIG. 1A is a schematic diagram of a code pattern definition of a 64/66 code in an embodiment of the present application
  • FIG. 1B is a schematic diagram of a code pattern definition of a free block in the embodiment of the present application.
  • FIG. 2A is a schematic structural diagram of a PE device according to an embodiment of the present application.
  • FIG. 2B is a schematic structural diagram of a P device according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an X-E time slot switching network according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of an X-E time slot exchange method according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a frame node device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of an X-E time slot exchange method according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a box type node device according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart of an X-E time slot exchange method according to an embodiment of the present invention.
  • FIG. 9A is a schematic flowchart of a mapping of a transmitting end according to an embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram of a mapping of a transmitting end according to an embodiment of the present disclosure.
  • FIG. 9C is a schematic diagram of another transmitter mapping according to an embodiment of the present invention.
  • FIG. 9D is a schematic diagram of still another mapping of a transmitting end according to an embodiment of the present invention.
  • FIG. 9E is a schematic diagram of still another mapping of a transmitting end according to an embodiment of the present invention.
  • 10A is a schematic flowchart diagram of a slot rate matching method according to an embodiment of the present invention.
  • FIG. 10B is a structural diagram of a slot rate matching circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic flowchart diagram of a time slot exchange method according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic flowchart of a demapping at a receiving end according to an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of a bit block stream processing apparatus according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a bit block flow rate adaptation apparatus according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a bit block stream switching apparatus according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a bit block stream processing apparatus according to an embodiment of the present disclosure.
  • Ethernet port In Ethernet, the Ethernet port usually appears as a logical concept for data-oriented, called a logical port. Or simply referred to as a port, the Ethernet physical interface appears as a concept on the hardware, called a physical interface or simply an interface. Typically, an Ethernet port is tagged with a MAC address. Traditionally, the rate of the Ethernet port is determined based on the rate of the Ethernet physical interface. In general, the maximum bandwidth of an Ethernet port corresponds to the bandwidth of an Ethernet physical interface, such as 10 Mbps, 100 Mbps, 1000 Mbps (1 Gbps), 10 Gbps, 40 Gbps, 100 Gbps, and 400 Gbps Ethernet physical interfaces.
  • Ethernet has gained widespread adoption and significant growth over the past quite a while.
  • the Ethernet port rate is 10 times higher, and it is evolving from 10 Mbps to 100 Mbps, 1000 Mbps (1 Gbps), 10 Gbps, 40 Gbps, 100 Gbps, and 400 Gbps.
  • the bandwidth growth required by mainstream applications does not exhibit such a 10-fold growth feature, such as 50 Gbps, 75 Gbps, 200 Gbps, and the like.
  • the industry wants to provide support for Ethernet ports (virtual connections) for bandwidths such as 50Gbps, 60Gbps, 75Gbps, 200Gbps and 150Gbps.
  • flexible bandwidth ports which can use one or several Ethernet physical interfaces together, for example, two 40GE ports and two 10GE ports use one 100G physical interface together; Flexible rate adjustments are made to changes in demand, such as from 200 Gbps to 330 Gbps, or 50 Gbps to 20 Gbps to increase port efficiency or extend its lifecycle.
  • Flexible rate adjustments are made to changes in demand, such as from 200 Gbps to 330 Gbps, or 50 Gbps to 20 Gbps to increase port efficiency or extend its lifecycle.
  • they can be bundled in cascade to support stacking of logical port rates (for example, bundling two 100GE physical interface stacks to support 200GE logical ports).
  • the bandwidth resources obtained by the flexible stacking of the physical interfaces can be pooled, and the bandwidth is allocated to a specific Ethernet logical port according to the granularity (for example, 5G is a granularity), and several Ethernet virtual connection pairs are cascaded. Efficient sharing of physical link groups.
  • FlexE supports sub-rate, channelization, and inverse multiplexing for Ethernet services.
  • FlexE can support the transmission of 250G Ethernet traffic (MAC code stream) using 3 existing 100GE physical interfaces.
  • FlexE can support the transmission of 200G Ethernet services using two existing 100GE Physical Medium Dependent (PMD).
  • PMD Physical Medium Dependent
  • FlexE can support several logical ports to use one or more physical interfaces together, which can support multiplexing multiple low-rate Ethernet services into high-speed flexible Ethernet.
  • Ethernet is used as a service interface in the access network and the metropolitan area network
  • the FlexE technology of the service aggregation function based on the Ethernet technology can seamlessly connect with the Ethernet interface of the underlying service network.
  • the introduction of these FlexE sub-rate, channelization and inverse multiplexing functions greatly expands the application of Ethernet, enhances the flexibility of Ethernet applications, and makes Ethernet technology gradually penetrate into the transmission network.
  • FlexE provides a viable evolution path for the virtualization of Ethernet physical links.
  • Flexible Ethernet requires several virtual Ethernet data connections on a cascaded set of physical interfaces. For example, four 100GE physical interfaces are cascaded and support several logical ports. When the bandwidth of some logical ports is reduced, the bandwidth of the other logical ports is increased, and the total amount of bandwidth reduction is equal to the total amount of bandwidth increase. The bandwidth of several logical ports is flexibly adjusted and used together. 100GE physical interfaces.
  • FlexE draws on the Synchronous Digital Hierarchy (SDH)/Optical Transfer Network (OTN) technology to construct a fixed frame format for physical interface transmission.
  • the time slot division of the TDM Unlike SDH/OTN, FlexE's TDM slot division granularity is 66 bits, which can correspond to a 64B/66B bit block.
  • a FlexE frame consists of 8 lines, the first 66b block position of each line is the FlexE overhead area, and the overhead area is the payload area for slot division, with a granularity of 66 bits, corresponding to 20x1023 66-bit bearer space, 100GE interface
  • the bandwidth is divided into 20 time slots, and the bandwidth of each time slot is about 5 Gbps. FlexE implements multiple transmission channels on a single physical interface by means of interleaving multiplexing, that is, multiple time slots are implemented.
  • a plurality of physical interfaces may be bundled in cascade, and all time slots of the plurality of physical interfaces may be combined to carry one Ethernet logical port. For example, 10GE requires two time slots, 25GE requires 5 time slots, and so on.
  • the 66b block that is still visible in the logical port is a serial transmission.
  • Each logical port corresponds to a MAC, and the corresponding Ethernet packet is transmitted. The start of the packet and the identification of the idle padding are the same as those of the traditional Ethernet.
  • FlexE is just an interface technology, and the related switching technology is still based on Ethernet packets.
  • 5G fifth-generation communication technology
  • deterministic low-latency, reliability, and security isolation technologies have become an important issue that needs to be overcome.
  • the inventor has defined a hard-pipe based switching technology based on physical interfaces.
  • X-Ethernet (XE) is a bit-block switching technology based on the Ethernet physical layer, such as 64/66 Bit Block, which has deterministic ultra-low latency technology. feature.
  • the bit block mentioned in the embodiment of the present application may be an M1/M2 bit block, or an M1B/M2B bit block, and M1/M2 represents an encoding mode, where M1 represents the number of payload bits in each bit block. M2 represents the total number of bits per bit block, and M1 and M2 are positive integers, and M2>M1.
  • This M1/M2 bit block stream is transmitted on the Ethernet physical layer link.
  • 1G Ethernet uses 8/10Bit encoding
  • 1GE physical layer link delivers 8/10 bit block stream
  • 10GE/40GE/100GE adopts 64/.
  • 66Bit coded the 10GE/40GE/100GE physical layer link delivers a 64/66 bit block stream.
  • other coding methods will also appear, such as 128/130 Bit coding and 256/258 Bit coding.
  • the embodiment of the present application is uniformly represented by an M1/M2 bit block stream.
  • FIG. 1A For the M1/M2 bit block stream, there are different types of bit blocks and are explicitly specified in the standard.
  • the following is an example of a 64/66 Bit coded pattern definition, as shown in FIG. 1A, in which the first two bits “10" " or “01” is a 64/66-bit block sync header bit, and the last 64 Bit is used to carry payload data or protocols.
  • Figure 1A includes 16 pattern definitions, each row representing a pattern definition of a block of bits, where D0-D7 represents the data byte, C0-C7 represents the control byte, S0 represents the start byte, and T0-T7 represents the code.
  • the end byte, the second line corresponds to the pattern definition of the idle bit block (idle block), and the free bit block can be represented by /I/, as shown in FIG. 1B.
  • the seventh line corresponds to the pattern definition of the start block, the start block can be represented by /S/, the 9th-16th line respectively corresponds to the pattern definition of the eight end blocks, and the eight end blocks can be uniformly represented by /T/.
  • the interface mentioned in the embodiment of the present application may be the Ethernet physical interface mentioned above, or may be another physical interface, for example, an Optical Transport Network (OTN) interface, a Flexible Optical Transport Network (Flexible OTN, FlexOTN). Interface, flexible Ethernet FlexE interface, Common Public Radio Interface (CPRI), Synchronous Digital Hierarchy (SDH) interface, Fibre Channel (FC) interface or InfiniBand interface For example, it may also be a physical interface C2C interface inside the device or the like.
  • OTN Optical Transport Network
  • FlexOTN Flexible Optical Transport Network
  • CPRI Common Public Radio Interface
  • SDH Synchronous Digital Hierarchy
  • FC Fibre Channel
  • InfiniBand interface it may also be a physical interface C2C interface inside the device or the like.
  • the port mentioned in the embodiment of the present application may be the Ethernet port mentioned above, and may of course be other logic.
  • the service port can be, for example, an optical transport network OTN logical service port, a flexible optical transport network FlexOTN logical service port, a flexible Ethernet FlexE logical service port, a general public wireless logical service port CPRI, a synchronous digital system SDH logical service port, and a Fibre Channel FC.
  • Logical functions are sender-side mapping, slot rate adaptation, time-slot switching, and receiver-side demapping, respectively.
  • the time slot of the physical interface can perform independent slot rate adaptation and independent time slot switching, and the service can be recovered at the receiving end. If a service occupies multiple time slots, each time slot is independently adapted and exchanged, the transmission delays of different time slots may be different, and the positions of insertion or deletion of idle time blocks of different time slots may be different, by the present invention.
  • the four logic functions provided in the embodiment can perform time slot rate adaptation or time slot exchange separately in each time slot, and can eliminate differences in delay and position difference at the receiving end, and correctly recover the bit block stream to be received. .
  • the embodiment of the present invention can use the device shown in FIG. 2A and FIG. 2B to transmit a bit block stream.
  • a provider edge (PE) device and an operator (Provider) , P) equipment The PE device is an edge device. One end is connected to the user device.
  • the interface is the user network interface (UNI), and the other end is connected to the network device.
  • the interface is the network to network interface (NNI).
  • the key capability is convergence, encapsulation/decapsulation, and the path between the PE device and the PE device may be a pseudowire PW or a tunnel according to a starting point.
  • the P device represents a network device and is a core device in the network.
  • the main capability is a strong switching capability. Both ends are connected to network devices, and the interface is NNI.
  • the client adaptation unit represents a user-side processing unit for accessing user service signals, and performs interface adaptation, rate adaptation, etc.
  • the interface adaptation may include XE slot mapping and / or demapping
  • XE slot mapping can map one bit block stream into multiple slot bit block streams
  • XE slot demapping can demap multiple slot bit block streams into one bit block stream
  • interface adaptation It can also include pattern conversion and the like.
  • the network adaptation unit (nAdpt) represents the network side processing unit of the XE technology system, and is configured to send the service signal in the device to the network side and complete corresponding function processing; or receive the network side service signal and transmit it to other processing units in the device.
  • XE slot mapping and/or demapping may also be implemented by a network adaptation unit.
  • the L1.5switch or the X-Ethernet switch, that is, the X-Ethernet Relay (that is, the forwarding of the intermediate node), is embodied as a switching unit.
  • an XE time slot switching network includes a node 301, a node 302, a node 303, and a node 304, wherein the node 301 is a source PE device, and the node 302 is The node 303 is the intermediate P device, the node 304 is the destination PE device, and the node 301 receives the 10GE service from its UNI interface, and needs to send the 10GE service to the node 304 through the node 302 and/or the node 303, and the node 304 will receive the 10GE service. Sent to the client through its UNI interface.
  • FIG. 4 is a schematic diagram of an XE time slot exchange method according to an embodiment of the present invention.
  • the method is applied to the network shown in FIG. 3, and specifically includes:
  • Step 401 The client adaptation unit 3012 of the node 301 performs sender mapping, and the bitstream to be processed is to be processed. It is mapped to a first slotted bit block stream and a second slotted bit block stream.
  • An embodiment of the present invention is described by taking an example of mapping a to-be-processed bit block stream into a first time slot bit block stream and a second time slot bit block stream.
  • the to-be-processed bit block stream may also be mapped to other blocks.
  • the number of time slot bit block streams is not limited in this embodiment of the present invention.
  • the sender mapping may also be performed by the network adaptation unit 3014 of the node 301. After the adaptation is completed, the slot bit block stream is directly transmitted through the NNI interface 30151, the NNI interface 30152 or other interfaces.
  • the first slot bit block stream includes a first boundary bit block and a second boundary bit block
  • the second slot bit block stream includes a third boundary bit block and a fourth boundary bit block, where a first boundary bit block corresponding to the third boundary bit block, the second boundary bit block and the fourth boundary bit block being corresponding, and the first boundary bit block and the second boundary bit block are included N first bit blocks, including N first bit blocks between the third boundary bit block and the fourth boundary bit block, the first bit block being a non-idle bit block, and N being greater than or equal to 1 Integer.
  • Step 402 the client adaptation unit 3012 of the node 301 performs slot rate adaptation, the switching unit 3013 of the node 301 performs slot exchange, and the network adaptation unit 3014 of the node 301 performs slot rate adaptation, and the first slot bit is used.
  • the block stream is sent to node 302 through NNI interface 30151, and the second slot bit block stream is sent to node 303 through NNI interface 30152.
  • Load balancing can be achieved by transmitting the first slotted bitstream through the NNI interface 30151 to the node 302 and the second slotted bitstream to the node 303 via the NNI interface 30152.
  • the first time slot bit block stream and the second time slot bit block stream may be transmitted to the node 302 through different time slots of the NNI interface 30151, such that the node 302 is required to process the first time slot bit block stream and the second time slot bit block. flow.
  • Step 403 the node 302 receives the first time slot bit block stream through the NNI interface 3021, the network adaptation unit 3022 of the node 302 performs time slot rate adaptation, the switching unit 3023 of the node 302 performs time slot exchange, and the network adaptation of the node 302 Unit 3024 performs slot rate adaptation and transmits the first slotted bitstream to node 304 via NNI interface 3025.
  • step 404 the node 303 receives the first slotted bitstream through the NNI interface 3031, the network adaptation unit 3032 of the node 303 performs slot rate adaptation, the switching unit 3033 of the node 303 performs slot switching, and the network adaptation of the node 303 Unit 3034 performs slot rate adaptation and transmits the first slotted bitstream to node 304 via NNI interface 3035.
  • Step 405 the node 304 receives the first slotted bitstream through the NNI interface 30411, the node 304 receives the second slotted bitstream through the NNI interface 30412, and the network adaptation unit 3042 of the node 304 performs slot rate adaptation, the node 304 The switching unit 3043 performs time slot switching, and the client adaptation unit 3044 of the node 304 performs slot rate adaptation.
  • Step 406 the client adaptation unit 3044 of the node 304 performs the receiving end demapping, and demaps the first slot bit block stream and the second slot bit block stream into a bit block stream to be received.
  • the embodiment of the present invention may also use a packet bearer node device as shown in FIG. 5 or FIG. 7 to process a bit block stream.
  • an interface card of a box device or an interface chip of a line card of a frame device implements a client adaptation unit.
  • the network adapter unit function, and the XE time slot switching unit, the secondary switch board can also be modified to support the XE slot switching function or to keep the original switching network design intact.
  • a frame node device includes a line card 501, a switching plane 502, a switching plane 503, and a line card 504.
  • the switching plane 502 and the switching plane 503 may be located on different boards. On the card, the same card can be located on the same card.
  • the line card 501 and the line card 504 are usually located in different boards.
  • the frame node device can also include other boards, which is not limited by the embodiment of the present invention.
  • the line card line card 501, the switching plane 502, the switching plane 503, and the line card 504 are interconnected through a C2C interface, and may be electrically connected or optically interconnected.
  • an XE time slot switching method is provided in the embodiment of the present invention.
  • the method is applied to the network shown in FIG. 5, and specifically includes:
  • Step 601 The client adaptation unit 50121 of the line card 501 performs a sender mapping, and maps the to-be-processed bit block stream into a first slot bit block stream and a second bit block stream.
  • Step 602 the client adaptation unit 50121 of the line card 501 performs time slot rate adaptation, and the switching unit 5013 of the line card 501 performs time slot exchange, and switches the first time slot bit block stream to the C2C adaptation unit 50141 of the line card 501.
  • the C2C adapting unit 50141 of the line card 501 performs time slot rate adaptation, and then sends the first time slot bit block stream to the switching plane 502 through the C2C interface 50151, and the switching unit 5013 of the line card 501 performs time slot switching, and the second
  • the slotted bit block stream is switched to the C2C adaptation unit 50142 of the line card 501, and the C2C adaptation unit 50142 of the line card 501 performs slot rate adaptation and sends the first slotted bitstream to the switching plane 503 through the C2C interface 50152.
  • the C2C adaptation unit 50141 can send the handover plane to the switching plane for slot exchange processing without performing slot rate adaptation processing.
  • the switching plane 502 receives the first slotted bit block stream through the C2C interface 5021, the C2C adapting unit 5022 of the switching plane 502 performs slot rate adaptation, and the switching unit 5023 of the switching plane 502 performs slot switching, and the switching plane 502
  • the C2C adaptation unit 5024 performs slot rate adaptation, and sends the first slot bit block stream to the line card 504 through the C2C interface 5025.
  • step 604 the switching plane 503 receives the first slotted bitstream stream through the C2C interface 5031, the C2C adaptation unit 5032 of the switching plane 503 performs slot rate adaptation, and the switching unit 5033 of the switching plane 503 performs slot switching, and the switching plane 503
  • the C2C adaptation unit 5034 performs slot rate adaptation, and sends the first slot bit block stream to the line card 504 through the C2C interface 5035.
  • Step 605 the line card 504 receives the first time slot bit block stream through the C2C interface 50411, and the line card 504 receives the second time slot bit block stream through the C2C interface 50412, and the C2C adaptation unit 30421 and the C2C adaptation unit 30422 of the line card 504.
  • the slot rate adaptation is performed, the switching unit 5043 of the line card 504 performs time slot switching, and the client adaptation unit 50441 of the line card 504 performs slot rate adaptation.
  • Step 606 the client adaptation unit 50441 of the line card 504 performs the receiving end demapping, and demaps the first slot bit block stream and the second slot bit block stream into a bit block stream to be received.
  • a box-type node device includes an inbound interface board 701, a switching plane 702, and an egress interface board 704.
  • the inbound interface board 701, the switching plane 702, and the egress interface board 704 are usually located.
  • the box node device usually has only one switching plane, and the interface board does not have a switching function, which is not limited by the embodiment of the present invention.
  • the inbound interface board 701, the switching plane 702, and the outbound interface board 704 are interconnected through a C2C interface, and may be electrically connected or optically interconnected.
  • an X-E time slot exchange method is provided for an embodiment of the present invention, where
  • time slot rate adaptation, time slot exchange, and receiver demapping refer to the following embodiments.
  • the method is applied to the network shown in FIG.
  • Step 801 The client adaptation unit 70121 of the inbound interface board 701 performs a sender mapping, and maps the to-be-processed bit block stream into a first slotted bitstream and a secondbitstream.
  • Step 802 the client adaptation unit 70121 of the inbound interface board 701 performs slot rate adaptation, and the C2C adaptation unit 7014 of the inbound interface board 701 performs the slot rate adaptation to the first slotted bitstream and the second slot.
  • the bit block stream is sent to the switching plane 702 through the C2C interface 5015.
  • Step 803 the switching plane 702 receives the first slotted bitstream and the second slotted bitstream through the C2C interface 7021.
  • the C2C adaptation unit 7022 of the switching plane 702 performs slot rate adaptation, and the switching unit 702 of the switching plane 702 The time slot exchange is performed, and the C2C adaptation unit 7024 of the switching plane 702 performs slot rate adaptation, and sends the first slotted bitstream and the secondslotted chunkstream to the outbound interface board 704 through the C2C interface 7025.
  • step 805 the outbound interface board 704 receives the first slotted bitstream and the second slotted bitstream through the C2C interface 7041, and the C2C adaptation unit 3042 of the outbound interface board 704 performs slot rate adaptation.
  • Step 806 The client adaptation unit 70441 of the outbound interface board 704 performs the receiving end demapping, and demaps the first slotted bitstream stream and the second slotted bitstream stream into a to-be-received blockstream.
  • an embodiment of the present invention provides a schematic diagram of a mapping of a transmitting end, including:
  • Step 901 Obtain a first to-be-processed bit block stream.
  • Step 902 Map the first to-be-processed bit block stream into at least two time slot bit block streams, where the at least two time slot bit block streams correspond to at least two time slots on at least one physical interface, different The slotted bitstream corresponds to different time slots, and the at least two slotted bitstreams include a first slotted bitstream and a secondslotped blockstream, the first slotted bitstream comprising the first a boundary bit block and a second boundary bit block, the second slot bit block stream including a third boundary bit block and a fourth boundary bit block, the first boundary bit block and the third boundary bit block corresponding to Corresponding to the second boundary bit block and the fourth boundary bit block, the first boundary bit block and the second boundary bit block include N first bit blocks, and the third boundary bit block and the The first boundary block includes N first bit blocks, the first bit block is a non-idle bit block, and N is an integer greater than or equal to 1.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the M1/M2 bit block is a coded bit block.
  • the first time slot bit block stream is sent through a first time slot of the first physical interface, and the second time slot bit block stream is sent through a second time slot of the first physical interface; Or sending the first time slot bit block stream through a first time slot of the first physical interface, and sending the second time slot bit block stream by using a second time slot of the second physical interface.
  • the obtaining the first to-be-processed bit block stream specifically includes: obtaining a first to-be-processed service; performing bit block coding on the first to-be-processed service to obtain a first to-be-processed bit-block stream. That is, for a service stream that is not subjected to bit block coding, bit block coding is required.
  • the sending, by the first time slot of the first physical interface, the first time slot bit block stream specifically includes: adding or deleting idle bits between the first boundary bit block and the second boundary bit block. Block, obtaining a rate-adapted first time slot bit block stream; transmitting the rate-adapted channel by using a first time slot of the first physical interface The first time slot bit block stream.
  • the second time slot bit block stream is sent through a second time slot of the first physical interface or the second time slot bit block stream is sent through a second time slot of the second physical interface.
  • the method includes: adding or deleting an idle bit block between the third boundary bit block and the fourth boundary bit block, and obtaining a rate-adjusted second slot bit block stream;
  • the method further includes: switching the first slotted bitstream of the first slot of the first physical interface to the third slot of the third physical interface.
  • mapping the first to-be-processed bit block stream to at least two time slot bit block streams specifically includes: mapping the first to-be-processed bit block stream to at least in a round-robin scheduling manner Two slotted bit block streams.
  • the time slot bit block stream is finally transmitted in the time slot of the physical interface, and the time slot rate matching, time slot switching, and the like may also be performed before the transmission, which is not limited in this embodiment of the present invention.
  • step 902 may also be to map the first to-be-processed bit block stream into at least two slot-bit block streams, the at least two slot-bit block streams and at least one physical interface.
  • different time slot bit block streams correspond to different time slots
  • the at least two time slot bit block streams include corresponding boundary bit blocks, and each time between two sets of corresponding boundary bit blocks The number of non-idle bit blocks included in the slot block stream is the same.
  • the embodiment of the present invention needs to insert a corresponding boundary bit block in each slot slot stream, for example, the first slot bit stream and the second slot bit block stream are respectively inserted into the corresponding first.
  • the boundary bit block and the third boundary bit block are respectively inserted into the corresponding second boundary bit block and the fourth boundary bit block in the first slot bit block stream and the second slot bit block stream.
  • the corresponding boundary bit blocks may be the same bit block or different bit blocks.
  • the number of bit blocks included in each slotted block stream between the two sets of corresponding boundary bit blocks is the same, the number of non-idle bit blocks included is the same, and the number of free bit blocks included is also the same.
  • At least two time slot bit block streams each include a corresponding boundary bit block, and the number of non-idle bit blocks included in each slot bit block stream between the two sets of corresponding boundary bit blocks is the same.
  • the number of non-idle bit blocks included in each slotted block stream between two sets of corresponding boundary bit blocks is the same, and the number of free bit blocks included in each slotted bitstream is different. That is, the number of total bit blocks included in each slotted bitstream is also different.
  • corresponding boundary bit blocks can be inserted in each slot bit block stream at the same time, for example, boundary bit blocks can be inserted in the first slot bit block stream and the second slot bit block stream at the same time, That is, the first boundary bit block and the third boundary bit block are simultaneously inserted while the second boundary bit block and the fourth boundary bit block are inserted.
  • the corresponding boundary bit block is used for the alignment operation when the demapping is performed at the receiving end. Therefore, the insertion of the corresponding boundary bit block may also be performed at different times, as long as the receiving end can perform the alignment operation.
  • a starting time slot bit block stream may be determined in each time slot bit block stream, or may also be referred to as a start time slot.
  • the insertion of the boundary bit block can be performed when the initial slot mapping is performed, for example If the bitstream to be processed needs to be mapped to slot S, slot B and slot C, the mapping order may be ABC, CBA, etc. If the mapping order is ABC, slot A is the initial slot. .
  • the insertion of a corresponding set of boundary bit blocks may be periodic, such as once inserted in 50 milliseconds, or may be aperiodic, such as when data is interrupted and no traffic is currently being transmitted.
  • the number of non-idle bit blocks between different sets of boundary bit blocks may be different.
  • the bit block mapping may be performed in a round-robin scheduling manner, that is, the bit block to be mapped is taken out from the bit block stream to be processed, and is mapped to the two slot bit block streams in units of one bit block.
  • the mapping may also be performed in units of other numbers of bit blocks, or other mapping rules may be used, for example, mapping two bit blocks in the first slot bit block stream first. Three bit blocks are mapped in the two-slot bit block stream, three bit blocks are mapped in the first slot bit block stream, and two bit blocks are mapped in the second slot bit block stream.
  • the receiving end demapping can be performed as long as the receiving end knows the mapping rule of the non-idle bit block used by the transmitting end mapping.
  • the idle time may be mapped in the slot bit block stream.
  • bit block to be mapped if the bit block to be mapped is not empty or an idle bit block, but the last mapped bit block is an idle bit block, then the number of consecutive idle bit blocks mapped is an integer multiple of the number of time slot bit block streams In this case, the bitmap block to be mapped is mapped, and the idle bit block is continued to be mapped if the number of consecutive contiguous idle bit blocks is not an integer multiple of the number of slot bit block streams, so that two slots can be idle in the bit block stream.
  • the number of bit blocks is the same, and the number of non-idle bit blocks is also the same.
  • the bit block in the slotted bit block stream is an Ethernet M1/M2 bit block.
  • the bit block stream to be processed can be directly obtained, and for the idle bit block therein, the block is sent.
  • the idle bit block can be deleted or not deleted.
  • the idle bit block is usually an inter-packet gap (IPG).
  • IPG inter-packet gap
  • M1/M2 bit block coding is usually required to be processed.
  • the bit block stream for example, can be 64/66 encoded with a common public radio interface (CPRI) service stream.
  • CPRI public radio interface
  • FIG. 9B is a schematic diagram of a mapping of a transmitting end according to an embodiment of the present invention.
  • a 15G Ethernet service is mapped into three 5G time slots, and time slot mapping is performed in units of one bit block.
  • the three 5G time slots are slot_a, slot_b, and slot_c, respectively, and the inserted boundary bit block is Slot aligned mark (SAM).
  • Step 1 Receive a service bit block stream, delete all idle bit blocks in the service bit block stream, and then perform buffer waiting mapping on the service bit block stream of the deleted idle bit block, and process the bit block stream 1 into a bit block as shown in FIG. 9B. As shown in stream 2, the free bit block between B15 and B16 is deleted;
  • Step 2 Determine whether the mapping start time slot is currently in the current state. If yes, determine whether the SAM needs to be inserted. If it needs to be inserted, insert the SAM into slot_a, slot_b, and slot_c respectively. If no insertion is required, go to step 3.
  • Step 3 Detect whether there is a bit block to be mapped in the buffer, if yes, go to step 4; if not, go to step 5;
  • Step 4 Read a bit block from the buffer, put it into the time slot corresponding to the mapping pointer, and modify the mapping pointer to point to the next time slot, and then jump to step 1 for the next round of cycles;
  • Step 5 Insert 3 idle bit blocks, and map them to 3 time slots in turn.
  • the mapping pointer points to the time slot pointed to before the insertion of the idle bit block, and then jumps to step 1 for the next round of cycles, such as Figure In block 9B, the bit block stream 2 is processed as shown in the three slot bit block streams. If there is no bit block to be mapped in the buffer after B15, the idle bit block is mapped in three slots in turn.
  • FIG. 9C is a schematic diagram of a mapping of a sender according to an embodiment of the present invention.
  • a 10G CPRI service is mapped into two 5G time slots, and time slot mapping is performed in units of one bit block.
  • the two 5G time slots are slot_a and slot_b, respectively, and the inserted boundary bit block is SAM.
  • Step 1 Receive the CPRI service data stream input and perform coding, and perform buffer waiting mapping on the encoded bit block stream, as shown in FIG. 9C, the service stream 1 is processed as the bit block stream 2;
  • Step 2 judging whether the mapping start slot is currently being mapped, if yes, determining whether the SAM needs to be inserted, and if the insertion is required, inserting the SAM for slot_a and slot_b respectively, if not, then going to step 3;
  • Step 3 Detect whether there is a bit block to be mapped in the buffer, if yes, go to step 4; if not, go to step 5;
  • Step 4 reading a bit block from the buffer, placing it in the time slot corresponding to the mapping pointer, and modifying the mapping pointer to point to the next time slot, and then jumping to step 1 for the next round of cycles;
  • Step 5 Insert 2 idle bit blocks, and map them to 2 time slots in turn.
  • the mapping pointer points to the time slot pointed to before the insertion of the idle bit block, and then jumps to step 1 for the next round of cycles, such as
  • the bit block stream 2 is processed as a two-slot bit block stream in Fig. 9C. If there is no bit block to be mapped in the buffer after B15, the idle bit block is mapped in two slots in turn.
  • the difference between the embodiment shown in FIG. 9C and the embodiment shown in FIG. 9B is that the accessed service is a non-Ethernet service, and the encoding process needs to be performed before the slot mapping can be performed, and the non-Ethernet service has no IPG and idle bit blocks. No need for idle bit block deletion.
  • FIG. 9D is a schematic diagram of a mapping of a transmitting end according to an embodiment of the present invention.
  • a 15G Ethernet service is mapped into three 5G time slots, and time slot mapping is performed in units of two bit blocks.
  • the three 5G time slots are slot_a, slot_b, and slot_c, respectively, and the inserted boundary bit block.
  • SAM SAM
  • Step 1 Receive the traffic bit block stream input, delete all idle bit blocks in the service flow, and then buffer the waiting mapping, as shown in FIG. 9D, the bit block stream 1 is processed as the bit block stream 2, where the bit block stream 2 and the graph
  • the bit block stream 2 in 9B can be the same, just for the sake of easy understanding, put every 2 bit blocks together;
  • Step 2 Determine whether the mapping start time slot is currently in the current state. If yes, determine whether the SAM needs to be inserted. If it needs to be inserted, insert the SAM into slot_a, slot_b, and slot_c respectively. If no insertion is required, go to step 3.
  • Step 3 Check whether the buffer has enough bit blocks of a mapping unit, where two are taken as an example, if any, go to step four; if not, go to step five;
  • Step 4 Read 2 bit blocks from the buffer, put them into the time slot corresponding to the mapping pointer, and modify the mapping pointer to point to the next time slot, and then jump to step 1 for the next round of cycles;
  • Step 5 Insert 6 idle bit blocks, and map them to 3 time slots in turn, 2 idle bit blocks in each time slot.
  • the mapping pointer points to the time slot pointed to before the insertion of the idle bit block, and then jumps. Going to step 1 for the next round of loops, as shown in Figure 9D, the bit block stream 2 is processed into 3 slotted bit block streams. If there is no bit block to be mapped after B15, the polling is mapped in three slots. Free bit block.
  • time slot mapping is performed in units of 2 bit blocks.
  • FIG. 9E is a schematic diagram of a mapping of a transmitting end according to an embodiment of the present invention.
  • a 15G Ethernet service is mapped into three 5G time slots, and time slot mapping is performed in units of one bit block.
  • the three 5G time slots are slot_a, slot_b, and slot_c, respectively, and the inserted boundary bit block is Slot aligned mark.
  • the IPG idle bit block deletion process is not performed when the Ethernet service is input, and the idle adjustment process is performed during the mapping. The purpose of the idle adjustment is to make the number of consecutive idles an integer multiple of the number of slots, and delete and insert at the same time. The amount of free space should be balanced.
  • Step 1 Receive the traffic bit block stream input, do not delete the IPG idle bit block in the service flow, and directly buffer the waiting mapping, as shown in the bit block stream 1 in FIG. 9E;
  • Step 2 Determine whether the mapping start time slot is currently in the current position. If yes, determine whether the slot align mark needs to be inserted. If it needs to be inserted, insert slot align mark for slot_a, slot_b, slot_c respectively, if not, then go to step 3;
  • Step 3 The buffer takes out a block to be mapped. If the block to be mapped is a non-idle block and the previous block is also a non-idle block, then step 6 is performed if the block to be mapped is not idle. a bit block, and the previous mapping bit block is an idle bit block, then skip to step 5, if the to-be-mapped bit block is an idle bit block, go to step 4;
  • Step 4 Determine whether the current idle bit block needs to be deleted. If the inserted valid idle bit block count is greater than zero, delete the idle bit block, decrement the inserted valid idle bit block count by one, and skip to step one for the next round. If the inserted valid idle bit block count is equal to zero, the consecutive mapped idle bit block count is incremented by one, the free bit block to be mapped is mapped to the time slot pointed by the mapping pointer, and the mapping pointer is modified to point to the next time slot, and then to step one Carry out the next cycle;
  • Step 5 determining whether the continuous mapping idle bit block count is an integer multiple of 3, if yes, mapping the to-be-mapped bit block to the time slot pointed by the mapping pointer, and modifying the mapping pointer to point to the next time slot, and then proceeding to step one
  • One round of looping otherwise inserting one or more idle bit blocks to map the to-be-mapped bit block to the corresponding time slot, so that the number of consecutive idle bit blocks is an integer multiple of 3, and the inserted effective idle is updated according to the number of inserted idle bit blocks.
  • the number of bit block counts as shown in FIG. 9E, there is only one free bit block after the B8 bit block, so it is necessary to insert 2 free bit blocks, then map B9, and then go to step 1 for the next round of loops;
  • step 6 the bit block to be mapped is mapped to the time slot pointed by the mapping pointer, and the mapping pointer is modified to point to the next time slot, and then to the next cycle in step one.
  • the insertion manner of the idle bit block only gives several easy implementation manners.
  • the time is counted.
  • the number of idle bit blocks in the slot block flow, before the next insertion of the boundary block, as long as the number of free blocks in each bit slot stream is the same, that is, the non-idle block in each slot block stream The number is also the same.
  • the demapping at the receiving end all the free bit blocks can be deleted, and the boundary bit block is used to perform the alignment operation on each time slot bit block stream, and then the mapping rule corresponding to the non-free bit block of the transmitting end is used to perform the demapping rule. Demap, recovering the bit block stream to be received.
  • an independent slot rate matching can be performed.
  • an embodiment of the present invention provides a slot rate matching method.
  • Step 1001 Obtain a first slot bit block stream, where the first slot bit block stream includes a first boundary bit block and a second boundary bit block, and the first boundary bit block and the second boundary bit block Including N first bit blocks, the first bit block is a non-idle bit block, and N is an integer greater than or equal to 1;
  • Step 1002 Add or delete an idle bit block between the first boundary bit block and the second boundary bit block to obtain a rate-matched first slot bit block stream.
  • Step 1003 Send the rate-adjusted first slot bit block stream by using a second time slot of the second physical interface.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • a time slot rate matching circuit diagram is provided in the embodiment of the present invention, including a first in first out buffer (FIFO) 1011, a FIFO water level detector 1012, a FIFO write controller 1013, and a FIFO read controller 1014.
  • FIFO first in first out buffer
  • Bit block stream transmitter 1015 idle bit block detector 1016.
  • the input time slot bit block stream is divided into two paths, one way to the idle detector 1016, one way to the FIFO 1011, and if the FIFO water level detector 1012 detects that the water level line of the FIFO is higher than the water line, the FIFO write controller 1013 is notified.
  • the FIFO write controller 1013 masks the writing of the idle bit block according to the detection of the idle bit block detector 1016, that is, deletes the idle bit block; if the FIFO water level detector 1012 detects that the water level line of the FIFO is lower than the water line, the FIFO reading is notified.
  • the controller 1014, the FIFO read controller 1014 masks the reading of the FIFO bit block, and the bit block stream transmitter 1015 outputs the free bit block.
  • Slot rate adaptation usually exists between the ingress interface and the switching network or between the switching network and the outgoing interface, or between two functional modules with different rates. Each time slot can be processed independently. As shown in FIG. 10B, there is an asynchronous buffer, that is, a FIFO, which determines whether it is necessary to delete an idle bit block or insert an idle bit block according to the upper and lower lines of the buffer.
  • a FIFO asynchronous buffer
  • an independent time slot exchange can be performed.
  • the embodiment of the present invention provides a schematic diagram of a time slot exchange method.
  • Step 1101 Obtain a first time slot bit block stream by using a first time slot of the first physical interface, where the first time slot bit block stream includes a first boundary bit block and a second boundary bit block, where the first boundary bit N first first bit blocks are included between the block and the second boundary bit block, the first bit block is a non-idle bit block, and N is an integer greater than or equal to 1;
  • Step 1102 Switch the first slot bit block stream to a second slot of the second physical interface.
  • Step 1103 Send the first slotted bitstream to the second slot of the second physical interface.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the sending, by the second time slot of the second physical interface, the first time slot bit block stream specifically includes: adding or deleting between a first boundary bit block and a second boundary bit block.
  • the idle bit block obtains the rate-adjusted first slot bit block stream; and the rate-matched first slot bit block stream is sent through the second slot of the second physical interface.
  • the switching the first time slot bit block stream to the second time slot of the second physical interface specifically includes: according to the first time slot of the first interface physical interface and the second interface physical Corresponding relationship of the second time slot of the interface, the first time slot bit block stream is switched to the second time slot of the second interface physical interface.
  • time slot exchange The purpose of the time slot exchange is that the time slot bit block stream can be switched from one time slot of the physical interface to one time slot of the physical interface in a slot unit, and the exchange relationship can be implemented according to the pre-configured correspondence relationship. It can be temporarily configured through the time slot allocation table.
  • time slot switching can be based on circuit switching, SDH/OTN TDM switching, packet cell switching, and the like.
  • each received or mapped slotted bitstream is used as one input
  • each transmitted slotted bitstream is used as one output
  • the input and output are one-to-one correspondence
  • non-blocking switching is implemented by the NxN full space division cross circuit.
  • N is the number of input and output lines.
  • the switching path can be shared by space division plus time division multiplexing, and each bit block in the slotted bit block stream is used as a time slot switching unit, corresponding to one time of the SDH/OTN TDM switching network.
  • a slot such that a block of bits in a slotted bitstream can be switched from one interface to another.
  • the slotted bit block stream may be segmented by the cell in the order of reception, and sequenced, sent to the cell switching network for exchange, and the cell encapsulation is stripped after the exchange is completed, and according to the number Arrange sequentially to recover the original slotted bitstream.
  • an embodiment of the present invention provides a schematic diagram of demapping at a receiving end, including:
  • Step 1201 Obtain at least two time slot bit block streams, where the at least two time slot bit block streams correspond to at least two time slots on at least one physical interface, and different time slot bit block streams correspond to different time slots.
  • the at least two time slot bit block streams include a first time slot bit block stream and a second time slot bit block stream, the first time slot bit block stream including a first boundary bit block and a second boundary bit block,
  • the second slotted bit block stream includes a third boundary bit block and a fourth boundary bit block, the first boundary bit block and the third boundary bit block, the second boundary bit block and the fourth
  • the first boundary bit block and the second boundary bit block include N first bit blocks
  • the third boundary bit block and the fourth boundary bit block include N a first block of bits, the first block of bits being a non-idle block of bits;
  • Step 1202 Delete an idle bit block between the first boundary bit block and the second boundary bit block, and delete an idle bit block between the third boundary bit block and the fourth boundary bit block.
  • Step 1203 The first slotted bit block after the idle bit block is deleted according to the first boundary bit block and the third boundary bit block, and the second boundary bit block and the fourth boundary bit block. Aligning the stream and the second slot bit block stream after the idle bit block is deleted;
  • Step 1204 Demap the aligned first slotted bit block stream and the second slotted bitstream stream into a first to-be-received blockstream.
  • the number of non-idle bit blocks between the first boundary bit block and the second boundary bit block received by the receiving end device is equal to the number of non-idle bit blocks between the third boundary bit block and the fourth boundary bit block, and the receiving end device may After all the free bit blocks are deleted, the boundary bit blocks are used for alignment, thereby recovering the bit block stream to be received.
  • the demapping after the alignment can be implemented by using the demapping rule corresponding to the non-idle bit block mapping rule of the transmitting end, and details are not described herein.
  • step 1201 may also be to obtain at least two time slot bit block streams, where the at least two time slot bit block streams correspond to at least two time slots on at least one physical interface, at different times
  • the slot bit block stream corresponds to different time slots
  • different time slot bit block streams correspond to different time slots
  • the at least two time slot bit block streams include corresponding boundary bit blocks, between two sets of corresponding boundary bit blocks.
  • the number of non-idle bit blocks included in each slotted bitstream is the same.
  • step 1202 may also be to delete the free bit blocks contained in the bit slot stream of each slot.
  • step 1203 may also be to align the time slot block flows after the free bit block is deleted according to the corresponding boundary bit block.
  • step 1204 may also be to demap the aligned time slot bit block streams into a first to-be-received bit block stream.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the method further includes: performing bit block decoding on the first to-be-received bit block stream to obtain a first to-be-received service.
  • the method further includes: performing IPG recovery on the first to-be-received bit block stream to obtain a first to-be-received service.
  • obtaining at least two time slot bit block streams specifically includes: obtaining the first time slot bit block stream by using a first time slot of the first physical interface, and adopting a second time of the first physical interface Obtaining the second time slot bit block stream; or obtaining the first time slot bit block stream by using a first time slot of the first physical interface, and obtaining the second time by using a second time slot of the second physical interface Gap block flow.
  • the receiving end demapping can delete all the idle bit blocks in the bit block stream of each time slot, and then perform alignment processing on the plurality of time slot bit block streams according to the boundary bit block, thereby recovering the bit block stream to be received and recovering.
  • the bit block stream to be received can be post-processed and then output through the user interface.
  • IPG recovery can be performed.
  • M1/M2 decoding can be performed to output the original service stream.
  • FIG. 13 is a schematic diagram of a bit block stream processing apparatus 1300 according to an embodiment of the present application.
  • the bit block stream processing apparatus 1300 can be implemented in the client adaptation unit in FIG. 3, FIG. 5 or FIG. It can be implemented in the network adaptation unit or the C2C adaptation unit in FIG. 3, FIG. 5 or FIG. 7, and can also be implemented in other network devices or network modules.
  • the bit block stream processing apparatus 1300 includes:
  • a receiver 1301, configured to obtain a first to-be-processed bit block stream
  • the processor 1302 is configured to map the first to-be-processed bit block stream into at least two time slot bit block streams, where the at least two time slot bit block streams correspond to at least two time slots on at least one physical interface
  • the different time slot bit block streams correspond to different time slots
  • the at least two time slot bit block streams include a first time slot bit block stream and a second time slot bit block stream, the first time slot bit block stream a first boundary bit block and a second boundary bit block, the second slot bit block stream including a third boundary bit block and a fourth boundary bit block, the first boundary bit block and the third boundary bit block
  • the second boundary bit block and the fourth boundary bit block are corresponding
  • the first boundary bit block and the second boundary bit block include N first bit blocks, the third boundary bit N first first bit blocks are included between the block and the fourth boundary bit block, the first bit block is a non-idle bit block, and N is an integer greater than or equal to 1.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the method further includes: a transmitter, configured to send, by using a first time slot of the first physical interface, a first time slot bit block stream, where the second time slot is sent by the second time slot of the first physical interface a time slot bit block stream; or a transmitter, configured to send a first time slot bit block stream through a first time slot of the first physical interface, and send a second time slot bit block stream through a second time slot of the second physical interface.
  • the receiver is specifically configured to obtain the first pending service; and the first pending service
  • the bit block coding is performed to obtain a first to-be-processed bit block stream.
  • the transmitter is specifically configured to add or delete an idle bit block between the first boundary bit block and the second boundary bit block, and obtain a rate-matched first time slot bit block stream;
  • the first time slot of a physical interface transmits a rate-adapted first time slot bit block stream.
  • the transmitter is specifically configured to add or delete an idle bit block between the third boundary bit block and the fourth boundary bit block, and obtain a rate-matched second slot bit block stream;
  • the second time slot of a physical interface sends the rate-adapted second time slot bit block stream, or the rate-adapted second time slot bit block stream is sent through the second time slot of the second physical interface.
  • the method further includes: a switch, configured to exchange the first slotted bitstream of the first slot of the first physical interface to the third slot of the third physical interface.
  • the processor is specifically configured to map the first to-be-processed bit block stream into at least two slot-bit block streams in a round-robin scheduling manner.
  • FIG. 14 is a schematic diagram of a bit block stream rate adaptation apparatus 1400 according to an embodiment of the present application.
  • the bit block stream rate adaptation apparatus 1400 may be suitable for customers in FIG. 3, FIG. 5 or FIG.
  • the implementation in the configuration unit can be implemented in the network adaptation unit or the C2C adaptation unit in FIG. 3, FIG. 5 or FIG. 7, and can also be implemented in other network devices or network modules.
  • the bit block flow rate adaptation device 1400 includes:
  • the receiver 1401 is configured to obtain a first slot bit block stream, where the first slot bit block stream includes a first boundary bit block and a second boundary bit block, and the first boundary bit block and the second boundary bit block include N a first bit block, the first bit block is a non-idle bit block, and N is an integer greater than or equal to 1;
  • a rate adapter 1402 configured to add or delete an idle bit block between the first boundary bit block and the second boundary bit block, to obtain a rate-adjusted first slot bit block stream;
  • the transmitter 1403 is configured to send the rate-adjusted first slot bit block stream by using the second slot of the second physical interface.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • FIG. 15 is a schematic diagram of a bit block stream switching apparatus 1500 according to an embodiment of the present application.
  • the bit block stream switching apparatus 1500 can be implemented in the switching unit in FIG. 3, FIG. 5 or FIG. It can be implemented in other network devices or network modules, and the bit block stream switching device 1500 includes:
  • the receiver 1501 is configured to obtain, by using a first time slot of the first physical interface, a first time slot bit block stream, where the first time slot bit block stream includes a first boundary bit block and a second boundary bit block, and the first boundary bit block And the first boundary block includes N first bit blocks, the first bit block is a non-idle bit block, and N is an integer greater than or equal to 1;
  • the switch 1502 is configured to exchange the first slot bit block stream to the second slot of the second physical interface
  • the transmitter 1503 is configured to send, by using a second time slot of the second physical interface, a first time slot bit block stream.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the transmitter is specifically configured to add or delete an idle bit block between the first boundary bit block and the second boundary bit block, and obtain a rate-matched first time slot bit block stream;
  • the second time slot of the two physical interfaces sends the rate-adapted first time slot bit block stream.
  • the switch is specifically configured to use the first time slot and the second time according to the physical interface of the first interface Corresponding relationship of the second time slot of the interface physical interface, the first time slot bit block stream is switched to the second time slot of the second interface physical interface.
  • FIG. 16 is a schematic diagram of a bit block stream processing apparatus 1600 according to an embodiment of the present application.
  • the bit block stream processing apparatus 1600 can be implemented in the client adaptation unit in FIG. 3, FIG. 5 or FIG. It can be implemented in the network adaptation unit or the C2C adaptation unit in FIG. 3, FIG. 5 or FIG. 7, and can also be implemented in other network devices or network modules.
  • the bit block stream processing apparatus 1600 includes:
  • a receiver configured to obtain at least two time slot bit block streams, where the at least two time slot bit block streams correspond to at least two time slots on at least one physical interface, and different time slot bit block streams correspond to different times
  • the at least two time slot bit block streams include a first time slot bit block stream and a second time slot bit block stream, the first time slot bit block stream including a first boundary bit block and a second boundary bit block
  • the second slot bit block stream includes a third boundary bit block and a fourth boundary bit block, the first boundary bit block and the third boundary bit block corresponding to the second boundary bit block and the Corresponding to the fourth boundary bit block, the first boundary bit block and the second boundary bit block include N first bit blocks, and the third boundary bit block and the fourth boundary bit block are included N first bit blocks, the first bit block being a non-idle bit block;
  • a processor configured to delete an idle bit block between the first boundary bit block and the second boundary bit block, and delete an idle bit block between the third boundary bit block and the fourth boundary bit block; according to the first boundary bit block and a third boundary bit block, and a second boundary bit block and a fourth boundary bit block, aligning the first slot bit block stream after the idle bit block is deleted and the second slot bit block stream after the idle bit block is deleted; The aligned first slotted bit block stream and the second slotted bitstream stream are demapped into a first to-be-received blockstream.
  • the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M1, M2 Is a positive integer, M2>M1.
  • the method further includes: a decoder, configured to perform bit block decoding on the first to-be-received bit block stream to obtain a first to-be-received service.
  • the method further includes: an IPG recovery unit, configured to perform IPG recovery on the first to-be-received bit block stream to obtain a first to-be-received service.
  • an IPG recovery unit configured to perform IPG recovery on the first to-be-received bit block stream to obtain a first to-be-received service.
  • the receiver is specifically configured to obtain a first time slot bit block stream by using a first time slot of the first physical interface, and obtain a second time slot bit block stream by using a second time slot of the first physical interface. Or obtaining a first time slot bit block stream through a first time slot of the first physical interface, and obtaining a second time slot bit block stream by using a second time slot of the second physical interface.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the steps of the method disclosed in the embodiments of the present application may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software units in the processor.
  • the software unit can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.
  • the size of the serial numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not be taken to the embodiments of the present invention.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of cells is only a logical function division.
  • multiple units or components may be combined or integrated. Go to another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • a computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, computer instructions can be wired from a website site, computer, server or data center (eg Coax, fiber, digital subscriber line (DSL) or wireless (eg, infrared, wireless, microwave, etc.) is transmitted to another website, computer, server, or data center.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • Useful media can be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)).

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Abstract

本发明实施例提供一种比特块流处理方法，包括：获得第一待处理比特块流，将第一待处理比特块流映射为至少两个时隙比特块流，至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，第一时隙比特块流包括第一边界比特块和第二边界比特块，第二时隙比特块流包括第三边界比特块和第四边界比特块，第一边界比特块和第三边界比特块对应，第二边界比特块和第四边界比特块对应，第一边界比特块和第二边界比特块之间包括N个第一比特块，第三边界比特块和第四边界比特块之间包括N个第一比特块，第一比特块为非空闲比特块，N为大于等于1的整数。经过比特块流处理的时隙比特块流可以独立进行时隙速率匹配和时隙交换。

Description

一种比特块流处理、速率匹配、交换的方法和装置 技术领域
本申请涉及通信技术领域，特别涉及一种比特块流处理、速率匹配、交换的方法和装置
背景技术
电气及电子工程师学会(Institute of Electrical and Electronics Engineers,IEEE)定义的基于802.3的以太网作为业务的接口，应用在各种场合并取得了巨大的成功应用，但是随着技术越发展，带宽颗粒差异越大，越容易出现与实际应用需求期望的过大偏差。主流的应用需求带宽可能不属于任意一种以太网标准速率，例如50Gbps如果用100GE来传输存在资源浪费，而200Gbps当前没有对应的以太网标准颗粒可以承载。人们期望有一种灵活带宽的端口(虚拟连接)能够共享一个或者若干个以太网物理接口，例如2个40GE端口和2个10GE端口共享一个100G物理接口。灵活以太网(Flexible Ethernet，FlexE)的概念应运而生，具体是通过将几个以太网物理层(Physical layer,PHY)装置绑定成一个FlexE组，以及物理层通道化(子速率)等功能，满足灵活带宽的端口应用需求。因此FlexE提供的介质访问控制(Media Access Control,MAC)速率可以大于单条PHY的速率(通过绑定实现)，也可以小于单条PHY的速率(通过通道化实现)。
FlexE对物理接口传输构建固定帧格式，并进行时分复用(time division multiplexing,TDM)的时隙划分。FlexE的TDM时隙划分基于66B比特块，或者称为比特块，时隙间插通过66B比特块间插实现，FlexE标准针对100G物理接口划分20个时隙，每个时隙5G带宽。时隙间插周期为20个比特块，时隙定位通过开销比特块实现，每1023个时隙循环周期(即1023x20比特块)插入一个定位开销。FlexE客户信号带宽如为5G，则正好占用一个时隙，如果是5*n G则占用n个时隙。
一个FlexE客户信号的业务会被映射到物理接口的一个或多个时隙中进行传输，多个时隙中的传输的比特块流无法单独进行速率适配或交换。
发明内容
本申请实施例提供一种比特块流处理、速率匹配、交换的方法和装置，用以解决在单个时隙的比特块流无法单独进行速率适配或交换的问题。
第一方面，一种比特块流处理方法，包括：发送端设备获得第一待处理比特块流；发送端设备将第一待处理比特块流映射为至少两个时隙比特块流，至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，第一时隙比特块流包括第一边界比特块和第二边界比特块，第二时隙比特块流包括第三边界比特块和第四边界比特块，第一边界比特块和第三边界比特块对应，第二边界比特块和第四边界比特块对应，第一边界比特块和第二边界比特块之间包括N个第一比特块，第三边界比特块和第四边界比特块之间包括N个第一比特块，第一比特块为非空闲比特 块，N为大于等于1的整数。
第一边界比特块和第二边界比特块之间非空闲比特块的数量和第三边界比特块和第四边界比特块之间非空闲比特块的数量相等，因此在传输过程中，单个时隙比特块流可以单独进行时隙速率匹配和时隙交换，不同的时隙比特块流也可以通过不同的传输路径或不同的中间节点传输到接收端设备，接收端设备可以在删除所有的空闲比特块后利用边界比特块进行对齐，从而恢复出待接收比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，还包括：通过第一物理接口的第一时隙发送第一时隙比特块流，通过第一物理接口的第二时隙发送第二时隙比特块流；或者通过第一物理接口的第一时隙发送第一时隙比特块流，通过第二物理接口的第二时隙发送第二时隙比特块流。
在一种可能的设计中，获得第一待处理比特块流具体包括：获得第一待处理业务；对第一待处理业务进行比特块编码，获得第一待处理比特块流。
在一种可能的设计中，通过第一物理接口的第一时隙发送第一时隙比特块流具体包括：增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第一物理接口的第一时隙发送速率适配后的第一时隙比特块流。
在一种可能的设计中，通过第一物理接口的第二时隙发送第二时隙比特块流或者通过第二物理接口的第二时隙发送第二时隙比特块流具体包括：增加或删除第三边界比特块和第四边界比特块之间的空闲比特块，获得速率适配后的第二时隙比特块流；通过第一物理接口的第二时隙发送速率适配后的第二时隙比特块流，或者通过第二物理接口的第二时隙发送速率适配后的第二时隙比特块流。
在一种可能的设计中，还包括：将第一物理接口的第一时隙的第一时隙比特块流交换到第三物理接口的第三时隙。
在一种可能的设计中，将第一待处理比特块流映射为至少两个时隙比特块流具体包括：以轮循调度的方式将第一待处理比特块流映射为至少两个时隙比特块流。
第二方面，一种比特块流速率适配方法，包括：获得第一时隙比特块流，第一时隙比特块流包括第一边界比特块和第二边界比特块，第一边界比特块和第二边界比特块之间包括N个第一比特块，第一比特块为非空闲比特块,N为大于等于1的整数；增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第二物理接口的第二时隙发送速率适配后的第一时隙比特块流。
单个时隙比特块流包括边界比特块，边界比特块之间包括非空闲比特块，从而可以在边界比特块之间增加或删除空闲比特块，接收端设备可以在删除所有的空闲比特块后利用边界比特块进行对齐，从而恢复出待接收比特块流
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
第三方面，一种比特块流交换方法，包括：通过第一物理接口的第一时隙获得第 一时隙比特块流，第一时隙比特块流包括第一边界比特块和第二边界比特块，第一边界比特块和第二边界比特块之间包括N个第一比特块，第一比特块为非空闲比特块,N为大于等于1的整数；将第一时隙比特块流交换到第二物理接口的第二时隙；通过第二物理接口的第二时隙发送第一时隙比特块流。
单个时隙比特块流包括边界比特块，边界比特块之间包括非空闲比特块，从而对该单个时隙比特块流进行单独的时隙交换，接收端设备可以在删除所有的空闲比特块后利用边界比特块进行对齐，从而恢复出待接收比特块流
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，通过第二物理接口的第二时隙发送第一时隙比特块流具体包括：增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第二物理接口的第二时隙发送速率适配后的第一时隙比特块流。
在一种可能的设计中，将第一时隙比特块流交换到第二物理接口的第二时隙具体包括：根据第一接口物理接口的第一时隙和第二接口物理接口的第二时隙的对应关系，将第一时隙比特块流交换到第二接口物理接口的第二时隙。
第四方面，一种比特块流处理方法，包括：接收端设备获得至少两个时隙比特块流，至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，第一时隙比特块流包括第一边界比特块和第二边界比特块，第二时隙比特块流包括第三边界比特块和第四边界比特块，第一边界比特块和第三边界比特块对应，第二边界比特块和第四边界比特块对应，第一边界比特块和第二边界比特块之间包括N个第一比特块，第三边界比特块和第四边界比特块之间包括N个第一比特块，第一比特块为非空闲比特块；接收端设备删除第一边界比特块和第二边界比特块之间的空闲比特块，删除第三边界比特块和第四边界比特块之间的空闲比特块；根据第一边界比特块和第三边界比特块，以及第二边界比特块和第四边界比特块，对空闲比特块删除后的第一时隙比特块流和空闲比特块删除后的第二时隙比特块流进行对齐；将对齐后的第一时隙比特块流和第二时隙比特块流解映射为第一待接收比特块流。
接收端设备接收的第一边界比特块和第二边界比特块之间非空闲比特块的数量和第三边界比特块和第四边界比特块之间非空闲比特块的数量相等，接收端设备可以在删除所有的空闲比特块后利用边界比特块进行对齐，从而恢复出待接收比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，还包括：对第一待接收比特块流进行比特块解码，获得第一待接收业务。
在一种可能的设计中，还包括：对第一待接收比特块流进行IPG恢复，获得第一待接收业务。
在一种可能的设计中，获得至少两个时隙比特块流具体包括：通过第一物理接口的第一时隙获得第一时隙比特块流，通过第一物理接口的第二时隙获得第二时隙比特 块流；或者通过第一物理接口的第一时隙获得第一时隙比特块流，通过第二物理接口的第二时隙获得第二时隙比特块流。
第五方面，一种比特块流处理装置，包括接收器，处理器，比特块流处理装置用于完成上述第一方面或第一方面的任意可能的实现方式中的方法。
第六方面，一种比特块流速率适配装置，包括接收器，速率适配器和发送器，比特块流速率适配装置用于完成上述第二方面或第二方面的任意可能的实现方式中的方法。
第七方面，一种比特块流交换装置，包括接收器，交换器和发送器，比特块流交换装置用于完成上述第三方面或第三方面的任意可能的实现方式中的方法。
第八方面，一种比特块流处理装置，包括接收器，处理器，比特块流处理装置用于完成上述第四方面或第四方面的任意可能的实现方式中的方法。
附图说明
图1A为本申请实施例中64/66编码的码型定义示意图；
图1B为本申请实施例中空闲块的码型定义示意图；
图2A为本申请实施例中PE设备的结构示意图；
图2B为本申请实施例中P设备的结构示意图；
图3为本申请实施例提供的一种X-E时隙交换网络的结构示意图；
图4为本发明实施例提供的一种X-E时隙交换方法流程示意图；
图5为本申请实施例提供的一种框式节点设备的结构示意图；
图6为本发明实施例提供的一种X-E时隙交换方法流程示意图；
图7为本申请实施例提供的一种盒式节点设备的结构示意图；
图8为本发明实施例提供的一种X-E时隙交换方法流程示意图；
图9A为本发明实施例提供的一种发射端映射的流程示意图；
图9B为本发明实施例提供的一种发射端映射的示意图；
图9C为本发明实施例提供的另一种发射端映射的示意图；
图9D为本发明实施例提供的再一种发射端映射的示意图；
图9E为本发明实施例提供的再一种发射端映射的示意图；
图10A为本发明实施例提供的一种时隙速率匹配方法的流程示意图；
图10B为本发明实施例提供的一种时隙速率匹配电路结构图；
图11为本发明实施例提供的一种时隙交换方法的流程示意图；
图12为本发明实施例提供的一种接收端解映射的流程示意图；
图13为本申请实施例提供的一种比特块流处理装置的结构示意图；
图14为本申请实施例提供的一种比特块流速率适配装置的结构示意图；
图15为本申请实施例提供的一种比特块流交换装置的结构示意图；
图16为本申请实施例提供的一种比特块流处理装置的结构示意图。
具体实施方式
在以太网中，以太网端口通常作为面向数据的逻辑上的概念出现，称为逻辑端口 或简称为端口，以太网物理接口则为硬件上的概念出现，称为物理接口或简称为接口。通常，用一个MAC地址标记一个以太网端口。传统地，以太网端口的速率的确定以以太网物理接口的速率为基础。一般情况下，一个以太网端口最大带宽对应一个以太网物理接口的带宽，例如10Mbps、100Mbps、1000Mbps(1Gbps)、10Gbps、40Gbps、100Gbps以及400Gbps等以太网物理接口。
以太网在过去的相当一段时间内获得了广泛的应用和长足的发展。以太网端口速率以10倍提升，从10Mbps向100Mbps、1000Mbps(1Gbps)、10Gbps、40Gbps、100Gbps、400Gbps不断演进发展。技术越发展，带宽颗粒差异越大，越容易出现与实际应用需求期望的偏差。主流应用需求的带宽增长并不呈现这样的10倍增长特征，例如50Gbps、75Gbps、200Gbps等。业界希望提供对50Gbps、60Gbps、75Gbps、200Gbps和150Gbps等带宽的以太网端口(虚拟连接)的支持。
一方面，更进一步地，希望能够提供一些灵活带宽的端口，这些端口可以共同使用一个或者若干个以太网物理接口，例如2个40GE端口和2个10GE端口共同使用一个100G物理接口；并能够随着需求的变化做出灵活的速率调整，例如从200Gbps调整为330Gbps，或者50Gbps调整为20Gbps，以提高端口使用效率或者延长其使用生命周期。对于固定速率的物理链路，可以将其级联捆绑，以支持逻辑端口速率的堆叠增加(例如，将2个100GE物理接口堆叠级联捆绑以支持200GE逻辑端口)。另一方面，能够将物理接口灵活堆叠所得到的带宽资源池化，将其带宽按照颗粒(例如，5G为一个颗粒)分配给特定的以太网逻辑端口，实现若干以太网虚拟连接对堆叠级联的物理链路组的高效共享。
由此，FlexE的概念应运而生，灵活以太网又称为灵活虚拟以太网。FlexE支持针对以太网业务的子速率、通道化、反向复用等功能。例如，针对以太网业务的子速率应用场景，FlexE能够支持将250G的以太网业务(MAC码流)采用3路现有的100GE的物理接口进行传送。针对以太网业务的反向复用场景，FlexE能够支持将200G的以太网业务采用2路现有的100GE的物理媒质相关子层(Physical Medium Dependent，PMD)进行传送。针对以太网业务的通道化场景，FlexE能够支持若干个逻辑端口共同使用一个或者多个物理接口，能够支持将多路低速率的以太网业务复用到高速率的灵活以太网的中。
由于接入网和城域网中大量采用以太网作为业务接口，这种基于以太网技术的业务流量汇聚功能的FlexE技术能够实现和底层业务网络的以太网接口的无缝连接。这些FlexE的子速率、通道化和反向复用功能的引入，极大的扩展了以太网的应用场合，增强了以太网应用的灵活性，并使得以太网技术逐渐向传送网领域渗透。
FlexE为以太网物理链路的虚拟化，提供了一个可行的演进方向。灵活以太网需要在级联的一组物理接口上支持若干个虚拟的以太网数据连接。例如，4个100GE物理接口级联捆绑，支持若干逻辑端口。若干逻辑端口中一部分逻辑端口的带宽减小，则另外一部分逻辑端口的带宽增大，并且带宽减小的总量和带宽增大的总量相等，若干逻辑端口的带宽快速弹性调整，共同使用4个100GE物理接口。
FlexE借鉴同步数字体系(Synchronous digital hierarchy,SDH)/光传输网络(Optical transfer network，OTN)技术，对物理接口传输构建固定帧格式，并进 行TDM的时隙划分。与SDH/OTN不同的是，FlexE的TDM时隙划分粒度是66比特，正好可以对应承载一个64B/66B比特块。一个FlexE帧包含8行，每行第一个66b块位置为FlexE开销区域，开销区域后为进行时隙划分的净荷区域，以66比特为粒度，对应20x1023个66比特承载空间，100GE接口的带宽划分20个时隙，每个时隙的带宽约为5Gbps。FlexE通过交织复用的方式在单个物理接口上实现了多个传输通道，即实现了多个时隙。
若干个物理接口可以级联捆绑，该若干个物理接口的全部的时隙可以组合承载一个以太网逻辑端口。例如10GE需要两个时隙，25GE需要5个时隙等。逻辑端口上可见的仍为顺序传输的66b编比特块，每个逻辑端口对应一个MAC，传输相应的以太网报文，对报文的起始结束和对空闲填充的识别与传统以太网相同。
FlexE只是一种接口技术，相关的交换技术依旧是基于以太网包进行。但是随着第五代通信技术(即5G)以及物联网的广泛研究，确定性低延时、可靠性、安全隔离技术已经成为急需攻克的重要课题。发明人定义了一种基于物理接口硬管道的交换技术，X-Ethernet(简称X-E)是一种基于Ethernet物理层的Bit Block交换技术，比如64/66Bit Block，具备确定性超低时延的技术特征。
本申请实施例中提到的比特块可以为M1/M2比特块,或者叫做M1B/M2B比特块，M1/M2代表一种编码方式，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在Ethernet物理层链路传递的就是这种M1/M2比特块流，比如1G Ethernet采用8/10Bit编码，1GE物理层链路传递的就是8/10比特块流；10GE/40GE/100GE采用64/66Bit编码，10GE/40GE/100GE物理层链路传递的就是64/66比特块流。未来随着Ethernet技术发展，还也会出现其他编码方式，比如可能出现128/130Bit编码、256/258Bit编码等。为了描述方便，本申请实施例中统一用M1/M2比特块流表示。
对于M1/M2比特块流，存在不同类型的比特块并且在标准中明确规范，下面以64/66Bit编码的码型定义为例进行说明，如图1A所示，其中首部的2个Bit“10”或“01”是64/66比特块同步头比特，后64Bit用于承载净荷数据或协议。图1A中包括16种码型定义，每一行代表一种比特块的码型定义，其中，D0-D7代表数据字节，C0-C7代表控制字节，S0代表开始字节，T0-T7代表结束字节，第2行对应空闲比特块(空闲Block)的码型定义，空闲比特块可以用/I/来表示，具体如图1B所示。第7行对应开始块的码型定义，开始块可以用/S/来表示，第9-16行分别对应8种结束块的码型定义，8种结束块可以统一用/T/来表示。
本申请实施例提到的接口可以是上面提到的以太网物理接口，也可以是其它物理接口，例如可以是光传送网(Optical Transport Network，OTN)接口、灵活光传送网Flexible OTN，FlexOTN)接口、灵活以太网FlexE接口、通用公共无线接口(Common Public Radio Interface，CPRI)、同步数字体系(Synchronous Digital Hierarchy，SDH)接口、光纤通道(Fibre Channel，FC)接口或无限带宽(InfiniBand)接口等，例如还可以是设备内部的物理接口C2C接口等。
本申请实施例提到的端口可以是上面提到的以太网端口，当然也可以是其它逻辑 业务端口，例如可以是光传送网OTN逻辑业务端口、灵活光传送网FlexOTN逻辑业务端口、灵活以太网FlexE逻辑业务端口、通用公共无线逻辑业务端口CPRI、同步数字体系SDH逻辑业务端口、光纤通道FC逻辑业务端口或无限带宽InfiniBand逻辑业务端口等。
一个flexE client的业务被映射到一个或多个物理接口的多个时隙中进行传输时，各个时隙中传输的比特块流无法单独进行速率适配或交换，本发明实施例主要提供四个逻辑功能，分别是发送端映射、时隙速率适配，时隙交换以及接收端解映射。通过发送端的映射，物理接口的时隙可以进行独立的时隙速率适配以及独立的时隙交换，并且在接收端可以恢复出业务。如果一个业务占用多个时隙，每个时隙独立速率适配、交换，不同的时隙的传输延时可能不同，不同时隙的空闲比特块的插入或删除的位置可能不同，通过本发明实施例提供的四个逻辑功能，可以在每个时隙单独进行时隙速率适配或时隙交换，并且可以在接收端消除延时不同和位置不同的差异，正确恢复出待接收比特块流。
本发明实施例可以采用如图2A和图2B所示的设备传递比特块流，具体的，如图2A和图2B所示，分别为运营商边缘(Provider Edge,PE)设备和运营商(Provider,P)设备。其中，PE设备代表边缘设备，其一端与用户设备连接，接口为用户网络接口接口(User network interface，UNI)，另一端与网络设备连接，接口为网间网接口(Network to Network interface，NNI)，重点能力是汇聚、封装/解封装，PE设备和PE设备之间的路径根据起始点不同，可以是伪线PW，也可以是隧道等，P设备代表网络设备，是网络中的核心设备，主要能力就是强大的交换能力，两端均与网络设备连接，接口为NNI。
图2A和图2B中，客户适配单元(uAdpt)代表用户侧处理单元，用于接入用户业务信号，并进行接口适配，速率适配等工作，接口适配可以包括X-E时隙映射和/或解映射，X-E时隙映射可以将一个比特块流映射为多个时隙比特块流，X-E时隙解映射可以将多个时隙比特块流解映射为一个比特块流，接口适配还可以包括码型转换等。网络适配单元(nAdpt)代表X-E技术体系的网络侧处理单元，用于将设备内业务信号发送到网络侧，并完成相应的功能处理；或者接收网络侧业务信号传递到设备内其他处理单元，X-E时隙映射和/或解映射也可以由网络适配单元来实现。L1.5switch或者X-Ethernet switch，即X-Ethernet Relay(即中间节点的转发)，体现为交换单元。
如图3所示，为本发明实施例提供的一种X-E时隙交换网络，包括节点301、节点302、节点303以及节点304共四个节点，其中节点301为源端PE设备，节点302和节点303为中间P设备，节点304为目的端PE设备，节点301从其UNI接口接收10GE业务，需要通过节点302和/或节点303将10GE业务发送到节点304，节点304将收到的10GE业务通过其UNI接口发送到客户端。
如图4所示，为本发明实施例提供的一种X-E时隙交换方法，其中对于发送端映射、时隙速率适配，时隙交换以及接收端解映射的详细实现可以参考后面的实施例，该方法应用于如图3所示的网络中，具体包括：
步骤401，节点301的客户适配单元3012进行发送端映射，将待处理比特块流 映射为第一时隙比特块流和第二时隙比特块流。
本发明实施例以将待处理比特块流映射为第一时隙比特块流和第二时隙比特块流为例进行说明，在其它设计中，也可以将待处理比特块流映射到其它个数的时隙比特块流中，本发明实施例对此不作限定。
在一种可能的设计中，发送端映射也可以由节点301的网络适配单元3014来完成，适配完成后直接通过NNI接口30151,NNI接口30152或其它接口将时隙比特块流发送出去。
本发明实施例中，第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块，N为大于等于1的整数。
步骤402，节点301的客户适配单元3012进行时隙速率适配，节点301的交换单元3013进行时隙交换，节点301的网络适配单元3014进行时隙速率适配，将第一时隙比特块流通过NNI接口30151发送到节点302，将第二时隙比特块流通过NNI接口30152发送到节点303。
通过将第一时隙比特块流通过NNI接口30151发送到节点302，将第二时隙比特块流通过NNI接口30152发送到节点303，可以实现负载均衡，当然，在一种可能的设计中，可以将第一时隙比特块流和第二时隙比特块流通过NNI接口30151的不同时隙都发送到节点302，这样要求节点302处理第一时隙比特块流和第二时隙比特块流。
步骤403，节点302通过NNI接口3021接收第一时隙比特块流，节点302的网络适配单元3022进行时隙速率适配，节点302的交换单元3023进行时隙交换，节点302的网络适配单元3024进行时隙速率适配，将第一时隙比特块流通过NNI接口3025发送到节点304。
步骤404，节点303通过NNI接口3031接收第一时隙比特块流，节点303的网络适配单元3032进行时隙速率适配，节点303的交换单元3033进行时隙交换，节点303的网络适配单元3034进行时隙速率适配，将第一时隙比特块流通过NNI接口3035发送到节点304。
步骤405，节点304通过NNI接口30411接收第一时隙比特块流，节点304通过NNI接口30412接收第二时隙比特块流，节点304的网络适配单元3042进行时隙速率适配，节点304的交换单元3043进行时隙交换，节点304的客户适配单元3044进行时隙速率适配。
步骤406，节点304的客户适配单元3044进行接收端解映射，将第一时隙比特块流和第二时隙比特块流解映射为待接收比特块流。
本发明实施例还可以采用如图5或图7所示的分组承载节点设备来处理比特块流，具体地，盒式设备的接口卡或框式设备的线卡的接口芯片实现客户适配单元或网络适配单元功能，以及X-E时隙交换单元，其次交换板也可以改造以支持X-E slot交换功能或保留原交换网设计不动。
如图5所示，为本发明实施例提供的一种框式节点设备，包括线卡501、交换平面502、交换平面503和线卡504，其中交换平面502和交换平面503可以位于不同的板卡上，也可以位于相同的板卡上，线卡501和线卡504通常位于不同的板卡中，该框式节点设备还可以包括其它板卡，本发明实施例对此不作限定。线卡线卡501、交换平面502、交换平面503和线卡504之间通过C2C接口互联，可以采用电互联，也可以采用光互联。
如图6所示，为本发明实施例提供的一种X-E时隙交换方法，其中对于发送端映射、时隙速率适配，时隙交换以及接收端解映射的详细实现可以参考后面的实施例，该方法应用于如图5所示的网络中，具体包括：
步骤601，线卡501的客户适配单元50121进行发送端映射，将待处理比特块流映射为第一时隙比特块流和第二比特块流。
步骤602，线卡501的客户适配单元50121进行时隙速率适配，线卡501的交换单元5013进行时隙交换，将第一时隙比特块流交换到线卡501的C2C适配单元50141，线卡501的C2C适配单元50141进行时隙速率适配后将第一时隙比特块流通过C2C接口50151发送到交换平面502，线卡501的交换单元5013进行时隙交换，将第二时隙比特块流交换到线卡501的C2C适配单元50142，线卡501的C2C适配单元50142进行时隙速率适配后将第一时隙比特块流通过C2C接口50152发送到交换平面503。
在一种可能的设计中,由于客户适配单元50121进行了时隙速率适配,C2C适配单元50141可以不进行时隙速率适配处理就可以送到交换平面进行时隙交换处理。
步骤603，交换平面502通过C2C接口5021接收第一时隙比特块流，交换平面502的C2C适配单元5022进行时隙速率适配，交换平面502的交换单元5023进行时隙交换，交换平面502的C2C适配单元5024进行时隙速率适配，将第一时隙比特块流通过C2C接口5025发送到线卡504。
步骤604，交换平面503通过C2C接口5031接收第一时隙比特块流，交换平面503的C2C适配单元5032进行时隙速率适配，交换平面503的交换单元5033进行时隙交换，交换平面503的C2C适配单元5034进行时隙速率适配，将第一时隙比特块流通过C2C接口5035发送到线卡504。
步骤605，线卡504通过C2C接口50411接收第一时隙比特块流，线卡504通过C2C接口50412接收第二时隙比特块流，线卡504的C2C适配单元30421和C2C适配单元30422进行时隙速率适配，线卡504的交换单元5043进行时隙交换，线卡504的客户适配单元50441进行时隙速率适配。
步骤606，线卡504的客户适配单元50441进行接收端解映射，将第一时隙比特块流和第二时隙比特块流解映射为待接收比特块流。
如图7所示，为本发明实施例提供的一种盒式节点设备，包括入接口板701、交换平面702和出接口板704，入接口板701、交换平面702和出接口板704通常位于不同的板卡中，盒式节点设备通常只有一个交换平面，且接口板不具备交换功能，本发明实施例对此不作限定。入接口板701、交换平面702和出接口板704之间通过C2C接口互联，可以采用电互联，也可以采用光互联。
如图8所示，为本发明实施例提供的一种X-E时隙交换方法，其中对于发送端映 射、时隙速率适配，时隙交换以及接收端解映射的详细实现可以参考后面的实施例，该方法应用于如图7所示的网络中，具体包括：
步骤801，入接口板701的客户适配单元70121进行发送端映射，将待处理比特块流映射为第一时隙比特块流和第二比特块流。
步骤802，入接口板701的客户适配单元70121进行时隙速率适配，入接口板701的C2C适配单元7014进行时隙速率适配后将第一时隙比特块流和第二时隙比特块流通过C2C接口5015发送到交换平面702
步骤803，交换平面702通过C2C接口7021接收第一时隙比特块流和第二时隙比特块流，交换平面702的C2C适配单元7022进行时隙速率适配，交换平面702的交换单元7023进行时隙交换，交换平面702的C2C适配单元7024进行时隙速率适配，将第一时隙比特块流和第二时隙比特块流通过C2C接口7025发送到出接口板704。
步骤805，出接口板704通过C2C接口7041接收第一时隙比特块流和第二时隙比特块流，出接口板704的C2C适配单元3042进行时隙速率适配。
步骤806，出接口板704的客户适配单元70441进行接收端解映射，将第一时隙比特块流和第二时隙比特块流解映射为待接收比特块流。
如图9A所示，本发明实施例提供一种发射端映射的示意图，包括：
步骤901，获得第一待处理比特块流；
步骤902，将所述第一待处理比特块流映射为至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。M1/M2比特块为编码比特块。
在一种可能的设计中，通过第一物理接口的第一时隙发送所述第一时隙比特块流，通过第一物理接口的第二时隙发送所述第二时隙比特块流；或者通过第一物理接口的第一时隙发送所述第一时隙比特块流，通过第二物理接口的第二时隙发送所述第二时隙比特块流。
在一种可能的设计中，所述获得第一待处理比特块流具体包括：获得第一待处理业务；对所述第一待处理业务进行比特块编码，获得第一待处理比特块流。即对于未进行比特块编码的业务流，需要进行比特块编码。
在一种可能的设计中，通过第一物理接口的第一时隙发送所述第一时隙比特块流具体包括：增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第一物理接口的第一时隙发送所述速率适配后的 第一时隙比特块流。
在一种可能的设计中，通过第一物理接口的第二时隙发送所述第二时隙比特块流或者通过第二物理接口的第二时隙发送所述第二时隙比特块流具体包括：增加或删除第三边界比特块和第四边界比特块之间的空闲比特块，获得速率适配后的第二时隙比特块流；
通过第一物理接口的第二时隙发送所述速率适配后的第二时隙比特块流，或者通过第二物理接口的第二时隙发送所述速率适配后的第二时隙比特块流。
在一种可能的设计中，还包括：将第一物理接口的第一时隙的所述第一时隙比特块流交换到第三物理接口的第三时隙。
在一种可能的设计中，将所述第一待处理比特块流映射为至少两个时隙比特块流具体包括：以轮循调度的方式将所述第一待处理比特块流映射为至少两个时隙比特块流。
将待处理比特块流映射为至少两个时隙比特块流，至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙。这些时隙比特块流最终会在物理接口的时隙中传输，传输之前也可以进行时隙速率匹配，时隙交换等操作，本发明实施例对此不作限定。
在一种可能的设计中，步骤902也可以为将所述第一待处理比特块流映射为至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括对应的边界比特块，两组对应的边界比特块之间的各个时隙比特块流中包含的非空闲比特块的数量相同。
在映射的过程中，本发明实施例需要在各个时隙比特块流中分别插入对应的边界比特块，例如在第一时隙比特块流和第二时隙比特块流分别插入对应的第一边界比特块和第三边界比特块，在第一时隙比特块流和第二时隙比特块流分别插入对应的第二边界比特块和第四边界比特块。对应的边界比特块可以是相同的比特块，也可以是不同的比特块。两组对应的边界比特块之间的各个时隙比特块流中包含的比特块的数量相同，包含的非空闲比特块的数量相同，包含的空闲比特块的数量也相同。即至少两个时隙比特块流均包括对应的边界比特块，两组对应的边界比特块之间的各个时隙比特块流中包含的非空闲比特块的数量相同。在一种可能的设计中，两组对应的边界比特块之间的各个时隙比特块流中包含的非空闲比特块的数量相同,各个时隙比特块流中包含的空闲比特块的数量不同,即各个时隙比特块流中包含的总比特块的数量也不同。
在一种可能的设计中，可以同时在各个时隙比特块流中插入对应的边界比特块，例如可以同时在第一时隙比特块流和第二时隙比特块流中插入边界比特块，即同时插入第一边界比特块和第三边界比特块，同时插入第二边界比特块和第四边界比特块。对应边界比特块用于接收端解映射时进行对齐操作，因此插入对应的边界比特块也可以不同时进行，只要接收端能够进行对齐操作即可。
在一种可能的设计中，可以在各个时隙比特块流中确定一个起始时隙比特块流，或者也可以称为起始时隙。可以在进行起始时隙映射时进行边界比特块的插入，例 如需要将待处理比特块流映射到时隙A，时隙B和时隙C三个时隙中，映射顺序可以是ABC，CBA等，如果映射顺序为ABC，则时隙A为初始时隙。
一组对应的边界比特块的插入可以是周期性的，例如50毫秒插入一次，也可以是非周期性的，例如当数据断流当前无业务数据传输时插入。不同组边界比特块之间非空闲比特块的数量可以不同。
在一种可能的设计中，可以采用轮循调度方式进行比特块的映射，即从待处理比特块流取出待映射比特块，以一个比特块为单位轮流映射到两个时隙比特块流中，当然，在其它可能的设计中，也可以以其它数量的比特块为单位进行轮流映射，也可以采用其它映射规则，例如先在第一时隙比特块流中映射两个比特块，在第二时隙比特块流中映射三个比特块，再在第一时隙比特块流中映射三个比特块，在第二时隙比特块流中映射两个比特块。只要接收端知道发送端映射采用的非空闲比特块的映射规则即可进行接收端解映射。
对于从待处理比特块流取出的待映射比特块，如果待映射比特块为空，即当前无业务数据传输，或者待映射比特块为空闲比特块，则可以在时隙比特块流中映射空闲比特块，如果待映射比特块不为空或空闲比特块，但是上次映射的比特块为空闲比特块，则在映射的连续空闲比特块的数量为时隙比特块流的数量的整数倍的情况下映射该待映射比特块，在映射的连续空闲比特块的数量不是时隙比特块流的数量的整数倍的情况下继续映射空闲比特块，这样可以达到两个时隙比特块流中空闲比特块的数量相同，非空闲比特块的数量也相同。
在一种可能的设计中，时隙比特块流中的比特块为以太网M1/M2比特块，对于以太网业务流，可以直接得到待处理比特块流，对于其中的空闲比特块，在发送端映射之前可以删除，也可以不删除，其中的空闲比特块通常为以太网帧间间隔(interpacket gap,IPG)；对于非以太网业务流，通常需要进行M1/M2比特块编码，得到待处理比特块流，例如可以对通用公共无线接口(common public radio interface,CPRI)业务流进行64/66编码。
如图9B所示，为本发明实施例提供的一种的发送端映射示意图。
本发明实施例将一个15G的以太网业务映射到3个5G时隙中，以一个比特块为单位进行时隙映射，3个5G时隙分别为slot_a、slot_b和slot_c，插入的边界比特块为时隙对齐标识(slot aligned mark,SAM)。
步骤一，接收业务比特块流，删除业务比特块流中的全部空闲比特块，然后将删除空闲比特块的业务比特块流进行缓冲等待映射，如图9B中将比特块流1处理为比特块流2所示，B15和B16之间的空闲比特块被删除；
步骤二，判断当前是否在映射起始时隙，如果是则判断是否需要插入SAM，如果需要插入，则为slot_a、slot_b、slot_c分别插入SAM，如果不需要插入则到步骤三；
步骤三，检测缓冲区是否有比特块待映射，如有则到步骤四；如无则到步骤五；
步骤四:从缓冲区读取一个比特块，放到映射指针所对应的时隙，并修改映射指针指向下一个时隙，然后跳到步骤一进行下一轮循环；
步骤五:插入3个空闲比特块，轮流映射到3个时隙，映射指针经过一轮映射后重新指向空闲比特块插入之前所指向的时隙，然后跳到步骤一进行下一轮循环，如图 9B中将比特块流2处理为3个时隙比特块流所示，如果B15之后缓冲区没有比特块待映射，则轮流在三个时隙中映射空闲比特块。
如图9C所示，为本发明实施例提供的一种的发送端映射示意图。
本发明实施例将一个10G的CPRI业务映射到2个5G时隙中，以一个比特块为单位进行时隙映射，2个5G时隙分别为slot_a和slot_b，插入的边界比特块为SAM。
步骤一，接收CPRI业务数据流输入并进行编码，对编码后的比特块流进行缓冲等待映射,如图9C中将业务流1处理为比特块流2所示；
步骤二，判断当前是否在映射起始时隙，如果是则判断是否需要插入SAM，如果需要插入，则为slot_a和slot_b分别插入SAM，如果不需要插入则到步骤三；
步骤三，检测缓冲区是否有比特块待映射，如有则到步骤四；如无则到步骤五；
步骤四，从缓冲区读取一个比特块，放到映射指针所对应的时隙，并修改映射指针指向下一个时隙，然后跳到步骤一进行下一轮循环；
步骤五，插入2个空闲比特块，轮流映射到2个时隙，映射指针经过一轮映射后重新指向空闲比特块插入之前所指向的时隙，然后跳到步骤一进行下一轮循环,如图9C中将比特块流2处理为2个时隙比特块流所示，如果B15之后缓冲区没有比特块待映射，则轮流在两个时隙中映射空闲比特块。
图9C所示的实施例和图9B所示的实施例的差别在于接入的业务为非以太网业务，需要先进行编码处理，才能进行时隙映射，同时非以太业务没有IPG和空闲比特块，无需空闲比特块删除动作。
如图9D所示，为本发明实施例提供的一种的发送端映射示意图。
本发明实施例将一个15G的以太网业务映射到3个5G时隙中，以2个比特块为单位进行时隙映射，3个5G时隙分别为slot_a、slot_b和slot_c，插入的边界比特块为SAM。
步骤一，接收业务比特块流输入，删除业务流中的全部空闲比特块，然后缓冲等待映射，如图9D中将比特块流1处理为比特块流2所示，其中比特块流2和图9B中的比特块流2可以是一样的，只是为了方便理解，将每2个比特块放到了一起；
步骤二，判断当前是否在映射起始时隙，如果是则判断是否需要插入SAM，如果需要插入，则为slot_a、slot_b、slot_c分别插入SAM，如果不需要插入则到步骤三；
步骤三，检测缓冲区是否有足够一个映射单位的比特块，在这里以2个为例，如有则到步骤四；如无则到步骤五；
步骤四，从缓冲区读取2个比特块，放到映射指针所对应的时隙，并修改映射指针指向下一个时隙，然后跳到步骤一进行下一轮循环；
步骤五，插入6个空闲比特块，轮流映射到3个时隙，每个时隙2个空闲比特块，映射指针经过一轮映射后重新指向空闲比特块插入之前所指向的时隙，然后跳到步骤一进行下一轮循环,如图9D中将比特块流2处理为3个时隙比特块流所示，如果B15之后缓冲区没有比特块待映射，则轮流在三个时隙中映射空闲比特块。
图9D所示的实施例和图9B所示的实施例的差别在于以2个比特块为单位进行时隙映射。
如图9E所示，为本发明实施例提供的一种的发送端映射示意图。
本发明实施例将一个15G的以太网业务映射到3个5G时隙中，以一个比特块为单位进行时隙映射，3个5G时隙分别为slot_a、slot_b和slot_c，插入的边界比特块为时隙对齐标识(slot aligned mark)。本发明实施例中以太网业务输入时不进行IPG空闲比特块删除处理，在映射时进行空闲调整处理，空闲调整的目的是使每次连续空闲的数量是slot数量的整数倍，同时删除和插入的空闲数量要均衡。
步骤一，接收业务比特块流输入，不删除业务流中的IPG空闲比特块，直接缓冲等待映射,如图9E中比特块流1所示；
步骤二，判断当前是否在映射起始时隙，如果是则判断是否需要插入slot align mark，如果需要插入，则为slot_a、slot_b、slot_c分别插入slot align mark，如果不需要插入则到步骤三；
步骤三，缓冲区取出一个待映射比特块，如果该待映射比特块为非空闲比特块，且前一个映射比特块也是非空闲比特块，则到步骤六，如果该待映射比特块为非空闲比特块，且前一个映射比特块为空闲比特块，则跳步骤五，如果该待映射比特块为空闲比特块则到步骤四；
步骤四，判断当前空闲比特块是否需要删除，如果已插入有效空闲比特块计数大于零，则删除该空闲比特块，将已插入有效空闲比特块计数减一，跳到步骤一进行下一轮循环；如果已插入有效空闲比特块计数等于零，将连续映射空闲比特块计数加一，将待映射空闲比特块映射到映射指针指向的时隙，并修改映射指针指向下一个时隙，然后到步骤一进行下一轮循环；
步骤五，判断连续映射空闲比特块计数是否为3的整数倍,如果是，将待映射比特块映射到映射指针指向的时隙，并修改映射指针指向下一个时隙，然后到步骤一进行下一轮循环，否则插入一个或多个空闲比特块后将待映射比特块映射到相应时隙，使连续空闲比特块数量是3的整数倍，根据插入的空闲比特块的数量更新已插入有效空闲比特块计数的数量，如图9E所示B8比特块后面只有一个空闲比特块，所以需要插入2个空闲比特块，然后映射B9，然后到步骤一进行下一轮循环；
步骤六，将待映射比特块映射到映射指针指向的时隙，并修改映射指针指向下一个时隙，然后到步骤一进行下一轮循环。
图9B至图9E给出的发送端映射实施例中，空闲比特块的插入方式只是给出了几种容易实现的方式，在一种可能的设计中，在插入边界比特块之后，统计各个时隙比特块流中空闲比特块的数量，在下次插入边界比特块之前，只要保证各个时隙比特块流中空闲比特块的数量相同即可，即各个时隙比特块流中非空闲比特块的数量也相同，在接收端解映射时可以在删除所有空闲比特块后利用边界比特块对各时隙比特块流进行对齐操作，进而利用和发送端非空闲比特块的映射规则对应解映射规则进行解映射，恢复出待接收比特块流。
对于包含边界比特块的单个时隙比特块流，可以进行独立的时隙速率匹配，如图10A所示，本发明实施例提供了一种时隙速率匹配方法示意图。
步骤1001，获得第一时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数；
步骤1002，增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；
步骤1003，通过第二物理接口的第二时隙发送所述速率适配后的第一时隙比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
如图10B所示，为本发明实施例提供的一种时隙速率匹配电路图，包括先入先出缓存器(FIFO)1011，FIFO水位检测器1012，FIFO写控制器1013，FIFO读控制器1014，比特块流发送器1015，空闲比特块检测器1016。
输入的时隙比特块流分为两路，一路送到空闲检测器1016，一路送到FIFO1011，如果FIFO水位检测器1012检测到FIFO的水位线高于上水线，则通知FIFO写控制器1013，FIFO写控制器1013根据空闲比特块检测器1016的检测屏蔽空闲比特块的写入，即删除空闲比特块；如果FIFO水位检测器1012检测到FIFO的水位线低于下水线，则通知FIFO读控制器1014，FIFO读控制器1014屏蔽FIFO比特块的读取，比特块流发送器1015输出空闲比特块。
时隙速率适配通常存在于入接口与交换网之间或交换网与出接口之间，或者其它速率存在差异的两个功能模块之间。每一个时隙可以独立处理，如图10B所示，有一个异步缓冲区，即FIFO，根据缓冲区的上、下水线判断是否需要删除空闲比特块或插入空闲比特块块。
对于包含边界比特块的单个时隙比特块流，可以进行独立的时隙交换，如图11所示，本发明实施例提供了一种时隙交换方法示意图。
步骤1101，通过第一物理接口的第一时隙获得第一时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数；
步骤1102，将所述第一时隙比特块流交换到第二物理接口的第二时隙；
步骤1103，通过所述第二物理接口的第二时隙发送所述第一时隙比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，通过所述第二物理接口的第二时隙发送所述第一时隙比特块流具体包括：增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第二物理接口的第二时隙发送所述速率适配后的第一时隙比特块流。
在一种可能的设计中，所述将所述第一时隙比特块流交换到第二物理接口的第二时隙具体包括：根据第一接口物理接口的第一时隙和第二接口物理接口的第二时隙的对应关系，将所述第一时隙比特块流交换到第二接口物理接口的第二时隙。
时隙交换的目的在于，可以以时隙为单位，将时隙比特块流从入物理接口的一个时隙交换到出物理接口的一个时隙，交换关系可以根据预先配置的对应关系实现，也可以通过时隙分配表来临时配置。
时隙交换的具体物理实现可以基于电路交换,SDH/OTN的TDM交换，分组信元交换等交换方式。
对于电路交换，每个接收或映射的时隙比特块流作为一路输入，每个发送的时隙比特块流作为一路输出，输入和输出一一对应，通过NxN全空分交叉电路实现无阻塞交换，N为输入输出线路数量。
对于SDH/OTN的TDM交换，可以通过空分加时分复用的方式共享交换通路，把时隙比特块流里每个比特块作为一个时隙交换单元，对应SDH/OTN TDM交换网的一个时隙，从而可以将一个时隙比特块流中的比特块从一个接口交换到另一个接口。
对于分组信元交换，可以把时隙比特块流按接收顺序分段以信元来装载，并打上顺序编号，送到信元交换网进行交换，完成交换后剥掉信元封装，并根据编号顺序排列，恢复出原始的时隙比特块流。
如图12所示，本发明实施例提供一种接收端解映射的示意图，包括：
步骤1201，获得至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块；
步骤1202，删除所述第一边界比特块和所述第二边界比特块之间的空闲比特块，删除所述第三边界比特块和所述第四边界比特块之间的空闲比特块；
步骤1203，根据所述第一边界比特块和所述第三边界比特块，以及所述第二边界比特块和所述第四边界比特块，对空闲比特块删除后的第一时隙比特块流和空闲比特块删除后的第二时隙比特块流进行对齐；
步骤1204，将对齐后的第一时隙比特块流和第二时隙比特块流解映射为第一待接收比特块流。
接收端设备接收的第一边界比特块和第二边界比特块之间非空闲比特块的数量和第三边界比特块和第四边界比特块之间非空闲比特块的数量相等，接收端设备可以在删除所有的空闲比特块后利用边界比特块进行对齐，从而恢复出待接收比特块流。对齐后的解映射只要使用和发送端非空闲比特块映射规则对应的解映射规则即可实现，在此不做赘述。
在一种可能的设计中，步骤1201也可以为获得至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括对应的边界比特块，两组对应的边界比特块之间的各个时隙比特块流中包含的非空闲比特块的数量相同。
在一种可能的设计中，步骤1202也可以为删除各个时隙比特块流中包含的空闲比特块。
在一种可能的设计中，步骤1203也可以为根据对应的边界比特块对删除空闲比特块后的各个时隙比特块流进行对齐。
在一种可能的设计中，步骤1204也可以为将对齐后的各个时隙比特块流解映射为第一待接收比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，还包括：对所述第一待接收比特块流进行比特块解码，获得第一待接收业务。
在一种可能的设计中，还包括：对所述第一待接收比特块流进行IPG恢复，获得第一待接收业务。
在一种可能的设计中，获得至少两个时隙比特块流具体包括：通过第一物理接口的第一时隙获得所述第一时隙比特块流，通过第一物理接口的第二时隙获得所述第二时隙比特块流；或者通过第一物理接口的第一时隙获得所述第一时隙比特块流，通过第二物理接口的第二时隙获得所述第二时隙比特块流。
接收端解映射可以删除每个时隙比特块流中的所有空闲比特块，然后根据边界比特块对多个时隙比特块流进行对齐处理，进而可以恢复出待接收比特块流，恢复出的待接收比特块流可以经过后处理然后经用户接口输出，对于以太网业务，可以进行IPG恢复，对于非以太网业务，可以进行M1/M2解码，输出原始业务流。
基于以上实施例以及相同构思，图13为本申请实施例提供的比特块流处理装置1300的示意图，比特块流处理装置1300可以在图3，图5或图7中的客户适配单元中实现，可以图3，图5或图7中的网络适配单元或C2C适配单元中实现，也可以在其他网络设备或网络模块中实现，比特块流处理装置1300包括：
接收器1301，用于获得第一待处理比特块流；
处理器1302，用于将所述第一待处理比特块流映射为至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，还包括：发送器，用于通过第一物理接口的第一时隙发送第一时隙比特块流，用于通过第一物理接口的第二时隙发送第二时隙比特块流；或者发送器，用于通过第一物理接口的第一时隙发送第一时隙比特块流，通过第二物理接口的第二时隙发送第二时隙比特块流。
在一种可能的设计中，接收器具体用于获得第一待处理业务；对第一待处理业务 进行比特块编码，获得第一待处理比特块流。
在一种可能的设计中，发送器具体用于增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第一物理接口的第一时隙发送速率适配后的第一时隙比特块流。
在一种可能的设计中，发送器具体用于增加或删除第三边界比特块和第四边界比特块之间的空闲比特块，获得速率适配后的第二时隙比特块流；通过第一物理接口的第二时隙发送速率适配后的第二时隙比特块流，或者通过第二物理接口的第二时隙发送速率适配后的第二时隙比特块流。
在一种可能的设计中，还包括：交换器，用于将第一物理接口的第一时隙的第一时隙比特块流交换到第三物理接口的第三时隙。
在一种可能的设计中，处理器具体用于以轮循调度的方式将第一待处理比特块流映射为至少两个时隙比特块流。
基于以上实施例以及相同构思，图14为本申请实施例提供的比特块流速率适配装置1400的示意图，比特块流速率适配装置1400可以在图3，图5或图7中的客户适配单元中实现，可以图3，图5或图7中的网络适配单元或C2C适配单元中实现，也可以在其他网络设备或网络模块中实现，比特块流速率适配装置1400包括：
接收器1401，用于获得第一时隙比特块流，第一时隙比特块流包括第一边界比特块和第二边界比特块，第一边界比特块和第二边界比特块之间包括N个第一比特块，第一比特块为非空闲比特块,N为大于等于1的整数；
速率适配器1402，用于增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；
发送器1403，用于通过第二物理接口的第二时隙发送速率适配后的第一时隙比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
基于以上实施例以及相同构思，图15为本申请实施例提供的比特块流交换装置1500的示意图，比特块流交换装置1500可以在图3，图5或图7中的交换单元中实现，也可以在其他网络设备或网络模块中实现，比特块流交换装置1500包括：
接收器1501，用于通过第一物理接口的第一时隙获得第一时隙比特块流，第一时隙比特块流包括第一边界比特块和第二边界比特块，第一边界比特块和第二边界比特块之间包括N个第一比特块，第一比特块为非空闲比特块,N为大于等于1的整数；
交换器1502，用于将第一时隙比特块流交换到第二物理接口的第二时隙；
发送器1503，用于通过第二物理接口的第二时隙发送第一时隙比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，发送器具体用于增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第二物理接口的第二时隙发送速率适配后的第一时隙比特块流。
在一种可能的设计中，交换器具体用于根据第一接口物理接口的第一时隙和第二 接口物理接口的第二时隙的对应关系，将第一时隙比特块流交换到第二接口物理接口的第二时隙。
基于以上实施例以及相同构思，图16为本申请实施例提供的比特块流处理装置1600的示意图，比特块流处理装置1600可以在图3，图5或图7中的客户适配单元中实现，可以图3，图5或图7中的网络适配单元或C2C适配单元中实现，也可以在其他网络设备或网络模块中实现，比特块流处理装置1600包括：
接收器，用于获得至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块；
处理器，用于删除第一边界比特块和第二边界比特块之间的空闲比特块，删除第三边界比特块和第四边界比特块之间的空闲比特块；根据第一边界比特块和第三边界比特块，以及第二边界比特块和第四边界比特块，对空闲比特块删除后的第一时隙比特块流和空闲比特块删除后的第二时隙比特块流进行对齐；将对齐后的第一时隙比特块流和第二时隙比特块流解映射为第一待接收比特块流。
在一种可能的设计中，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
在一种可能的设计中，还包括：解码器，用于对第一待接收比特块流进行比特块解码，获得第一待接收业务。
在一种可能的设计中，还包括：IPG恢复器，用于对第一待接收比特块流进行IPG恢复，获得第一待接收业务。
在一种可能的设计中，接收器具体用于通过第一物理接口的第一时隙获得第一时隙比特块流，通过第一物理接口的第二时隙获得第二时隙比特块流；或者通过第一物理接口的第一时隙获得第一时隙比特块流，通过第二物理接口的第二时隙获得第二时隙比特块流。
在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件单元组合执行完成。软件单元可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
还应理解，本文中涉及的第一、第二、第三、第四以及各种数字编号仅为描述方便进行的区分，并不用来限制本发明实施例的范围。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独 存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系，除非有特殊说明。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各种说明性逻辑块(illustrative logical block)和步骤(step)，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本发明实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
以上，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (38)

  1. 一种比特块流处理方法，其特征在于，包括：
    获得第一待处理比特块流；
    将所述第一待处理比特块流映射为至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块，N为大于等于1的整数。
  2. 根据权利要求1所述的方法，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  3. 根据权利要求1所述的方法，其特征在于，还包括：
    通过第一物理接口的第一时隙发送所述第一时隙比特块流，通过第一物理接口的第二时隙发送所述第二时隙比特块流；或者
    通过第一物理接口的第一时隙发送所述第一时隙比特块流，通过第二物理接口的第二时隙发送所述第二时隙比特块流。
  4. 根据权利要求1所述的方法，其特征在于，所述获得第一待处理比特块流具体包括：
    获得第一待处理业务；
    对所述第一待处理业务进行比特块编码，获得第一待处理比特块流。
  5. 根据权利要求3所述的方法，其特征在于，通过第一物理接口的第一时隙发送所述第一时隙比特块流具体包括：
    增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；
    通过第一物理接口的第一时隙发送所述速率适配后的第一时隙比特块流。
  6. 根据权利要求5所述的方法，其特征在于，通过第一物理接口的第二时隙发送所述第二时隙比特块流或者通过第二物理接口的第二时隙发送所述第二时隙比特块流具体包括：
    增加或删除第三边界比特块和第四边界比特块之间的空闲比特块，获得速率适配后的第二时隙比特块流；
    通过第一物理接口的第二时隙发送所述速率适配后的第二时隙比特块流，或者通过第二物理接口的第二时隙发送所述速率适配后的第二时隙比特块流。
  7. 根据权利要求3所述的方法，其特征在于，还包括：
    将第一物理接口的第一时隙的所述第一时隙比特块流交换到第三物理接口的第三时隙。
  8. 根据权利要求1所述的方法，其特征在于，将所述第一待处理比特块流映射为至少两个时隙比特块流具体包括：
    以轮循调度的方式将所述第一待处理比特块流映射为至少两个时隙比特块流。
  9. 一种比特块流速率适配方法，其特征在于，包括：
    获得第一时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数；
    增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；
    通过第二物理接口的第二时隙发送所述速率适配后的第一时隙比特块流。
  10. 根据权利要求9所述的方法，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  11. 一种比特块流交换方法，其特征在于，包括：
    通过第一物理接口的第一时隙获得第一时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数；
    将所述第一时隙比特块流交换到第二物理接口的第二时隙；
    通过所述第二物理接口的第二时隙发送所述第一时隙比特块流。
  12. 根据权利要求11所述的方法，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  13. 根据权利要求11所述的方法，其特征在于，通过所述第二物理接口的第二时隙发送所述第一时隙比特块流具体包括：
    增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；
    通过第二物理接口的第二时隙发送所述速率适配后的第一时隙比特块流。
  14. 根据权利要求11所述的方法，其特征在于，所述将所述第一时隙比特块流交换到第二物理接口的第二时隙具体包括：
    根据第一接口物理接口的第一时隙和第二接口物理接口的第二时隙的对应关系，将所述第一时隙比特块流交换到第二接口物理接口的第二时隙。
  15. 一种比特块流处理方法，其特征在于，包括：
    获得至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所 述第一比特块为非空闲比特块；
    删除所述第一边界比特块和所述第二边界比特块之间的空闲比特块，删除所述第三边界比特块和所述第四边界比特块之间的空闲比特块；
    根据所述第一边界比特块和所述第三边界比特块，以及所述第二边界比特块和所述第四边界比特块，对空闲比特块删除后的第一时隙比特块流和空闲比特块删除后的第二时隙比特块流进行对齐；
    将对齐后的第一时隙比特块流和第二时隙比特块流解映射为第一待接收比特块流。
  16. 根据权利要求15所述的方法，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  17. 根据权利要求15所述的方法，其特征在于，还包括：
    对所述第一待接收比特块流进行比特块解码，获得第一待接收业务。
  18. 根据权利要求15所述的方法，其特征在于，还包括：
    对所述第一待接收比特块流进行IPG恢复，获得第一待接收业务。
  19. 根据权利要求15所述的方法，其特征在于，获得至少两个时隙比特块流具体包括：
    通过第一物理接口的第一时隙获得所述第一时隙比特块流，通过第一物理接口的第二时隙获得所述第二时隙比特块流；或者
    通过第一物理接口的第一时隙获得所述第一时隙比特块流，通过第二物理接口的第二时隙获得所述第二时隙比特块流。
  20. 一种比特块流处理装置，其特征在于，包括：
    接收器，用于获得第一待处理比特块流；
    处理器，用于将所述第一待处理比特块流映射为至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数。
  21. 根据权利要求20所述的装置，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  22. 根据权利要求20所述的装置，其特征在于，还包括：
    发送器，用于通过第一物理接口的第一时隙发送所述第一时隙比特块流，用于通过第一物理接口的第二时隙发送所述第二时隙比特块流；或者
    发送器，用于通过第一物理接口的第一时隙发送所述第一时隙比特块流，通过第 二物理接口的第二时隙发送所述第二时隙比特块流。
  23. 根据权利要求20所述的装置，其特征在于，所述接收器具体用于获得第一待处理业务；对所述第一待处理业务进行比特块编码，获得第一待处理比特块流。
  24. 根据权利要求22所述的装置，其特征在于，所述发送器具体用于增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第一物理接口的第一时隙发送所述速率适配后的第一时隙比特块流。
  25. 根据权利要求24所述的装置，其特征在于，所述发送器具体用于增加或删除第三边界比特块和第四边界比特块之间的空闲比特块，获得速率适配后的第二时隙比特块流；通过第一物理接口的第二时隙发送所述速率适配后的第二时隙比特块流，或者通过第二物理接口的第二时隙发送所述速率适配后的第二时隙比特块流。
  26. 根据权利要求22所述的装置，其特征在于，还包括：
    交换器，用于将第一物理接口的第一时隙的所述第一时隙比特块流交换到第三物理接口的第三时隙。
  27. 根据权利要求20所述的装置，其特征在于，所述处理器具体用于以轮循调度的方式将所述第一待处理比特块流映射为至少两个时隙比特块流。
  28. 一种比特块流速率适配装置，其特征在于，包括：
    接收器，用于获得第一时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数；
    速率适配器，用于增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；
    发送器，用于通过第二物理接口的第二时隙发送所述速率适配后的第一时隙比特块流。
  29. 根据权利要求28所述的装置，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  30. 一种比特块流交换装置，其特征在于，包括：
    接收器，用于通过第一物理接口的第一时隙获得第一时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块,N为大于等于1的整数；
    交换器，用于将所述第一时隙比特块流交换到第二物理接口的第二时隙；
    发送器，用于通过所述第二物理接口的第二时隙发送所述第一时隙比特块流。
  31. 根据权利要求30所述的装置，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  32. 根据权利要求30所述的装置，其特征在于，所述发送器具体用于增加或删除第一边界比特块和第二边界比特块之间的空闲比特块，获得速率适配后的第一时隙比特块流；通过第二物理接口的第二时隙发送所述速率适配后的第一时隙比特块流。
  33. 根据权利要求30所述的装置，其特征在于，所述交换器具体用于根据第一接口物理接口的第一时隙和第二接口物理接口的第二时隙的对应关系，将所述第一时隙比特块流交换到第二接口物理接口的第二时隙。
  34. 一种比特块流处理装置，其特征在于，包括：
    接收器，用于获得至少两个时隙比特块流，所述至少两个时隙比特块流与至少一个物理接口上的至少两个时隙对应，不同的时隙比特块流对应不同的时隙，所述至少两个时隙比特块流包括第一时隙比特块流和第二时隙比特块流，所述第一时隙比特块流包括第一边界比特块和第二边界比特块，所述第二时隙比特块流包括第三边界比特块和第四边界比特块，所述第一边界比特块和所述第三边界比特块对应，所述第二边界比特块和所述第四边界比特块对应，所述第一边界比特块和所述第二边界比特块之间包括N个第一比特块，所述第三边界比特块和所述第四边界比特块之间包括N个第一比特块，所述第一比特块为非空闲比特块；
    处理器，用于删除所述第一边界比特块和所述第二边界比特块之间的空闲比特块，删除所述第三边界比特块和所述第四边界比特块之间的空闲比特块；根据所述第一边界比特块和所述第三边界比特块，以及所述第二边界比特块和所述第四边界比特块，对空闲比特块删除后的第一时隙比特块流和空闲比特块删除后的第二时隙比特块流进行对齐；将对齐后的第一时隙比特块流和第二时隙比特块流解映射为第一待接收比特块流。
  35. 根据权利要求34所述的装置，其特征在于，每个比特块的类型为M1/M2比特块，其中，M1表示每个比特块中的净荷比特数，M2表示每个比特块的总比特数，M1、M2为正整数，M2＞M1。
  36. 根据权利要求34所述的装置，其特征在于，还包括：
    解码器，用于对所述第一待接收比特块流进行比特块解码，获得第一待接收业务。
  37. 根据权利要求34所述的装置，其特征在于，还包括：
    IPG恢复器，用于对所述第一待接收比特块流进行IPG恢复，获得第一待接收业务。
  38. 根据权利要求34所述的装置，其特征在于，所述接收器具体用于通过第一物理接口的第一时隙获得所述第一时隙比特块流，通过第一物理接口的第二时隙获得所述第二时隙比特块流；或者通过第一物理接口的第一时隙获得所述第一时隙比特块流，通过第二物理接口的第二时隙获得所述第二时隙比特块流。
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