WO2019022206A1 - Dispositif semiconducteur - Google Patents

Dispositif semiconducteur Download PDF

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Publication number
WO2019022206A1
WO2019022206A1 PCT/JP2018/028143 JP2018028143W WO2019022206A1 WO 2019022206 A1 WO2019022206 A1 WO 2019022206A1 JP 2018028143 W JP2018028143 W JP 2018028143W WO 2019022206 A1 WO2019022206 A1 WO 2019022206A1
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Prior art keywords
semiconductor chip
heat sink
resistor
layer
mosfet
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PCT/JP2018/028143
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English (en)
Japanese (ja)
Inventor
河野　憲司
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株式会社デンソー
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Priority claimed from JP2018117317A external-priority patent/JP6769458B2/ja
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN201880048889.7A priority Critical patent/CN110998810B/zh
Publication of WO2019022206A1 publication Critical patent/WO2019022206A1/fr
Priority to US16/695,422 priority patent/US11101259B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present disclosure is a semiconductor having a first semiconductor chip on which a junction type FET (Field Effect Transistor: hereinafter simply referred to as JFET) is formed and a second semiconductor chip on which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed. It relates to the device.
  • JFET Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Patent Document 1 proposes a semiconductor device having a first semiconductor chip on which a normally-on JFET is formed and a second semiconductor chip on which a normally-off MOSFET is formed. Specifically, in this semiconductor device, the JFET and the MOSFET are cascode connected, and the source electrode of the MOSFET and the gate electrode of the JFET are connected via one resistor for adjusting the switching speed.
  • the switching speed is adjusted by adjusting the resistance value of the resistor disposed between the source electrode of the MOSFET and the gate electrode of the JFET.
  • the semiconductor device may be in the on state when current flows in the JFET and the MOSFET, and the current flowing in the JFET and the MOSFET is shut off (that is, current does not flow). It is also said that the semiconductor device is off.
  • the on state is the time when the off state is switched to the on state (that is, the transient state), and hereinafter, it is also referred to as the switching on operation.
  • the turning-off state is the turning-on state to the turning-off state (that is, the transient state), and hereinafter also referred to as the switching-off operation.
  • An object of the present disclosure is to provide a semiconductor device in which the switching speed at switching on operation and the switching speed at switching off operation can be adjusted in a semiconductor device in which JFET and MOSFET are cascode-connected. .
  • the semiconductor device is disposed between the first semiconductor chip on which the JFET is formed, the second semiconductor chip on which the MOSFET is formed, and the gate electrode of the JFET and the source electrode of the MOSFET. And the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected to form a cascode connection, and the adjustment resistor for JFET is for switching on operation.
  • a first resistor circuit and a second resistor circuit for switching off operation are included.
  • the JFET adjustment resistor disposed between the source electrode of the MOSFET and the gate electrode of the JFET has the first resistance circuit for switching on operation and the second resistance circuit for switching off operation. doing.
  • the parenthesized reference symbol attached to each component etc. shows an example of the correspondence of the component etc. and the specific component etc. as described in the embodiment to be described later.
  • FIG. 3 is a cross-sectional view taken along the line III-III in FIG. It is a top view of a 1st semiconductor chip.
  • FIG. 5 is a cross-sectional view taken along the line VV in FIG. 4; It is a top view of a 2nd semiconductor chip.
  • FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. It is a plane schematic diagram of the semiconductor device in a 2nd embodiment. It is a circuit diagram of the semiconductor device in a 2nd embodiment. It is a plane schematic diagram of the semiconductor device in a 3rd embodiment.
  • FIG. 25 is a circuit diagram of a U layer in FIG. 24. It is a circuit diagram of the semiconductor device in a 13th embodiment.
  • the circuit configuration in the semiconductor device of the present embodiment will be described.
  • the normally-on JFET 10 formed in the first semiconductor chip 100 and the normally-off MOSFET 20 formed in the second semiconductor chip 200 are cascode connected. Is configured.
  • the JFET 10 and the MOSFET 20 are each N-channel type.
  • the JFET 10 has a source electrode 11, a drain electrode 12, and a gate layer (i.e., a gate electrode) 13, although a specific configuration will be described later.
  • the MOSFET 20 has a source electrode 21, a drain electrode 22, and a gate electrode 23, although the specific configuration will be described later.
  • the source electrode 11 of the JFET 10 and the drain electrode 22 of the MOSFET 20 are electrically connected.
  • the drain electrode 12 of the JFET 10 is connected to the first terminal 31, and the source electrode 21 of the MOSFET 20 is connected to the second terminal 32.
  • the gate electrode 23 of the MOSFET 20 is connected to the gate drive circuit 51 via the MOSFET adjustment resistor 41 and the gate pad 24.
  • the gate layer 13 of the JFET 10 is electrically connected to the source electrode 21 of the MOSFET 20 via the adjustment resistor 42 for JFET and the gate pad 14.
  • the JFET adjustment resistor 42 includes a first resistor circuit 421 in which a first diode 421a and a first resistor 421b are connected in series, a second diode 422a, and a second resistor 422b in series. And a second resistance circuit 422.
  • the first resistance circuit 421 and the second resistance circuit 422 are arranged in parallel so that the cathode of the first diode 421a and the anode of the second diode 422a are connected to the gate layer 13 of the JFET 10, respectively.
  • the JFET adjustment resistor 42 of this embodiment is a component packaged including the first resistor circuit 421 and the second resistor circuit 422, and is a separate component different from the first semiconductor chip 100 and the second semiconductor chip 200. It is an external part configured as Further, in the present embodiment, the first resistance 421b is set to a value larger than that of the second resistance 422b. More specifically, the first resistor 421 b controls the switching speed when the semiconductor device is turned on as described later, and has a resistance value according to the desired desired application.
  • the gate layer 13 of the JFET 10 and the source electrode 21 of the MOSFET 20 are connected via such a JFET adjustment resistor 42. Therefore, the gate current of the JFET 10 is adjusted by different resistance circuits in the switching on operation and the switching off operation. That is, in the semiconductor device of the present embodiment, the switching speed is adjusted by different resistance circuits in the switching on operation and the switching off operation.
  • the diode 15 is connected between the drain electrode 12 and the source electrode 11 of the JFET 10.
  • a P-type body layer 116 is formed in the N ⁇ -type channel layer 114.
  • the diode 15 is configured to include the body layer 116.
  • the cathode of the diode 15 is electrically connected to the drain electrode 12, and the anode is electrically connected to the source electrode 11.
  • a diode 25 is connected between the drain electrode 22 and the source electrode 21 of the MOSFET 20.
  • the diode 25 is a parasitic diode formed on the configuration of the MOSFET 20, the cathode is electrically connected to the drain electrode 22, and the anode is electrically connected to the source electrode 21.
  • Such a semiconductor device operates as a normally off as a whole since it has the MOSFET 20 which is normally off.
  • a positive voltage is applied to the first terminal 31, and the second terminal 32 is grounded.
  • a predetermined positive gate voltage is applied to the gate electrode 23 of the MOSFET 20 from the gate drive circuit 51.
  • the normally-off MOSFET 20 is turned on.
  • the gate layer 13 is connected to the second terminal 32. Therefore, in the normally-on JFET 10, the potential difference between the gate layer 13 and the source electrode 11 becomes almost zero, and the on state is achieved. Therefore, current flows between the first terminal 31 and the second terminal 32, and the semiconductor device is finally turned on.
  • the gate charging current of the JFET is adjusted by the first resistance circuit 421 (that is, the first resistor 421 b). That is, in the present embodiment, when the JFE 10 performs switching on operation, the gate layer 13 is connected to the second terminal 32 via the first resistance circuit 421. That is, the first resistance circuit 421 functions as a speed adjustment resistor for switching on operation in the JFET 10.
  • a high breakdown voltage element is generally disposed on the upper side. That is, the JFET 10 has a breakdown voltage higher than that of the MOSFET 20. For this reason, in the cascode circuit, if it is attempted to adjust the speed of the switching-on operation by the MOSFET adjustment resistor 41, the following phenomenon may occur. That is, since the JFET 10 has a breakdown voltage higher than that of the MOSFET 20, if the JFET 10 is turned on even a little, the MOSFET 20 in the transition state from off to on will break and turn on at once. That is, in such a cascode circuit, it is difficult to adjust the speed of the switching-on operation by the MOSFET adjustment resistor 41.
  • the speed adjustment of the switching-on operation in the cascode circuit be adjusted by the first resistance circuit 421 while fixing the value of the MOSFET adjustment resistance 41.
  • the MOSFET adjustment resistor 41 is preferably set to a relatively small value so that the MOSFET 20 can be turned on quickly.
  • the gate discharge current of the JFET 10 is adjusted by the second resistance circuit 422 (that is, the second resistor 422 b). That is, in the present embodiment, when the JFE 10 performs the switching-off operation, the gate layer 13 is connected to the second terminal 32 via the second resistance circuit 422. That is, the second resistance circuit 422 functions as a speed adjustment resistor for switching off operation in the JFET 10.
  • the speed adjustment of the switching off operation in the cascode circuit be adjusted by the MOSFET adjusting resistor 41.
  • the MOSFET 20 withstands a breakdown as long as the JFET 10 is not completely turned off even when the MOSFET 20 is turned off, and the reliability is lowered. is there. Therefore, it is preferable to adjust the speed of the switching-off operation in the cascode circuit by fixing the value of the second resistor 422 b in the second resistor circuit 422 and adjusting it by the MOSFET adjustment resistor 41.
  • the second resistor 422 b is preferably set to a relatively small value so that the JFET 10 is quickly turned off.
  • FIG. 1 The above is the operation of the semiconductor device in this embodiment. Next, the configuration of the semiconductor device of the present embodiment will be described with reference to FIGS. 2 and 3. FIG.
  • the semiconductor device includes a first semiconductor chip 100, a second semiconductor chip 200, a substrate 300, a first terminal 31, a second terminal 32, first to third control terminals 61 to 63, an adjustment resistor 42 for JFET, and the like. There is. And these are constituted by being suitably sealed by mold resin 400. Although specifically described later, the JFET adjustment resistor 42 is disposed outside the mold resin 400. Further, in the present embodiment, as described above, the JFET 10 is formed in the first semiconductor chip 100, and the MOSFET 20 is formed in the second semiconductor chip 200. Then, FIG. 2 is a plan view of the semiconductor device, but in order to make the configuration in the mold resin 400 easy to understand, the configuration in the mold resin 400 is shown by a solid line, and the mold resin 400 is shown by a broken line.
  • the substrate 300 is configured using a DCB substrate in which wiring patterns 301 to 303 made of Cu (copper) are formed on an alumina ceramic substrate by DCB (that is, Direct Copper Bond) method.
  • the first wiring pattern 301, the second wiring pattern 302, and the third wiring pattern 303 are formed on the first surface 300a of the substrate 300.
  • the first semiconductor chip 100 is disposed on the first wiring pattern 301, and the second semiconductor chip 200 is disposed on the second wiring pattern 302.
  • the first semiconductor chip 100 is rectangular in plan view, and has a cell area 101 and an outer peripheral area 102 surrounding the cell area 101. Then, in the cell region 101, the JFET 10 is formed.
  • the first semiconductor chip 100 includes a semiconductor substrate 110 having a drain layer 111 formed of an N ++ -type silicon carbide (hereinafter referred to as SiC) substrate. . Then, an N + -type buffer layer 112 having an impurity concentration lower than that of the drain layer 111 is disposed on the drain layer 111, and an N concentration lower than that of the buffer layer 112 on the buffer layer 112. - drift layer 113 of the mold is disposed. Although the buffer layer 112 is provided to suppress voltage oscillation at the time of switching of the first semiconductor chip 100, the buffer layer 112 may not be provided.
  • the buffer layer 112 and the drift layer 113 are formed by growing an epitaxial film of SiC on the SiC substrate constituting the drain layer 111.
  • An N ⁇ -type channel layer 114 having an impurity concentration equal to that of the drift layer 113 is disposed on the drift layer 113, and the surface layer of the channel layer 114 has an N + -type impurity concentration higher than that of the channel layer 114.
  • Source layer 115 is formed.
  • the channel layer 114 is configured by growing an epitaxial film of SiC, and the source layer 115 is configured by, for example, ion implantation of an N-type impurity and heat treatment.
  • a P + -type gate layer (that is, a gate electrode) 13 and a P + -type body layer 116 having a higher impurity concentration than the channel layer 114 are formed so as to penetrate the source layer 115.
  • the gate layer 13 and the body layer 116 are formed, for example, by forming a trench so as to penetrate the source layer 115 and growing an epitaxial film of SiC so as to be embedded in the trench.
  • the gate layers 13 and the body layers 116 extend in one direction in the surface direction of the semiconductor substrate 110, and are alternately arranged in the surface direction and in a direction orthogonal to the extension direction. . That is, in FIG. 5, the gate layer 13 and the body layer 116 extend in the direction perpendicular to the paper surface. The gate layers 13 and the body layers 116 are alternately arranged in the left-right direction in the drawing.
  • the gate layer 13 and the body layer 116 have the same impurity concentration and the same width along the arrangement direction.
  • the body layer 116 is formed to a position deeper than the gate layer 13. That is, the body layer 116 protrudes toward the drain layer 111 more than the gate layer 13.
  • an interlayer insulating film 117 is formed on the one surface 110 a of the semiconductor substrate 110. Then, in the interlayer insulating film 117, a contact hole 117a for exposing the source layer 115 and the body layer 116 is formed. On interlayer insulating film 117, source electrode 11 electrically connected to source layer 115 and body layer 116 through contact hole 117a is formed.
  • the source electrode 11 is formed to include the entire surface of the cell region 101. That is, the source electrode 11 is formed in a so-called solid shape. For this reason, it can be said that the cross-sectional area of the source electrode 11 is sufficiently large compared to the gate wiring 118 described later. In other words, it can be said that the current capacity of the source electrode 11 is sufficiently larger than that of the gate wiring 118 described later.
  • a drain electrode 12 electrically connected to the drain layer 111 is formed on the other surface 110 b side of the semiconductor substrate 110.
  • the gate pad 14 and the gate wiring 118 are formed in the outer peripheral region 102.
  • the gate wiring 118 is connected to the gate pad 14 and electrically connected to the gate layer 13 in a cross section different from that in FIG. 5.
  • an annular P-type well area or a plurality of P-types are provided so as to surround the cell area 101 so that the withstand voltage can be improved.
  • Guard rings are formed as a multiple ring structure.
  • the N ⁇ -type, the N-type, the N + -type, and the N ++ -type correspond to the first conductivity type
  • the P + -type corresponds to the second conductivity type.
  • the semiconductor substrate 110 is configured to include the drain layer 111, the buffer layer 112, the drift layer 113, the channel layer 114, the source layer 115, the gate layer 13, and the body layer 116. There is.
  • the drain layer 111 is formed of a SiC substrate, and the buffer layer 112, the drift layer 113, the channel layer 114, and the like are formed by growing an epitaxial film of SiC. ing. Therefore, it can be said that the semiconductor device of the present embodiment is a SiC semiconductor device. Further, in the present embodiment, the first semiconductor chip 100 is formed with a P-type body layer 116. Therefore, the diode 15 in FIG. 1 is a diode configured to include the body layer 116 and the drift layer 113.
  • the body layer 116 is thus provided. Therefore, when a surge occurs, it becomes difficult for a surge current to flow through the gate layer 13 to the gate wiring 118 having a small cross section, and it is possible to suppress breakage of the first semiconductor chip 100 due to melting of the gate wiring 118. .
  • the body layer 116 when the body layer 116 is not provided as in the present embodiment, most of the surge current flows to the gate wiring through the gate layer, and there is a concern that the gate wiring may be broken (that is, melted).
  • the provision of the body layer 116 makes it possible to make the surge current less likely to flow through the gate layer 13 as compared to the case where the body layer 116 is not provided.
  • the surge current that has flowed into the body layer 116 flows into the source electrode 11 via the body layer 116.
  • the source electrode 11 is formed in a solid shape and is sufficiently large compared to the gate wiring 118, the possibility of the source electrode 11 being fused is low.
  • the body layer 116 is formed deeper than the gate layer 13. That is, the length of the body layer 116 from the one surface 110 a to the bottom of the semiconductor substrate 110 is longer than the length from the one surface 110 a of the semiconductor substrate 110 to the bottom of the gate layer 13. That is, the body layer 116 protrudes to the drain layer 111 side more than the gate layer 13. Therefore, the electric field strength tends to be higher on the bottom side of the body layer 116 than on the bottom side of the gate layer 13. Therefore, when a surge occurs, breakdown tends to occur in the region on the bottom side of body layer 116, and the surge current tends to flow into body layer 116. Therefore, in the present embodiment, the surge current is less likely to flow into the gate layer 13, and the surge current flowing through the gate wiring 118 can be further reduced.
  • the second semiconductor chip 200 is rectangular in plan view, and has a cell area 201 and an outer peripheral area 202 surrounding the cell area 201. Then, the MOSFET 20 is formed in the cell region 201.
  • the second semiconductor chip 200 includes a semiconductor substrate 210 having a drain layer 211 formed of an N + -type silicon (hereinafter referred to as Si) substrate. Then, on the drain layer 211, an N ⁇ -type drift layer 212 having an impurity concentration lower than that of the drain layer 211 is disposed. On the drift layer 212, a P-type channel layer 213 having a higher impurity concentration than the drift layer 212 is disposed.
  • Si N + -type silicon
  • a plurality of trenches 214 are formed so as to penetrate the channel layer 213 and reach the drift layer 212, and the channel layer 213 is separated into a plurality by the trenches 214.
  • the plurality of trenches 214 are formed in stripes at equal intervals along one of the surface directions of the one surface 210 a of the semiconductor substrate 210 (the depth direction in FIG. 7).
  • the plurality of trenches 214 may have an annular structure by being drawn around the tip.
  • each trench 214 is embedded by a gate insulating film 215 formed to cover the wall surface of each trench 214 and a gate electrode 23 formed of polysilicon or the like formed on the gate insulating film 215. It is done.
  • a trench gate structure is configured.
  • an N + -type source layer 216 and a P + -type contact layer 217 are formed so as to be sandwiched between the source layers 216.
  • the source layer 216 is configured to have a higher impurity concentration than the drift layer 212, is terminated in the channel layer 213, and formed to be in contact with the side surface of the trench 214.
  • the contact layer 217 is configured to have a higher impurity concentration than the channel layer 213, and is formed to end in the channel layer 213, like the source layer 216.
  • the source layer 216 extends in a rod shape along the longitudinal direction of the trench 214 so as to contact the side surface of the trench 214 in the region between the trenches 214 and terminates inside the tip of the trench 214 It is done. Further, the contact layer 217 is sandwiched between the two source layers 216 and extends in a rod-like shape along the longitudinal direction of the trench 214 (ie, the source layer 216). The contact layer 217 in the present embodiment is formed deeper than the source layer 216 with reference to the one surface 210 a of the semiconductor substrate 210.
  • An interlayer insulating film 218 is formed on the channel layer 213 (that is, one surface 210 a of the semiconductor substrate 210). Then, in the interlayer insulating film 218, a contact hole 218a for exposing a part of the source layer 216 and the contact layer 217 is formed. On interlayer insulating film 218, source electrode 21 electrically connected to source layer 216 and contact layer 217 through contact hole 218a is formed.
  • a drain electrode 22 electrically connected to the drain layer 211 is formed on the other surface 210 b side of the semiconductor substrate 210.
  • the gate pad 24 and the gate wiring 219 are formed in the outer peripheral region 202.
  • the gate wiring 219 is electrically connected to the gate electrode 23 in a cross section different from that in FIG. 7.
  • an annular P-type well region or a plurality of P-type regions surrounding the cell region 201 can be provided so that the withstand voltage can be improved.
  • Guard rings are formed as a multiple ring structure.
  • the semiconductor substrate 210 is configured to include the drain layer 211, the drift layer 212, the channel layer 213, the source layer 216, and the contact layer 217.
  • the first semiconductor chip 100 is mounted on the one surface 300 a of the substrate 300 such that the drain electrode 12 is connected to the first wiring pattern 301 via the bonding member 501. It is done. That is, the first semiconductor chip 100 is mounted such that the gate pad 14 and the not-shown source electrode 11 are on the opposite side to the first wiring pattern 301 side.
  • the second semiconductor chip 200 is mounted on the one surface 300 a of the substrate 300 such that the drain electrode 22 is connected to the second wiring pattern 302 via the bonding member 502. That is, the second semiconductor chip 200 is mounted such that the gate pad 24 and the not-shown source electrode 21 are on the opposite side to the second wiring pattern 302 side.
  • the first semiconductor chip 100 and the second semiconductor chip 200 are also thermally connected to the substrate 300.
  • connection member 503 is formed of a Cu ribbon or the like having a longitudinal direction, one end portion is connected to the source electrode 11 via the bonding member 504, and the other end portion is the second wiring pattern 302 (that is, , And the drain electrode 22) via a bonding member 505.
  • solder or the like is used for each of the bonding members 501, 502, 504, and 505, for example.
  • the source electrode 21 of the second semiconductor chip 200 is connected to the third wiring pattern 303 via the connection member 506.
  • the first wiring pattern 301 is connected to the first terminal 31 via the connection member 507.
  • the third wiring pattern 303 is connected to the second terminal 32 via the connection member 508.
  • the first terminal 31 and the second terminal 32 are each in a flat plate shape, one end side is disposed on the substrate 300 side, and the other end side is disposed on the opposite side to the substrate 300.
  • One end of the first terminal 31 is connected to the connection member 507, and one end of the second terminal 32 is connected to the connection member 508.
  • a Cu ribbon or the like is used as the connection members 506 to 508, and they are connected via solder or the like.
  • the third wiring pattern 303 is for mounting the connection member 507 and the connection member 508 on the same plane. Therefore, the source electrode 21 and the second terminal 32 of the second semiconductor chip 200 may be directly connected via the connection member 506 without the third wiring pattern 303 and the connection member 508.
  • the first to third control terminals 61 to 63 are each in a flat plate shape, one end side is disposed on the substrate 300 side, and the other end side is disposed on the opposite side to the substrate 300.
  • the first control terminal 61 is electrically connected to the gate pad 24 of the second semiconductor chip 200 via the bonding wire 71 at one end, and the other end via the gate drive circuit 51 and the MOSFET adjustment resistor 41. Is connected.
  • One end of the second control terminal 62 is electrically connected to the source electrode 21 of the second semiconductor chip 200 via the bonding wire 72, and the other end is connected to the gate drive circuit 51.
  • One end portion of the third control terminal 63 is electrically connected to the gate pad 14 of the first semiconductor chip 100 via the bonding wire 73.
  • the third control terminal 63 is connected to the other end of the second control terminal 62 via the JFET adjustment resistor 42 on the other end side.
  • the source electrode 21 of the MOSFET 20 and the gate layer 13 of the JFET 10 are connected via the JFET adjustment resistor 42.
  • the JFET adjustment resistor 42 is an externally attached component configured as a separate component from the first semiconductor chip 100 and the second semiconductor chip 200 as described above.
  • the first semiconductor chip 100, the second semiconductor chip 200, the substrate 300, the first terminal 31, the second terminal 32, the first to third control terminals 61 to 63, etc. are sealed in the mold resin 400 and integrated. It is done. Specifically, these are such that the other surface 300b opposite to the one surface 300a of the substrate 300, the first terminal 31, the second terminal 32, and the other end sides of the first to third control terminals 61 to 63 are exposed. , And is sealed by the mold resin 400. As a result, in the present embodiment, the heat generated in the first and second semiconductor chips 100 and 200 is released in the portion of the substrate 300 exposed from the mold resin 400. That is, the semiconductor device of this embodiment has a so-called single-sided heat dissipation structure.
  • the adjustment resistance for JFET 42 is provided in a portion of the second control terminal 62 and the third control terminal 63 exposed from the mold resin 400. That is, the JFET adjustment resistor 42 is provided in a state where it can be easily attached and detached and exchanged.
  • the adjustment resistor for JFET 42 is disposed so as to be exposed from the mold resin 400. Therefore, the JFET adjustment resistor 42 whose resistance value is adjusted can be easily attached and detached and replaced according to the application. Therefore, a highly versatile semiconductor device can be obtained.
  • the JFET adjustment resistor 42 includes a first resistor circuit 421 and a second resistor circuit 422. Therefore, when the semiconductor device is switched on and switched off, it is possible to individually adjust the switching speed to a desired one. Therefore, a highly reliable semiconductor device can be obtained.
  • the second resistor 422b has a smaller value than the first resistor 421b. For this reason, for example, compared with the case where the second resistor 422b has a value larger than that of the first resistor 421b, the switching speed at the time of the switching-off operation can be increased. Then, the switching-off operation of the JFET 10 can quickly follow the switching-off operation of the MOSFET 20. Therefore, even when the MOSFET 20 is switched off, the switching of the JFET 10 is not switched off, so that occurrence of an overvoltage applied to the MOSFET 20 can be suppressed. As a result, the occurrence of avalanche breakdown in the MOSFET 20 can be suppressed, and the reliability of the semiconductor device can be improved.
  • Second Embodiment The second embodiment will be described. This embodiment is different from the first embodiment in that the first semiconductor chip 100 is provided with a temperature sense, and the second semiconductor chip 200 is provided with a current sense. The description is omitted here because it is similar.
  • the first semiconductor chip 100 is formed with the temperature sense 120 for detecting the temperature of the first semiconductor chip 100, and is electrically connected to the temperature sense 120.
  • the temperature sense pads 121 and 122 connected to each other are formed.
  • FIG. 8 is a plan view of the semiconductor device, in order to make the configuration in the mold resin 400 easy to understand, the configuration in the mold resin 400 is indicated by a solid line and the mold resin 400 is indicated by a broken line.
  • a current sense 220 for detecting a current flowing to the second semiconductor chip 200 is formed, and a current sense pad 221 electrically connected to the current sense 220 is formed.
  • a Kelvin source pad 222 electrically connected to the source layer 115 of the MOSFET 20 and having the same potential as the source layer 115 is formed.
  • the ON resistance of the first semiconductor chip 100 is higher than that of the second semiconductor chip 200. That is, the ON resistance of the JFET 10 is higher than that of the MOSFET 20.
  • fourth to seventh control terminals 64 to 67 are disposed around the substrate 300.
  • the fourth to seventh control terminals 64 to 67 are flat like the first and third control terminals 61 and 63, one end side is disposed on the substrate 300 side, and the other end side is disposed on the substrate 300 It is located on the opposite side.
  • One end of the fourth control terminal 64 is electrically connected to the current sense pad 221 of the second semiconductor chip 200 via the bonding wire 74, and the other end is electrically connected to the gate driving circuit 51. There is. As a result, the detection result detected by the current sense 220 is input to the gate drive circuit 51.
  • the fifth control terminal 65 is electrically connected to the Kelvin source pad 222 of the second semiconductor chip 200 via the bonding wire 75, and the other end is connected to the gate drive circuit 51.
  • the fifth control terminal 65 is connected to the other end of the third control terminal 63 via the JFET adjustment resistor 42 on the other end side. Furthermore, the fifth control terminal 65 is connected to the fourth control terminal 64 via the resistor 43 on the other end side.
  • One ends of the sixth and seventh control terminals 66 and 67 are electrically connected to the temperature sense pads 121 and 122 of the first semiconductor chip 100 via the bonding wires 76 and 77, respectively.
  • the other ends of the sixth and seventh control terminals 66 and 67 are electrically connected to the gate drive circuit 51.
  • the detection result detected by the temperature sense 120 is input to the gate drive circuit 51.
  • the gate drive circuit 51 compares the detection result of the current sense 220 and the detection result of the temperature sense 120 with the threshold, and when each detection result is less than the threshold, the gate voltage applied based on the input signal from the external circuit. Control. That is, in the case where the gate drive circuit 51 causes the semiconductor device to perform the switching on operation based on the input signal from the external circuit or to maintain the semiconductor device in the on state, the amount of current flowing through the semiconductor device is appropriate. It is determined whether the chip 100 is at an appropriate temperature. The gate drive circuit 51 applies a predetermined positive gate voltage when it determines that the amount of current flowing through the semiconductor device is appropriate and the first semiconductor chip 100 has an appropriate temperature.
  • the gate drive circuit 51 determines that the detection result of the current sense 220 or the detection result of the temperature sense 120 is equal to or higher than the threshold, the gate drive circuit 51 reduces the gate voltage regardless of the input signal from the external circuit (for example, 0 V ), The semiconductor device is turned off. That is, when the gate drive circuit 51 determines that the current flowing through the semiconductor device is an abnormal current (that is, an overcurrent) and the first semiconductor chip 100 has an abnormal temperature, regardless of the input signal from the external circuit, The gate voltage is reduced and the semiconductor device is turned off.
  • the temperature sense 120 is formed in the first semiconductor chip 100, and the current sense 220 is formed in the second semiconductor chip 200. For this reason, first, as compared with the case where the current sense 220 is formed in each of the first semiconductor chip 100 and the second semiconductor chip 200, the region in the first semiconductor chip 100 can be effectively used. Further, as compared with the case where the temperature sense 120 is formed in each of the first semiconductor chip 100 and the second semiconductor chip 200, the region in the second semiconductor chip 200 can be effectively used.
  • the current sense 220 is disposed in the second semiconductor chip 200.
  • the 2nd semiconductor chip 200 is constituted using a Si substrate, and a manufacturing process becomes easy to become easy rather than the 1st semiconductor chip 100 constituted using a SiC substrate. Therefore, the cost can be reduced. That is, by providing the current sense 220 in the second semiconductor chip 200, the cost of the entire semiconductor device can be reduced.
  • the temperature sense 120 is disposed on the first semiconductor chip 100 having a high on-resistance. That is, since the temperature (that is, the amount of heat generation) depends on the on resistance and increases as the on resistance increases, the temperature sense 120 is formed in the first semiconductor chip 100 in which the temperature tends to be high. Therefore, by adjusting the gate voltage based on the high temperature of the first semiconductor chip 100, the destruction of the first semiconductor chip 100 can be suppressed. That is, destruction of the semiconductor device can be suppressed.
  • the present embodiment is the same as the second embodiment except that the temperature sense 120 is formed in the second semiconductor chip 200 with respect to the second embodiment, and the other respects are the same as the second embodiment, and thus the description thereof is omitted here.
  • the temperature sense 120 is formed in the second semiconductor chip 200.
  • temperature sense pads 121 and 122 are also arranged in the second semiconductor chip 200. That is, in the present embodiment, the temperature of the second semiconductor chip 200 is detected by the temperature sense 120.
  • FIG. 10 is a plan view of the semiconductor device, in order to make the configuration in the mold resin 400 easy to understand, the configuration in the mold resin 400 is shown by a solid line, and the mold resin 400 is shown by a broken line.
  • the gate drive circuit 51 of the present embodiment includes a first semiconductor chip temperature deriving circuit (hereinafter simply referred to as a temperature deriving circuit) 51a, an overheat protection circuit 51b, an overcurrent protection circuit 51c, and a gate output. It has a circuit 51d and the like.
  • a temperature deriving circuit hereinafter simply referred to as a temperature deriving circuit
  • an overheat protection circuit 51b an overcurrent protection circuit 51c
  • a gate output has a circuit 51d and the like.
  • the temperature derivation circuit 51a has a storage unit and a derivation unit (not shown). Then, when a detection signal from the temperature sense 120 formed in the second semiconductor chip 200 is input, the temperature of the first semiconductor chip 100 is derived based on the temperature of the second semiconductor chip 200.
  • a storage unit for example, a non-transitional substantial storage medium such as a memory is used.
  • the temperature change ⁇ T of the JFET 10 (that is, the first semiconductor chip 100) and the MOSFET 20 (that is, the second semiconductor chip 200) differ depending on the flowing current.
  • the relationship between the temperature change ⁇ T of the MOSFET 20 and the temperature change ⁇ T of the JFET 10 can be derived from the relationship of FIG. 12. Therefore, in the storage unit, the relationship between the temperature change ⁇ T of the MOSFET 20 and the temperature change ⁇ T of the JFET 10 is stored in advance.
  • the temperature change ⁇ T of the JFET 10 is four times the temperature change ⁇ T of the MOSFET 20.
  • the temperature derivation circuit 51a calculates the temperature change ⁇ T of the MOSFET 20 from the detection signal. Then, the temperature deriving circuit 51a calculates the temperature change ⁇ T of the JFET 10 from the temperature change ⁇ T of the MOSFET 20, derives the temperature of the JFET 10 from the temperature change ⁇ T, and outputs the temperature to the overheat protection circuit 51b.
  • the overheat protection circuit 51b determines whether the temperature of the second semiconductor chip 200 is equal to or higher than a threshold temperature.
  • the overheat protection circuit 51b determines whether the temperature of the first semiconductor chip 100 is equal to or higher than a threshold.
  • the overheat protection circuit 51b determines that at least one of the temperatures is equal to or higher than the threshold value, the overheat protection circuit 51b outputs a signal indicating an abnormal temperature to the gate output circuit 51d.
  • the overcurrent protection circuit 51c When a detection signal is input from the current sense 220 formed in the second semiconductor chip 200, the overcurrent protection circuit 51c causes the current flowing in the second semiconductor chip 200 (that is, the current flowing in the semiconductor device) to exceed the threshold current. Determine if there is. Then, when it is determined that the current flowing through the second semiconductor chip 200 is equal to or greater than the threshold value, the overcurrent protection circuit 51c outputs a signal indicating that an abnormal current is flowing to the gate output circuit 51d.
  • the gate output circuit 51 d controls the gate voltage applied to the gate electrode 23 of the MOSFET 20 based on an input signal from the external circuit 52 and the like.
  • the gate voltage applied to the gate electrode 23 of the MOSFET 20 is reduced (for example, 0 V). That is, in the present embodiment, the gate voltage is controlled in consideration of the temperature of the first semiconductor chip 100 in which the temperature sense 120 is not formed. Thus, as in the second embodiment, destruction of the semiconductor device can be suppressed.
  • the temperature sense 120 is formed in the second semiconductor chip 200. Therefore, as described above, the second semiconductor chip 200 is configured using the Si substrate, and the manufacturing process is easier than the first semiconductor chip 100 configured using the SiC substrate. Therefore, the cost can be reduced.
  • the source electrode 11 of the first semiconductor chip 100 and the second wiring pattern 302 are connected to each other by a bonding wire in the first embodiment. Further, in the present embodiment, the source electrode 21 of the second semiconductor chip 200 and the third wiring pattern 303 are connected to each other by bonding wires in the first embodiment.
  • the other aspects are the same as in the first embodiment, and thus the description thereof is omitted here.
  • FIG. 14 is a plan view of the semiconductor device, in order to facilitate understanding of the configuration in the mold resin 400, the configuration and the like in the mold resin 400 are indicated by solid lines and the mold resin 400 is indicated by broken lines.
  • connection members 503 and 506 may be configured by bonding wires.
  • the connection members 503 and 506 are connected by bonding wires, the inductance changes and the switching speed changes by changing the number of bonding wires. Therefore, in the present embodiment, the switching speed can be easily changed also by adjusting the number of bonding wires.
  • the present embodiment is different from the first embodiment in that the plurality of first semiconductor chips 100 and the plurality of second semiconductor chips 200 are provided, and the others are the same as the first embodiment. The description is omitted here.
  • three first semiconductor chips 100 are mounted on the first wiring pattern 301.
  • the drain electrode 12 of each first semiconductor chip 100 is electrically connected to the first wiring pattern 301.
  • three second semiconductor chips 200 are mounted on the second wiring pattern 302.
  • the drain electrode 22 of each second semiconductor chip 200 is electrically connected to the second wiring pattern 302.
  • each source electrode 11 is electrically connected to the second wiring pattern 302 via the connection member 503.
  • each source electrode 21 is electrically connected to the third wiring pattern 303 via the connection member 506. That is, the first semiconductor chips 100 and the second semiconductor chips 200 are connected in parallel, respectively.
  • the first terminal 31, the second terminal 32, the adjustment resistor for JFET, the first to third control terminals 61 to 63, the mold resin 400 and the like are omitted.
  • a semiconductor device in which the plurality of first semiconductor chips 100 and the plurality of second semiconductor chips 200 are mounted on the substrate 300 may be used. Also, by arranging a plurality of first semiconductor chips 100 and a plurality of second semiconductor chips 200 in this way, it is compared with the case where one first and second semiconductor chips 100 and 200 having the same size are arranged. Thus, the non-defective efficiency of the wafer can be increased.
  • each first semiconductor chip 100 and each second semiconductor chip 200 are usually configured by being divided into chip units after a predetermined manufacturing process is performed on a wafer. Therefore, for example, as shown in FIG. 16, when the effective area ratio (ie, yield) of the semiconductor chip having 0.1 cm 2 is 95%, three semiconductor chips having 0.5 cm 2 are used. The effective area ratio can be approximately doubled as compared with the case of using a semiconductor chip of 1.5 cm 2 . That is, according to the present embodiment, the cost can be reduced by increasing the non-defective product efficiency of the wafer.
  • the sixth embodiment is a combination of the fifth embodiment and the second embodiment, and is otherwise the same as the fifth embodiment, and therefore the description thereof is omitted here.
  • the three first semiconductor chips 100 are arranged along one direction in the surface direction of the substrate 300 (that is, in the left-right direction in FIG. 17).
  • the temperature sense pads 121 and 122 are formed on the first semiconductor chip 100 located at the center along the arrangement direction of the three first semiconductor chips 100.
  • the temperature sense 120 is also formed on the first semiconductor chip 100 in which the temperature sense pads 121 and 122 are formed. That is, in the present embodiment, the temperature sense 120 and the temperature sense are applied to the first semiconductor chip 100 in which the temperature is most likely to be raised by the influence of the heat generation of the adjacent first semiconductor chips 100 among the three first semiconductor chips 100.
  • Pads 121 and 122 are formed.
  • the three second semiconductor chips 200 are arranged along one direction in the surface direction of the substrate 300 (that is, the left-right direction in the drawing of FIG. 17).
  • the current sense pad 221 and the kelvin source pad 222 are formed on one of the three second semiconductor chips 200.
  • the current sense 220 is also formed on the second semiconductor chip 200 in which the current sense pad 221 is formed.
  • the first terminal 31, the second terminal 32, the adjustment resistor for JFET, the first to third control terminals 61 to 63, the mold resin 400 and the like are omitted.
  • the fifth embodiment may be combined with the second embodiment to include the temperature sense 120 and the current sense 220. Further, in the present embodiment, since the temperature sense 120 is formed only on one first semiconductor chip 100, the area efficiency of the remaining first semiconductor chips 100 can be improved. Similarly, since the current sense 220 is formed only in one second semiconductor chip 200, the area efficiency of the remaining second semiconductor chips 200 can be improved.
  • the temperature sense 120 is formed only on the first semiconductor chip 100 where the temperature tends to be the highest. For this reason, while detecting the temperature which becomes the highest temperature among the first semiconductor chips 100, the area can be effectively used in the other first semiconductor chips 100.
  • the seventh embodiment has a double-sided heat radiation structure with respect to the first embodiment, and the other parts are the same as the first embodiment, so the description will be omitted here.
  • the drain electrode 12 side of the first semiconductor chip 100 is connected to the first lower heat sink 601 via the bonding member 611. Further, the drain electrode 22 side of the second semiconductor chip 200 is connected to the second lower heat sink 602 via the bonding member 612.
  • the rectangular parallelepiped first metal block 603 is mounted on the first semiconductor chip 100 via the bonding member 613, and the first upper heat sink 604 is formed on the first metal block 603 via the bonding member 614. It is arranged.
  • the first metal block 603 is disposed on the source electrode 11 formed in the first semiconductor chip 100, and has a planar shape substantially equal to the planar shape of the source electrode 11.
  • a rectangular second metal block 605 is mounted on the second semiconductor chip 200 via a bonding member 615, and a second upper heat sink 606 is disposed on the second metal block 605 via a bonding member 616. ing.
  • the second metal block 605 is disposed on the source electrode 21 formed in the second semiconductor chip 200, and has a planar shape substantially equal to the planar shape of the source electrode 21.
  • the first semiconductor chip 100 is disposed between the first lower heat sink 601 and the first upper heat sink 604 which are disposed to face each other.
  • the second semiconductor chip 200 is disposed between the second lower heat sink 602 and the second upper heat sink 606 which are disposed to face each other.
  • the first upper heat sink 604 and the second lower heat sink 602 are connected by an intermediate member 607.
  • the intermediate member 607 is integrally formed with the second lower heat sink 602, and is joined to the first upper heat sink 604 via the joining member 617.
  • the first lower heat sink 601, the second lower heat sink 602, the first upper heat sink 604, the second upper heat sink 606, the first metal block 603, and the second metal block 605 are made of, for example, Cu or the like. Be done. Also, each of the bonding members 611 to 617 is configured using, for example, a solder.
  • the gate pad 14 of the first semiconductor chip 100 is electrically connected to the third control terminal 63 via the bonding wire 73.
  • the gate pad 24 of the second semiconductor chip 200 is electrically connected to the first control terminal 61 via the bonding wire 71.
  • the second control terminal 62 electrically connected to the source electrode 21 of the second semiconductor chip 200 is disposed, and the second control terminal 62 and the third control terminal 63 are provided.
  • the adjustment resistance 42 for JFET is arrange
  • the first lower heat sink 601 is connected to the first terminal 31, and the second upper heat sink 606 is connected to the second terminal 32.
  • the first terminal 31 may be configured as a part of the first lower heat sink 601
  • the second terminal 32 may be configured as a part of the second upper heat sink 606.
  • the intermediate member 607 may be configured as a separate member from the second lower heat sink 602 and may be joined to the second lower heat sink 602 via a joining member. Furthermore, the intermediate member 607 may be integrated with the first upper heat sink 604 and be joined to the second lower heat sink 602 via a joining member.
  • the mold resin 400 is provided so that the portion of the first lower heat sink 601 and the first upper heat sink 604 opposite to the first semiconductor chip 100 is exposed.
  • the mold resin 400 is provided so that the portion of the second lower heat sink 602 and the second upper heat sink 606 on the opposite side to the second semiconductor chip 200 is exposed.
  • the first and second semiconductor chips 100 and 200 are exposed at portions of the first and second lower heat sinks 601 and 602 and the first and second upper heat sinks 604 and 606 exposed from the mold resin 400.
  • the heat generated by is released. That is, the semiconductor device of this embodiment has a so-called double-sided heat radiation structure.
  • the circuit configuration shown in FIG. 1 can be realized, and the same effect as that of the first embodiment can be obtained. Further, the heat is easily released from the first semiconductor chip 100 and the second semiconductor chip 200 by adopting the double-sided heat radiation structure, and the first semiconductor chip 100 and the second semiconductor chip 200 are broken when the temperature becomes high. Can be suppressed.
  • the substrate 300 is provided as in the first embodiment, and the first semiconductor chip 100 and the second semiconductor chip 200 are provided. May be mounted on the substrate 300.
  • the eighth embodiment is the same as the first embodiment except that the first semiconductor chip 100 and the second semiconductor chip 200 are stacked and arranged with respect to the seventh embodiment. I omit explanation.
  • the first semiconductor chip 100 is stacked on the lower heat sink 601 via the bonding member 611, and the first semiconductor chip 100 is stacked on the first semiconductor chip 100 via the bonding member 613.
  • a metal block 603 is disposed.
  • the second semiconductor chip 200 is disposed on the first metal block 603 via a bonding member 618 formed of solder or the like. That is, the second semiconductor chip 200 is stacked and disposed on the first semiconductor chip 100.
  • the second metal block 605 is disposed on the second semiconductor chip 200 via the bonding member 615, and the upper heat sink 604 is disposed on the second metal block 605 via the bonding member 616.
  • the first semiconductor chip 100 has a planar shape larger than that of the second semiconductor chip 200.
  • the first semiconductor chip 100 is arranged such that the gate pad 14 is located outside the second semiconductor chip when viewed in the stacking direction of the first semiconductor chip 100 and the second semiconductor chip 200.
  • the first semiconductor chip 100 is connected to the third control terminal 63 via a bonding wire 73.
  • the second semiconductor chip 200 is connected to the first control terminal 61 via a bonding wire 71.
  • the second control terminal 62 electrically connected to the source electrode 21 of the second semiconductor chip 200 is disposed in a cross section different from that of FIG. .
  • the JFET adjustment resistor 42 is disposed between the second control terminal 62 and the third control terminal 63.
  • the mold resin 400 is provided so that the portion of the lower heat sink 601 and the upper heat sink 604 opposite to the first and second semiconductor chips 100 and 200 is exposed.
  • the ninth embodiment A ninth embodiment will be described.
  • the ninth embodiment is the same as the eighth embodiment except that the first semiconductor chip 100 is smaller than the second semiconductor chip 200 with respect to the eighth embodiment, so the description will be omitted here. .
  • the first semiconductor chip 100 is smaller than the second semiconductor chip 200. Therefore, when the rectangular first metal block 603 is disposed as it is on the first semiconductor chip 100 and the second semiconductor chip 200 is disposed on the first metal block 603, the following configuration is obtained. That is, a part of the drain electrode 22 of the second semiconductor chip 200 is not connected to the first metal block 603. In this case, electrical and mechanical connection failures may occur between the first metal block 603 and the second semiconductor chip 200.
  • the spacer 608 is disposed between the first semiconductor chip 100 and the first metal block 603.
  • the first metal block 603 is bonded to the spacer 608 via a bonding member 619 made of solder or the like.
  • the spacer 608 is made of Cu or the like, and has a planar shape corresponding to the first semiconductor chip 100. Specifically, the spacer 608 has a planar shape substantially equal to the size of the source electrode 11 in the first semiconductor chip 100. Further, the first metal block 603 has a planar shape corresponding to the second semiconductor chip 200. Specifically, the first metal block 603 has a planar shape substantially equal to the size of the drain electrode 22 in the second semiconductor chip 200. As a result, the second semiconductor chip 200 is securely bonded to the first metal block 603, and the occurrence of electrical and mechanical bonding defects is suppressed.
  • the second control terminal 62 electrically connected to the source electrode 21 of the second semiconductor chip 200 is disposed in a cross section different from that in FIG. .
  • the JFET adjustment resistor 42 is disposed between the second control terminal 62 and the third control terminal 63.
  • the planar shape of the first semiconductor chip 100 is smaller than that of the second semiconductor chip 200.
  • Spacer 608 is disposed between the first semiconductor chip 100 and the first metal block 603, . Therefore, a junction area between the first metal block 603 and the drain electrode 22 in the second semiconductor chip 200 can be sufficiently secured.
  • the spacer 608 By disposing the spacer 608, the distance between the first semiconductor chip 100 and the first metal block 603 can be widened. Therefore, it is possible to secure a space where the bonding wire 73 connecting the gate pad 14 of the first semiconductor chip 100 and the third control terminal 63 is arranged.
  • a chip whose planar shape is smaller than that of the second semiconductor chip 200 can be used as the first semiconductor chip 100, and the degree of freedom in design can be improved.
  • the tenth embodiment is one in which the semiconductor devices of the seventh embodiment are arranged side by side, and the other parts are the same as the seventh embodiment, so the description will be omitted here.
  • the configuration of the portion excluding the mold resin 400 described in the seventh embodiment is a component
  • two components 631 and 632 are arranged side by side.
  • the respective constituent members 631 and 632 are sealed by the mold resin 400.
  • the second upper heat sink 606 in the component member 631 and the first lower heat sink 601 in the component member 632 are connected by the intermediate member 609.
  • the intermediate member 609 is integrally formed with the first lower heat sink 601 in the component member 632, and is joined to the first upper heat sink 604 in the component member 631 via the joining member 620.
  • the intermediate member 609 may be configured as a separate member from the first lower heat sink 601 in the component member 632 and may be joined to the first lower heat sink 601 in the component member 632 via a joining member. Further, the intermediate member 609 may be integrated with the first upper heat sink 604 in the component member 631 and may be joined to the first lower heat sink 601 in the component member 632 via a joining member. Furthermore, in the cross section different from FIG. 21, the first and second control terminals 61 and 62 connected to the second semiconductor chip 200 of the component 631 are disposed. In addition, a third control terminal 63 connected to the first semiconductor chip 100 of the component member 632 and a second control terminal 62 connected to the second semiconductor chip 200 of the component member 632 are disposed. The JFET adjustment resistor 42 is disposed between the second control terminal 62 and the third control terminal 63 in each of the component members 631, 632.
  • the semiconductor device may be provided with the two components 631 and 632.
  • the structure provided with the two structural members 631, 632 was demonstrated here, the several structural member may be further provided.
  • the eleventh embodiment is an arrangement in which the semiconductor devices of the eighth embodiment are arranged side by side, and the other respects are the same as those of the eighth embodiment, and thus the description thereof is omitted here.
  • the configuration of the portion excluding the mold resin 400 described in the eighth embodiment is a component member
  • two component members 633 and 634 are arranged side by side.
  • the respective constituent members 633 and 634 are sealed by the mold resin 400.
  • the intermediate member 610 is integrally formed with the lower heat sink 601 in the component member 634, and is joined to the upper heat sink 604 in the component member 633 via the joining member 621.
  • the intermediate member 610 may be configured as a separate member from the lower heat sink 601 in the component member 634, and may be joined to the lower heat sink 601 in the component member 634 via a joining member.
  • the intermediate member 610 may be integrated with the upper heat sink 604 in the component 633 and may be joined to the lower heat sink 601 in the component 634 via a joining member.
  • each second control terminal 62 connected to the second semiconductor chip 200 of the component 633, 634 is disposed.
  • the JFET adjustment resistor 42 is disposed between the second control terminal 62 and the third control terminal 63 in each of the constituent members 633 and 634.
  • the semiconductor device may be provided with two component members 633 and 634.
  • the structure provided with the two structural members 634 and 634 was demonstrated here, the several structural member may be further provided.
  • the MOSFET adjustment resistor 41 has the following configuration. That is, the MOSFET adjustment resistor 41 is a fourth resistor circuit 411 in which the third diode 411a and the third resistor 411b are connected in series, and a fourth resistor circuit in which the fourth diode 412a and the fourth resistor 412b are connected in series. And a resistor circuit 412.
  • the third resistance circuit 411 and the fourth resistance circuit 412 are arranged in parallel so that the cathode of the third diode 411a and the anode of the fourth diode 412a are connected to the gate electrode 23 of the MOSFET 20, respectively.
  • the MOSFET adjustment resistor 41 is a component packaged including the third resistor circuit 411 and the fourth resistor circuit 412, and is a separate component different from the first semiconductor chip 100 and the second semiconductor chip 200. It is an external part configured as That is, the MOSFET adjustment resistor 41 is disposed so as to be exposed from the mold resin 400. Therefore, the MOSFET adjustment resistor 41 whose resistance value is adjusted can be easily attached and detached and replaced according to the application.
  • the fourth resistor 412 b has a larger value than the third resistor 411 b. More specifically, the fourth resistor 412 b controls the switching speed when the semiconductor device is turned off as described later, and has a resistance value according to the desired desired application.
  • the gate electrode 23 of the MOSFET 20 and the gate drive circuit 51 are connected via such a MOSFET adjustment resistor 41. Therefore, the switching speed of the MOSFET 20 is adjusted by different resistance circuits in the switching on operation and the switching off operation.
  • the gate electrode 23 of the MOSFET 20 is connected to the gate drive circuit 51 via the third resistance circuit 411 when performing the switching on operation. That is, the third resistance circuit 411 functions as a speed adjustment resistor for the switching on operation of the MOSFET 20.
  • the gate electrode 23 of the MOSFET 20 is connected to the gate drive circuit 51 via the fourth resistance circuit 412 when performing the switching off operation. That is, the fourth resistance circuit 412 functions as a speed adjustment resistor for the switching off operation of the MOSFET 20. Therefore, by adjusting the resistance values of the respective resistance circuits 411 and 412, the switching speed of the MOSFET 20 can be appropriately adjusted.
  • Such a semiconductor device is used, for example, as a switching element of an inverter circuit for driving a three-phase motor as shown in FIG.
  • the inverter circuit has three U, V and W phases between power supply line 710 to which voltage Vcc from power supply 700 is applied and ground line 720 connected to ground.
  • a circuit is provided.
  • Each layer is connected to the gate drive circuit 51 and the three-phase motor M, respectively.
  • the detailed configuration of the U layer will be described with reference to FIG.
  • V layer and W layer is the same as that of U layer, it is abbreviate
  • the U layer has a configuration in which two semiconductor devices shown in FIG. 23 are provided.
  • the drain electrode 12 of the JFET 10 in the upper arm is connected to the power supply line 710 via the first terminal 31, and the source electrode 21 of the MOSFET 20 in the lower arm is grounded via the second terminal 32. It is connected to the line 720.
  • the source electrode 21 of the MOSFET 20 in the upper arm is electrically connected to the drain electrode 12 of the JFET 10 in the lower arm. That is, the second terminal 32 of the upper arm is electrically connected to the first terminal 31 of the lower arm.
  • the three-phase motor M is connected between the second terminal 32 of the upper arm and the first terminal 31 of the lower arm.
  • the gate electrodes 23 of the MOSFETs 20 in the upper and lower arms are connected to the gate drive circuit 51, respectively.
  • the semiconductor device of this embodiment can be used as a switching element of an inverter circuit.
  • the gate electrode 23 of the MOSFET 20 is connected to the gate drive circuit 51 via the third resistance circuit 411 when performing the switching on operation.
  • the gate electrode 23 of the MOSFET 20 is connected to the gate drive circuit 51 via the fourth resistance circuit 412 when the switching off operation is performed. Therefore, when the semiconductor device is to be switched on and off, it is possible to adjust the semiconductor device to have a desired switching speed. Therefore, a semiconductor device with higher reliability can be obtained.
  • the semiconductor device of the twelfth embodiment is used for the inverter circuit for driving the three-phase motor M
  • the semiconductor device of the first embodiment also naturally drives the three-phase motor M It can also be used in circuits.
  • the basic configuration of the semiconductor device is the same as that of the twelfth embodiment.
  • the second resistor 422b is formed of a wiring resistance, a parasitic resistance or the like, and an external resistance is not used.
  • the first resistance 421b is in the order of tens to hundreds of ohms
  • the second resistance 422b is in the order of several ohms.
  • the third resistor 411b is formed of a wiring resistor, a parasitic resistor, etc., and an external resistor is not used.
  • the third resistor 411b is several ohms
  • the fourth resistor 412b is on the order of tens to hundreds of ohms.
  • the 1st resistance circuit 421 is not equipped with the 1st diode 421a in adjustment resistance 42 for JFETs.
  • the fourth resistor circuit 412 is not provided with the fourth diode 412a.
  • the second resistor 422b is smaller than the first resistor 421b. Therefore, when the JFET 10 performs the switching off operation, the gate layer 13 of the JFET 10 substantially functions as the source electrode of the MOSFET 20 through the second resistor 422 b without arranging the first diode 421 a in the first resistance circuit 421. 21 and connected.
  • the third resistor 411b is set to a smaller value than the fourth resistor 412b. Therefore, when the MOSFET 20 is switched on, the gate electrode 23 of the MOSFET 20 is substantially connected to the gate drive circuit 51 via the third resistor 411 b without arranging the fourth diode 412 a. Become.
  • the present embodiment it is possible to obtain the same effect as the twelfth embodiment while reducing the number of parts.
  • the present embodiment is also applicable to only one of the MOSFET adjustment resistor 41 and the JFET adjustment resistor 42. That is, for example, the first diode 421a is not disposed in the first resistor circuit 421 of the JFET adjustment resistor 42, and the fourth diode 412a is disposed in the fourth resistor circuit 412 of the MOSFET adjustment resistor 41. You may Further, as in the first embodiment, the MOSFET adjustment resistor 41 may be configured of only a resistance component.
  • the first semiconductor chip 100 (that is, the JFET 10) may be configured not to include the body layer 116.
  • the body layer 116 may not be deeper than the gate layer 13 as long as the bottom side of the body layer 116 is likely to have a higher electric field strength than the bottom side of the gate layer 13.
  • the bottom side of the body layer 116 has a higher electric field strength than the bottom side of the gate layer 13 by making the bottom of the body layer 116 tapered or making the width of the body layer 116 narrower than the width of the gate layer 13.
  • the configuration may be easy.
  • the region connected to the bottom of the body layer 116 an N-type region having a higher impurity concentration than the region connected to the bottom of the gate layer 13, the electric field strength of the bottom of the body layer 116 is higher than the bottom of the gate 13. May be configured to be high.
  • the configuration of the adjustment resistor for JFET 42 may be changed. For example, even if a switch is provided and the gate current is adjusted by the first resistor 421b when the semiconductor device is switched on, the gate current is adjusted by the second resistor 422b when switched off. Good.
  • the JFET 10 and the MOSFET 20 may be appropriately P-channel type.
  • the first semiconductor chip 100 and the second semiconductor chip 200 may be provided with the temperature sense 120 and the current sense 220, respectively.
  • the overheat protection circuit 51b is formed of the first semiconductor chip 100 derived by the temperature deriving circuit 51a. Only the temperature may be determined.
  • the temperature sense 120 and the temperature sense pads 121 and 122 may be formed on each of the first semiconductor chips 100.
  • each second semiconductor chip 200 may be provided with a current sense 220, a current sense pad 221, and a Kelvin source pad 222.
  • the first metal block 603 and the spacer 608 may be integrated.
  • the first metal block 603 may be configured to have a projection that functions as the spacer 608 by appropriately cutting or polishing the portion on the first semiconductor chip 100 side.
  • the JFET 10 may be configured to be normally off, and the MOSFET 20 may be configured to be normally on.
  • the JFET adjustment resistor 42 may be disposed in the mold resin 400 as long as it has the first resistor circuit 421 and the second resistor circuit 422.
  • the first resistor 421b and the second resistor 422b may have the same size, or the first resistor 421b may be smaller than the second resistor 422b.
  • the third resistor 411b and the fourth resistor 412b may have the same size, or the third resistor 411b may be smaller than the fourth resistor 412b.
  • each said embodiment may be combined suitably.
  • the second embodiment may be combined with the seventh to thirteenth embodiments to form the temperature sense 120, the current sense 220, and the like.
  • the third embodiment may be combined with the sixth to thirteenth embodiments to form the temperature sense 120, the current sense 220, etc. in the second semiconductor chip 200.
  • the fifth and sixth embodiments may be combined with the seventh to thirteenth embodiments to provide a plurality of first semiconductor chips 100 and second semiconductor chips 200.
  • the seventh to eleventh embodiments may be combined with the twelfth and thirteenth embodiments. Furthermore, combinations of the above embodiments may be further combined.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention comprend : un JFET (10) ; un transistor MOS (20) ; et une résistance de réglage de JFET (42) disposée entre une électrode grille (13) du JFET (10) et une électrode source (21) du transistor MOS (20). Le JFET (10) et le transistor MOS (20) sont configurés de telle sorte qu'une électrode source (11) du JFET (10) et une électrode drain (22) du transistor MOS (20) sont connectées électriquement et en cascade. La résistance de réglage de JFET (42) comprend un premier circuit de résistance (421) servant à une opération de mise sous tension et un second circuit de résistance (422) servant à une opération de mise hors tension.
PCT/JP2018/028143 2017-07-26 2018-07-26 Dispositif semiconducteur WO2019022206A1 (fr)

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CN201880048889.7A CN110998810B (zh) 2017-07-26 2018-07-26 半导体装置
US16/695,422 US11101259B2 (en) 2017-07-26 2019-11-26 Semiconductor device

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JP2017144727 2017-07-26
JP2017-144727 2017-07-26
JP2018117317A JP6769458B2 (ja) 2017-07-26 2018-06-20 半導体装置
JP2018-117317 2018-06-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7470086B2 (ja) 2021-09-13 2024-04-17 株式会社東芝 半導体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012522410A (ja) * 2009-03-27 2012-09-20 エー・テー・ハー・チューリッヒ カスコード回路を有するスイッチング装置
JP2013153079A (ja) * 2012-01-25 2013-08-08 Toyota Motor Corp 半導体装置およびその製造方法
JP2014220434A (ja) * 2013-05-09 2014-11-20 古河電気工業株式会社 半導体装置
JP2015015301A (ja) * 2013-07-03 2015-01-22 株式会社デンソー 半導体装置
JP2015056564A (ja) * 2013-09-12 2015-03-23 古河電気工業株式会社 半導体装置及びその製造方法
WO2015166523A1 (fr) * 2014-04-28 2015-11-05 株式会社日立産機システム Dispositif à semi-conducteurs et dispositif de conversion de puissance
JP2017051049A (ja) * 2015-09-04 2017-03-09 富士電機株式会社 半導体素子の駆動装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012522410A (ja) * 2009-03-27 2012-09-20 エー・テー・ハー・チューリッヒ カスコード回路を有するスイッチング装置
JP2013153079A (ja) * 2012-01-25 2013-08-08 Toyota Motor Corp 半導体装置およびその製造方法
JP2014220434A (ja) * 2013-05-09 2014-11-20 古河電気工業株式会社 半導体装置
JP2015015301A (ja) * 2013-07-03 2015-01-22 株式会社デンソー 半導体装置
JP2015056564A (ja) * 2013-09-12 2015-03-23 古河電気工業株式会社 半導体装置及びその製造方法
WO2015166523A1 (fr) * 2014-04-28 2015-11-05 株式会社日立産機システム Dispositif à semi-conducteurs et dispositif de conversion de puissance
JP2017051049A (ja) * 2015-09-04 2017-03-09 富士電機株式会社 半導体素子の駆動装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7470086B2 (ja) 2021-09-13 2024-04-17 株式会社東芝 半導体装置

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