WO2019019763A1 - 一种化合物半导体器件的背面制程方法 - Google Patents

一种化合物半导体器件的背面制程方法 Download PDF

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Publication number
WO2019019763A1
WO2019019763A1 PCT/CN2018/086009 CN2018086009W WO2019019763A1 WO 2019019763 A1 WO2019019763 A1 WO 2019019763A1 CN 2018086009 W CN2018086009 W CN 2018086009W WO 2019019763 A1 WO2019019763 A1 WO 2019019763A1
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Prior art keywords
layer
wafer
compound semiconductor
back surface
semiconductor device
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PCT/CN2018/086009
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English (en)
French (fr)
Inventor
周泽阳
邱宗德
庄秉翰
魏鸿基
程海英
吴小琦
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厦门市三安集成电路有限公司
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Publication of WO2019019763A1 publication Critical patent/WO2019019763A1/zh
Priority to US16/745,705 priority Critical patent/US11264231B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Definitions

  • the present invention relates to a semiconductor device fabrication process, and more particularly to a backside process method for a compound semiconductor device.
  • HBTs Heterojunction bipolar transistors
  • HEMTs high electron mobility transistors
  • Advanced multifunction devices must consider not only the performance of integrated circuits, but also the cost of the product. In order to achieve this goal, many efforts have been made to the development and improvement of reliable manufacturing processes.
  • the device backside fabrication process is one of the key process steps in the fabrication of integrated semiconductor devices. Regardless of the device type and function, it is necessary to provide grounding for those transistors fabricated on the front surface of the semiconductor chip.
  • the grounding plate is composed of a surface metal layer, a back through hole and a back metal layer, and the back metal layer is in electrical contact with the surface metal layer through the back through hole.
  • HBT or HEMT devices start with a surface metal layer from the front surface.
  • Back-end processes typically require mechanical grinding to thin the wafer thickness to facilitate subsequent wafer via etching processes. The location, size and shape of the holes are made using conventional photolithographic techniques, dry or wet chemical etching.
  • the backside metal layer is deposited on the backside of the wafer, whereby good electrical contact with the surface metal layer via the backside vias can be achieved.
  • the surface metal layer of the ground plane is not only in electrical contact with the entire backside metal layer through the via, but also in thermal contact, acting as a front surface device for the heat sink.
  • a conventional device back surface process includes a process of a back scribe line, which is performed by photolithography to etch a back metal to form a dicing street; then, separation of a wafer and a wafer support material, such as thermal separation or solvent separation; Finally, the wafer is cut into small chips by the position corresponding to the scribe line.
  • the formation of the back scribe line requires a yellow process and a chemical etching of the metal. The process is very cumbersome, and the cost of the day, material and labor is high. This is because the conventional mechanical dicing method cannot cut the back metal layer of about 5 ⁇ m. Therefore, it must be etched to form a scribe line.
  • Laser scribing is a recent development of new technology that can directly perform cutting on metals or semiconductors.
  • a composite structure of a semiconductor and a metal for example, a GaAs semiconductor wafer having a back metal process
  • the back side The mainstream process of metal is TiW/Au composite layer, and TiW and GaAs semiconductor are combined by van der Waals force.
  • the bonding force is weak. After the laser cutting, the metal peeling phenomenon is easily generated at the edge of the contact surface of the two, and the reliability of the product is invalid. Therefore, it is inevitable that the cutting process is required first, and it is difficult to directly cut. technical problem
  • a back surface processing method of a compound semiconductor device includes the following steps:
  • the TiW layer has a thickness of 2 to 10 nm;
  • the second scan repeats the path of the first scan to cut the wafer into discrete chips.
  • the moving speed of the laser dicing is 100 ⁇ 400 mm/s.
  • the power of the laser is 3.0 ⁇ 6.5W.
  • the laser incident angle is perpendicular to the back surface of the wafer.
  • the wafer is ground to a thickness of 70-120 ⁇ m.
  • the first scanning forms a plurality of linear first slots parallel to the first direction
  • the Au layer is formed by depositing a seed layer of 10 to 250 nm and then depositing by electroplating.
  • the NiV layer and the TiW layer are deposited on the semiconductor chip by magnetron sputtering atomic precipitation to form a thin film.
  • the III-V compound semiconductor is gallium arsenide, indium phosphide or gallium nitride.
  • the interlayer bonding ability between the back metal and the III-V compound semiconductor is improved, and the fabricated III-V compound semiconductor wafer can be directly scanned by the laser through the secondary scanning.
  • FIG. 1 is a schematic structural view of a GaAs wafer in which a back metal process is completed;
  • FIG. 2 is an optical micrograph of the back side of a GaAs wafer that performs laser scribing
  • 3 is an optical micrograph of the back side of a GaAs chip that is completed
  • FIG. 4 is an optical micrograph of the back side of a single chip.
  • a backside process method for a compound semiconductor device is to laminate a III-V compound semiconductor wafer having a front side process on a support material in a front-down manner, to perform polishing and thinning, and to fabricate a back via hole.
  • the III-V compound semiconductor is gallium arsenide, indium phosphide or gallium nitride
  • the wafer is ground to a thickness of 70-120 ⁇ m
  • a NiV layer is deposited on the back side of the wafer, and the NiV layer is composed of a mass fraction.
  • the moving speed of the laser dicing is 100-400 mm/s
  • the power of the laser is 3.0-6.5 W
  • the incident angle of the laser is perpendicular to the back surface of the wafer
  • the first scanning is formed along the first direction.
  • the method of the present invention can perform direct dicing of a compound semiconductor with a back metal by a laser.
  • GaAs semiconductor wafer will be specifically described as an example.
  • the GaAs wafer 1 on which the front side process has been completed is attached to the support material 2 in a face-down manner, the polishing is thinned to 100 ⁇ m, and then the back via hole 11 is formed by a photolithography process.
  • a NiV layer 3 having a thickness of 100 nm is deposited on the back surface 1 of the wafer by magnetron sputtering, and the NiV layer is composed of nickel having a mass fraction of 95% and 5% of vanadium;
  • Controlled sputtering deposits a TiW layer 4 on the NiV layer 3, the TiW layer 4 having a thickness of 6 nm, and the NiV layer 3 and the TiW layer 4 as an adhesion layer.
  • a 100 nm thick Au seed layer is deposited on the Ti layer 4 by means of a radio frequency magnetron, a DC magnetron, an RF diode, an ion beam sputtering or an electron beam deposition method, and then a 5 ⁇ thick Au plating layer is deposited by electroplating.
  • the plating layer and the seed layer constitute the Au layer 5.
  • Ni can form NiGa and NiAs with GaAs at a relatively low temperature of magnetron sputtering deposited on the surface of the GaAs wafer, that is, a thin layer is formed by chemical bonding between the GaAs semiconductor and the metal layer.
  • the bonding layer in combination with other metal van der Waals forces, greatly enhances the bonding force, and thus is less susceptible to peeling by external force or other energy.
  • the nickel-based alloy After adding a certain amount of vanadium to nickel, the nickel-based alloy exhibits non-magnetic properties and is advantageous for magnetron sputtering.
  • TiW has strong bonding ability with both NiV and Au, and the same as a diffusion barrier prevents Au from diffusing into the GaAs semiconductor. Through the setting of the NiV/TiW adhesive layer, the interlayer bonding ability is greatly improved.
  • the wafer 1 and the support material 2 are separated by a thermal separation method or a solvent separation method, and the front surface of the wafer 1 is attached to a sheet having elasticity and adhesion, and is diced by laser.
  • Technique focusing the laser on the metal on the back side of the wafer and performing a second scan.
  • the path of the first scan is sequentially traveling in the X direction and the Y direction, thereby forming a plurality of linear first slits in the parallel X direction and a plurality of linear second slits in the parallel Y direction, wherein the X direction and the Y direction are perpendicular to each other .
  • the thickness of the slit for the first scan is about 50% of the total thickness of the wafer, for example, about 55 ⁇ m.
  • the second scan is then repeated for a second scan to further deepen the grooving to the bottom to completely separate the wafers into discrete chiplets, see Figure 2.
  • the scanning speed of the two scanning lasers is 100 ⁇ 400
  • the laser power is 5W
  • the laser incident angle is perpendicular to the back of the wafer.
  • the edge of the chiplet after laser dicing is flat, no metal peeling occurs, and no discoloration defect occurs.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Dicing (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)
  • Led Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本发明公开了一种化合物半导体器件的背面制程方法，是在III-V族化合物半导体晶片的背面依次沉积形成NiV/Ti的粘合层以及Au层，然后将激光聚焦在完成背面金属制程的晶片背面并进行二次扫描，其中第一次扫描形成深度为所述晶片总厚度40~60%的切槽，第二次扫描重复第一次扫描的路径以将晶片切割成分立的小芯片。通过NiV/Ti粘结层的设置，提高了背面金属和III-V族化合物半导体之间的层间结合能力，制成的晶片可以直接用激光扫描切割达到划片的目的，而无需蚀刻背面金属形成切割道再来进行切割，不仅减少了黄光、刻蚀等多项工艺，而且解决由非均匀腐蚀引起的变色的缺陷，切割后的产品其边缘不会出现金属剥离的现象，显著提高产品的良率。

Description

发明名称：一种化合物半导体器件的背面制程方法 技术领域
[0001] 本发明涉及半导体器件制作工艺， 特别是涉及一种化合物半导体器件的背面制 程方法。
背景技术
[0002] 异质结双极晶体管 (HBT)以及高电子迁移率晶体管 (HEMT)是重要的半导体电子 器件， 在微波、 毫米波、 光电等领域具有重要的应用。 先进的多功能器件不仅 要考虑集成电路的性能， 而且需要考虑产品成本的降低。 为了实现这一目标， 对可靠制造工艺的幵发和改进进行了许多努力。
[0003] 器件背面制造过程是集成半导体器件的制造的一个关键流程步骤之一。 无论器 件类型和功能， 都需要为在半导体芯片的前表面上制造的那些晶体管提供接地 。 接地盘由表面金属层， 背面通孔和背面金属层组成， 背面金属层通过背面通 孔与表面金属层电接触。 通常 HBT或者 HEMT器件先从前端表面幵始制作表面 金属层。 后端制程通常需要机械研磨使晶片厚度变薄以方便后续的晶片通孔刻 蚀工艺。 孔洞的位置、 大小和形状通过使用传统的光刻技术、 干法或湿化学蚀 刻来制成。 背侧金属层沉积在晶片背侧上， 由此可以实现经由背侧通孔与表面 金属层的良好电接触。 接地面的表面金属层不仅通过通孔与整个背侧金属层电 接触， 而且热接触， 充当散热器的正面器件。
[0004] 通常， 传统的器件背面工艺包含背面切割道的制程， 是通过光刻技术蚀刻背面 金属以形成切割道； 然后是晶片和晶片支撑材料的分离， 有热分离法或者溶剂 分离法等； 最后通过对应切割道的位置将晶圆切成小芯片。 形成背面切割道需 要黄光制程以及金属的化学蚀刻等步骤， 过程十分繁琐， 吋间、 材料及人力成 本都较高， 这是由于传统的机械式划片方法无法切割 5μηι左右厚度的背面金属层 ， 因而必须加以蚀刻形成切割道。
[0005] 激光划片是近来发展的新技术， 可以直接对金属或半导体实施切割。 但是对于 半导体和金属的复合结构一例如完成背面金属制程的 GaAs半导体晶片， 背面 金属的主流工艺是 TiW/Au的复合层， TiW与 GaAs半导体之间通过范德华力结合
， 结合力较弱， 激光切割后在两者的接触面边缘极易产生金属剥离的现象， 而 导致产品的可靠性失效， 因而仍然不可避免的需要先进行切割道制程， 难以直 接进行切割。 技术问题
问题的解决方案
技术解决方案
[0006] 本发明的目的在于克服现有技术之不足， 提供一种无需形成切割道的化合物半 导体器件的背面制程方法。
[0007] 本发明解决其技术问题所采用的技术方案是：
[0008] 一种化合物半导体器件的背面制程方法包括以下步骤：
[0009] 1) 将已完成正面制程的 III-V族化合物半导体晶片以正面向下的方式贴合于支 撑材料上， 进行研磨减薄以及制作背面通孔的工艺；
[0010] 2) 于所述晶片背面沉积 NiV层， 所述 NiV层由质量分数为 90~97%的镍以及 3~1
0%的钒组成， 厚度为 3~200nm;
[0011] 3) 于所述 NiV层上沉积 TiW层， 所述 TiW层厚度为 2~10nm;
[0012] 4) 于所述 TiW层上沉积 Au层， 所述 Au层的厚度为 0.5~25μηι;
[0013] 5) 将完成背面金属制程的晶片与支撑材料分离， 利用激光划片技术， 将激光 聚焦在晶片背面并进行二次扫描， 其中第一次扫描形成深度为所述晶片总厚度 4
0~60%的切槽， 第二次扫描重复第一次扫描的路径以将所述晶片切割成分立的芯 片。
[0014] 优选的， 所述激光划片的移动速度为 100~400 mm/s。
[0015] 优选的， 所述激光的功率为 3.0~6.5W。
[0016] 优选的， 所述激光入射角度与所述晶片背面垂直。
[0017] 优选的， 步骤 1) 中， 所述晶片研磨减薄至 70~120μηι。
[0018] 优选的， 所述第一次扫描形成平行第一方向的多个线状第一切槽
方向的多个线状第二切槽， 且所述第一方向和第二方向互相垂直。 [0019] 优选的， 所述 Au层是先沉积 10~250nm的种子层， 然后通过电镀沉积形成。
[0020] 优选的， 所述 NiV层和 TiW层通过磁控溅射原子沉淀积累在半导体芯片而形成 薄膜。
[0021] 优选的， 所述 III- V族化合物半导体是砷化镓， 磷化铟或镓氮化物。
发明的有益效果
有益效果
[0022] 本发明的有益效果是：
[0023] 通过 NiV/TiW粘结层的设置， 提高了背面金属和 III- V族化合物半导体之间的层 间结合能力， 制成的 III- V族化合物半导体晶片可以直接用激光通过二次扫描切 割达到划片的目的， 而无需蚀刻背面金属形成切割道再来进行切割， 不仅减少 了背面金属光阻涂布的步骤， 减少光阻用量及制成吋间， 减少化学药剂及水的 使用亦可减少废液的处理， 减少贵金属金的回收流程， 大大减少制作半导体器 件成本和吋间， 提高产量； 避免了因非均匀腐蚀引起的变色等缺陷， 切割后的 产品其边缘不会出现金属剥离的现象， 显著提高产品的良率， 加速产品的产业 化进程。
对附图的简要说明
附图说明
[0024] 图 1为完成背面金属制程的 GaAs晶片的结构示意图；
[0025] 图 2为完成激光划片的 GaAs晶片背面的光学显微镜照片；
[0026] 图 3为完成伸展的 GaAs芯片背面的光学显微镜照片；
[0027] 图 4是单个芯片背面的光学显微镜照片。
本发明的实施方式
[0028] 以下结合附图及实施例对本发明作进一步详细说明。 本发明的各附图仅为示意 以更容易了解本发明， 其具体比例可依照设计需求进行调整。 文中所描述的图 形中相对元件的上下关系， 在本领域技术人员应能理解是指构件的相对位置而 言， 因此皆可以翻转而呈现相同的构件， 此皆应同属本说明书所揭露的范围。 此外， 图中所示的元件及结构的个数， 均仅为示例， 并不以此对数目进行限制 ， 实际可依照设计需求进行调整。
[0029] 一种化合物半导体器件的背面制程方法， 是将已完成正面制程的 III-V族化合物 半导体晶片以正面向下的方式贴合于支撑材料上， 进行研磨减薄以及制作背面 通孔的工艺， 所述 III- V族化合物半导体是砷化镓， 磷化铟或镓氮化物， 所述晶 片研磨减薄至 70~120μηι; 于所述晶片背面沉积 NiV层， 所述 NiV层由质量分数为 90~97%的镍以及 3~10%的钒组成， 厚度为 3~200nm; 于所述 NiV层上沉积 Ti层， 所述 Ti层厚度为 2~10nm; 于所述 Ti层上沉积 Au层， 所述 Au层的厚度为 0.5~25μηι ， 所述 Au层是先沉积 10~250nm的种子层， 然后通过电镀沉积形成； 将完成背面 金属制程的晶片与支撑材料分离， 利用激光划片技术， 将激光聚焦在晶片背面 并进行二次扫描， 其中第一次扫描形成深度为所述晶片总厚度 40~60%的切槽， 第二次扫描重复第一次扫描的路径以将所述晶片切割成分立的小芯片， 所述激 光划片的移动速度为 100~400 mm/s， 所述激光的功率为 3.0~6.5W， 所述激光入 射角度与所述晶片背面垂直， 所述第一次扫描形成沿第一方向平行排列的多个 线状第一切槽以及沿第二方向平行排列的多个线状第二切槽， 且所述第一方向 和第二方向互相垂直。 本发明的方法可通过激光进行带背面金属的化合物半导 体的直接切割。
[0030] 以下以 GaAs半导体晶片为例进行具体的说明。
[0031] 将已完成正面制程的 GaAs晶片 1以正面向下的方式贴合于支撑材料 2上， 研磨 减薄至 100μηι， 然后通过光刻工艺制作背面通孔 11。 通过清洗去除氧化层后， 通 过磁控溅射于所述晶片背面 1沉积厚度为 lOOnm厚的 NiV层 3， 所述 NiV层由质量 分数为 95%的镍以及 5%的钒组成； 然后通过磁控溅射于所述 NiV层 3上沉积 TiW 层 4， 所述 TiW层 4厚度为 6nm， NiV层 3和 TiW层 4作为粘合层。 然后通过射频磁 控管、 DC磁控管、 RF二极管、 离子束溅射或电子束沉积等方法于所述 Ti层 4上 沉积 lOOnm厚的 Au种子层， 然后通过电镀沉积 5μηι厚的 Au电镀层， 电镀层和种 子层组成 Au层 5， 具体结构请参考图 1。
[0032] 其中， Ni在磁控溅射沉积于 GaAs晶片表面的相对低的温度下可以与 GaAs作用 形成 NiGa和 NiAs， 即 GaAs半导体和金属层间通过化学键合结合形成一层薄薄的 结合层， 相对于其他金属范德华力的结合方式， 大大增强了结合力， 因而不易 受外力或其他能量作用而发生剥离。 镍中添加一定量的钒后， 镍基合金呈现非 磁性也利于磁控溅射。 TiW与 NiV和 Au均具有较强的结合能力， 同吋作为扩散阻 挡层防止 Au扩散进入 GaAs半导体中。 通过 NiV/TiW粘合层的设置， 大大提高了 层间结合能力。
[0033] 完成背面金属制程后， 将晶片 1与支撑材料 2通过热分离法或者溶剂分离法进行 分离， 将晶片 1正面贴附于具有伸缩性和粘结性的片材上， 利用激光划片技术， 将激光聚焦在晶片背面的金属上并进行二次扫描。 第一次扫描的路径是依次沿 X 方向和 Y方向行进， 从而形成平行 X方向的若干线状第一切槽和平行 Y方向的若 干线状第二切槽， 其中 X方向和 Y方向互相垂直。 本实施例中， 第一次扫描的切 槽的厚度为晶片总厚度的 50%左右， 例如约为 55μηι。 然后重复第一次扫描的路 径进行第二次扫描以将切槽进一步加深至底部， 从而将晶片完全分隔形成分立 的小芯片， 参考图 2。 两次扫描激光的移动速度为 100~400
mm/s, 激光的功率为 5W， 激光入射角度与晶片背面垂直。 激光划片完成后， 通 过伸展片材使小芯片之间彼此远离形成一定的间隔， 具体参考图 3。
[0034] 参考图 4， 通过激光划片后的小芯片其边缘平整， 未发生金属剥离的现象， 也 没有变色缺陷产生。
[0035] 上述实施例仅用来进一步说明本发明的一种化合物半导体器件的背面制程方法 ， 但本发明并不局限于实施例， 凡是依据本发明的技术实质对以上实施例所作 的任何简单修改、 等同变化与修饰， 均落入本发明技术方案的保护范围内。

Claims

权利要求书
一种化合物半导体器件的背面制程方法， 其特征在于包括以下步骤： 将已完成正面制程的 III-V族化合物半导体晶片以正面向下的方式贴合 于支撑材料上， 进行研磨减薄以及制作背面通孔的工艺；
于所述晶片背面沉积 NiV层， 所述 NiV层由质量分数为 90~97%的镍以 及 3~10%的钒组成， 厚度为 3~200nm;
于所述 NiV层上沉积 Ti层， 所述 TiW层厚度为 2~10nm;
于所述 Ti层上沉积 Au层， 所述 Au层的厚度为 0.5~25μιη;
将完成背面金属制程的晶片与支撑材料分离， 利用激光划片技术， 将 激光聚焦在晶片背面并进行二次扫描， 其中第一次扫描形成深度为所 述晶片总厚度 40~60%的切槽， 第二次扫描重复第一次扫描的路径以 将所述晶片切割成分立的芯片。
根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 所述激光划片的移动速度为 100~400 mm/s。
根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 所述激光的功率为 3.0~6.5W。
根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 所述激光入射角度与所述晶片背面垂直。
根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 步骤 1) 中， 所述晶片研磨减薄至 70~120μηι。
根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 所述第一次扫描形成平行第一方向的多个线状第一切槽以及平行 第二方向的多个线状第二切槽， 且所述第一方向和第二方向互相垂直 根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 所述 Au层是先沉积 10~250nm的种子层， 然后通过电镀沉积形成
[权利要求 8] 根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 所述 NiV层和 TiW层通过磁控溅射原子沉淀积累在半导体芯片而 形成薄膜。
[权利要求 9] 根据权利要求 1所述的化合物半导体器件的背面制程方法， 其特征在 于： 所述 III- V族化合物半导体是砷化镓， 磷化铟或镓氮化物。
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