WO2019015185A1 - 时钟信号输出电路及液晶显示装置 - Google Patents

时钟信号输出电路及液晶显示装置 Download PDF

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Publication number
WO2019015185A1
WO2019015185A1 PCT/CN2017/111435 CN2017111435W WO2019015185A1 WO 2019015185 A1 WO2019015185 A1 WO 2019015185A1 CN 2017111435 W CN2017111435 W CN 2017111435W WO 2019015185 A1 WO2019015185 A1 WO 2019015185A1
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Prior art keywords
unit
clock signal
electrically connected
field effect
effect transistor
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PCT/CN2017/111435
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English (en)
French (fr)
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张先明
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深圳市华星光电半导体显示技术有限公司
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Priority to KR1020207004528A priority Critical patent/KR102285161B1/ko
Priority to EP17917966.8A priority patent/EP3657486A4/en
Priority to JP2020502256A priority patent/JP6906825B2/ja
Priority to US15/579,944 priority patent/US10339877B2/en
Publication of WO2019015185A1 publication Critical patent/WO2019015185A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a clock signal output circuit and a liquid crystal display device.
  • LCD Liquid crystal display
  • PDA personal digital assistant
  • digital camera computer screen Or laptop screens, etc.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the gate scan driving circuit is directly fabricated on the thin film transistor array substrate by using an array process ( Gate Driver on Array (GOA) to replace the external gate scan driver IC and other technologies is also a hot topic for many LCD panel manufacturers to further reduce production costs.
  • GOA Gate Driver on Array
  • the GOA technology can use the array process of the liquid crystal display panel to fabricate the gate driving circuit on the TFT array substrate to realize the driving mode of the gate progressive scanning.
  • an initial clock signal is generally boosted by a level shifter and output to a GOA circuit of a liquid crystal display panel. Due to the large number of clock signals in the GOA, short circuits are prone to occur due to the process.
  • an overcurrent protection (OCP) unit is provided at the output of the level shifting unit to overcurrent. Detecting, when there is an overcurrent, the overcurrent protection unit can control the level unit switching to stop outputting the clock signal outward, which can effectively avoid the problem of the melting screen caused by the short circuit signal.
  • Another object of the present invention is to provide a liquid crystal display device capable of preventing erroneously triggering overcurrent protection of a peak current generated when a liquid crystal display device is quickly switched.
  • the present invention first provides a clock signal output circuit, including a clock signal conversion unit, a voltage dividing unit, a protection signal generating unit, an overcurrent protection unit, and a switching unit;
  • the input end of the clock signal conversion unit is connected to the initial clock signal, and the output end is electrically connected to the first end of the switch unit and outputs the converted clock signal; the first end of the voltage dividing unit is electrically connected to the switch unit The second end is electrically connected to the display panel;
  • the protection signal generating unit includes a subtractor, a comparator, a switch, a current source, and a capacitor; and the non-inverting input terminal and the inverting input terminal of the subtractor are respectively electrically Connecting the first end and the second end of the voltage dividing unit, the output end is electrically connected to the non-inverting input end of the comparator; the inverting input end of the comparator is connected to the reference voltage, and the output end is electrically connected to the control end of the switch;
  • the first end and the second end are respectively electrically connected to the first end and the second end of the capacitor, and the switch is closed when its control end is at a high level, and is turned off when its control end is at a low level;
  • the overcurrent protection unit is configured to generate a corresponding control signal to control the switch unit when the voltage of the first input terminal is greater than or equal to a predetermined protection value, and the current of the second input terminal is greater than a preset current value for a predetermined time. cutoff.
  • the clock signal conversion unit includes: a logic controller, a first field effect transistor, and a second field effect transistor; an input end of the logic controller is an input end of the clock signal conversion unit, and an output end is electrically connected a gate of an effect transistor and a gate of the second field effect transistor; a drain of the first field effect transistor is connected to a constant voltage high potential, and a source is electrically connected to a drain of the second field effect transistor and is a clock An output end of the signal conversion unit; the source of the second FET is connected to a constant voltage low potential;
  • the logic controller is configured to control the on or off of the first FET and the second FET according to the initial clock signal, so that the output of the clock signal conversion unit outputs the converted clock signal.
  • the first field effect transistor is an N-type field effect transistor
  • the second field effect transistor is a P-type field effect tube.
  • the voltage dividing unit is a resistor.
  • the clock signal conversion unit and the protection signal generation unit are disposed on the same level conversion chip.
  • the display panel has a GOA circuit; the second end of the voltage dividing unit is electrically connected to the GOA circuit of the display panel.
  • the switching unit is a third FET, the gate of the third FET is the control end of the switching unit, the drain is the first end of the switching unit, and the source is the second end of the switching unit.
  • the present invention also provides a liquid crystal display device comprising the above-described clock signal output circuit.
  • the invention also provides a clock signal output circuit, comprising a clock signal conversion unit, a voltage dividing unit, a protection signal generating unit, an overcurrent protection unit, and a switching unit;
  • the input end of the clock signal conversion unit is connected to the initial clock signal, and the output end is electrically connected to the first end of the switch unit and outputs the converted clock signal; the first end of the voltage dividing unit is electrically connected to the switch unit The second end is electrically connected to the display panel;
  • the protection signal generating unit includes a subtractor, a comparator, a switch, a current source, and a capacitor; and the non-inverting input terminal and the inverting input terminal of the subtractor are respectively electrically Connecting the first end and the second end of the voltage dividing unit, the output end is electrically connected to the non-inverting input end of the comparator; the inverting input end of the comparator is connected to the reference voltage, and the output end is electrically connected to the control end of the switch;
  • the first end and the second end are respectively electrically connected to the first end and the second end of the capacitor, and the switch is closed when its control end is at a high level, and is turned off when its control end is at a low level;
  • the overcurrent protection unit is configured to generate a corresponding control signal to control the switch unit when the voltage of the first input terminal is greater than or equal to a predetermined protection value, and the current of the second input terminal is greater than a preset current value for a predetermined time. cutoff;
  • the clock signal conversion unit includes: a logic controller, a first field effect transistor, and a second field effect transistor; an input end of the logic controller is an input end of the clock signal conversion unit, and an output end is electrically Connecting the gate of the first field effect transistor and the gate of the second field effect transistor; the drain of the first field effect transistor is connected to a constant voltage high potential, and the source is electrically connected to the drain of the second field effect transistor and An output end of the clock signal conversion unit; the source of the second FET is connected to a constant voltage low potential;
  • the logic controller is configured to control the on or off of the first FET and the second FET according to the initial clock signal, so that the output of the clock signal conversion unit outputs the converted clock signal;
  • the voltage dividing unit is a resistor
  • the clock signal conversion unit and the protection signal generation unit are disposed on the same level conversion chip;
  • the display panel has a GOA circuit; the second end of the voltage dividing unit is electrically connected to the GOA circuit of the display panel.
  • the present invention provides a clock signal output circuit including a clock signal conversion unit, a switch unit, a voltage dividing unit, a protection signal generating unit, and an overcurrent protection unit, wherein the protection signal generating unit includes a subtractor The comparator, the switch, the current source, and the capacitor, when the clock signal output circuit outputs a clock signal to the display panel, the peak current generated after the second power-on of the fast switching machine flows through the voltage dividing unit, so that the current source cannot be Charging the voltage at the first end of the capacitor to a predetermined protection value, and when the peak current disappears, the current source can quickly charge the voltage at the first end of the capacitor to a preset protection value and input the overcurrent protection unit to start
  • the overcurrent protection function prevents the peak current erroneously triggered overcurrent protection generated when the liquid crystal display device is quickly switched.
  • the liquid crystal display device provided by the present invention can prevent the peak current erroneously triggering overcurrent protection generated when the liquid crystal display device is quickly switched.
  • FIG. 1 is a circuit diagram of a clock signal output circuit of the present invention.
  • the present invention provides a clock signal output circuit, including a clock signal conversion unit 100, a voltage dividing unit 200, a protection signal generating unit 300, an overcurrent protection unit 400, and a switching unit 500;
  • the input end of the clock signal conversion unit 100 is connected to the initial clock signal CK, and the output end is electrically connected to the first end of the switch unit 500 and outputs the converted clock signal CK'; the first end of the voltage dividing unit 200
  • the second end of the switch unit 500 is electrically connected to the display panel 10;
  • the protection signal generating unit 300 includes a subtractor 310, a comparator 320, a switch S1, a current source DC, and a capacitor C1.
  • the non-inverting input terminal and the inverting input terminal of the subtractor 310 are electrically connected to the first end and the second end of the voltage dividing unit 200, respectively, and the output end is electrically connected to the non-inverting input end of the comparator 320; the inverting input end of the comparator 320
  • the reference voltage Vref is connected, and the output end is electrically connected to the control end of the switch S1; the first end and the second end of the switch S1 are electrically connected to the capacitor respectively
  • the first end and the second end of the C1, and the switch S1 is closed when its control terminal is high level, and is turned off when its control terminal is low level; the first end of the capacitor C1 is electrically connected to the current source DC
  • the first input end of the overcurrent protection unit 400 is electrically connected to the first end of the capacitor C1, and the second input end is electrically connected to the first end or the second end of the voltage dividing unit 200.
  • the output end is electrically connected to the control end of the switch unit 500
  • the overcurrent protection unit 400 is configured to generate a corresponding control signal control switch when the voltage of the first input terminal is greater than or equal to a predetermined protection value, and the current of the second input terminal is greater than a preset current value for a predetermined time.
  • Unit 500 is turned off.
  • the clock signal conversion unit 100 includes: a logic controller 110, a first FET Q1, and a second FET Q2; an input end of the logic controller 110 For the input end of the clock signal conversion unit 100, the output end is electrically connected to the gate of the first FET Q1 and the gate of the second FET Q2; the drain of the first FET Q1 is connected a constant voltage high potential VGH, the source is electrically connected to the drain of the second field effect transistor Q2 and is the output end of the clock signal conversion unit 100; the source of the second field effect transistor Q2 is connected to the constant voltage low potential VGL;
  • the logic controller 110 is configured to control the on or off of the first FET Q1 and the second FET Q2 according to the initial clock signal CK, so that the output of the clock signal conversion unit 100 outputs the converted clock signal CK'. .
  • the first field effect transistor Q1 is an N-type field effect transistor
  • the second field effect transistor Q2 is a P-type field effect transistor.
  • the voltage dividing unit 200 is a resistor R1.
  • the voltage dividing unit 200 can also be configured as a plurality of resistors in series or in parallel, or other components having a voltage dividing function.
  • the clock signal conversion unit 100 and the protection signal generating unit 300 are disposed on the same level conversion chip.
  • the display panel 10 has a GOA circuit 11; the second end of the voltage dividing unit 200 is electrically connected to the GOA circuit 11 of the display panel 10.
  • the switch unit 500 is a third FET Q3, the gate of the third FET Q3 is the control end of the switch unit 500, the drain is the first end of the switch unit 500, and the source is the switch unit 500. Second end.
  • the third field effect transistor Q3 may be an N-type field effect transistor or a P-type field effect transistor.
  • the third field effect transistor Q3 is an N-type field effect transistor, correspondingly, the voltage of the overcurrent protection unit 400 at the first input end thereof is greater than or equal to the preset protection value, and the current of the second input terminal is greater than the a control signal that generates a low potential when the current value is preset and continues for the preset time is controlled to be turned off, and the voltage at the first input terminal thereof is less than the preset protection value, or the first thereof
  • the control signal that generates the high potential controls the switch unit 500 to be turned on; when the third field effect transistor is turned on;
  • Q3 is a P-type field effect transistor, correspondingly, the voltage of the overcurrent protection unit 400 at the first input end thereof is greater than or equal to the preset
  • the control signal that generates a high potential at the preset time controls the switch unit 500 to be turned off, the voltage at the first input end thereof is less than the preset protection value, or the voltage at the first input end thereof is greater than or equal to the preset protection value but
  • the control signal that controls the switching unit 500 is turned on when the current of the second input terminal does not satisfy the preset current value and continues to generate a low potential for a preset time.
  • the clock signal output circuit of the present invention when applied to a liquid crystal display device to output a clock signal to the display panel 10, in the case of a liquid crystal display device quickly switching on and off, there is a peak current flow after the second power-on.
  • the voltage is divided by the unit 200, and the output of the subtractor 310 outputs a voltage difference across the voltage dividing unit 200.
  • the voltage difference is positively correlated with the current flowing through the voltage dividing unit 200, so that the voltage value of the reference voltage Vref can be specifically selected.
  • the voltage at the output end of the subtractor 310 that is, the voltage difference across the voltage dividing unit 200 is greater than the reference voltage Vref, so that the output terminal of the comparator 320 outputs a high potential to the control terminal of the switch S1.
  • the switch S1 is turned off, that is, when the peak current flows through the voltage dividing unit 200, the first end of the capacitor C1 is grounded to discharge the capacitor C1, and the liquid crystal display device can be second in the specific setting of the preset protection value.
  • the current source DC cannot charge the voltage of the first end of the capacitor C1 to the preset protection value at the time when the secondary power has a peak current, and when the peak current disappears, the reference is passed.
  • the specific selection of the voltage Vref voltage value can make the voltage of the output terminal of the subtractor 310 always lower than the reference voltage Vref, that is, the output end of the comparator 320 is always low, the switch S1 is always disconnected, and the current source DC can be quickly.
  • the voltage of the first end of the capacitor C1 is charged to a preset protection value and input to the first input end of the overcurrent protection unit 400, after which when a current greater than the preset current value flows into the second input end of the current protection unit 400, and The current continues for a preset time, and the overcurrent protection unit 400 generates a corresponding control signal, and the control switch unit 500 is turned off, that is, the output of the clock signal to the display panel 10 is stopped, thereby achieving overcurrent protection, and the overcurrent protection only disappears at the peak current. It will be carried out later, which can effectively prevent the peak current erroneously triggered overcurrent protection generated when the liquid crystal display device is quickly switched.
  • the present invention further provides a liquid crystal display device comprising the above-mentioned clock signal output circuit, which can prevent the peak current erroneously triggered overcurrent protection generated when the liquid crystal display device is quickly switched, and no longer outputs the clock signal.
  • a liquid crystal display device comprising the above-mentioned clock signal output circuit, which can prevent the peak current erroneously triggered overcurrent protection generated when the liquid crystal display device is quickly switched, and no longer outputs the clock signal.
  • the clock signal output circuit of the present invention includes a clock signal conversion unit, a switch unit, a voltage dividing unit, a protection signal generating unit, and an overcurrent protection unit, wherein the protection
  • the signal generating unit includes a subtractor, a comparator, a switch, a current source, and a capacitor.
  • the unit prevents the current source from charging the voltage at the first end of the capacitor to a predetermined protection value, and when the peak current disappears, the current source can quickly charge the voltage at the first end of the capacitor to a preset protection value and input
  • the overcurrent protection unit activates the overcurrent protection function to prevent the peak current erroneously triggered overcurrent protection generated when the liquid crystal display device is quickly switched.
  • the liquid crystal display device provided by the present invention can prevent the peak current erroneously triggering overcurrent protection generated when the liquid crystal display device is quickly switched.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Electronic Switches (AREA)

Abstract

一种时钟信号输出电路及液晶显示装置。时钟信号输出电路包括时钟信号转换单元（100）、开关单元（500）、分压单元（200）、保护信号产生单元（300）、及过电流保护单元（400），其中，保护信号产生单元（300）包括减法器（310）、比较器（320）、开关（S1）、电流源（DC）、及电容（C1），在利用时钟信号输出电路向显示面板（10）输出时钟信号（CK'）时，快速开关机的第二次起电后产生的峰值电流流过分压单元（200），使电流源（DC）无法将电容（C1）第一端的电压充电至一预设的保护值，而当峰值电流消失后，电流源（DC）可快速地将电容（C1）第一端的电压充电至预设的保护值并输入过电流保护单元（400），启动过电流保护功能，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。

Description

时钟信号输出电路及液晶显示装置 技术领域
本发明涉及液晶显示领域，尤其涉及一种时钟信号输出电路及液晶显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(Backlight Module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
随着液晶显示装置产业制造技术的不断发展，降低成本已是目前业界最主要的发展方向之一。除了优化液晶显示装置的制程、开发新型材料来降低生产成本以外，将相关功能模块、电路等集成至液晶显示面板内部，如利用阵列制程将栅极扫描驱动电路直接制作在薄膜晶体管阵列基板上(Gate Driver on Array，GOA)来取代外接的栅极扫描驱动IC等技术也是众多液晶显示面板厂商争相开发的热点内容，以进一步降低生产成本。GOA技术可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA电路中一般需要接入若干时钟信号，以实现其栅极逐行扫描的功能。现有技术中，通常利用电平转换单元(level shifter)将初始的时钟信号进行升压后输出至液晶显示面板的GOA电路中。由于GOA内部的时钟信号走线较多，由于制程的原因，容易出现短路，为了防止液晶显示面板被烧坏，会在电平转换单元的输出端设置过电流保护(OCP)单元对过电流进行侦测，当有过电流时，过电流保护单元能够控制电平单元转换停止向外输出时钟信号，能够有效避免由时钟信号短路导致的熔屏的问题。液晶显示装置在实际的使用过程中，由于快速的开关机，使第二次起电的时候，液晶显示面板中的部分栅线没有 关闭，这个时候就会导致有大电流出现，触发过电流保护，但是这种大电流属于安全的大电流，并不会造成液晶显示面板的异常，也即误触发了过电流保护。
发明内容
本发明的目的在于提供一种时钟信号输出电路，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。
本发明的另一目的在于提供一种液晶显示装置，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。
为实现上述目的，本发明首先提供一种时钟信号输出电路，包括时钟信号转换单元、分压单元、保护信号产生单元、过电流保护单元、及开关单元；
所述时钟信号转换单元的输入端接入初始的时钟信号，输出端电性连接开关单元的第一端并输出转换后的时钟信号；所述分压单元的第一端电性连接开关单元的第二端，第二端电性连接显示面板；所述保护信号产生单元包括减法器、比较器、开关、电流源、及电容；所述减法器的同相输入端及反相输入端分别电性连接分压单元的第一端及第二端，输出端电性连接比较器的同相输入端；比较器的反相输入端接入参考电压，输出端电性连接开关的控制端；所述开关的第一端及第二端分别电性连接电容的第一端及第二端，且所述开关在其控制端为高电平时闭合，在其控制端为低电平时断开；所述电容的第一端电性连接电流源的输出端，第二端接地；所述过电流保护单元的第一输入端电性连接电容的第一端，第二输入端电性连接分压单元的第一端或第二端，输出端电性连接开关单元的控制端；
所述过电流保护单元用于在其第一输入端的电压大于等于一预设保护值、且第二输入端的电流大于一预设电流值并持续一预设时间时产生对应的控制信号控制开关单元截止。
所述时钟信号转换单元包括：逻辑控制器、第一场效应管、及第二场效应管；所述逻辑控制器的输入端为所述时钟信号转换单元的输入端，输出端电性连接第一场效应管的栅极及第二场效应管的栅极；所述第一场效应管的漏极接入恒压高电位，源极电性连接第二场效应管的漏极且为时钟信号转换单元的输出端；所述第二场效应管的源极接入恒压低电位；
所述逻辑控制器用于根据初始时钟信号控制第一场效应管及第二场效应管的导通或截止，使时钟信号转换单元的输出端输出转换后的时钟信号。
所述第一场效应管为N型场效应管，所述第二场效应管为P型场效应 管。
所述分压单元为一电阻。
所述时钟信号转换单元及保护信号产生单元设于同一电平转换芯片上。
所述显示面板具有GOA电路；所述分压单元的第二端与显示面板的GOA电路电性连接。
所述开关单元为第三场效应管，所述第三场效应管的栅极为开关单元的控制端，漏极为开关单元的第一端，源极为开关单元的第二端。
本发明还提供一种液晶显示装置，包括上述的时钟信号输出电路。
本发明还提供一种时钟信号输出电路，包括时钟信号转换单元、分压单元、保护信号产生单元、过电流保护单元、及开关单元；
所述时钟信号转换单元的输入端接入初始的时钟信号，输出端电性连接开关单元的第一端并输出转换后的时钟信号；所述分压单元的第一端电性连接开关单元的第二端，第二端电性连接显示面板；所述保护信号产生单元包括减法器、比较器、开关、电流源、及电容；所述减法器的同相输入端及反相输入端分别电性连接分压单元的第一端及第二端，输出端电性连接比较器的同相输入端；比较器的反相输入端接入参考电压，输出端电性连接开关的控制端；所述开关的第一端及第二端分别电性连接电容的第一端及第二端，且所述开关在其控制端为高电平时闭合，在其控制端为低电平时断开；所述电容的第一端电性连接电流源的输出端，第二端接地；所述过电流保护单元的第一输入端电性连接电容的第一端，第二输入端电性连接分压单元的第一端或第二端，输出端电性连接开关单元的控制端；
所述过电流保护单元用于在其第一输入端的电压大于等于一预设保护值、且第二输入端的电流大于一预设电流值并持续一预设时间时产生对应的控制信号控制开关单元截止；
其中，所述时钟信号转换单元包括：逻辑控制器、第一场效应管、及第二场效应管；所述逻辑控制器的输入端为所述时钟信号转换单元的输入端，输出端电性连接第一场效应管的栅极及第二场效应管的栅极；所述第一场效应管的漏极接入恒压高电位，源极电性连接第二场效应管的漏极且为时钟信号转换单元的输出端；所述第二场效应管的源极接入恒压低电位；
所述逻辑控制器用于根据初始时钟信号控制第一场效应管及第二场效应管的导通或截止，使时钟信号转换单元的输出端输出转换后的时钟信号；
其中，所述分压单元为一电阻；
其中，所述时钟信号转换单元及保护信号产生单元设于同一电平转换芯片上；
其中，所述显示面板具有GOA电路；所述分压单元的第二端与显示面板的GOA电路电性连接。
本发明的有益效果：本发明提供的一种时钟信号输出电路，包括时钟信号转换单元、开关单元、分压单元、保护信号产生单元、及过电流保护单元，其中，保护信号产生单元包括减法器、比较器、开关、电流源、及电容，在利用该时钟信号输出电路向显示面板输出时钟信号时，快速开关机的第二次起电后产生的峰值电流流过分压单元，使电流源无法将电容第一端的电压充电至一预设的保护值，而当峰值电流消失后，电流源可快速地将电容第一端的电压充电至预设的保护值并输入过电流保护单元，启动过电流保护功能，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。本发明提供的一种液晶显示装置，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的时钟信号输出电路的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种时钟信号输出电路，包括时钟信号转换单元100、分压单元200、保护信号产生单元300、过电流保护单元400、及开关单元500；
所述时钟信号转换单元100的输入端接入初始的时钟信号CK，输出端电性连接开关单元500的第一端并输出转换后的时钟信号CK’；所述分压单元200的第一端电性连接开关单元500的第二端，第二端电性连接显示面板10；所述保护信号产生单元300包括减法器310、比较器320、开关S1、电流源DC、及电容C1；所述减法器310的同相输入端及反相输入端分别电性连接分压单元200的第一端及第二端，输出端电性连接比较器320的同相输入端；比较器320的反相输入端接入参考电压Vref，输出端电性连接开关S1的控制端；所述开关S1的第一端及第二端分别电性连接电容 C1的第一端及第二端，且所述开关S1在其控制端为高电平时闭合，在其控制端为低电平时断开；所述电容C1的第一端电性连接电流源DC的输出端，第二端接地；所述过电流保护单元400的第一输入端电性连接电容C1的第一端，第二输入端电性连接分压单元200的第一端或第二端，输出端电性连接开关单元500的控制端；
所述过电流保护单元400用于在其第一输入端的电压大于等于一预设保护值、且第二输入端的电流大于一预设电流值并持续一预设时间时产生对应的控制信号控制开关单元500截止。
具体地，在本发明的一实施例中，所述时钟信号转换单元100包括：逻辑控制器110、第一场效应管Q1、及第二场效应管Q2；所述逻辑控制器110的输入端为所述时钟信号转换单元100的输入端，输出端电性连接第一场效应管Q1的栅极及第二场效应管Q2的栅极；所述第一场效应管Q1的漏极接入恒压高电位VGH，源极电性连接第二场效应管Q2的漏极且为时钟信号转换单元100的输出端；所述第二场效应管Q2的源极接入恒压低电位VGL；
所述逻辑控制器110用于根据初始时钟信号CK控制第一场效应管Q1及第二场效应管Q2的导通或截止，使时钟信号转换单元100的输出端输出转换后的时钟信号CK’。
具体地，所述第一场效应管Q1为N型场效应管，所述第二场效应管Q2为P型场效应管。
具体地，所述分压单元200为一电阻R1。当然所述分压单元200也可设置为多个电阻串联或并联的结构，或者采用其他具有分压功能的元件。
优选地，所述时钟信号转换单元100及保护信号产生单元300设于同一电平转换芯片上。
具体地，所述显示面板10具有GOA电路11；所述分压单元200的第二端与显示面板10的GOA电路11电性连接。
具体地，所述开关单元500为第三场效应管Q3，所述第三场效应管Q3的栅极为开关单元500的控制端，漏极为开关单元500的第一端，源极为开关单元500的第二端。
进一步地，所述第三场效应管Q3可为N型场效应管或P型场效应管。当第三场效应管Q3为N型场效应管时，对应地，所述过电流保护单元400在其第一输入端的电压大于等于所述预设保护值、且第二输入端的电流大于所述预设电流值并持续所述预设时间时产生低电位的控制信号控制开关单元500截止，在其第一输入端的电压小于所述预设保护值、或者其第一 输入端的电压大于等于所述预设保护值但其第二输入端的电流没有满足大于预设电流值并持续预设时间时产生高电位的控制信号控制开关单元500导通；当第三场效应管Q3为P型场效应管时，对应地，所述过电流保护单元400在其第一输入端的电压大于等于所述预设保护值、且第二输入端的电流大于所述预设电流值并持续所述预设时间时产生高电位的控制信号控制开关单元500截止，在其第一输入端的电压小于所述预设保护值、或者其第一输入端的电压大于等于所述预设保护值但其第二输入端的电流没有满足大于预设电流值并持续预设时间时产生低电位的控制信号控制开关单元500导通。
需要说明的是，在将本发明的时钟信号输出电路应用于液晶显示装置中向显示面板10输出时钟信号时，液晶显示装置快速开关机的情况下，第二次起电后会有峰值电流流过分压单元200，而减法器310的输出端输出的为分压单元200两端的电压差，该电压差与流过分压单元200的电流正相关，因此可通过对参考电压Vref电压值的具体选取，使有峰值电流流过分压单元200后，减法器310输出端的电压也即分压单元200两端的电压差大于参考电压Vref，使比较器320的输出端输出高电位至开关S1的控制端控制开关S1关闭，也即有峰值电流流过分压单元200的时刻，电容C1的第一端会接地使电容C1放电，通过对预设的保护值的具体设定，可使液晶显示装置在第二次起电有峰值电流的时刻内电流源DC无法将电容C1第一端的电压充电至该预设的保护值，而当峰值电流消失后，通过对参考电压Vref电压值的具体选取，可使减法器310的输出端的电压始终小于参考电压Vref，也即比较器320的输出端始终为低电位，开关S1始终断开，电流源DC可快速地将电容C1第一端的电压充电至预设的保护值并输入至过电流保护单元400的第一输入端，此后当有大于预设电流值的电流流入电流保护单元400的第二输入端，并且该电流持续预设时间，过电流保护单元400即产生对应的控制信号，控制开关单元500截止，也即停止向显示面板10输出时钟信号，实现过电流保护，同时过电流保护仅在峰值电流消失后才会进行，能够有效防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。
基于同一发明构思，本发明还提供一种液晶显示装置，包括上述的时钟信号输出电路，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护，在此不再对时钟信号输出电路的结构进行赘述。
综上所述，本发明的时钟信号输出电路，包括时钟信号转换单元、开关单元、分压单元、保护信号产生单元、及过电流保护单元，其中，保护 信号产生单元包括减法器、比较器、开关、电流源、及电容，在利用该时钟信号输出电路向显示面板输出时钟信号时，快速开关机的第二次起电后产生的峰值电流流过分压单元，使电流源无法将电容第一端的电压充电至一预设的保护值，而当峰值电流消失后，电流源可快速地将电容第一端的电压充电至预设的保护值并输入过电流保护单元，启动过电流保护功能，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。本发明提供的一种液晶显示装置，能够防止在快速开关液晶显示装置时产生的峰值电流误触发过电流保护。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种时钟信号输出电路，包括时钟信号转换单元、分压单元、保护信号产生单元、过电流保护单元、及开关单元；
    所述时钟信号转换单元的输入端接入初始的时钟信号，输出端电性连接开关单元的第一端并输出转换后的时钟信号；所述分压单元的第一端电性连接开关单元的第二端，第二端电性连接显示面板；所述保护信号产生单元包括减法器、比较器、开关、电流源、及电容；所述减法器的同相输入端及反相输入端分别电性连接分压单元的第一端及第二端，输出端电性连接比较器的同相输入端；比较器的反相输入端接入参考电压，输出端电性连接开关的控制端；所述开关的第一端及第二端分别电性连接电容的第一端及第二端，且所述开关在其控制端为高电平时闭合，在其控制端为低电平时断开；所述电容的第一端电性连接电流源的输出端，第二端接地；所述过电流保护单元的第一输入端电性连接电容的第一端，第二输入端电性连接分压单元的第一端或第二端，输出端电性连接开关单元的控制端；
    所述过电流保护单元用于在其第一输入端的电压大于等于一预设保护值、且第二输入端的电流大于一预设电流值并持续一预设时间时产生对应的控制信号控制开关单元截止。
  2. 如权利要求1所述的时钟信号输出电路，其中，所述时钟信号转换单元包括：逻辑控制器、第一场效应管、及第二场效应管；所述逻辑控制器的输入端为所述时钟信号转换单元的输入端，输出端电性连接第一场效应管的栅极及第二场效应管的栅极；所述第一场效应管的漏极接入恒压高电位，源极电性连接第二场效应管的漏极且为时钟信号转换单元的输出端；所述第二场效应管的源极接入恒压低电位；
    所述逻辑控制器用于根据初始时钟信号控制第一场效应管及第二场效应管的导通或截止，使时钟信号转换单元的输出端输出转换后的时钟信号。
  3. 如权利要求2所述的时钟信号输出电路，其中，所述第一场效应管为N型场效应管，所述第二场效应管为P型场效应管。
  4. 如权利要求1所述的时钟信号输出电路，其中，所述分压单元为一电阻。
  5. 如权利要求1所述的时钟信号输出电路，其中，所述时钟信号转换单元及保护信号产生单元设于同一电平转换芯片上。
  6. 如权利要求1所述的时钟信号输出电路，其中，所述显示面板具有 GOA电路；所述分压单元的第二端与显示面板的GOA电路电性连接。
  7. 如权利要求1所述的时钟信号输出电路，其中，所述开关单元为第三场效应管，所述第三场效应管的栅极为开关单元的控制端，漏极为开关单元的第一端，源极为开关单元的第二端。
  8. 一种液晶显示装置，包括如权利要求1所述的时钟信号输出电路。
  9. 一种时钟信号输出电路，包括时钟信号转换单元、分压单元、保护信号产生单元、过电流保护单元、及开关单元；
    所述时钟信号转换单元的输入端接入初始的时钟信号，输出端电性连接开关单元的第一端并输出转换后的时钟信号；所述分压单元的第一端电性连接开关单元的第二端，第二端电性连接显示面板；所述保护信号产生单元包括减法器、比较器、开关、电流源、及电容；所述减法器的同相输入端及反相输入端分别电性连接分压单元的第一端及第二端，输出端电性连接比较器的同相输入端；比较器的反相输入端接入参考电压，输出端电性连接开关的控制端；所述开关的第一端及第二端分别电性连接电容的第一端及第二端，且所述开关在其控制端为高电平时闭合，在其控制端为低电平时断开；所述电容的第一端电性连接电流源的输出端，第二端接地；所述过电流保护单元的第一输入端电性连接电容的第一端，第二输入端电性连接分压单元的第一端或第二端，输出端电性连接开关单元的控制端；
    所述过电流保护单元用于在其第一输入端的电压大于等于一预设保护值、且第二输入端的电流大于一预设电流值并持续一预设时间时产生对应的控制信号控制开关单元截止；
    其中，所述时钟信号转换单元包括：逻辑控制器、第一场效应管、及第二场效应管；所述逻辑控制器的输入端为所述时钟信号转换单元的输入端，输出端电性连接第一场效应管的栅极及第二场效应管的栅极；所述第一场效应管的漏极接入恒压高电位，源极电性连接第二场效应管的漏极且为时钟信号转换单元的输出端；所述第二场效应管的源极接入恒压低电位；
    所述逻辑控制器用于根据初始时钟信号控制第一场效应管及第二场效应管的导通或截止，使时钟信号转换单元的输出端输出转换后的时钟信号；
    其中，所述分压单元为一电阻；
    其中，所述时钟信号转换单元及保护信号产生单元设于同一电平转换芯片上；
    其中，所述显示面板具有GOA电路；所述分压单元的第二端与显示面板的GOA电路电性连接。
  10. 如权利要求9所述的时钟信号输出电路，其中，所述第一场效应 管为N型场效应管，所述第二场效应管为P型场效应管。
  11. 如权利要求9所述的时钟信号输出电路，其中，所述开关单元为第三场效应管，所述第三场效应管的栅极为开关单元的控制端，漏极为开关单元的第一端，源极为开关单元的第二端。
PCT/CN2017/111435 2017-07-18 2017-11-16 时钟信号输出电路及液晶显示装置 WO2019015185A1 (zh)

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