WO2019015023A1 - 阵列基板及制作方法、显示面板 - Google Patents

阵列基板及制作方法、显示面板 Download PDF

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WO2019015023A1
WO2019015023A1 PCT/CN2017/099484 CN2017099484W WO2019015023A1 WO 2019015023 A1 WO2019015023 A1 WO 2019015023A1 CN 2017099484 W CN2017099484 W CN 2017099484W WO 2019015023 A1 WO2019015023 A1 WO 2019015023A1
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thin film
film transistor
layer
driving thin
gate
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French (fr)
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李松杉
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the invention relates to a display panel technology, in particular to an array substrate for an OLED, a manufacturing method thereof and a display panel.
  • the thickness is thinner than that of LCD panels because no additional backlight components are required, among which IGZO (Indium Gallium Zinc Oxide) in metal oxide semiconductors due to electron mobility High, low leakage current, low preparation temperature and other characteristics have caused widespread concern.
  • IGZO Indium Gallium Zinc Oxide
  • the gate insulating layer of the switching thin film transistor (Switch TFT) and the driving thin film transistor (Driver TFT) is generally made of SiOx material, but the hydrophilicity of SiOx It is relatively strong, and it has strong absorption capacity for water and oxygen at room temperature. After working for a period of time, the thin film transistor will seriously affect the electrical properties of the thin film transistor, resulting in a large shift in threshold voltage, poor reliability, and thin film transistor properties. The deterioration is serious.
  • the present invention provides an array substrate, a manufacturing method thereof, and a display panel, thereby improving the typicality and reliability of the thin film transistor and ensuring the normal operation of the driving thin film transistor.
  • the present invention provides an array substrate including a substrate on which a driving thin film transistor and a switching thin film transistor are disposed, the driving thin film transistor and the switching thin film transistor each including a gate electrode, a gate insulating layer, an active layer, and a source, A drain is further provided with a barrier layer between the gate of the driving thin film transistor and the gate insulating layer.
  • the material for preparing the barrier layer is SiNx.
  • the active layer is an oxide thin film transistor and/or the driving thin film transistor and the switching thin film transistor is a bottom gate thin film transistor.
  • the method further includes covering the driving thin film transistor and the passivation layer on the switching thin film transistor and the flat layer, and the anode is in contact with the source or the drain of the driving thin film transistor through the flat layer via hole and the passivation layer via hole.
  • the invention also provides a method for fabricating an array substrate, comprising the following steps:
  • Step S1 forming a gate layer on the substrate and patterning to form a gate as a driving thin film transistor and a switching thin film transistor;
  • Step S2 forming a barrier layer on the gate of the driving thin film transistor
  • Step S3 depositing a gate insulating layer on the substrate
  • Step S4 forming an active layer above the gates of the driving thin film transistor and the switching thin film transistor on the gate insulating layer;
  • Step S5 forming a source and a drain on the active layer.
  • the step S2 is to form a barrier layer on the gate of the driving thin film transistor, specifically, depositing a SiNx layer on the gate of the driving thin film transistor by a plasma enhanced chemical vapor deposition process and patterning to obtain a barrier layer. .
  • the active layer is an oxide thin film transistor.
  • the driving thin film transistor and the switching thin film transistor are bottom gate type thin film transistors.
  • Step S6 forming a passivation layer on the substrate, the passivation layer covering the source and the drain;
  • Step S7 forming a flat layer on the passivation layer
  • Step S8 forming an anode on the flat layer, the anode passing through the flat layer via, and the passivation layer via contacting the source or the drain of the driving thin film transistor.
  • the invention also provides a display panel comprising the array substrate.
  • the present invention improves the thin film transistor by providing a barrier layer between the gate electrode and the gate insulating layer as a driving thin film transistor to prevent the influence of water and oxygen active impurity ions on the active layer of the driving thin film transistor.
  • the electrical and reliability ensure that the driving thin film transistor driving the organic light emitting diode works normally.
  • FIG. 1 is a schematic view showing the formation of a barrier layer and a gate insulating layer of the present invention
  • FIG. 2 is a schematic view showing the active layer and the source and drain electrodes formed on the gate insulating layer of the present invention
  • FIG 3 is a schematic view of the present invention after the passivation layer, the planarization layer, and the anode are formed.
  • an array substrate of the present invention is used in an OLED (Organic Light Emitting Diode) panel
  • the array substrate includes a substrate 1 on which a driving thin film transistor and a switching thin film transistor are provided, specifically, driving
  • the thin film transistor and the switching thin film transistor each include a gate electrode 2, a gate insulating layer 3, an active layer 4, and a source 5 and a drain 6.
  • the gate electrode 2 and the gate insulating layer 3 of the driving thin film transistor are further provided with a barrier.
  • the layer 7 is provided on the source 5 and the drain 6 with a passivation layer 8 covering the driving thin film transistor and the switching thin film transistor.
  • the passivation layer 8 is provided with a flat layer 10, and the flat layer 10 is provided with an anode 9 and an anode. 9 via the via of the planar layer 10, the via of the passivation layer 8 is in contact with the source 5 or the drain 6 of the driving thin film transistor.
  • a barrier layer 7 is provided between the gate electrode 2 as a driving thin film transistor and the gate insulating layer 3, thereby blocking the influence of water, oxygen and impurity ions on the active layer as a driving thin film transistor, and improving the thin film transistor Electrical and reliability to ensure the normal operation of the driving thin film transistor for driving OLED;
  • the barrier layer 7 is made of SiNx (silicon nitride), and since SiNx is much less hydrophilic than SiOx used as a material for preparing the gate insulating layer 3, it can block water, oxygen, and impurity ions.
  • SiNx silicon nitride
  • the active layer 4 is an oxide thin film transistor, specifically a metal oxide thin film transistor.
  • the active layer 4 is IGZO (indium gallium zinc oxide).
  • the driving thin film transistor and the switching thin film transistor are bottom-gate thin film transistors.
  • the method for fabricating the array substrate of the present invention comprises the following steps:
  • Step S1 as shown in FIG. 1, a gate layer is formed on the substrate 1 and patterned to form a driving thin film.
  • a gate electrode 2 of the membrane transistor and the switching thin film transistor specifically, a layer of Mo (molybdenum) is deposited on the glass substrate 1 by a physical vapor deposition process and patterned to obtain a gate electrode 2 as a driving thin film transistor and a switching thin film transistor;
  • Step S2 as shown in FIG. 1, a barrier layer 7 is formed on the gate electrode 2 as a driving thin film transistor, specifically, a SiNx layer is deposited on the gate electrode 2 as a driving thin film transistor by a plasma enhanced chemical vapor deposition process. And graphically obtained a barrier layer 7;
  • Step S3 depositing a gate insulating layer 3 on the substrate 1, such that the gate insulating layer 3 covers the barrier layer 7, the deposition material of the gate insulating layer 3 is SiOx (silicon oxide);
  • Step S4 an active layer 4 is formed on the gate insulating layer 3 above the gate electrode 2 of the driving thin film transistor and the switching thin film transistor, and the active layer 4 is an oxide thin film transistor, specifically, by physical vapor deposition.
  • An active layer 4 is formed by patterning an indium gallium zinc oxide (IGZO) layer, and the active layer 4 is located above the gate 2 of the driving thin film transistor and the switching thin film transistor;
  • IGZO indium gallium zinc oxide
  • Step S5 as shown in FIG. 2, the source 5 and the drain 6 are formed on the active layer 4. Specifically, a metal layer is deposited by physical vapor deposition and patterned by a back channel etch (BCE) process. After the metal layer, the source 5 and the drain 6 are obtained;
  • BCE back channel etch
  • Step S6 as shown in FIG. 3, a passivation layer 8 is formed on the substrate 1, and the passivation layer 8 covers the source 5 and the drain 6, specifically, a layer of SiOx is formed on the source 5 and the drain 6.
  • a passivation layer 8 is formed, and a via hole is formed on the passivation layer 8 on the source 5 or the drain 6 as a driving thin film transistor, specifically, a via hole is formed on the drain electrode 6;
  • Step S7 as shown in FIG. 3, a flat layer 10 is formed on the passivation layer 8, specifically, by forming an organic photoresist insulating layer and patterning to form a flat layer 10, where the flat layer 10 is located on the passivation layer 8. Forming a via at the hole;
  • Step S8 as shown in FIG. 3, an anode 9 is formed on the flat layer 10, the anode 9 is via the via layer 10, and the passivation layer 8 is in contact with the source 5 or the drain 6 of the driving thin film transistor.
  • the driving thin film transistor and the switching thin film transistor are bottom-gate thin film transistors.
  • the present invention also discloses a display panel, including the above array substrate, which will not be further described herein.
  • the array substrate of the present invention is particularly suitable for use as a TFT backplane of an AM-OLED (Active Matrix Organic Light Emitting Diode, Active Matrix Organic Light Emitting Diode or Active Matrix Organic Light Emitting Diode).
  • AM-OLED Active Matrix Organic Light Emitting Diode, Active Matrix Organic Light Emitting Diode or Active Matrix Organic Light Emitting Diode.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供一种阵列基板，包括基板（1），在基板（1）上设置有驱动薄膜晶体管以及开关薄膜晶体管，驱动薄膜晶体管和开关薄膜晶体管均包括栅极（2）、栅极绝缘层（3）、主动层（4）以及源极（5）、漏极（6），驱动薄膜晶体管的栅极（2）与栅极绝缘层（3）之间还设有阻挡层（7）。还提供一种阵列基板的制作方法，包括在作为驱动薄膜晶体管的栅极（2）上制作阻挡层（7）。通过在作为驱动薄膜晶体管的栅极（2）与栅极绝缘层（3）之间设置阻挡层（7），防止水、氧活泼杂质离子对驱动薄膜晶体管的主动层（4）的影响，从而改善薄膜晶体管的电性和可靠性，保证驱动有机发光二极管的驱动薄膜晶体管正常工作。

Description

阵列基板及制作方法、显示面板 技术领域
本发明涉及一种显示面板技术，特别是一种用于OLED的阵列基板及制作方法、显示面板。
背景技术
随着OLED(有机发光二极管)面板日益普及，其由于不需要额外的背光组件，因此厚度相对于LCD面板更加的薄，其中，金属氧化物半导体中IGZO(铟镓锌氧化物)由于电子迁移率高，漏电流低，制备温度低等特点，引起了广泛的关注。传统的底栅型的铟镓锌氧化物薄膜晶体管在制程过程中，开关薄膜晶体管(Switch TFT)和驱动薄膜晶体管(Driver TFT)处的栅极绝缘层一般采用SiOx材料，但是SiOx的亲水性比较强，在室温下对水和氧的吸收能力较强，在薄膜晶体管工作一段时间后会严重影响薄膜晶体管的电性，致使阈值电压出现较大的偏移，可靠性变差，薄膜晶体管性质劣化严重。
发明内容
为克服现有技术的不足，本发明提供一种阵列基板及制作方法、显示面板，从而改善薄膜晶体管的典型和可靠性，保证驱动薄膜晶体管的正常工作。
本发明提供了一种阵列基板，包括基板，在基板上设置有驱动薄膜晶体管以及开关薄膜晶体管，所述驱动薄膜晶体管和开关薄膜晶体管均包括栅极、栅极绝缘层、主动层以及源极、漏极，所述驱动薄膜晶体管的栅极与栅极绝缘层之间还设有阻挡层。
进一步地，所述阻挡层的制备材料为SiNx。
进一步地，所述主动层为氧化物薄膜晶体管和/或所述驱动薄膜晶体管以及开关薄膜晶体管为底栅型薄膜晶体管。
进一步地，还包括覆盖驱动薄膜晶体管以及开关薄膜晶体管上的钝化层以及平坦层，阳极经平坦层过孔、钝化层过孔与驱动薄膜晶体管的源极或漏极接触。
本发明还提供了一种阵列基板的制作方法，包括如下步骤：
步骤S1、在基板上制作栅极层并图形化后形成作为驱动薄膜晶体管和开关薄膜晶体管的栅极；
步骤S2、在作为驱动薄膜晶体管的栅极上制作阻挡层；
步骤S3、在基板上沉积栅极绝缘层；
步骤S4、在栅极绝缘层上位于驱动薄膜晶体管和开关薄膜晶体管的栅极上方形成主动层；
步骤S5、在主动层上制作源极和漏极。
进一步地，所述步骤S2在作为驱动薄膜晶体管的栅极上制作阻挡层具体为通过等离子体增强化学气相沉积工艺在作为驱动薄膜晶体管的栅极上沉积一层SiNx层并图形化后得到阻挡层。
进一步地，所述主动层为氧化物薄膜晶体管。
进一步地，所述驱动薄膜晶体管以及开关薄膜晶体管为底栅型薄膜晶体管。
进一步地，还包括
步骤S6、在基板上制作钝化层，钝化层覆盖源极和漏极；
步骤S7、在钝化层上制作平坦层；
步骤S8、在平坦层上制作阳极，阳极经平坦层过孔、钝化层过孔与驱动薄膜晶体管的源极或漏极接触。
本发明还提供了一种显示面板，包括所述的阵列基板。
本发明与现有技术相比，通过在作为驱动薄膜晶体管的栅极与栅极绝缘层之间设置阻挡层，防止水、氧活泼杂质离子对驱动薄膜晶体管的主动层的影响，从而改善薄膜晶体管的电性和可靠性，保证驱动有机发光二极管的驱动薄膜晶体管正常工作。
附图说明
图1是本发明制作阻挡层以及栅极绝缘层的示意图；
图2是本发明在栅极绝缘层上制作主动层以及源漏极的示意图；
图3是本发明制作钝化层、平坦层以及阳极后的示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步详细说明。
如图3所示，本发明的一种阵列基板，其用于OLED(有机发光二极管)面板中，该阵列基板包括基板1，在基板1设置有驱动薄膜晶体管以及开关薄膜晶体管，具体地，驱动薄膜晶体管和开关薄膜晶体管均包括栅极2、栅极绝缘层3、主动层4以及源极5、漏极6，在驱动薄膜晶体管的栅极2与栅极绝缘层3之间还设有阻挡层7，在源极5和漏极6上设有覆盖驱动薄膜晶体管以及开关薄膜晶体管上的钝化层8，钝化层8上设有平坦层10，平坦层10上设有阳极9，阳极9经平坦层10过孔、钝化层8过孔与驱动薄膜晶体管的源极5或漏极6接触。
本发明中通过在作为驱动薄膜晶体管的栅极2与栅极绝缘层3之间设置一层阻挡层7，从而阻挡水、氧以及杂质离子对作为驱动薄膜晶体管的主动层的影响，改善薄膜晶体管的电性和可靠性，保证驱动OLED用的驱动薄膜晶体管的正常工作；
本发明中阻挡层7的制备材料为SiNx(氮化硅)，由于SiNx的亲水性远小于用于作为栅极绝缘层3制备材料的SiOx，因此能够对水、氧以及杂质离子的阻挡。
本发明中主动层4为氧化物薄膜晶体管，具体为金属氧化物薄膜晶体管，作为本发明的一种实施方式，主动层4为IGZO(铟镓锌氧化物)。
本发明中驱动薄膜晶体管以及开关薄膜晶体管为底栅型薄膜晶体管。
本发明的阵列基板的制作方法，包括如下步骤：
步骤S1、如图1所示，在基板1上制作栅极层并图形化后形成作为驱动薄 膜晶体管和开关薄膜晶体管的栅极2，具体为，在玻璃基板1上利用物理气相沉积工艺沉积一层Mo(钼)并图形化后得到作为驱动薄膜晶体管和开关薄膜晶体管的栅极2；
步骤S2、如图1所示，在作为驱动薄膜晶体管的栅极2上制作阻挡层7，具体为，通过等离子体增强化学气相沉积工艺在作为驱动薄膜晶体管的栅极2上沉积一层SiNx层并图形化后得到阻挡层7；
步骤S3、如图1所示，在基板1上沉积栅极绝缘层3，使栅极绝缘层3覆盖阻挡层7，所述栅极绝缘层3的沉积材料为SiOx(氧化硅)；
步骤S4、如图2所示，在栅极绝缘层3上位于驱动薄膜晶体管和开关薄膜晶体管的栅极2上方形成主动层4，主动层4为氧化物薄膜晶体管，具体为，通过物理气相沉积一层铟镓锌氧化物(IGZO)层并图形化后，形成主动层4，主动层4位于驱动薄膜晶体管和开关薄膜晶体管的栅极2上方；
步骤S5、如图2所示，在主动层4上制作源极5和漏极6，具体为，通过物理气相沉积一层金属层后采用反向通道蚀刻(back channel etch、BCE)工艺图形化金属层后得到源极5和漏极6；
步骤S6、如图3所示，在基板1上制作钝化层8，钝化层8覆盖源极5和漏极6，具体地，在源极5和漏极6上制作一层SiOx层并图形化后形成钝化层8，在钝化层8上位于作为驱动薄膜晶体管的源极5或漏极6上制作过孔，具体为在漏极6上制作过孔；
步骤S7、如图3所示，在钝化层8上制作平坦层10，具体为，通过制作有机光阻绝缘层并图形化后形成平坦层10，在平坦层10位于钝化层8的过孔处形成过孔；
步骤S8、如图3所示，在平坦层10上制作阳极9，阳极9经平坦层10过孔、钝化层8过孔与驱动薄膜晶体管的源极5或漏极6接触。
本发明中驱动薄膜晶体管以及开关薄膜晶体管为底栅型薄膜晶体管。
本发明还公开了一种显示面板，包括上述的阵列基板，在此不再具体赘述。
本发明的阵列基板特别适用于将其作为AMOLED(Active-matrix organic light emitting diode、有源矩阵有机发光二极体或主动矩阵有机发光二极体)的薄膜晶体管背板(TFT backplane)中。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种阵列基板，其中：包括基板，在基板上设置有驱动薄膜晶体管以及开关薄膜晶体管，所述驱动薄膜晶体管和开关薄膜晶体管均包括栅极、栅极绝缘层、主动层以及源极、漏极，所述驱动薄膜晶体管的栅极与栅极绝缘层之间还设有阻挡层。
  2. 根据权利要求1所述的阵列基板，其中：所述阻挡层的制备材料为SiNx。
  3. 根据权利要求1所述的阵列基板，其中：所述主动层为氧化物薄膜晶体管和/或所述驱动薄膜晶体管以及开关薄膜晶体管为底栅型薄膜晶体管。
  4. 根据权利要求1所述的阵列基板，其中：还包括覆盖驱动薄膜晶体管以及开关薄膜晶体管上的钝化层以及平坦层，阳极经平坦层过孔、钝化层过孔与驱动薄膜晶体管的源极或漏极接触。
  5. 一种阵列基板的制作方法，其中：包括如下步骤：
    步骤S1、在基板上制作栅极层并图形化后形成作为驱动薄膜晶体管和开关薄膜晶体管的栅极；
    步骤S2、在作为驱动薄膜晶体管的栅极上制作阻挡层；
    步骤S3、在基板上沉积栅极绝缘层；
    步骤S4、在栅极绝缘层上位于驱动薄膜晶体管和开关薄膜晶体管的栅极上方形成主动层；
    步骤S5、在主动层上制作源极和漏极。
  6. 根据权利要求5所述的阵列基板的制作方法，其中：所述步骤S2在作为驱动薄膜晶体管的栅极上制作阻挡层具体为通过等离子体增强化学气相沉积工艺在作为驱动薄膜晶体管的栅极上沉积一层SiNx层并图形化后得到阻挡层。
  7. 根据权利要求5所述的阵列基板的制作方法，其中：所述主动层为氧化物薄膜晶体管。
  8. 根据权利要求7所述的阵列基板的制作方法，其中：所述驱动薄膜晶体管以及开关薄膜晶体管为底栅型薄膜晶体管。
  9. 根据权利要求5所述的阵列基板的制作方法，其中：还包括：
    步骤S6、在基板上制作钝化层，钝化层覆盖源极和漏极；
    步骤S7、在钝化层上制作平坦层；
    步骤S8、在平坦层上制作阳极，阳极经平坦层过孔、钝化层过孔与驱动薄膜晶体管的源极或漏极接触。
  10. 一种显示面板，其中：包括阵列基板，所述阵列基板包括基板，在基板上设置有驱动薄膜晶体管以及开关薄膜晶体管，所述驱动薄膜晶体管和开关薄膜晶体管均包括栅极、栅极绝缘层、主动层以及源极、漏极，所述驱动薄膜晶体管的栅极与栅极绝缘层之间还设有阻挡层。
  11. 根据权利要求10所述的显示面板，其中：所述阻挡层的制备材料为SiNx。
  12. 根据权利要求10所述的显示面板，其中：所述主动层为氧化物薄膜晶体管和/或所述驱动薄膜晶体管以及开关薄膜晶体管为底栅型薄膜晶体管。
  13. 根据权利要求10所述的显示面板，其中：还包括覆盖驱动薄膜晶体管以及开关薄膜晶体管上的钝化层以及平坦层，阳极经平坦层过孔、钝化层过孔与驱动薄膜晶体管的源极或漏极接触。
PCT/CN2017/099484 2017-07-18 2017-08-29 阵列基板及制作方法、显示面板 Ceased WO2019015023A1 (zh)

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