WO2019015004A1 - 一种阵列基板、显示装置及其制作方法 - Google Patents

一种阵列基板、显示装置及其制作方法 Download PDF

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WO2019015004A1
WO2019015004A1 PCT/CN2017/097988 CN2017097988W WO2019015004A1 WO 2019015004 A1 WO2019015004 A1 WO 2019015004A1 CN 2017097988 W CN2017097988 W CN 2017097988W WO 2019015004 A1 WO2019015004 A1 WO 2019015004A1
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layer
electrode layer
drain electrode
source electrode
array substrate
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French (fr)
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石龙强
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering

Definitions

  • the present invention relates to the field of planar display technologies, and in particular, to an array substrate, a display device, and a method of fabricating the same.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • LCD liquid crystal display
  • OLED organic light emitting display
  • a vertical thin film transistor Very Thin Film Transistor It is widely used because it has a small footprint and is advantageous for designs with resolutions greater than 2000 ppi.
  • the support layer between the source electrode layer and the drain electrode layer of the vertical thin film transistor is processed by using a material containing fluorine atoms in the fabrication process.
  • a large amount of fluorine atoms remain, and the diffusion of fluorine atoms into the active layer affects the electrical properties of the thin film transistor, thereby affecting the reliability of the array substrate.
  • the technical problem to be solved by the present invention is to provide an array substrate, a display device and a manufacturing method thereof.
  • fluorine atoms in the support layer can be prevented from entering the active layer, thereby improving the array substrate. reliability.
  • the present invention adopts a technical solution to provide a display device
  • the display device includes an array substrate, the array substrate includes: a substrate; a source electrode layer formed on the substrate; and a support layer formed at the source a drain electrode layer formed on the support layer; a barrier layer overlying the drain electrode layer; an active layer formed on the barrier layer; the barrier layer isolating the support layer from the active layer; the barrier layer An insulating layer formed of silicon oxide or silicon nitride; the barrier layer has a thickness of 200 A to 10000 ⁇ .
  • an array substrate the array substrate includes: a substrate; a source electrode layer formed on the substrate; and a support layer formed on the source electrode layer; a drain electrode layer formed on the support layer; a barrier layer overlying the drain electrode layer; an active layer formed on the barrier layer; and a barrier layer separating the support layer from the active layer.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: sequentially forming a source electrode layer and a support layer on a substrate; forming on the support layer a drain electrode layer; a barrier layer deposited on the drain electrode layer; an active layer deposited on the barrier layer, the barrier layer isolating the support layer from the active layer.
  • the invention has the beneficial effects that by covering the drain electrode layer with the barrier layer and isolating the support layer between the source electrode layer and the drain electrode layer from the active layer, the fluorine atoms in the support layer can be prevented from entering the active layer. Layers, which in turn improve the reliability of the array substrate.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention.
  • Figure 4 is a schematic view showing the structure of a display device of the present invention.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate according to the present invention.
  • the array substrate includes: a substrate 10; a source electrode layer 11 formed on the substrate 10; and a support layer 12 formed on the source electrode layer 11. Upper; drain electrode layer 13 formed on support layer 12; barrier layer 14 overlying drain electrode layer 13; active layer 15 formed on barrier layer 14; barrier layer 14 supporting layer 12 and active Layer 15 is isolated.
  • the substrate 10 may be a glass substrate or a flexible substrate.
  • a silicon dioxide substrate or a polyvinyl chloride (PVC), a soluble polytetrafluoroethylene (PFA), or a poly pair may also be used.
  • a buffer layer of a certain thickness may be deposited on the substrate before the source electrode layer 11 is formed.
  • the deposition material may be a single layer or a multilayer of silicon oxide (SiO x) / silicon nitride (SiN x), for increasing the degree of adhesion between the source electrode layer 11 to be formed in the substrate 10, help to reduce the effect of heat conduction.
  • the source electrode layer 11 and the drain electrode layer 13 are disposed in parallel with the substrate 10.
  • the support layer 12 is an insulating layer for supporting/separating the source electrode layer 11 and the drain electrode layer 13.
  • CF 4 carbon tetrafluoride
  • O 2 oxygen
  • the barrier layer 14 may specifically be silicon oxide (SiO x ), and may be silicon nitride (SiN x ) or the like in some application scenarios. Of course, in other application scenarios, other insulating materials may also be used.
  • the barrier layer 14 has a thickness of 200A-10000A.
  • the active layer 15 is an oxide semiconductor layer, and specifically may be an amorphous oxide such as at least one of indium oxide, zinc oxide, tin oxide, gallium oxide, or the like.
  • the barrier layer 14 is provided with a first contact hole 14a to expose a portion of the drain electrode layer 13; the barrier layer 14 is further provided with a second contact hole 14b to expose a portion of the source electrode layer 11; the active layer 15 passes The first contact hole 14a and the second contact hole 14b are electrically connected to the drain electrode layer 13 and the source electrode layer 11.
  • the support layer between the source electrode layer and the drain electrode layer is isolated from the active layer, thereby preventing fluorine atoms in the support layer from entering the active layer, thereby improving the reliability of the array substrate.
  • FIG. 2 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • the array substrate further includes a gate insulating layer 26 formed on the active layer 25, and a gate electrode layer 27 formed on the gate insulating layer 26.
  • the gate insulating layer 26 may specifically be silicon oxide (SiO x )/silicon nitride (SiN x ) or the like.
  • the gate electrode layer 27 may specifically be a single metal layer or a composite metal layer such as chromium (Cr), molybdenum (Mo), molybdenum (Mo) / aluminum (Al), copper (Cu) or the like.
  • the gate electrode layer 27 and the source electrode layer 21 and the drain electrode layer 23 form a thin film transistor of a top gate structure, and the source and the drain can be regarded as two electrodes which are not distinguished.
  • the active layer 25 is an oxide semiconductor layer; the oxide semiconductor layer is electrically connected to the drain electrode layer 23 and the source electrode layer 21 through the first contact hole 24a and the second contact hole 24b of the barrier layer 24 to form a vertical Type oxide thin film transistor.
  • the active layer 25 is specifically an indium gallium zinc oxide (IGZO), which can improve the charge and discharge rate of the thin film transistor to the pixel electrode, improve the response speed of the pixel, achieve a faster refresh rate, and further improve the pixel.
  • IGZO indium gallium zinc oxide
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention.
  • the method for fabricating the array substrate includes the following steps:
  • the base substrate may be a transparent material, and specifically may be a water-proof and oxygen-transparent organic material or glass. Commonly used are glass substrates, silica substrates, and some applications can use polyvinyl chloride (PVC), soluble polytetrafluoroethylene (PFA), polyethylene terephthalate (Polyethylene). Terephthalate, PET) substrate, etc. In other embodiments, a buffer layer of a certain thickness (not shown) may be deposited on the substrate before the source electrode layer is formed.
  • PVC polyvinyl chloride
  • PFA soluble polytetrafluoroethylene
  • PET polyethylene terephthalate
  • a buffer layer of a certain thickness may be deposited on the substrate before the source electrode layer is formed.
  • the deposition material may be a single layer or a multilayer of silicon oxide (SiO x) / silicon nitride (SiN x), for increasing the degree of adhesion to be formed between the source electrode layer and the substrate, help to reduce the effect of heat conduction.
  • a process such as photoresist coating, exposure, development, etching, and photoresist stripping is performed on a substrate by a physical vapor deposition (PVD) method to form a source electrode layer having a predetermined pattern.
  • PVD physical vapor deposition
  • S31 depositing silicon oxide and/or silicon nitride on the source electrode layer by chemical vapor deposition to form an insulating material layer, depositing a metal substance on the insulating material layer by physical vapor deposition, and performing pattern processing to form a leak
  • the electrode layer is formed with a drain electrode layer as a mask, and the insulating material layer is dry etched to form a support layer.
  • a single layer of a silicon oxide (SiO x ) film layer or a silicon nitride (SiN x ) film layer is deposited on the source electrode layer by a chemical vapor deposition (CVD) method and a yellow light etching process, or It is a laminate of silicon oxide (SiO x ) and silicon nitride (SiN x ) to form an insulating material layer in preparation for subsequent formation of the support layer.
  • CVD chemical vapor deposition
  • a drain electrode layer is formed on the insulating material layer by a physical vapor deposition (PVD) method through exposure, etching, or the like, and the insulating material layer is dry-etched by using a drain as a photomask to finally form a support layer. Due to the addition of carbon tetrafluoride (CF 4 ) and oxygen (O 2 ), some fluorine atoms remain in the support layer during the etching process.
  • PVD physical vapor deposition
  • S32 depositing silicon oxide and/or silicon nitride on the drain electrode layer to form a barrier layer.
  • the barrier layer has a thickness of 200A-10000A.
  • the method further includes sequentially forming a gate insulating layer and a gate electrode layer on the active layer; the gate electrode layer and the source electrode layer and the drain electrode layer form a thin film transistor of a top gate structure.
  • the active layer is an oxide semiconductor layer; depositing the active layer on the barrier layer includes: opening a hole in the barrier layer to form a first contact hole and a second contact to the drain electrode layer and the source electrode layer a hole; an oxide semiconductor layer is deposited on the barrier layer such that the oxide semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the first contact hole and the second contact hole to form a vertical oxide thin film transistor.
  • a hole is formed in the barrier layer to form a first contact hole and a second contact hole to the drain electrode layer and the source electrode layer, and indium oxide, zinc oxide, tin is deposited on the barrier layer.
  • the active layer can be effectively prevented from being affected by the fluorine atoms in the support layer, thereby improving the reliability of the array substrate.
  • the present invention also includes a display device.
  • the display device 40 includes the array substrate 41 of any of the above structures, or the array substrate 41 prepared by any of the above methods. The method can be used to form the array substrate shown in FIG. 1/ FIG. 2, and details are not described herein again.
  • the display device may be an active-matrix organic light emitting diode (AMOLED) or a TFT LCD display device.
  • AMOLED active-matrix organic light emitting diode
  • TFT LCD display device a TFT LCD display device.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板、显示装置及其制作方法。其中，所述阵列基板包括：基板（10）；源极电极层（11），形成在所述基板（10）上；支撑层（12），形成在所述源极电极层（11）上；漏极电极层（13），形成在所述支撑层（12）上；阻挡层（14），覆盖在所述漏极电极层（13）上；有源层（15），形成在所述阻挡层（14）上；所述阻挡层（14）将所述支撑层（12）与所述有源层（15）隔离。通过上述方式，可以防止支撑层（12）中的氟原子进入有源层（15），进而提高阵列基板的可靠性。

Description

一种阵列基板、显示装置及其制作方法 【技术领域】
本发明涉及平面显示技术领域，特别是涉及一种阵列基板、显示装置及其制作方法。
【背景技术】
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，LCD)及有机发光二极管显示器件(Organic Light Emitting Display，OLED)，在显示器的制作过程中，垂直型薄膜晶体管(Vertical Thin Film Transistor)由于占用面积少，有利于分辨率大于2000ppi的设计而被广泛使用。
本申请的发明人在长期的研发中发现，现有技术中，垂直型薄膜晶体管的源极电极层与漏极电极层之间的支撑层在制作过程中，由于采用含有氟原子的材料进行加工，会残留大量氟原子，而氟原子扩散到有源层中，会影响薄膜晶体管的电性，进而影响阵列基板的可靠性。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板、显示装置及其制作方法，通过将支撑层与有源层进行隔离，可以防止支撑层中的氟原子进入有源层，进而提高阵列基板的可靠性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示装置，显示装置包括阵列基板，上述阵列基板包括：基板；源极电极层，形成在基板上；支撑层，形成在源极电极层上；漏极电极层，形成在支撑层上；阻挡层，覆盖在漏极电极层上；有源层，形成在阻挡层上；阻挡层将支撑层与有源层隔离；阻挡层为氧化硅或氮化硅形成的绝缘层；阻挡层的厚度为200A-10000A。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板包括：基板；源极电极层，形成在基板上；支撑层，形成在源极电极层上；漏极电极层，形成在支撑层上；阻挡层，覆盖在漏极电极层上；有源层，形成在阻挡层上；阻挡层将支撑层与有源层隔离。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制作方法，该方法包括：在一衬底基板上依次形成源极电极层、支撑层；在支撑层上形成漏极电极层；在漏极电极层上沉积阻挡层；在阻挡层上沉积有源层，阻挡层将支撑层及有源层隔离。
本发明的有益效果是：通过在漏极电极层上覆盖阻挡层，将源极电极层及漏极电极层之间的支撑层与有源层隔离，可以防止支撑层中的氟原子进入有源层，进而提高阵列基板的可靠性。
【附图说明】
图1是本发明阵列基板一实施方式的结构示意图；
图2是本发明阵列基板另一实施方式的结构示意图；
图3是本发明阵列基板制作方法一实施方式的流程示意图；
图4是本发明显示装置的结构示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
请参阅图1，图1是本发明阵列基板一实施方式的结构示意图，该阵列基板包括：基板10；源极电极层11，形成在基板10上；支撑层12，形成在源极电极层11上；漏极电极层13，形成在支撑层12上；阻挡层14，覆盖在漏极电极层13上；有源层15，形成在阻挡层14上；阻挡层14将支撑层12与有源层15隔离。
其中，基板10可以为玻璃基板或柔性基板，在一些应用中，也可以采用二氧化硅基板，或者聚氯乙烯(Polyvinyl chloride，PVC)、可溶性聚四氟乙烯(Polytetrafluoro ethylene，PFA)、聚对苯二甲酸乙二醇酯(Polyethylene terephthalate，PET)基板等。在其他实施例中，形成源极电极层11之前，还可以在衬底基板上沉积一层一定厚度的缓冲层(图未示)。沉积材料可以为单层或多层氧化硅(SiOx)/氮化硅(SiNx)，用于提高待形成的源极电极层11与基板10之间的附着程度，有利于降低热传导效应。源极电极层11与漏极电极层13平行设置与基板10上。支撑层12为绝缘层，用于支撑/隔离源极电极层11与漏极电极层13，支撑层12在刻蚀过程中，由于加入大量的四氟化碳(CF4) 和氧气(O2)，会导致支撑层12中残留部分氟原子。阻挡层14具体可以为氧化硅(SiOx)，在一些应用场景中也可以为氮化硅(SiNx)等，当然在其它应用场景中也可以由其它绝缘物质制作而成。
可选的，阻挡层14的厚度为200A-10000A。有源层15为氧化物半导体层，具体可以为非晶氧化物，如铟氧化物、锌氧化物、锡氧化物、镓氧化物等中的至少一种。
进一步的，阻挡层14上设有第一接触孔14a，以露出部分漏极电极层13；阻挡层14还设有第二接触孔14b，以露出部分源极电极层11；有源层15通过第一接触孔14a及第二接触孔14b与漏极电极层13和源极电极层11电连接。
通过上述方式，将源极电极层及漏极电极层之间的支撑层与有源层隔离，可以防止支撑层中的氟原子进入有源层，进而提高阵列基板的可靠性。
请参阅图2，图2是本发明阵列基板另一实施方式的结构示意图。如图2所示，阵列基板还包括：栅极绝缘层26，形成在有源层25上；栅极电极层27，形成在栅极绝缘层26上。
其中，栅极绝缘层26具体可以为氧化硅(SiOx)/氮化硅(SiNx)等。栅极电极层27具体可以为单金属层或复合金属层，如铬(Cr)、钼(Mo)、钼(Mo)/铝(Al)、铜(Cu)等。栅极电极层27与源极电极层21及漏极电极层23形成顶栅结构的薄膜晶体管，源极和漏极可以视作不区分的两个电极。
进一步的，有源层25为氧化物半导体层；氧化物半导体层通过阻挡层24的第一接触孔24a及第二接触孔24b与漏极电极层23和源极电极层21电连接，形成垂直型氧化物薄膜晶体管。
其中，有源层25具体为铟镓锌氧化物(indiumgallium zinc oxide，IGZO)，可以提高薄膜晶体管对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，进而提高了像素的行扫描速率。
参考图3，图3是本发明阵列基板制作方法一实施方式的流程示意图。其中，阵列基板的制作方法包括以下步骤：
S30：在一衬底基板上通过物理气相沉积方法形成源极电极层。
衬底基板可以为透明材质，具体可以为隔水隔氧透明有机材质或玻璃。常见的有玻璃基板、二氧化硅基板，也有一些应用中可采用聚氯乙烯(Polyvinyl chloride，PVC)、可溶性聚四氟乙烯(Polytetrafluoro ethylene，PFA)、聚对苯二甲酸乙二醇酯(Polyethylene terephthalate，PET)基板等。在其他实 施例中，形成源极电极层之前，还可以在衬底基板上沉积一层一定厚度的缓冲层(图未示)。沉积材料可以为单层或多层氧化硅(SiOx)/氮化硅(SiNx)，用于提高待形成的源极电极层与基板之间的附着程度，有利于降低热传导效应。
在具体实施过程中，在衬底基板上通过物理气相沉积(PVD)方法，经过光刻胶涂覆、曝光、显影、蚀刻以及光刻胶剥离等工艺以形成具有预定图案的源极电极层。
S31：在源极电极层上采用化学气相沉积方法沉积氧化硅和/或氮化硅，以形成绝缘材料层，在绝缘材料层上通过物理气相沉积方法沉积金属物质并采用图形化处理以形成漏极电极层，并以漏极电极层为光罩，对绝缘材料层进行干刻蚀，以形成支撑层。
在具体实施过程中，在源极电极层上采用化学气相沉积(CVD)方法以及黄光蚀刻工艺，沉积单层的氧化硅(SiOx)膜层或氮化硅(SiNx)膜层，或者为氧化硅(SiOx)和氮化硅(SiNx)的叠层，以形成绝缘材料层，为后续形成支撑层做准备。通过物理气相沉积(PVD)方法，经过曝光、蚀刻等工艺，在绝缘材料层上形成漏极电极层，并以漏极为光罩，对绝缘材料层进行干刻蚀，以最终形成支撑层。由于加入了四氟化碳(CF4)和氧气(O2)，在刻蚀过程中，支撑层中会残留部分氟原子。
S32：在漏极电极层上沉积氧化硅和/或氮化硅以形成阻挡层。
通过在漏极图案上采用化学气相沉积(CVD)以及黄光蚀刻工艺，沉积单层的氧化硅(SiOx)膜层或氮化硅(SiNx)膜层，或者为氧化硅(SiOx)和氮化硅(SiNx)的叠层，以形成阻挡层，将支撑层与后面所形成的有源层进行隔离，有效防止氟原子进入有源层。
S33：在阻挡层上沉积金属材料以形成有源层，阻挡层将支撑层及有源层隔离。
可选的，阻挡层的厚度为200A-10000A。
进一步的，该方法还包括：在有源层上依次形成栅极绝缘层、栅极电极层；栅极电极层与源极电极层及漏极电极层形成顶栅结构的薄膜晶体管。
进一步的，有源层为氧化物半导体层；在阻挡层上沉积有源层包括：在阻挡层上开洞以形成通往漏极电极层和源极电极层的第一接触孔及第二接触孔；在阻挡层上沉积氧化物半导体层，使得氧化物半导体层通过第一接触孔及第二接触孔与源极电极层和漏极电极层电连接，形成垂直型氧化物薄膜晶体管。
具体实施过程中，在阻挡层上开洞，以形成通往漏极电极层以及源极电极层的第一接触孔及第二接触孔，在阻挡层上沉积铟氧化物、锌氧化物、锡氧化物、镓氧化物等中的至少一种，以形成有源层，使得该有源层通过第一接触孔和第二接触孔上分别与漏极电极层以及源极电极层相连接。
通过上述方法，可以有效防止有源层不受支撑层中氟原子的影响，进而提高阵列基板的可靠性。
本发明还包括一种显示装置，如图4所示，该显示装置40包括上述任意结构的阵列基板41，或者由上述任意一方法所制备的阵列基板41，具体方法如上述各实施方式，上述方法可用于制作形成图1/图2所示的阵列基板，在此处不再赘述。进一步地，显示装置可以为主动矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)或TFT LCD显示装置。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种显示装置，其中，所述显示装置包括阵列基板，
    所述阵列基板包括：基板；源极电极层，形成在所述基板上；支撑层，形成在所述源极电极层上；漏极电极层，形成在所述支撑层上；阻挡层，覆盖在所述漏极电极层上；有源层，形成在所述阻挡层上；所述阻挡层将所述支撑层与所述有源层隔离；所述阻挡层为氧化硅或氮化硅形成的绝缘层；所述阻挡层的厚度为200A-10000A。
  2. 根据权利要求1所述的显示装置，其中，所述阵列基板还包括：
    栅极绝缘层，形成在所述有源层上；
    栅极电极层，形成在所述栅极绝缘层上；
    所述栅极电极层与所述源极电极层及所述漏极电极层形成顶栅结构的薄膜晶体管。
  3. 根据权利要求2所述的显示装置，其中，所述有源层为氧化物半导体层；所述阻挡层上设有第一接触孔，以露出部分漏极电极层；所述阻挡层还设有第二接触孔，以露出部分源极电极层；所述氧化物半导体层通过所述第一接触孔及第二接触孔与所述漏极电极层和所述源极电极层电连接。
  4. 根据权利要求1所述的显示装置，其中，所述阵列基板包括以下制作方法：
    在一衬底基板上通过物理气相沉积方法形成源极电极层；
    在所述源极电极层上采用化学气相沉积方法沉积氧化硅和/或氮化硅，以形成绝缘材料层，在所述绝缘材料层上通过物理气相沉积方法沉积金属物质并采用图形化处理以形成漏极电极层，并以所述漏极电极层为光罩，对所述绝缘材料层进行干刻蚀，以形成支撑层；
    在所述漏极电极层上沉积氧化硅和/或氮化硅以形成阻挡层；
    在所述阻挡层上沉积金属材料以形成有源层，所述阻挡层将所述支撑层及所述有源层隔离。
  5. 根据权利要求4所述的显示装置，其中，所述阵列基板还包括以下制作方法：
    在所述有源层上依次形成栅极绝缘层、栅极电极层；
    所述栅极电极层与所述源极电极层及所述漏极电极层形成顶栅结构的薄膜晶体管。
  6. 根据权利要求5所述的显示装置，其中，所述显示装置为主动矩阵有机发光二极体AMOLED或TFT LCD显示装置。
  7. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    源极电极层，形成在所述基板上；
    支撑层，形成在所述源极电极层上；
    漏极电极层，形成在所述支撑层上；
    阻挡层，覆盖在所述漏极电极层上；
    有源层，形成在所述阻挡层上；
    所述阻挡层将所述支撑层与所述有源层隔离。
  8. 根据权利要求7所述的阵列基板，其中，所述阻挡层为氧化硅或氮化硅形成的绝缘层。
  9. 根据权利要求7所述的阵列基板，其中，所述阻挡层的厚度为200A-10000A。
  10. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括：
    栅极绝缘层，形成在所述有源层上；
    栅极电极层，形成在所述栅极绝缘层上；
    所述栅极电极层与所述源极电极层及所述漏极电极层形成顶栅结构的薄膜晶体管。
  11. 根据权利要求10所述的阵列基板，其中，所述有源层为氧化物半导体层；所述阻挡层上设有第一接触孔，以露出部分漏极电极层；所述阻挡层还设有第二接触孔，以露出部分源极电极层；
    所述氧化物半导体层通过所述第一接触孔及第二接触孔与所述漏极电极层和所述源极电极层电连接。
  12. 一种阵列基板的制作方法，其中，所述方法包括：
    在一衬底基板上通过物理气相沉积方法形成源极电极层；
    在所述源极电极层上采用化学气相沉积方法沉积氧化硅和/或氮化硅，以形成绝缘材料层，在所述绝缘材料层上通过物理气相沉积方法沉积金属物质并采用图形化处理以形成漏极电极层，并以所述漏极电极层为光罩，对所述绝缘材料层进行干刻蚀，以形成支撑层；
    在所述漏极电极层上沉积氧化硅和/或氮化硅以形成阻挡层；
    在所述阻挡层上沉积金属材料以形成有源层，所述阻挡层将所述支撑层及所述有源层隔离。
  13. 根据权利要求12所述的方法，其中，所述阻挡层的厚度为200A-10000A。
  14. 根据权利要求12所述的方法，其中，所述方法还包括：
    在所述有源层上依次形成栅极绝缘层、栅极电极层；
    所述栅极电极层与所述源极电极层及所述漏极电极层形成顶栅结构的薄膜晶体管。
  15. 根据权利要求14所述的方法，其中，
    所述有源层为氧化物半导体层；
    在所述阻挡层上沉积有源层包括：
    在所述阻挡层上开洞以形成通往所述漏极电极层和所述源极电极层的第一接触孔及第二接触孔；
    在所述阻挡层上沉积氧化物半导体层，使得所述氧化物半导体层通过所述第一接触孔及第二接触孔与所述漏极电极层和所述源极电极层电连接。
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