WO2019006818A1 - 一种显示面板和显示装置 - Google Patents

一种显示面板和显示装置 Download PDF

Info

Publication number
WO2019006818A1
WO2019006818A1 PCT/CN2017/096722 CN2017096722W WO2019006818A1 WO 2019006818 A1 WO2019006818 A1 WO 2019006818A1 CN 2017096722 W CN2017096722 W CN 2017096722W WO 2019006818 A1 WO2019006818 A1 WO 2019006818A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
insulating layer
layer
amorphous silicon
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/096722
Other languages
English (en)
French (fr)
Inventor
卓恩宗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US16/338,534 priority Critical patent/US10797081B2/en
Publication of WO2019006818A1 publication Critical patent/WO2019006818A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display panel and a display device.
  • the existing displays are generally controlled based on the active switch, and have many advantages such as thin body, power saving, no radiation, etc., and have been widely used, mainly including liquid crystal display, OLED (Organic Light-Emitting Diode) display, QLED (Quantum) Dot Light Emitting Diodes), such as displays and plasma displays, have both a flat display and a curved display.
  • OLED Organic Light-Emitting Diode
  • QLED Quadantum Dot Light Emitting Diodes
  • displays and plasma displays have both a flat display and a curved display.
  • the liquid crystal display works by placing liquid crystal molecules in two parallel glass substrates and applying a driving voltage on the two glass substrates to control the liquid crystal. The direction of rotation of the molecules to refract the light from the backlight module to produce a picture.
  • the self-luminous display of the machine light-emitting diode is used for display, and has the advantages of self-illumination, wide viewing angle, almost infinite contrast, low power consumption, and extremely high reaction speed.
  • the QLED display structure is very similar to the OLED technology. The main difference is that the luminescent center of the QLED is composed of Quantum dots. Its structure is that two electrons (Electron) and holes (Hole) converge in the quantum dot layer to form photons (Exciton), and recombine by photons.
  • the quality of the interface will be degraded, and the leakage current leakage will also increase, which not only causes the reliability of the active switch to be deteriorated, but also Will affect the normal use of the active switch.
  • the display panel provided by the embodiment of the present application includes:
  • the substrate being provided with a plurality of pixel regions
  • An active switch a plurality of the active switches are disposed on the substrate, the pixel area is disposed on the active switch, the active switch is in one-to-one correspondence with the pixel area, and the active switch comprises an insulating layer.
  • the insulating layer includes at least two films formed by chemical vapor deposition at a predetermined thickness.
  • the active switch includes a gate layer disposed at a bottom portion, and the gate layer is provided with an insulating layer, the insulating layer includes a first film of an insulating layer, a second film of an insulating layer, and a first film of the insulating layer The second film of the insulating layer is sequentially arranged, the first film of the insulating layer is disposed at an end away from the gate layer, and the second film of the insulating layer is disposed at an end of the insulating layer;
  • the insulating layer has a thickness of 3500 to 4000 angstroms
  • the insulating layer first film has a thickness of 500 to 2000 angstroms
  • the insulating layer second film has a thickness of 2000 to 3500 angstroms.
  • the insulating layer is provided with two layers of film, and the thickness of the insulating layer and the respective film are set.
  • the active switch includes a gate layer disposed at a bottom portion, the insulating layer includes a first film of an insulating layer, a second film of an insulating layer, a third film of an insulating layer, a first film of the insulating layer, and the insulating layer a second film, the third film of the insulating layer is sequentially arranged, the first film of the insulating layer is disposed at an end away from the gate layer, and the third film of the insulating layer is disposed at an end close to the gate layer
  • the insulating layer has a thickness of 3500 to 4000 angstroms, the insulating layer first film has a thickness of 500 to 2000 angstroms, and the insulating layer second film has a thickness of 1000 to 3000 angstroms, the insulating layer
  • the third film has a thickness of 500 to 2000 angstroms.
  • the insulating layer is provided with three layers of film, and the thickness of the insulating layer and the respective film are set.
  • the arrangement of the three-layer film can better improve the quality of the interface between the insulating layer and the amorphous silicon layer and the uniformity of the insulating layer.
  • the insulating layer is provided with an amorphous silicon layer
  • the amorphous silicon layer comprises two layers of a film: an amorphous silicon layer first film, an amorphous silicon layer second film, and the amorphous silicon layer first film.
  • the second film of the amorphous silicon layer is sequentially arranged, the first film of the amorphous silicon layer is disposed at one end away from the insulating layer, and the second film of the amorphous silicon layer is disposed adjacent to the insulating layer One end; the first film of the amorphous silicon layer has a thickness of 1000 angstroms, and the second film of the amorphous silicon layer has a thickness of 300 angstroms.
  • the amorphous silicon layer In the case of two layers of film, the respective thicknesses of the films are set. With the arrangement of the insulating layer, the quality of the interface can be improved, the uniformity of the amorphous silicon layer can be improved, and the rate of chemical vapor deposition for film deposition processing can be accelerated.
  • the silicon tetrachloride, ammonia gas and nitrogen gas in the first film of the insulating layer are respectively 2300 to 2530 standard milliliters per minute, 15000 to 16000 standard conditions, milliliters per minute, and 68000 to 83500 standard milliliters. Per minute;
  • the silicon dioxide, ammonia gas and nitrogen gas in the second film of the insulating layer are respectively 5500 standard milliliters per minute, 30000 standard conditions milliliters per minute, and 80,000 standard conditions per minute;
  • silicon tetrahydride, ammonia gas and nitrogen gas are respectively 7000 to 7200 standard milliliters per minute, 26,000 to 27,000 standard conditions, milliliters per minute, and 66,000 to 70,000 standard milliliters per minute.
  • the gas volume flow rate at the time of deposition of each film in the case where the insulating layer is provided with a three-layer film ensures the normal function of the formed insulating layer.
  • the pressure applied to the first film of the insulating layer is 1200 to 1400 mTorr
  • the pressure applied to the second film of the insulating layer is 1550 mTorr
  • the pressure applied to the third film of the insulating layer It is 1400 to 1500 mTorr.
  • the pressure setting required for deposition of each film in the case where the insulating layer is provided with a three-layer film.
  • the film of the insulating layer is formed by chemical vapor deposition at a preset temperature, and the temperature is 340 degrees Celsius or 360 degrees Celsius.
  • the temperature setting in the case where the insulating layer is provided with a three-layer film.
  • the amorphous silicon layer is provided with an ohmic contact layer corresponding to the amorphous silicon layer, and the two ends of the ohmic contact layer are provided with a source layer and a drain layer separated by the active switch, the source A channel is disposed between the pole layer and the drain layer, the channel passing through the ohmic contact layer, and the bottom of the channel is an amorphous silicon layer.
  • the specific settings for each layer of the active switch are the specific settings for each layer of the active switch.
  • Another object of the present application is to provide a display panel that cooperates with an active switch.
  • a display panel comprising:
  • the substrate being provided with a plurality of pixel regions
  • An active switch a plurality of the active switches are disposed on the substrate, the pixel area is disposed on the active switch, the active switch is in one-to-one correspondence with the pixel area, and the active switch comprises an insulating layer.
  • the insulating layer comprises at least two layers of films formed by chemical vapor deposition at a predetermined thickness;
  • the active switch includes a gate layer disposed at a bottom portion, the insulating layer includes a first film of an insulating layer, a second film of an insulating layer, a third film of an insulating layer, a first film of the insulating layer, and a second film of the insulating layer
  • the third film of the insulating layer is sequentially arranged, the first film of the insulating layer is disposed at an end away from the gate layer, and the third film of the insulating layer is disposed at an end of the insulating layer;
  • the insulating layer has a thickness of 3500 to 4000 angstroms
  • the insulating layer first film has a thickness of 500 to 2000 angstroms
  • the insulating layer second film has a thickness of 1000 to 3000 angstroms
  • the insulating layer is The thickness of the three films is 500 to 2000 angstroms;
  • An amorphous silicon layer is disposed on the insulating layer, and the amorphous silicon layer comprises two layers of a film: a first film of an amorphous silicon layer, a second film of an amorphous silicon layer, and a first film of the amorphous silicon layer.
  • the second film of the amorphous silicon layer is sequentially arranged, the first film of the amorphous silicon layer is disposed at one end away from the insulating layer, and the second film of the amorphous silicon layer is disposed at one end of the insulating layer;
  • the thickness of the first film of the amorphous silicon layer is 1000 angstroms, and the thickness of the second film of the amorphous silicon layer is 300 angstroms;
  • the silicon tetrachloride, ammonia gas and nitrogen gas in the first film of the insulating layer are respectively 2300 to 2530 standard milliliters per minute, 15000 to 16000 standard conditions, milliliters per minute, and 68000 to 83500 standard milliliters per minute.
  • the silicon dioxide, ammonia gas and nitrogen gas in the second film of the insulating layer are respectively 5500 standard milliliters per minute, 30,000 standard milliliters per minute, 80,000 standard milliliters per minute;
  • the fourth layer of the third thin film of the insulating layer Silicon, ammonia, and nitrogen are respectively 7000 to 7200 standard milliliters per minute, 26,000 to 27,000 standard conditions, milliliters per minute, and 66,000 to 70,000 standard milliliters per minute;
  • the pressure applied to the first film of the insulating layer is 1200 to 1400 mTorr, the pressure applied to the second film of the insulating layer is 1550 mTorr, and the pressure applied to the third film of the insulating layer is 1400. Up to 1500 mTorr;
  • the film of the insulating layer is formed by chemical vapor deposition at a preset temperature, which is 340 degrees Celsius or 360 degrees Celsius.
  • Another object of the present application is to provide a display device that cooperates with an active switch.
  • a display device includes a control component, and a display panel as described herein.
  • the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the uniformity of the insulating layer is formed by chemical vapor deposition, and the insulating layer is improved.
  • FIG. 1 is a schematic structural view of an active switch in a display panel according to an embodiment of the present application
  • FIG. 2 is a schematic view showing layered deposition of an insulating layer of a display panel according to an embodiment of the present application
  • FIG. 3 is a schematic structural view showing an insulating layer of a display panel divided into two layers and an amorphous silicon layer divided into two layers by a thin film according to an embodiment of the present application;
  • FIG. 4 is a schematic structural view showing an insulating layer of a display panel divided into three layers and an amorphous silicon layer divided into two layers by a thin film according to an embodiment of the present application;
  • FIG. 5 is a schematic diagram of a display device according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meanings of the above terms in the present application can be understood in the specific circumstances for those skilled in the art.
  • the display panel includes: a substrate 10, the substrate 10 is provided with a plurality of pixel regions; and an active switch, a plurality of the active switches are disposed on the substrate 10
  • the pixel area is disposed on the active switch, the active switch is in one-to-one correspondence with the pixel area, the active switch includes: an insulating layer 40, and the insulating layer 40 includes at least two layers of films, The film is formed by chemical vapor deposition at a predetermined thickness.
  • the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the insulating layer 40 is formed by chemical vapor deposition to have better uniformity and improved insulation.
  • CVD Chemical Vapor Deposition
  • gas phase reaction at high temperature developed as a means of coating, but not only for the coating of heat-resistant substances, but also for the purification of high-purity metals, powder synthesis , semiconductor film, etc.
  • the deposition temperature is low, the film composition is easy to control, the film thickness is proportional to the deposition time, the uniformity, the repeatability is good, and the step coverage is excellent.
  • the technical characteristics of the chemical vapor deposition method are: the high melting point substance can be synthesized at a low temperature; the form of the precipitated substance is various in a single crystal, a polycrystal, a whisker, a powder, a film, etc.; not only the coating can be performed on the substrate, but also Coating on the surface of the powder, etc.
  • high-melting substances can be synthesized at low temperatures, contributing to energy conservation, and it is promising as a new technology.
  • the display panel includes: a substrate 10, the substrate 10 is provided with a plurality of pixel regions; and an active switch, a plurality of the active switches are disposed on the substrate 10
  • the pixel area is disposed on the active switch, the active switch is in one-to-one correspondence with the pixel area, the active switch includes: an insulating layer 40, and the insulating layer 40 includes at least two layers of films, The film is formed by chemical vapor deposition at a predetermined thickness.
  • the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the insulating layer 40 is formed by chemical vapor deposition to have better uniformity and improved insulation.
  • the active switch includes a gate layer 21 disposed at the bottom, the gate layer 21 is provided with an insulating layer 40, and the insulating layer 40 is provided with an amorphous silicon layer 50 disposed on the amorphous silicon layer 50.
  • the insulating layer 40 includes an insulating layer first film 41 and an insulating layer second film 42. The insulating layer first film 41 and the insulating layer second film 42 are separated from one end of the gate layer 21 to the vicinity.
  • the insulating layer 40 has a thickness of 3500 to 4000 angstroms
  • the insulating layer first film 41 has a thickness of 500 to 2000 angstroms
  • the insulating layer second film 42 The thickness is 2,000 to 3,500 angstroms.
  • the display panel includes: a substrate 10, the substrate 10 is provided with a plurality of pixel regions; and an active switch, a plurality of the active switches are disposed on the substrate 10,
  • the pixel area is disposed on the active switch, the active switch is in one-to-one correspondence with the pixel area, the active switch includes: an insulating layer 40, the insulating layer 40 includes at least two layers of films, and the film passes The manner of chemical vapor deposition is formed with a predetermined thickness.
  • the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the insulating layer 40 is formed by chemical vapor deposition to have better uniformity and improved insulation.
  • the active switch includes a gate layer 21 disposed at the bottom, the gate layer 21 is provided with an insulating layer 40, and the insulating layer 40 is provided with an amorphous silicon layer 50 disposed on the amorphous silicon layer 50.
  • ohmic contact layer 60 corresponding to the amorphous silicon layer 50, and the source layer 22 and the drain layer 23 of the active switch are separated at both ends of the ohmic contact layer 60, and the source layer 22 and the A channel is disposed between the drain layers 23, and the channel passes through the ohmic contact layer 60, and the bottom of the channel is an amorphous silicon layer 50.
  • the insulating layer 40 includes an insulating layer first film 41, an insulating layer second film 42, and an insulating layer third film 43, the insulating layer first film 41, the insulating layer second film 42, and the insulating layer
  • the third thin film 43 is sequentially arranged from one end away from the gate layer 21 to one end close to the gate layer 21, and the insulating layer 40 has a thickness of 3500 to 4000 angstroms, and the insulating layer first film 41
  • the thickness of the second film 42 of the insulating layer is 1000 to 3000 angstroms
  • the thickness of the third film 43 of the insulating layer is 500 to 2000 angstroms.
  • the arrangement of the three-layer film can better improve the quality of the interface between the insulating layer 40 and the amorphous silicon layer 50 and the uniformity of the insulating layer 40.
  • the display panel includes: a substrate 10, The substrate 10 is provided with a plurality of pixel regions; an active switch, a plurality of the active switches are disposed on the substrate 10, the pixel area is disposed on the active switch, and the active switch is in one-to-one correspondence with the pixel area
  • the active switch includes an insulating layer 40 including at least two layers of thin films formed by chemical vapor deposition at a predetermined thickness. By providing at least two thin films to the insulating layer 40, the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the insulating layer 40 is formed by chemical vapor deposition to have better uniformity and improved insulation.
  • the active switch includes a gate layer 21 disposed at the bottom, the gate layer 21 is provided with an insulating layer 40, and the insulating layer 40 is provided with an amorphous silicon layer 50 disposed on the amorphous silicon layer 50.
  • the insulating layer 40 includes an insulating layer first film 41 and an insulating layer second film 42.
  • the insulating layer first film 41 and the insulating layer second film 42 are separated from one end of the gate layer 21 to the vicinity.
  • One end of the gate layer 21 is sequentially arranged, the insulating layer 40 has a thickness of 3500 to 4000 angstroms, and the insulating layer first film 41 has a thickness of 500 to 2000 angstroms, and the insulating layer second film 42 The thickness is 2,000 to 3,500 angstroms.
  • the amorphous silicon layer 50 includes two layers of a film: an amorphous silicon layer first film 51, an amorphous silicon layer second film 52, the amorphous silicon layer first film 51, and the amorphous silicon layer second film.
  • 52 is sequentially arranged from one end away from the insulating layer 40 to one end close to the insulating layer 40, the amorphous film first film 51 has a thickness of 1000 angstroms, and the amorphous silicon layer second film 52 The thickness is 300 angstroms.
  • the arrangement of the insulating layer 40 can improve the quality of the interface, improve the uniformity of the amorphous silicon layer 50, and accelerate the chemical vapor deposition for the film deposition processing rate.
  • the display panel includes: a substrate 10, the substrate 10 is provided with a plurality of pixel regions; and an active switch, a plurality of the active switches are disposed on the substrate 10, The pixel area is disposed on the active switch, and the active switch is in one-to-one correspondence with the pixel area.
  • the active switch includes: an insulating layer 40, and the insulating layer 40 includes at least two layers of films. The manner of chemical vapor deposition is formed at a predetermined thickness.
  • the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the insulating layer 40 is formed by chemical vapor deposition to have better uniformity and improved insulation.
  • the active switch includes a gate layer 21 disposed at the bottom, the gate layer 21 is provided with an insulating layer 40, and the insulating layer 40 is provided with an amorphous silicon layer 50 disposed on the amorphous silicon layer 50.
  • ohmic contact layer 60 corresponding to the amorphous silicon layer 50, and the source layer 22 and the drain layer 23 of the active switch are separated at both ends of the ohmic contact layer 60, and the source layer 22 and the A channel is disposed between the drain layers 23, and the channel passes through the ohmic contact layer 60, and the bottom of the channel is an amorphous silicon layer 50.
  • the insulating layer 40 includes an insulating layer first film 41, an insulating layer second film 42, and an insulating layer third film 43, the insulating layer first film 41, the insulating layer second film 42, and the insulating layer
  • the third thin film 43 is sequentially arranged from one end away from the gate layer 21 to one end close to the gate layer 21, and the insulating layer 40 has a thickness of 3500 to 4000 angstroms, and the insulating layer first film 41
  • the thickness of the second film 42 of the insulating layer is 1000 to 3000 angstroms
  • the thickness of the third film 43 of the insulating layer is 500 to 2000 angstroms.
  • the arrangement of the three-layer film can better improve the quality of the interface between the insulating layer 40 and the amorphous silicon layer 50 and the uniformity of the insulating layer 40.
  • the amorphous silicon layer 50 includes two layers of a film: an amorphous silicon layer first film 51, an amorphous silicon layer second film 52, the amorphous silicon layer first film 51, and the amorphous silicon layer second film. 52 is sequentially arranged from one end away from the insulating layer 40 to one end close to the insulating layer 40, the amorphous film first film 51 has a thickness of 1000 angstroms, and the amorphous silicon layer second film 52 The thickness is 300 angstroms.
  • the arrangement of the insulating layer 40 can improve the quality of the interface, improve the uniformity of the amorphous silicon layer 50, and accelerate the chemical vapor deposition for the film deposition processing rate.
  • the thickness of the insulating layer 40 may also be 4000 angstroms, the thickness of the first film 41 of the insulating layer is 1000 angstroms, and the thickness of the second film 42 of the insulating layer is 1000 angstroms, the insulating layer
  • the third film 43 has a thickness of 2000 angstroms.
  • the amorphous silicon layer first film 51 has a thickness of 1000 angstroms, and the amorphous silicon layer second film 52 has a thickness of 300 angstroms.
  • the ohmic contact layer 60 has a thickness of 400 angstroms.
  • the display panel includes: a substrate 10, the substrate 10 is provided with a plurality of pixel regions; and an active switch, a plurality of the active switches are disposed on the substrate 10,
  • the pixel area is disposed on the active switch, the active switch is in one-to-one correspondence with the pixel area, the active switch includes: an insulating layer 40, the insulating layer 40 includes at least two layers of films, and the film passes The manner of chemical vapor deposition is formed with a predetermined thickness.
  • the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the insulating layer 40 is formed by chemical vapor deposition to have better uniformity and improved insulation.
  • the active switch includes a gate layer 21 disposed at the bottom, the gate layer 21 is provided with an insulating layer 40, and the insulating layer 40 is provided with an amorphous silicon layer 50 disposed on the amorphous silicon layer 50.
  • ohmic contact layer 60 corresponding to the amorphous silicon layer 50, and the source layer 22 and the drain layer 23 of the active switch are separated at both ends of the ohmic contact layer 60, and the source layer 22 and the A channel is disposed between the drain layers 23, and the channel passes through the ohmic contact layer 60, and the bottom of the channel is an amorphous silicon layer 50.
  • the insulating layer 40 includes an insulating layer first film 41, an insulating layer second film 42, and an insulating layer third film 43, the insulating layer first film 41, the insulating layer second film 42, and the insulating layer
  • the third thin film 43 is sequentially arranged from one end away from the gate layer 21 to one end close to the gate layer 21, and the insulating layer 40 has a thickness of 3500 to 4000 angstroms, and the insulating layer first film 41
  • the thickness of the second film 42 of the insulating layer is 1000 to 3000 angstroms
  • the thickness of the third film 43 of the insulating layer is 500 to 2000 angstroms.
  • the arrangement of the three-layer film can better improve the quality of the interface between the insulating layer 40 and the amorphous silicon layer 50 and the uniformity of the insulating layer 40.
  • the amorphous silicon layer 50 includes two layers of a film: an amorphous silicon layer first film 51, an amorphous silicon layer second film 52, the amorphous silicon layer first film 51, and the amorphous silicon layer second film. 52 is sequentially arranged from one end away from the insulating layer 40 to one end close to the insulating layer 40, the amorphous film first film 51 has a thickness of 1000 angstroms, and the amorphous silicon layer second film 52 The thickness is 300 angstroms.
  • the arrangement of the insulating layer 40 can improve the quality of the interface, improve the uniformity of the amorphous silicon layer 50, and accelerate the chemical vapor deposition for the film deposition processing rate.
  • the standard condition is ML per minute, 30000 standard condition milliliters per minute, and 80,000 standard conditions per minute; the fourth film 43 of the insulating layer contains silicon tetrachloride, ammonia gas and nitrogen gas respectively of 7000 to 7200 standard conditions per minute, 26000 to 27000 standard conditions ml per minute, 66000 to 70,000 standard conditions per minute.
  • the pressure applied to the first film 41 of the insulating layer is 1200 to 1400 mTorr, and the pressure applied to the second film 42 of the insulating layer is 1550 mTorr, which is applied to the third film 43 of the insulating layer.
  • the pressure is 1400 to 1500 mTorr.
  • the film is formed by chemical vapor deposition at a preset temperature of 340 degrees Celsius or 360 degrees Celsius.
  • the thickness of the insulating layer 40 may also be 4500 mils, the thickness of the first film 41 of the insulating layer is 500 angstroms, and the thickness of the second film 42 of the insulating layer is 2000 angstroms, the insulating layer
  • the third film 43 has a thickness of 2000 angstroms.
  • the amorphous silicon layer first film 51 has a thickness of 1000 angstroms, and the amorphous silicon layer second film 52 has a thickness of 300 angstroms.
  • the silicon tetrahydride, ammonia gas and nitrogen gas in the first film 41 of the insulating layer are respectively 2300 standard milliliters per minute, 16,000 standard conditions milliliters per minute, and 70,000 standard conditions per minute;
  • the silicon tetrahydride, ammonia gas and nitrogen gas in the second film 42 are respectively 5500 standard milliliters per minute, 30,000 standard milliliters per minute, 80,000 standard milliliters per minute;
  • the fourth thin film 43 of the insulating layer is tetrahydrogen silicon and ammonia.
  • Gas and nitrogen are respectively 7000 standard conditions per minute, 27,000 standard conditions, milliliters per minute, and 70,000 standard conditions per minute.
  • the pressure applied to the first film 41 of the insulating layer is 1200 mTorr
  • the pressure applied to the second film 42 of the insulating layer is 1550 mTorr
  • the pressure applied to the third film 43 of the insulating layer is 1500 mTorr.
  • the film is formed by chemical vapor deposition at a preset temperature of 340 degrees Celsius or 360 degrees Celsius.
  • the display panel includes: a substrate 10, the substrate 10 is provided with a plurality of pixel regions; and an active switch, a plurality of the active switches are disposed on the substrate 10,
  • the pixel area is disposed on the active switch, the active switch is in one-to-one correspondence with the pixel area, the active switch includes: an insulating layer 40, the insulating layer 40 includes at least two layers of films, and the film passes The manner of chemical vapor deposition is formed with a predetermined thickness.
  • the thin film transistor includes an insulating layer 40, The insulating layer 40 includes at least two films which are formed by chemical vapor deposition at a predetermined thickness.
  • the thin film is formed by chemical vapor deposition at a predetermined thickness and at a predetermined deposition rate, and the insulating layer 40 is formed by chemical vapor deposition to have better uniformity and improved insulation.
  • the thin film transistor includes a gate layer 21 disposed at the bottom, the gate layer 21 is provided with an insulating layer 40, and the insulating layer 40 is provided with an amorphous silicon layer 50 disposed on the amorphous silicon layer 50.
  • ohmic contact layer 60 corresponding to the amorphous silicon layer 50, and the source layer 22 and the drain layer 23 of the thin film transistor are separated at both ends of the ohmic contact layer 60, and the source layer 22 and the A channel is disposed between the drain layers 23, and the channel passes through the ohmic contact layer 60, and the bottom of the channel is an amorphous silicon layer 50.
  • the insulating layer 40 includes an insulating layer first film 41, an insulating layer second film 42, and an insulating layer third film 43, the insulating layer first film 41, the insulating layer second film 42, and the insulating layer
  • the third thin film 43 is sequentially arranged from one end away from the gate layer 21 to one end close to the gate layer 21, and the insulating layer 40 has a thickness of 3500 to 4000 angstroms, and the insulating layer first film 41
  • the thickness of the second film 42 of the insulating layer is 1000 to 3000 angstroms
  • the thickness of the third film 43 of the insulating layer is 500 to 2000 angstroms.
  • the arrangement of the three-layer film can better improve the quality of the interface between the insulating layer 40 and the amorphous silicon layer 50 and the uniformity of the insulating layer 40.
  • the amorphous silicon layer 50 includes two layers of a film: an amorphous silicon layer first film 51, an amorphous silicon layer second film 52, the amorphous silicon layer first film 51, and the amorphous silicon layer second film. 52 is sequentially arranged from one end away from the insulating layer 40 to one end close to the insulating layer 40, the amorphous film first film 51 has a thickness of 1000 angstroms, and the amorphous silicon layer second film 52 The thickness is 300 angstroms.
  • the arrangement of the insulating layer 40 can improve the quality of the interface, improve the uniformity of the amorphous silicon layer 50, and accelerate the chemical vapor deposition for the film deposition processing rate.
  • the silicon tetrahydride, the ammonia gas, and the nitrogen gas in the first film 41 of the insulating layer are respectively 2300 to 2530 standard milliliters per minute, 15000 to 16000 standard conditions, milliliters per minute, and 68,000 to 83,500 standards.
  • the silicon tetrachloride, ammonia, and nitrogen in the second film 42 of the insulating layer are respectively 5500 standard milliliters per minute, 30,000 standard milliliters per minute, and 80,000 standard milliliters per minute;
  • the silicon tetrachloride, ammonia gas and nitrogen gas in the third film 43 are respectively 7000 to 7200 standard milliliters per minute, 26,000 to 27,000 standard milliliters per minute, and 66,000 to 70,000 standard milliliters per minute.
  • the pressure applied to the first film 41 of the insulating layer is 1200 to 1400 mTorr, and the pressure applied to the second film 42 of the insulating layer is 1550 mTorr, which is applied to the third film 43 of the insulating layer.
  • the pressure is 1400 to 1500 mTorr.
  • the film is formed by chemical vapor deposition at a preset temperature of 340 degrees Celsius or 360 degrees Celsius.
  • the thickness of the insulating layer 40 may also be 4500 mils, the thickness of the first film 41 of the insulating layer is 500 angstroms, and the thickness of the second film 42 of the insulating layer is 2000 angstroms, the insulating layer
  • the third film 43 has a thickness of 2000 angstroms.
  • the amorphous silicon layer first film 51 has a thickness of 1000 angstroms, and the amorphous silicon layer second film 52 has a thickness of 300 angstroms.
  • the silicon tetrahydride, ammonia gas and nitrogen gas in the first film 41 of the insulating layer are respectively 2300 standard milliliters per minute, 16,000 standard conditions milliliters per minute, and 70,000 standard conditions per minute;
  • the silicon tetrahydride, ammonia gas and nitrogen gas in the second film 42 are respectively 5500 standard milliliters per minute, 30,000 standard milliliters per minute, 80,000 standard milliliters per minute;
  • the fourth thin film 43 of the insulating layer is tetrahydrogen silicon and ammonia.
  • Gas and nitrogen are respectively 7000 standard conditions per minute, 27,000 standard conditions, milliliters per minute, and 70,000 standard conditions per minute.
  • the pressure applied to the first film 41 of the insulating layer is 1200 mTorr
  • the pressure applied to the second film 42 of the insulating layer is 1550 mTorr
  • the pressure applied to the third film 43 of the insulating layer is 1500 mTorr.
  • the film is formed by chemical vapor deposition at a preset temperature of 340 degrees Celsius or 360 degrees Celsius.
  • FIG. 1 Also included in FIG. 1 is a protective layer 70, a pixel electrode layer 80; and FIGS. 2-4 further includes a protective layer 70.
  • the display panel includes a liquid crystal panel, an OLED (Organic Light-Emitting Diode) panel, a QLED (Quantum Dot Light Emitting Diodes) panel, a plasma panel, a flat panel, a curved panel, and the like.
  • OLED Organic Light-Emitting Diode
  • QLED Quadantum Dot Light Emitting Diodes
  • the present embodiment discloses a display device 100.
  • the display device 100 includes the control unit 200, and the display panel 300 of the present application.
  • the display panel is taken as an example for detailed description. It should be noted that the above description of the structure of the display panel is also applicable to the display of the embodiment of the present application.
  • the liquid crystal display includes The backlight module and the backlight module can be used as a light source for supplying a sufficient light source and a uniform light source.
  • the backlight module of the embodiment can be either a front light type or a backlight type.
  • the backlight module is not limited to this.

Landscapes

  • Liquid Crystal (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板和显示装置。显示面板包括基板(10)，基板(10)设置有多个像素区；主动开关，多个主动开关设置在基板(10)上，像素区设置在主动开关上，主动开关与像素区一一对应，主动开关包括绝缘层(40)，绝缘层(40)包括至少两层薄膜，薄膜通过化学气相沉积的方式以预设的厚度形成。

Description

一种显示面板和显示装置 【技术领域】
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
【背景技术】
现有的显示器一般都基于主动开关进行控制，具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，主要包括液晶显示器、OLED(Organic Light-Emitting Diode)显示器、QLED(Quantum Dot Light Emitting Diodes)显示器、等离子显示器等、从外观结构来看，既有平面型显示器、也有曲面型显示器。
对于液晶显示器，包括液晶面板及背光模组(Backlight Module)两大部分，液晶显示器的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
对于OLED显示器，采用机发光二极管自发光来进行显示，具有自发光、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点。
QLED显示器结构与OLED技术非常相似，主要区别在于QLED的发光中心由量子点(Quantum dots)物质构成。其结构是两侧电子(Electron)和空穴(Hole)在量子点层中汇聚后形成光子(Exciton)，并且通过光子的重组发光。
然而对于主动开关中相关层的交界面，若使用常规的方式来提高绝缘层会使得该交界面的品质下降，同时漏电流的泄露量也增加，不仅致使主动开关的信赖性变差，同时还会影响主动开关的正常使用表现。
【发明内容】
本申请的一个目的在于提供一种与主动开关配合显示面板。
为解决上述问题，本申请的实施例提供的显示面板包括：
基板，所述基板设置有多个像素区；
主动开关，多个所述主动开关设置在所述基板上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括绝缘层，所述绝缘层包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。
其中，所述主动开关包括设置在底部的栅极层，所述栅极层上设置有绝缘层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第二薄膜设置在靠近所述栅极层的一端；
所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为2000至3500埃米。这里是绝缘层设置两层薄膜的情形，以及绝缘层与各薄膜相应的厚度设置。
其中，所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米。这里是绝缘层设置三层薄膜的情形，以及绝缘层与各薄膜相应的厚度设置。三层薄膜的设置可以更好的提高绝缘层与非晶硅层的交界面的品质以及绝缘层的均匀性。
其中，所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米。这里是非晶硅层设 置两层薄膜的情形，各薄膜相应的厚度设置。配合绝缘层的设置更能提高交界面的品质、提升非晶硅层的均匀性，更加快化学气相沉积用于薄膜沉积加工速率。
其中，进行化学气相沉积时，所述绝缘层第一薄膜中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；
所述绝缘层第二薄膜中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；
所述绝缘层第三薄膜中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分。这里是绝缘层设置三层薄膜的情形下各薄膜沉积时的气体体积流量，保证形成的绝缘层的正常功用。
其中，对所述绝缘层第一薄膜中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜中施加的压强为1550毫托，对所述绝缘层第三薄膜中施加的压强为1400至1500毫托。这里是绝缘层设置三层薄膜的情形下各薄膜沉积时所需的压强设置。
其中，所述绝缘层的薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。这里是绝缘层设置三层薄膜的情形下的温度设置。
其中，所述非晶硅层上设置有与非晶硅层对应的欧姆接触层，所述欧姆接触层上两端设置有分隔的所述主动开关的源极层和漏极层，所述源极层和所述漏极层之间设置有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层。这里是主动开关各层的具体设置。
本申请的另一个目的在于还提供一种与主动开关配合显示面板。
一种显示面板，所述显示面板包括：
基板，所述基板设置有多个像素区；
主动开关，多个所述主动开关设置在所述基板上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括绝缘层，所述绝缘层包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成；
所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米；
进行化学气相沉积时，所述绝缘层第一薄膜中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；所述绝缘层第二薄膜中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘层第三薄膜中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分；
对所述绝缘层第一薄膜中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜中施加的压强为1550毫托，对所述绝缘层第三薄膜中施加的压强为1400至1500毫托；
所述绝缘层的薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
本申请的另一个目的在于提供一种与主动开关配合显示装置。
一种显示装置，包括控制部件，以及本申请所述的显示面板。
通过对绝缘层设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层均匀性更好，同时提高绝缘层与非晶硅层的交界面的品质、主动开关的信赖性以及化学气相沉积的速率。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一个实施例显示面板中主动开关的结构示意图；
图2是本申请一个实施例显示面板的绝缘层分层沉积的示意图；
图3是本申请一个实施例显示面板的绝缘层分两层、非晶硅层分两层薄膜沉积的结构示意图；
图4是本申请一个实施例显示面板的绝缘层分三层、非晶硅层分两层薄膜沉积的结构示意图；
图5是本申请实施例显示装置的示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并 且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
在图中，结构相似的单元是以相同标号表示。
下面参考附图1至图5实施例进一步详细描述本申请的显示面板和显示装置。
作为本申请的一个实施例，如图1-2所示，显示面板包括：基板10，所述基板10设置有多个像素区；主动开关，多个所述主动开关设置在所述基板10 上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括：绝缘层40，所述绝缘层40包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。通过对绝缘层40设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层40均匀性更好，同时提高绝缘层40与非晶硅层50的交界面的品质、主动开关的信赖性以及化学气相沉积的速率。
其中，CVD(Chemical Vapor Deposition)化学气相沉积法，在高温下的气相反应，作为涂层的手段而开发，但不只应用于耐热物质的涂层，而且应用于高纯度金属的精制、粉末合成、半导体薄膜等。沉积温度低，薄膜成份易控，膜厚与淀积时间成正比，均匀性，重复性好，台阶覆盖性优良。化学气相沉积法的技术特征在于：高熔点物质能够在低温下合成；析出物质的形态在单晶、多晶、晶须、粉末、薄膜等多种；不仅可以在基片上进行涂层，而且可以在粉体表面涂层等。特别是在低温下可以合成高熔点物质，在节能方面做出了贡献，作为一种新技术是大有前途的。
作为本申请的又一个实施例，如图2-3所示，显示面板包括：基板10，所述基板10设置有多个像素区；主动开关，多个所述主动开关设置在所述基板10上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括：绝缘层40，所述绝缘层40包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。通过对绝缘层40设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层40均匀性更好，同时提高绝缘层40与非晶硅层50的交界面的品质、主动开关的信赖性以及化学气相沉积的速率。所述主动开关包括设置在底部的栅极层21，所述栅极层21上设置有绝缘层40，所述绝缘层40上设置有非晶硅层50，所述非晶硅层50上设置有与非晶硅层50对应的欧姆接触层60，所述欧姆接触层60上两端设置有分隔的所述主动开关的源极层22和漏极层23，所述源极层22和所述漏极层23之间设置有沟道，所述沟道穿过 欧姆接触层60，所述沟道底部为非晶硅层50。所述绝缘层40包括绝缘层第一薄膜41、绝缘层第二薄膜42，所述绝缘层第一薄膜41和所述绝缘层第二薄膜42由远离所述栅极层21的一端到靠近所述栅极层21的一端依次排布，所述绝缘层40的厚度为3500至4000埃米，所述绝缘层第一薄膜41的厚度为500至2000埃米，所述绝缘层第二薄膜42的厚度为2000至3500埃米。
作为本申请的又一个实施例，如图4所示，显示面板包括：基板10，所述基板10设置有多个像素区；主动开关，多个所述主动开关设置在所述基板10上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括：绝缘层40，所述绝缘层40包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。通过对绝缘层40设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层40均匀性更好，同时提高绝缘层40与非晶硅层50的交界面的品质、主动开关的信赖性以及化学气相沉积的速率。所述主动开关包括设置在底部的栅极层21，所述栅极层21上设置有绝缘层40，所述绝缘层40上设置有非晶硅层50，所述非晶硅层50上设置有与非晶硅层50对应的欧姆接触层60，所述欧姆接触层60上两端设置有分隔的所述主动开关的源极层22和漏极层23，所述源极层22和所述漏极层23之间设置有沟道，所述沟道穿过欧姆接触层60，所述沟道底部为非晶硅层50。所述绝缘层40包括绝缘层第一薄膜41、绝缘层第二薄膜42、绝缘层第三薄膜43，所述绝缘层第一薄膜41、所述绝缘层第二薄膜42、所述绝缘层第三薄膜43由远离所述栅极层21的一端到靠近所述栅极层21的一端依次排布，所述绝缘层40的厚度为3500至4000埃米，所述绝缘层第一薄膜41的厚度为500至2000埃米，所述绝缘层第二薄膜42的厚度为1000至3000埃米，所述绝缘层第三薄膜43的厚度为500至2000埃米。三层薄膜的设置可以更好的提高绝缘层40与非晶硅层50的交界面的品质以及绝缘层40的均匀性。
作为本申请的又一个实施例，如图3所示，显示面板包括：基板10，所述 基板10设置有多个像素区；主动开关，多个所述主动开关设置在所述基板10上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括：绝缘层40，所述绝缘层40包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。通过对绝缘层40设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层40均匀性更好，同时提高绝缘层40与非晶硅层50的交界面的品质、主动开关的信赖性以及化学气相沉积的速率。所述主动开关包括设置在底部的栅极层21，所述栅极层21上设置有绝缘层40，所述绝缘层40上设置有非晶硅层50，所述非晶硅层50上设置有与非晶硅层50对应的欧姆接触层60，所述欧姆接触层60上两端设置有分隔的所述主动开关的源极层22和漏极层23，所述源极层22和所述漏极层23之间设置有沟道，所述沟道穿过欧姆接触层60，所述沟道底部为非晶硅层50。所述绝缘层40包括绝缘层第一薄膜41、绝缘层第二薄膜42，所述绝缘层第一薄膜41和所述绝缘层第二薄膜42由远离所述栅极层21的一端到靠近所述栅极层21的一端依次排布，所述绝缘层40的厚度为3500至4000埃米，所述绝缘层第一薄膜41的厚度为500至2000埃米，所述绝缘层第二薄膜42的厚度为2000至3500埃米。所述非晶硅层50包括两层薄膜：非晶硅层第一薄膜51、非晶硅层第二薄膜52，所述非晶硅层第一薄膜51和所述非晶硅层第二薄膜52由远离所述绝缘层40的一端到靠近所述绝缘层40的一端依次排布，所述非晶硅层第一薄膜51的厚度为1000埃米，所述非晶硅层第二薄膜52的厚度为300埃米。配合绝缘层40的设置更能提高交界面的品质、提升非晶硅层50的均匀性，更加快化学气相沉积用于薄膜沉积加工速率。
作为本申请的又一个实施例，如图4所示，显示面板包括：基板10，所述基板10设置有多个像素区；主动开关，多个所述主动开关设置在所述基板10上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括：绝缘层40，所述绝缘层40包括至少两层薄膜，所述薄膜通 过化学气相沉积的方式以预设的厚度形成。通过对绝缘层40设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层40均匀性更好，同时提高绝缘层40与非晶硅层50的交界面的品质、主动开关的信赖性以及化学气相沉积的速率。所述主动开关包括设置在底部的栅极层21，所述栅极层21上设置有绝缘层40，所述绝缘层40上设置有非晶硅层50，所述非晶硅层50上设置有与非晶硅层50对应的欧姆接触层60，所述欧姆接触层60上两端设置有分隔的所述主动开关的源极层22和漏极层23，所述源极层22和所述漏极层23之间设置有沟道，所述沟道穿过欧姆接触层60，所述沟道底部为非晶硅层50。所述绝缘层40包括绝缘层第一薄膜41、绝缘层第二薄膜42、绝缘层第三薄膜43，所述绝缘层第一薄膜41、所述绝缘层第二薄膜42、所述绝缘层第三薄膜43由远离所述栅极层21的一端到靠近所述栅极层21的一端依次排布，所述绝缘层40的厚度为3500至4000埃米，所述绝缘层第一薄膜41的厚度为500至2000埃米，所述绝缘层第二薄膜42的厚度为1000至3000埃米，所述绝缘层第三薄膜43的厚度为500至2000埃米。三层薄膜的设置可以更好的提高绝缘层40与非晶硅层50的交界面的品质以及绝缘层40的均匀性。所述非晶硅层50包括两层薄膜：非晶硅层第一薄膜51、非晶硅层第二薄膜52，所述非晶硅层第一薄膜51和所述非晶硅层第二薄膜52由远离所述绝缘层40的一端到靠近所述绝缘层40的一端依次排布，所述非晶硅层第一薄膜51的厚度为1000埃米，所述非晶硅层第二薄膜52的厚度为300埃米。配合绝缘层40的设置更能提高交界面的品质、提升非晶硅层50的均匀性，更加快化学气相沉积用于薄膜沉积加工速率。
其中，所述绝缘层40的厚度也可以为4000埃米，所述绝缘层第一薄膜41的厚度为1000埃米，所述绝缘层第二薄膜42的厚度为1000埃米，所述绝缘层第三薄膜43的厚度为2000埃米。所述非晶硅层第一薄膜51的厚度为1000埃米，所述非晶硅层第二薄膜52的厚度为300埃米。所述欧姆接触层60的厚度为400埃米。
作为本申请的又一个实施例，如图4所示，显示面板包括：基板10，所述基板10设置有多个像素区；主动开关，多个所述主动开关设置在所述基板10上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括：绝缘层40，所述绝缘层40包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。通过对绝缘层40设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层40均匀性更好，同时提高绝缘层40与非晶硅层50的交界面的品质、主动开关的信赖性以及化学气相沉积的速率。所述主动开关包括设置在底部的栅极层21，所述栅极层21上设置有绝缘层40，所述绝缘层40上设置有非晶硅层50，所述非晶硅层50上设置有与非晶硅层50对应的欧姆接触层60，所述欧姆接触层60上两端设置有分隔的所述主动开关的源极层22和漏极层23，所述源极层22和所述漏极层23之间设置有沟道，所述沟道穿过欧姆接触层60，所述沟道底部为非晶硅层50。所述绝缘层40包括绝缘层第一薄膜41、绝缘层第二薄膜42、绝缘层第三薄膜43，所述绝缘层第一薄膜41、所述绝缘层第二薄膜42、所述绝缘层第三薄膜43由远离所述栅极层21的一端到靠近所述栅极层21的一端依次排布，所述绝缘层40的厚度为3500至4000埃米，所述绝缘层第一薄膜41的厚度为500至2000埃米，所述绝缘层第二薄膜42的厚度为1000至3000埃米，所述绝缘层第三薄膜43的厚度为500至2000埃米。三层薄膜的设置可以更好的提高绝缘层40与非晶硅层50的交界面的品质以及绝缘层40的均匀性。所述非晶硅层50包括两层薄膜：非晶硅层第一薄膜51、非晶硅层第二薄膜52，所述非晶硅层第一薄膜51和所述非晶硅层第二薄膜52由远离所述绝缘层40的一端到靠近所述绝缘层40的一端依次排布，所述非晶硅层第一薄膜51的厚度为1000埃米，所述非晶硅层第二薄膜52的厚度为300埃米。配合绝缘层40的设置更能提高交界面的品质、提升非晶硅层50的均匀性，更加快化学气相沉积用于薄膜沉积加工速率。
具体的，进行化学气相沉积时，所述绝缘层第一薄膜41中四氢化硅、氨气、 氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；所述绝缘层第二薄膜42中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘层第三薄膜43中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分。对所述绝缘层第一薄膜41中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜42中施加的压强为1550毫托，对所述绝缘层第三薄膜43中施加的压强为1400至1500毫托。所述薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
其中，所述绝缘层40的厚度也可以为4500埃米，所述绝缘层第一薄膜41的厚度为500埃米，所述绝缘层第二薄膜42的厚度为2000埃米，所述绝缘层第三薄膜43的厚度为2000埃米。所述非晶硅层第一薄膜51的厚度为1000埃米，所述非晶硅层第二薄膜52的厚度为300埃米。进行化学气相沉积时，所述绝缘层第一薄膜41中四氢化硅、氨气、氮气分别为2300标况毫升每分、16000标况毫升每分、70000标况毫升每分；所述绝缘层第二薄膜42中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘层第三薄膜43中四氢化硅、氨气、氮气分别为7000标况毫升每分、27000标况毫升每分、70000标况毫升每分。对所述绝缘层第一薄膜41中施加的压强为1200毫托，对所述绝缘层第二薄膜42中施加的压强为1550毫托，对所述绝缘层第三薄膜43中施加的压强为1500毫托。所述薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
作为本申请的又一个实施例，如图4所示，显示面板包括：基板10，所述基板10设置有多个像素区；主动开关，多个所述主动开关设置在所述基板10上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括：绝缘层40，所述绝缘层40包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。所述薄膜晶体管包括绝缘层40，所 述绝缘层40包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。通过对绝缘层40设置至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度、以预设的沉积速率形成，利用化学气相沉积形成绝缘层40均匀性更好，同时提高绝缘层40与非晶硅层50的交界面的品质、薄膜晶体管的信赖性以及化学气相沉积的速率。所述薄膜晶体管包括设置在底部的栅极层21，所述栅极层21上设置有绝缘层40，所述绝缘层40上设置有非晶硅层50，所述非晶硅层50上设置有与非晶硅层50对应的欧姆接触层60，所述欧姆接触层60上两端设置有分隔的所述薄膜晶体管的源极层22和漏极层23，所述源极层22和所述漏极层23之间设置有沟道，所述沟道穿过欧姆接触层60，所述沟道底部为非晶硅层50。所述绝缘层40包括绝缘层第一薄膜41、绝缘层第二薄膜42、绝缘层第三薄膜43，所述绝缘层第一薄膜41、所述绝缘层第二薄膜42、所述绝缘层第三薄膜43由远离所述栅极层21的一端到靠近所述栅极层21的一端依次排布，所述绝缘层40的厚度为3500至4000埃米，所述绝缘层第一薄膜41的厚度为500至2000埃米，所述绝缘层第二薄膜42的厚度为1000至3000埃米，所述绝缘层第三薄膜43的厚度为500至2000埃米。三层薄膜的设置可以更好的提高绝缘层40与非晶硅层50的交界面的品质以及绝缘层40的均匀性。所述非晶硅层50包括两层薄膜：非晶硅层第一薄膜51、非晶硅层第二薄膜52，所述非晶硅层第一薄膜51和所述非晶硅层第二薄膜52由远离所述绝缘层40的一端到靠近所述绝缘层40的一端依次排布，所述非晶硅层第一薄膜51的厚度为1000埃米，所述非晶硅层第二薄膜52的厚度为300埃米。配合绝缘层40的设置更能提高交界面的品质、提升非晶硅层50的均匀性，更加快化学气相沉积用于薄膜沉积加工速率。
具体的，进行化学气相沉积时，所述绝缘层第一薄膜41中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；所述绝缘层第二薄膜42中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘 层第三薄膜43中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分。对所述绝缘层第一薄膜41中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜42中施加的压强为1550毫托，对所述绝缘层第三薄膜43中施加的压强为1400至1500毫托。所述薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
其中，所述绝缘层40的厚度也可以为4500埃米，所述绝缘层第一薄膜41的厚度为500埃米，所述绝缘层第二薄膜42的厚度为2000埃米，所述绝缘层第三薄膜43的厚度为2000埃米。所述非晶硅层第一薄膜51的厚度为1000埃米，所述非晶硅层第二薄膜52的厚度为300埃米。进行化学气相沉积时，所述绝缘层第一薄膜41中四氢化硅、氨气、氮气分别为2300标况毫升每分、16000标况毫升每分、70000标况毫升每分；所述绝缘层第二薄膜42中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘层第三薄膜43中四氢化硅、氨气、氮气分别为7000标况毫升每分、27000标况毫升每分、70000标况毫升每分。对所述绝缘层第一薄膜41中施加的压强为1200毫托，对所述绝缘层第二薄膜42中施加的压强为1550毫托，对所述绝缘层第三薄膜43中施加的压强为1500毫托。所述薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
在附图1中还包括保护层70、像素电极层80；图2-4中还包括保护层70。
在上述实施例中，显示面板包括液晶面板、OLED(Organic Light-Emitting Diode)面板、QLED(Quantum Dot Light Emitting Diodes)面板、等离子面板、平面型面板、曲面型面板等。
参考图5，本实施方式公开一种显示装置100。该显示装置100包括控制部件200，以及本申请所述的显示面板300，以上以显示面板为例进行详细说明，需要说明的是，以上对显示面板结构的描述同样适用于本申请实施例的显示装置中。其中，当本申请实施例的显示装置为液晶显示器时，液晶显示器包括有 背光模组，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可以为背光式，需要说明的是，本实施例的背光模组并不限于此。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    基板，所述基板设置有多个像素区；
    主动开关，多个所述主动开关设置在所述基板上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括绝缘层，所述绝缘层包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成；
    所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米；
    进行化学气相沉积时，所述绝缘层第一薄膜中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；所述绝缘层第二薄膜中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘层第三薄膜中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况 毫升每分、66000至70000标况毫升每分；
    对所述绝缘层第一薄膜中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜中施加的压强为1550毫托，对所述绝缘层第三薄膜中施加的压强为1400至1500毫托；
    所述绝缘层的薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
  2. 一种显示面板，包括：
    基板，所述基板设置有多个像素区；
    主动开关，多个所述主动开关设置在所述基板上，所述像素区设置在所述主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括绝缘层，所述绝缘层包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。
  3. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述栅极层上设置有绝缘层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第二薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为2000至3500埃米。
  4. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第 三薄膜的厚度为500至2000埃米。
  5. 如权利要求3所述的显示面板，其中所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米。
  6. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述栅极层上设置有绝缘层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第二薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为2000至3500埃米；
    所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米。
  7. 如权利要求4所述的显示面板，其中所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米。
  8. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米。
  9. 如权利要求4所述的显示面板，其中进行化学气相沉积时，所述绝缘层第一薄膜中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；
    所述绝缘层第二薄膜中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；
    所述绝缘层第三薄膜中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分。
  10. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布， 所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    进行化学气相沉积时，所述绝缘层第一薄膜中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；
    所述绝缘层第二薄膜中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；
    所述绝缘层第三薄膜中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分。
  11. 如权利要求4所述的显示面板，其中对所述绝缘层第一薄膜中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜中施加的压强为1550毫托，对所述绝缘层第三薄膜中施加的压强为1400至1500毫托。
  12. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    对所述绝缘层第一薄膜中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜中施加的压强为1550毫托，对所述绝缘层第三薄膜中施加的压强为1400至1500毫托。
  13. 如权利要求4所述的显示面板，其中所述绝缘层的薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
  14. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    所述绝缘层的薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
  15. 如权利要求5所述的显示面板，其中所述非晶硅层上设置有与非晶硅层对应的欧姆接触层，所述欧姆接触层上两端设置有分隔的所述主动开关的源极层和漏极层，所述源极层和所述漏极层之间设置有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层。
  16. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述栅极层上设置有绝缘层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第二薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为2000至3500埃米；
    所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅 层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米；
    所述非晶硅层上设置有与非晶硅层对应的欧姆接触层，所述欧姆接触层上两端设置有分隔的所述主动开关的源极层和漏极层，所述源极层和所述漏极层之间设置有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层。
  17. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米；
    所述非晶硅层上设置有与非晶硅层对应的欧姆接触层，所述欧姆接触层上两端设置有分隔的所述主动开关的源极层和漏极层，所述源极层和所述漏极层之间设置有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层。
  18. 如权利要求2所述的显示面板，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布， 所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米；
    进行化学气相沉积时，所述绝缘层第一薄膜中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；所述绝缘层第二薄膜中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘层第三薄膜中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分；
    对所述绝缘层第一薄膜中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜中施加的压强为1550毫托，对所述绝缘层第三薄膜中施加的压强为1400至1500毫托；
    所述绝缘层的薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
  19. 一种显示装置，包括：
    控制部件，以及
    显示面板，所述显示面板包括：基板，所述基板设置有多个像素区；
    主动开关，多个所述主动开关设置在所述基板上，所述像素区设置在所述 主动开关上，所述主动开关与所述像素区一一对应，所述主动开关包括绝缘层，所述绝缘层包括至少两层薄膜，所述薄膜通过化学气相沉积的方式以预设的厚度形成。
  20. 如权利要求19所述的显示装置，其中所述主动开关包括设置在底部的栅极层，所述绝缘层包括绝缘层第一薄膜、绝缘层第二薄膜、绝缘层第三薄膜，所述绝缘层第一薄膜、所述绝缘层第二薄膜、所述绝缘层第三薄膜依次排布，所述绝缘层第一薄膜设置在远离所述栅极层的一端，所述绝缘层第三薄膜设置在靠近所述栅极层的一端；
    所述绝缘层的厚度为3500至4000埃米，所述绝缘层第一薄膜的厚度为500至2000埃米，所述绝缘层第二薄膜的厚度为1000至3000埃米，所述绝缘层第三薄膜的厚度为500至2000埃米；
    所述绝缘层上设置有非晶硅层，所述非晶硅层包括两层薄膜：非晶硅层第一薄膜、非晶硅层第二薄膜，所述非晶硅层第一薄膜、所述非晶硅层第二薄膜依次排布，所述非晶硅层第一薄膜设置在远离所述绝缘层的一端，所述非晶硅层第二薄膜设置在靠近所述绝缘层的一端；
    所述非晶硅层第一薄膜的厚度为1000埃米，所述非晶硅层第二薄膜的厚度为300埃米；
    进行化学气相沉积时，所述绝缘层第一薄膜中四氢化硅、氨气、氮气分别为2300至2530标况毫升每分、15000至16000标况毫升每分、68000至83500标况毫升每分；所述绝缘层第二薄膜中四氢化硅、氨气、氮气分别为5500标况毫升每分、30000标况毫升每分、80000标况毫升每分；所述绝缘层第三薄膜中四氢化硅、氨气、氮气分别为7000至7200标况毫升每分、26000至27000标况毫升每分、66000至70000标况毫升每分；
    对所述绝缘层第一薄膜中施加的压强为1200至1400毫托，对所述绝缘层第二薄膜中施加的压强为1550毫托，对所述绝缘层第三薄膜中施加的压强为1400至1500毫托；
    所述绝缘层的薄膜通过化学气相沉积的方式在预设的温度下形成，所述温度采用340摄氏度或者360摄氏度。
PCT/CN2017/096722 2017-07-06 2017-08-10 一种显示面板和显示装置 Ceased WO2019006818A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/338,534 US10797081B2 (en) 2017-07-06 2017-08-10 Display panel and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710546096.5 2017-07-06
CN201710546096.5A CN107591411A (zh) 2017-07-06 2017-07-06 一种显示面板和显示装置

Publications (1)

Publication Number Publication Date
WO2019006818A1 true WO2019006818A1 (zh) 2019-01-10

Family

ID=61041561

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/096722 Ceased WO2019006818A1 (zh) 2017-07-06 2017-08-10 一种显示面板和显示装置

Country Status (3)

Country Link
US (1) US10797081B2 (zh)
CN (1) CN107591411A (zh)
WO (1) WO2019006818A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119484B (zh) * 2018-07-16 2021-06-18 惠科股份有限公司 薄膜晶体管及薄膜晶体管的制造方法
CN109616510B (zh) 2018-12-03 2020-04-14 惠科股份有限公司 薄膜晶体管结构及其制作方法、显示装置
CN109545690A (zh) * 2018-12-03 2019-03-29 惠科股份有限公司 薄膜晶体管结构及其制作方法、显示装置
CN109727874A (zh) * 2018-12-21 2019-05-07 惠科股份有限公司 主动开关及其制作方法、显示装置
CN111430446A (zh) * 2019-01-09 2020-07-17 惠科股份有限公司 一种薄膜晶体管器件、驱动电路及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050142704A1 (en) * 2003-12-29 2005-06-30 Oh Jae Y. Method for fabricating liquid crystal display device
CN202423298U (zh) * 2011-12-31 2012-09-05 京东方科技集团股份有限公司 一种tft、阵列基板以及显示器件
CN103165680A (zh) * 2013-03-07 2013-06-19 北京京东方光电科技有限公司 一种透明薄膜及其制作方法、显示用基板及显示装置
CN103280429A (zh) * 2012-12-21 2013-09-04 上海中航光电子有限公司 一种tft阵列基板的制造方法及tft阵列基板
CN103489920A (zh) * 2013-09-26 2014-01-01 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN104362179A (zh) * 2014-10-13 2015-02-18 京东方科技集团股份有限公司 一种薄膜晶体管、其制作方法、阵列基板及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6395586B1 (en) * 1999-02-03 2002-05-28 Industrial Technology Research Institute Method for fabricating high aperture ratio TFT's and devices formed
US6885064B2 (en) * 2000-01-07 2005-04-26 Samsung Electronics Co., Ltd. Contact structure of wiring and a method for manufacturing the same
TWI234288B (en) * 2004-07-27 2005-06-11 Au Optronics Corp Method for fabricating a thin film transistor and related circuits
KR100818887B1 (ko) * 2005-12-14 2008-04-02 엘지.필립스 엘시디 주식회사 액정 표시장치 및 그 제조 방법
JP5485517B2 (ja) * 2008-03-17 2014-05-07 株式会社ジャパンディスプレイ 表示装置およびその製造方法
TWI388014B (zh) * 2009-03-06 2013-03-01 Chunghwa Picture Tubes Ltd 薄膜電晶體之製造方法
CN102768989A (zh) * 2011-05-06 2012-11-07 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板结构及制造方法
CN102593050B (zh) * 2012-03-09 2014-08-20 深超光电（深圳）有限公司 一种液晶显示面板阵列基板的制作方法
CN103354218B (zh) * 2013-06-28 2016-12-28 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050142704A1 (en) * 2003-12-29 2005-06-30 Oh Jae Y. Method for fabricating liquid crystal display device
CN202423298U (zh) * 2011-12-31 2012-09-05 京东方科技集团股份有限公司 一种tft、阵列基板以及显示器件
CN103280429A (zh) * 2012-12-21 2013-09-04 上海中航光电子有限公司 一种tft阵列基板的制造方法及tft阵列基板
CN103165680A (zh) * 2013-03-07 2013-06-19 北京京东方光电科技有限公司 一种透明薄膜及其制作方法、显示用基板及显示装置
CN103489920A (zh) * 2013-09-26 2014-01-01 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN104362179A (zh) * 2014-10-13 2015-02-18 京东方科技集团股份有限公司 一种薄膜晶体管、其制作方法、阵列基板及显示装置

Also Published As

Publication number Publication date
US10797081B2 (en) 2020-10-06
US20200035714A1 (en) 2020-01-30
CN107591411A (zh) 2018-01-16

Similar Documents

Publication Publication Date Title
JP7671897B2 (ja) 半導体装置
WO2019006818A1 (zh) 一种显示面板和显示装置
US9252393B2 (en) Flexible display apparatus including a thin-film encapsulating layer and a manufacturing method thereof
US8187919B2 (en) Oxide thin film transistor and method of fabricating the same
KR101475362B1 (ko) 박막 트랜지스터 및 그 제조 방법, 및 표시 장치
US20160343963A1 (en) Flexible oled display device and manufacturing method thereof
TW200302439A (en) Light emitting device and method of manufacturing the same
US20170198383A1 (en) Mask assembly, method of manufacturing thereof, and apparatus including the same
TW200915435A (en) Semiconductor device and manufacturing method thereof
WO2016173322A1 (zh) 一种阵列基板及其制作方法、及显示装置
JP5998232B2 (ja) 薄膜トランジスタ及びその製造方法
US20250107336A1 (en) Display panels
CN116568106A (zh) 掩模框架组件及显示装置的制造方法
CN108374145A (zh) 掩模组件
US11362162B2 (en) Method of manufacturing metal oxide film and display device including metal oxide film
WO2019134177A1 (zh) 显示面板和显示装置
US20080315188A1 (en) Apparatus and method for depositing thin film
CN106992189A (zh) 氧化物半导体tft基板结构及氧化物半导体tft基板的制作方法
US20240186406A1 (en) Semiconductor device
CN108198823A (zh) 一种阵列基板和显示面板
US20210151529A1 (en) Oled display panel, manufacturing method thereof, and oled display device
JP2024161035A (ja) 表示装置
JP2004253520A (ja) 表示装置とその製造方法
TWI545774B (zh) 薄膜電晶體及含有該薄膜電晶體之平板顯示裝置
US20140363932A1 (en) Zinc target including fluorine, method of fabricating zinc nitride thin film by using the same, and method of fabricating thin film transistor by using the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17916746

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17916746

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 31.07.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17916746

Country of ref document: EP

Kind code of ref document: A1