WO2019001046A1 - 信息处理的方法、装置和通信设备 - Google Patents
信息处理的方法、装置和通信设备 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
- H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Definitions
- Embodiments of the present invention relate to the field of communications, and in particular, to a method for information processing and a communication device.
- Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code.
- the LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission.
- LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.
- an LDPC matrix with special structured features can be used.
- the LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure.
- QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
- the LDPC matrix can be designed to be applied to channel coding.
- QC-LDPC is suitable for hardware with high parallelism and provides higher throughput.
- the LDPC matrix can be designed to be applied to channel coding.
- Embodiments of the present invention provide a method, a communication device, and a system for information processing, which can support encoding and decoding of information bit sequences of various lengths.
- an encoding method and an encoder are provided that encode an input sequence using a low density parity check LDPC matrix.
- a decoding method and decoder are provided that decode an input sequence using a low density parity check LDPC matrix.
- the LDPC matrix is obtained based on the spreading factor Z and the base matrix.
- the base matrix of the base map 30a may include the matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70 and The 0th to 4th rows and the 0th to 26th columns in one of the matrices shown in 30b-80, or the base matrix includes the matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, The 0th to 4th rows and the partial columns in the 0th to 26th columns in one of the matrices 30b-40, 30b-50, 30b-60, 30b-70, and 30b-80, or the base matrix may be the matrix 30b a row/column transformed matrix of the 0th to 4th rows and the 0th to 26th columns of one of the matrices of -10 to 30b-80, or the base matrix may be the matrix 30b-10, 30b-11, 30b- Parts 0 to 4 and parts
- the base matrix of the base map 30a may further include matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70, and 30b-
- the 0th line to the (m-1)th line in one of the matrices shown in 80, and the 0th column to the (n-1)th column, or the base matrix may be the matrix 30b-10, 30b-11, 30b- Lines 0 to (m-1) of one of the matrices 20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70, and 30b-80, and The row/column transformed matrix from column 0 to column (n-1). 5 ⁇ m ⁇ 46,27 ⁇ n ⁇ 68
- the LDPC code requires different spreading factors Z.
- a base matrix corresponding thereto is adopted based on different spreading factors Z.
- Z a ⁇ 2 j , 0 ⁇ j ⁇ 7, a ⁇ ⁇ 2, 3, 5, 7, 9, 11, 13, 15 ⁇ .
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-10 or 30b-11, or the base matrix may include the 0th of the matrix 30b-10 or 30b-11 To the 4 rows and the partial columns in columns 0 to 26. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-10 or 30b-11, and the 0th column to the (n-1)th column.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-20 or 30b-21, or the base matrix may include the 0th of the matrix 30b-20 or 30b-21 To the 4 rows and the partial columns in columns 0 to 26. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-20 or 30b-21, and the 0th column to the (n-1)th column.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-30, or the base matrix may include the 0th to 4th rows and the 0th to 26th of the matrix 30b-30.
- the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-30, and the 0th column to the (n-1)th column.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-40, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-40 A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-40, and the 0th column to the (n-1)th column.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-50, or the base matrix may include the 0th to 4th rows and the 0th to 26th of the matrix 30b-50 A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-50, and the 0th column to the (n-1)th column.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-60, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-60. A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-60, and the 0th column to the (n-1)th column.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-70, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-70. A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-70, and the 0th column to the (n-1)th column.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-80, or the base matrix includes the 0th to 4th rows and the 0th to 26th of the matrix 30b-80. A partial column in the column. Further, the base matrix further includes the 0th row to the (m-1)th row of the matrix 30b-80, and the 0th column to the (n-1)th column.
- the base matrix may be a matrix after the row/column transformation of the corresponding matrix.
- the LDPC matrix may be obtained based on the spreading factor Z and the matrix Hs compensated for each of the foregoing base matrices, or based on the spreading factor Z and the matrix after compensating the foregoing base matrices.
- the matrix after the row/column transformation of Hs is obtained.
- the offset value may be increased or decreased for an offset value greater than or equal to 0 in one or more of the columns.
- the base map and the base matrix of the LDPC matrix in each of the foregoing implementation manners can satisfy the performance requirements of the code blocks of various block lengths.
- the method further includes: determining the expansion factor Z.
- the value of the spreading factor Z is determined according to the length K of the input sequence, and in the supported set of spreading factors, the smallest Z 0 is found as the magnitude of the spreading factor Z, and Kb ⁇ Z 0 ⁇ K is satisfied.
- Kb can be the number of columns of information bits in the base matrix of the LDPC code.
- Kb 22.
- the value of Kb may also vary according to the value of K, but does not exceed the number of information bit columns in the base matrix of the LDPC code.
- the spreading factor Z may be determined by the encoder or the decoder according to the length K of the input sequence, or may be determined by other devices and provided as an input parameter to the encoder or the decoder.
- the LDPC matrix may be obtained according to the obtained spreading factor Z and the base matrix corresponding to the spreading factor Z.
- the LDPC matrix is obtained based on parameters of the spreading factor Z and the LDPC matrix.
- the parameters of the LDPC matrix may include: a row number, a column in which the non-zero element is located, and a non-zero element offset value, as shown in Table 3-10, Table 3-11, Table 3-20, Table 3-21, Table 3-30, The manners of Table 3-40, Table 3-50, Table 3-60, Table 3-70, and Table 3-80 are saved. It can also include line weights.
- the offset values in the positions of the non-zero elements and the non-zero element offset values are one-to-one correspondence.
- the encoder thus encodes the input sequence according to the spreading factor Z and the parameters of the LDPC matrix.
- the parameters saved according to Table 3-10 correspond to the matrix 30b-10
- the parameters saved according to Table 3-11 correspond to the matrix 30b-11
- the parameters saved according to Table 3-20 correspond to the matrix 30b-20, according to Table 3-
- the saved parameters correspond to the matrix 30b-21
- the parameters saved according to Table 3-30 correspond to the matrix 30b-30
- the parameters saved according to Table 3-40 correspond to the matrix 30b-40, according to the parameters saved in Table 3-50.
- the matrix 30b-50 corresponds to the parameters stored in Table 3-60 corresponding to the matrix 30b-60
- the parameters saved according to Table 3-70 correspond to the matrix 30b-70
- the parameters saved according to Table 3-80 correspond to the matrix 30b-80.
- encoding the input sequence using the LDPC matrix may include:
- the row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.
- decoding the input sequence using the LDPC matrix includes:
- the input sequence is decoded by using an LDPC matrix corresponding to the spreading factor Z; or the LDPC matrix corresponding to the spreading factor Z is subjected to row/column transformation, and the input sequence is encoded using the matrix after the row/column transformation to the input.
- the sequence is encoded.
- the row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.
- the LDPC matrix may be saved, the input sequence is encoded using the LDPC matrix, or transformed (row/column transform) or extended based on the LDPC matrix to obtain an LDPC matrix usable for encoding.
- parameters may be saved, and an LDPC matrix for encoding or decoding may be obtained according to the parameters, so that the input sequence may be encoded or decoded based on the LDPC matrix.
- the parameter includes at least one of: a base map, a base matrix, a transform matrix based on a base/column transformation of a base map or a base matrix, an extended matrix based on a base map or a base matrix, and an offset value of a non-zero element in the base matrix; Or any parameter related to obtaining an LDPC matrix.
- the base matrix of the LDPC matrix can be stored in a memory.
- the base map of the LDPC matrix is stored in a memory, and offset values of non-zero elements in the base matrix of the LDPC matrix may be stored in the memory.
- the parameters of the LDPC matrix are stored in the memory in the manner shown in Tables 3-10 to 3-80.
- At least one of the base map and the base matrix used for LDPC encoding or decoding is at least one of a base map and a base matrix of the foregoing LDPC matrix, or Column exchange, or row exchange and column exchange.
- a communication device can include corresponding modules for performing the above method design.
- the module can be software and/or hardware.
- a communication device provided by the third aspect includes a processor and a transceiver component that can be used to implement the functions of various portions of the encoding or decoding method described above.
- the transceiver component if the communication device is a terminal, a base station or other network device, the transceiver component thereof may be a transceiver. If the communication device is a baseband chip or a baseband single board, the transceiver component may be a baseband chip or a baseband single board. Input/output circuits for receiving/transmitting input/output signals.
- the communication device can optionally also include a memory for storing data and/or instructions.
- the processor may include the encoder and the determining unit as described in the first aspect above.
- the determining unit is operative to determine a spreading factor Z required to encode the input sequence.
- the encoder is configured to encode the input sequence using an LDPC matrix corresponding to the spreading factor Z.
- the processor may include the decoder and the obtaining unit as described in the second aspect above.
- the obtaining unit is configured to acquire a soft value and an expansion factor Z of the LDPC code.
- the decoder is configured to decode the soft value of the LDPC code based on the base matrix H B corresponding to the spreading factor Z to obtain an information bit sequence.
- a communication device in a fourth aspect, includes one or more processors.
- one or more of the processors may implement the functions of the encoder of the first aspect, and in another possible design, the encoder of the first aspect may be the processor In part, the processor can implement other functions in addition to the functions of the encoder described in the first aspect.
- one or more of the processors may implement the functions of the decoder of the second aspect, and in another possible design, the decoder of the second aspect may be Part of the processor.
- the communication device may further include a transceiver and an antenna.
- the communication device may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like.
- the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like.
- a demodulator for demodulation operation e.g., a demodulator for demodulation operation
- a deinterleaver for deinterleaving e.g., a device for de-rate matching
- the functionality of these devices can be implemented by one or more processors.
- the functionality of these devices can be implemented by one or more processors.
- an embodiment of the present invention provides a communication system, where the system includes the communication device described in the foregoing third aspect.
- an embodiment of the present invention provides a communication system, where the system includes one or more communication devices according to the fourth aspect.
- an embodiment of the present invention provides a computer storage medium having stored thereon a program, and when executed, causes a computer to perform the method described in the above aspect.
- Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
- the method, device, communication device and communication system of the information processing according to the embodiments of the present invention can adapt to the flexible code length code rate requirement of the system in coding performance and error leveling.
- 1 is a schematic diagram of a base map, a base matrix, and a cyclic permutation matrix of an LDPC code
- FIG. 2 is a schematic structural diagram of a base diagram of an LDPC code
- FIG. 3a is a schematic diagram of a LDPC code base diagram according to an embodiment of the present invention.
- FIG. 3b-1 is a schematic diagram of a base matrix according to an embodiment of the present invention.
- 3b-2 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- 3b-3 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- 3b-4 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- FIG. 3b is a schematic diagram of another base matrix according to an embodiment of the present disclosure.
- 3b-6 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- 3b-7 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- 3b-8 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- 3b-9 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- FIG. 3b-10 is a schematic diagram of another base matrix according to an embodiment of the present invention.
- FIG. 5 is a flowchart of an information processing method according to another embodiment of the present invention.
- FIG. 6 is a flowchart of an information processing method according to another embodiment of the present invention.
- FIG. 7 is a schematic structural diagram of an information processing apparatus according to another embodiment of the present invention.
- FIG. 8 is a schematic diagram of a communication system according to another embodiment of the present invention.
- FIG. 9 is a schematic diagram of offset values of a base matrix according to another embodiment of the present invention.
- the “communication device” may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device.
- a terminal is a device having a communication function, and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem.
- Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.
- a base station also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions.
- the name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network.
- a base station is called an evolved Node B (eNB or eNodeB).
- eNB evolved Node B
- NR transmission reception point
- gNB next generation node B
- Base stations in other various evolved networks may also adopt other names. The invention is not limited to this.
- the LDPC code can usually be represented by a parity check matrix H.
- the parity check matrix H of the LDPC code can be obtained by a base graph and a shift value.
- the base map can usually include m*n matrix elements, which can be represented by a matrix of m rows and n columns.
- the value of the matrix element is 0 or 1, and the element with a value of 0 is sometimes called a zero element. , indicating that the element can be replaced by Z*Z's zero matrix.
- An element with a value of 1, sometimes referred to as a non-zero element indicates that the element can be a cyclic permutation matrix of Z*Z (circulant permutation) Matrix) replacement.
- each matrix element represents an all-zero matrix or a cyclic permutation matrix.
- the row number and column number of the base map and the matrix are numbered from 0, for convenience of explanation, for example, the 0th column is represented as the base map and the first column of the matrix, the first The columns are represented as the base and the second column of the matrix, the 0th row represents the base map and the first row of the matrix, the first row is represented as the base map and the second row of the matrix, and so on.
- the line number and column number can also be numbered from 1, and the corresponding line number and column number are incremented by 1 on the basis of the line number and column number shown in this article, for example, if the line number or column number is from 1 Starting with the number, the first column represents the base column and the first column of the matrix, the second column represents the base map and the second column of the matrix, the first row represents the first row representing the base map and the matrix, and the second row represents the base map. And the second line of the matrix, and so on.
- the element value of the i-th row and the j-th column in the base map is 1, and the offset value is P i,j , P i,j is an integer greater than or equal to 0, the value of the j-th column of the i-th row is 1
- the element can be replaced by a cyclic permutation matrix of Z*Z corresponding to P i,j , which can be obtained by cyclically shifting the unit matrix of Z*Z by P i, j times to the right.
- each element with a value of 0 in the base map is replaced by an all-zero matrix of Z*Z, and each element having a value of 1 is replaced by a cyclic permutation matrix of Z*Z corresponding to its offset value,
- the parity check matrix of the LDPC code can be used to indicate the location of the offset value, and the non-zero elements in the base map correspond to the offset values.
- Z is a positive integer, which can also be called a lifting factor, sometimes called lifting size, or lifting factor, etc., which can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z).
- each zero element is replaced by a 4*4 size all-zero matrix 11a.
- the cyclic permutation matrix 11d is replaced by a quadrature cyclic shift of the 4*4 unit matrix 11b.
- the system usually defines a base matrix of m rows and n columns, sometimes called PCM (parity check matrix).
- PCM parity check matrix
- each element corresponds to the position of each element in the base map.
- the zero elements in the base map are in the same position in the base matrix, and can be represented by -1 or null "null".
- the non-zero elements of the j-th column with a value of 1 are invariant in the base matrix, and may be expressed as P i,j , P i,j may be offset values defined relative to a predetermined or specific spreading factor Z.
- the base matrix is sometimes referred to as an offset matrix of the base matrix.
- a base matrix corresponding to the base map 10a is shown.
- the LDPC code used in the wireless communication system is a QC-LDPC code, and the check bit portion has a double diagonal structure or a raptor-like structure, which can simplify coding and support incremental redundant hybrid retransmission.
- a QC-LDPC shift network QSN
- Banyan network a Banyan network
- Benes network is generally used to implement cyclic shift of information.
- the matrix size of the base map is m rows and n columns, and may include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by a non-zero element
- the number of rows refers to the number of non-zero elements included in a row
- the weight of the column refers to the number of non-zero elements included in a column.
- Submatrix A is a matrix of m A rows and n A columns, which may be of size M A *n A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.
- the sub-matrix B is a square matrix of m A rows and m A columns, and its size may be m A *m A , and each column corresponds to Z parity bits in the LDPC code.
- the sub-matrix B includes a sub-matrix B' with a double-diagonal structure and a matrix column with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 may be located before the sub-matrix B', as shown in FIG. 20a; the sub-matrix B may further include one or more columns of columns having a column weight of 1 (referred to as a single column of re-columns).
- a single column of re-columns referred to as a single column of re-columns
- a matrix that is typically generated based on sub-matrices A and B can be referred to as a core matrix and can be used to support high code rate encoding.
- Submatrix C is an all-zero matrix with a size of m A ⁇ m D .
- the sub-matrix E is an identity matrix having a size of m D ⁇ m D .
- the submatrix D has a size of m D ⁇ (n A + m A ) and can generally be used to generate a low bit rate check bit.
- the structure of the two sub-matrices A, B and D is one of the factors influencing the coding performance of the LDPC code.
- the matrix of the sub-matrices A and B may be encoded to obtain the parity bit corresponding to the sub-matrix B, and then The entire matrix is encoded to obtain parity bits corresponding to the E portion of the sub-matrix. Since the sub-matrix B can include the sub-matrix B' of the double-diagonal structure and a single-column re-column, the parity bits corresponding to the double-diagonal structure can be obtained first in the encoding, and the parity bits corresponding to the single-column re-column can be obtained.
- H core the core matrix part composed of sub-matrices A and B
- the last row and the last column are removed from the H core , that is, the single-column re-column and the row where the non-zero elements of the column are located are obtained, and the obtained matrix portion is H core-dual
- H core-dual ⁇ [S P e ] T 0, where S is an input sequence, represented by a vector of information bits, P e is a vector of check bits, and [S P e ] T represents The matrix consists of input sequences S and P e transposed.
- H core-dual H core-dual check bit corresponding to the input sequence S includes all information bits; then according to obtain H core-dual check bit corresponding to an input sequence and calculates S Obtaining the parity bits corresponding to the single column re-column in the sub-matrix B, in this case, all the parity bits corresponding to the sub-matrix B can be obtained; and then according to the input sequence S and the parity bits corresponding to the sub-matrix B, the sub-matrix D is partially encoded.
- the check bits corresponding to the sub-matrix E thus obtaining all information bits and all check bits, these bits constitute the encoded sequence, that is, an LDPC code sequence.
- the LDPC code encoding may also include shortening and puncturing operations. Both truncated bits and punctured bits are not transmitted.
- the truncation is generally truncated from the last bit of the information bit, and can be truncated in different ways.
- the truncated number of bits s 0 can be set to the last s 0 bits in the input sequence S to obtain the input sequence S', such as set to 0 or null, or some other value, and then through the LDPC matrix pair
- the input sequence S' is encoded.
- the last (s 0 mod Z) bits in the input sequence S may be set to the known bits to obtain the input sequence S', if set to 0 or null, or some other value.
- the input sequence S' is encoded using the LDPC matrix H', or the last in the submatrix A
- the column does not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.
- the punching may be a punching bit built in the input sequence or a punching bit.
- the last bit of the parity bit is usually punctured.
- the puncturing may be performed according to the preset puncturing order of the system.
- a possible implementation manner is that the input sequence is first encoded, and then the last p bits in the parity bit are selected according to the number of bits p to be punctured, or p bits are selected according to the system's preset puncturing order. p bits are not sent.
- the p columns of the matrix corresponding to the punctured bits and the p rows of the non-zero elements in the columns may also be determined, and the rows and columns do not participate in the coding, and the corresponding school is not generated. Check the bit.
- the decoding involved in the present application may be a plurality of decoding methods, for example, a min-sum (MS) decoding method or a belief propagation decoding method.
- MS decoding method is sometimes also referred to as a Flood MS decoding method.
- the input sequence is initialized and iteratively processed, the hard decision detection is performed after the iteration, and the hard decision result is verified. If the decoding result conforms to the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. .
- the decoding mode is only an example.
- the base map and/or the base matrix provided by the present application, other decoding methods known to those skilled in the art may be used.
- the decoding method is not limited in this application.
- the LDPC code can usually be obtained by designing a base map or a base matrix. For example, a density evolution method may be applied to the base map or the base matrix to determine an upper performance limit of the LDPC code, and an error leveling layer of the LDPC code is determined according to the offset value in the base matrix. By designing the base or base matrix, coding or decoding performance can be improved, and error leveling can be reduced.
- the code length in the wireless communication system is flexible, for example, it can be 2560 bits, 38400 bits, etc.
- FIG. 3a is an example of a base diagram 30a of an LDPC code
- FIG. 3b-1 to FIG. 3b-10 are base matrixes of the base diagram 30a.
- Figure 3a shows an example of a base map 30a of an LDPC code, in which the uppermost row 0 to 67 (i.e., columns 0 to 67) represents the column number, and the leftmost column 0 to 45 (i.e., 0 to 45 rows) represents the row.
- the number, that is, the matrix size of the base map 30a is 46 rows and 68 columns.
- portions of sub-matrix A and sub-matrix B can be viewed as the core matrix portion of the base map of the LDPC code, which can be used for high bit rate encoding.
- a matrix of 5 rows and 27 columns is constructed, and a matrix of 5 rows and 27 columns as shown in the base diagram 10a can be used as a core matrix portion of the base map.
- the sub-matrix A may include one or more columns of built-in punctured bit columns.
- the column may include two columns of built-in punctured bit columns.
- the core matrix can support a code rate of 0.88.
- the sub-matrix B may include one column and three columns of re-columns, that is, the 0th column of the sub-matrix B (the 22nd column of the core matrix) has a column weight of 3, and the first to third columns of the sub-matrix B (the core matrix) Columns 23 to 25), the 0th to 3rd behaviors are double-diagonal structures, and the sub-matrix B also includes 1 column of single column weights (the 26th column of the core matrix).
- the sub-matrix B may correspond to a parity bit having a size of m A rows and m A columns, and elements of the 0th row to the 4th row and the 22nd column to the 26th column in the base map 30a. .
- sub-matrices C, sub-matrices D, and sub-matrices E of corresponding sizes may be added based on the core matrix to obtain different code rates.
- the sub-matrix C is an all-zero matrix
- the sub-matrix is an identity matrix, and its size is mainly determined according to the code rate, and the structure is relatively fixed.
- the main factors affecting the performance of the compiled code are the core matrix and the sub-matrix D part. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates.
- the sub-matrix D may include the m D rows in the 5th line to the 41st line of the base map 30a.
- the two rows are orthogonal to each other. If there are only one non-zero element in the same column except for a partial column in the adjacent two rows in the base map, the adjacent two rows are quasi-orthogonal. For example, for two adjacent rows, except for the column other than the built-in punctured bit column, which has only one non-zero element, the adjacent two rows can be considered to be quasi-orthogonal.
- Lines 5 to 41 of the base map 30a may include a multi-row quasi-orthogonal structure and at least two rows of orthogonal structures.
- the fifth row to the 41st line in the base map 30a includes at least 15 rows conforming to the quasi-orthogonal structure, and in any of the adjacent two rows of the 15 rows, except for the built-in punch bit column, in the same column There is at most one non-zero element.
- Lines 5 to 41 of the base map 30a may further include 10 to 26 lines conforming to the orthogonal structure, that is, among the lines, any one of the adjacent two lines has at most one non-zero element, that is, built-in There is also at most one non-zero element in the hole bit column.
- the sub-matrix D in the LDPC code base map has a size of 15 rows and 27 columns, which may be composed of a matrix of the 5th to 19th rows and the 0th column to the 26th column of the base map 30a, corresponding to the LDPC code.
- the sub-matrix E is an element matrix of 15 rows and 15 columns
- the sub-matrix C is an all-zero matrix of 5 rows and 15 columns;
- the size of the sub-matrix D in the LDPC code base map is 19 rows and 27 columns, which may be composed of a matrix of the 5th to 23rd rows and the 0th column to the 26th column of the base map 30a, corresponding to the LDPC code.
- the sub-matrix E is an identity matrix of 19 rows and 19 columns
- the sub-matrix C is an all-zero matrix of 5 rows and 19 columns.
- row/column swapping may be performed on the base map and/or base matrix, that is, row swapping, or column swapping, or row swapping and column swapping.
- the row/column swap operation does not change the row weight and the column weight, and the number of non-zero elements does not change. Therefore, the base and/or base matrix after row/column swap has limited impact on system performance. That is to say, as a whole, the impact on system performance is acceptable, within tolerance, for example, performance may fall within the allowable range for certain scenarios or within certain ranges, but in some scenarios or certain ranges Within the performance, the performance has improved, and overall it has little effect on performance.
- the 34th row and the 36th row of the base map 30a can be exchanged, and the 44th column and the 45th column can be exchanged.
- the sub-matrix D includes m D rows in the matrix F.
- the m D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, and no row is performed.
- the column swap for example, performs row swapping of the 27th and 29th rows of the matrix F, the submatrix D includes the m D rows in the matrix F, and the submatrix E is still a diagonal structure. It can be understood that if the base map or the base matrix includes the sub-matrix D, when the columns of the core matrix are exchanged, the columns in the corresponding sub-matrix D also need to be exchanged.
- the matrices 30b-10 to 30b-80 shown in Figures 3b-1 to 3b-10 are the design of a plurality of base matrices of the base map 30a, respectively.
- the non-zero elements of the i-th row and the j-th column in the base map 30a are invariant positions in the matrices of the matrices 30b-10 to 30b-80, and the values are offset values V i,j , and the zero elements are in the offset matrix.
- the sub-matrix D in the group matrix which may include corresponding parts D m row matrix of any of which line 5 to line 45, and can choose different values of the bit rate according to D m.
- the base map is a matrix after row/column transformation with respect to the base map 30a
- the base matrix is also a matrix after row/column transformation corresponding to any one of the matrices 30b-10 to 30b-80.
- the base matrix of the LDPC code may include rows 0 to 4 and columns 0 to 26 of any of the matrices 30b-10 to 30b-80 shown in FIGS. 3b-1 to 3b-10.
- the matrix composed of the 0th to 4th rows and the 0th to 26th columns of the matrix shown in FIGS. 3b-1 to 3b-10 can be used as the core portion of the base matrix.
- the structure of the other part of the base matrix of the LDPC code, for example, the matrix C, D, E is not limited, for example, any of the structures shown in FIG. 3b-1 to FIG. Other matrix designs can be used.
- the base matrix of the LDPC code may include the 0th to (m-1)th rows of any of the matrices 30b-10 to 30b-80 shown in FIG. 3b-1 to FIG. And a matrix composed of columns 0 to (n-1), wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer.
- the structure of other parts of the base matrix of the LDPC code is not limited.
- any of the structures shown in FIG. 3b-1 to FIG. 3b-10 may be employed, and other matrix designs may be employed.
- the base matrix of the LDPC code may include the 0th to 4th rows and the 0th to 26th of any of the matrices 30b-10 to 30b-80 shown in FIGS. 3b-1 to 3b-10.
- the core portions (lines 0 to 4 and columns 0 to 26) of the matrix shown in Figures 3b-1 through 3b-10 can be shortened and/or punctured.
- the base matrix of the LDPC code may not include columns corresponding to truncated and/or punctured bits.
- the other portions of the base matrix of the LDPC code are not limited.
- the structure shown in FIG. 3b-1 to FIG. 3b-10 may be referred to, and other configurations may be employed.
- the base matrix of the LDPC code may include the 0th to (m-1)th rows of any of the matrices 30b-10 to 30b-80 shown in FIG. 3b-1 to FIG. And a matrix composed of partial columns in the 0th to (n-1)th columns, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer.
- the 0th to (m-1)th rows and the 0th to (n-1)th columns of any of the matrices 30b-10 to 30b-80 shown in FIGS. 3b-1 to 3b-10 may be truncated ( Shortening) and/or puncturing.
- the base matrix of the LDPC code may not include columns corresponding to truncated and/or punctured bits.
- the other portions of the base matrix of the LDPC code are not limited.
- the structure shown in FIG. 3b-1 to FIG. 3b-10 may be referred to, and other configurations may be employed.
- the truncating operation may be truncating the information bits.
- the base matrix of the LDPC code may not include FIG. 3b-1.
- the base matrix of the LDPC code may include columns 0 to 20 and columns 22 to 26 of any matrix of 30b-10 to 30b-80.
- the code rate is 7/8.
- the puncturing may be puncturing the parity bit.
- one or more columns in the 22nd to 26th columns are punched by taking any of the matrices shown in FIG. 3b-1 to FIG. 3b-10 as an example.
- the base matrix of the LDPC code may not include one or more columns that are perforated in the matrix shown in FIGS. 3b-1 to 3b-10.
- the base matrix of the LDPC code may include columns 0 to 25 of any matrix of 30b-10 to 30b-80.
- Different spreading factors Z are designed for the LDPC code to support information bit sequences of different lengths.
- different base factors can be used for different spreading factors to achieve better performance.
- the expansion factor Z a ⁇ 2 j , 0 ⁇ j ⁇ 7, a ⁇ ⁇ 2, 3, 5, 7, 9, 11, 13, 15 ⁇ .
- Table 1 shows a set of extension factors that may be supported ⁇ 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ , wherein each cell represents, in addition to the top row and the leftmost column, respectively
- the set of spreading factors supported by the base map may be all the spreading factors in Table 1, it may also be a part of the spreading factor, for example, it may be ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ , that is, Z is greater than or equal to 24.
- one or more of ⁇ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22 ⁇ The union of 24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384 ⁇ . It should be noted that this is only an example.
- the set of spreading factors supported by the base map can be divided into different subsets according to the value of a.
- the set of spreading factors supported by the base map can be divided according to different values of a to determine the corresponding base matrix:
- the base matrix may include lines 0 to 4 of the matrix 30b-10 or 30b-11 and Columns 0 to 26, or the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-10 or 30b-11, where 5 ⁇ m ⁇ 46, m is An integer, 27 ⁇ n ⁇ 68, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-10 or 30b-11 and the partial columns in the 0th to (n-1)th columns, Wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer.
- the base matrix may include lines 0 to 4 of the matrix 30b-20 or 30b-21 and Columns 0 to 26, or the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-20 or 30b-21, where 5 ⁇ m ⁇ 46, m is An integer, 27 ⁇ n ⁇ 68, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-20 or 30b-21 and the partial columns in the 0th to (n-1)th columns, Wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-30, Alternatively, the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-30, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, n is An integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-30 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, n is an integer.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-40, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-40, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; Alternatively, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-40 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68 , n is an integer.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-50, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-50, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; Alternatively, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-50 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, and 27 ⁇ n ⁇ 68 , n is an integer.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns of the matrix 30b-60, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix 30b-60, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; Alternatively, the base matrix includes the 0th to (m-1)th rows of the matrix 30b-60 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, and 27 ⁇ n ⁇ 68 , n is an integer.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-70, or the base matrix
- the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-70 are included, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; or
- the base matrix includes the 0th to (m-1)th rows of the matrix 30b-70 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68,n Is an integer.
- the base matrix may include the 0th to 4th rows and the 0th to 26th columns in the matrix 30b-80, or the base matrix
- the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix 30b-80 are included, wherein 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68, and n is an integer; or
- the base matrix includes the 0th to (m-1)th rows of the matrix 30b-80 and the partial columns in the 0th to (n-1)th columns, where 5 ⁇ m ⁇ 46, m is an integer, 27 ⁇ n ⁇ 68,n Is an integer.
- the offset value Offset s may be increased or decreased for the offset value of one or more columns of non-zero elements in the matrix, and the system performance is not greatly affected.
- the compensation values of the non-zero elements in different columns may be the same or different.
- one or more columns of the matrix may be compensated.
- the compensation values of different columns may be the same or different, and the application is not limited.
- a small impact on system performance means that the impact on system performance is acceptable and within tolerance. For example, performance may be degraded within certain limits for certain scenarios or within certain ranges, but performance may improve over certain scenarios or within certain ranges, and overall has little impact on performance.
- the compensation value Offset s for each offset value greater than or equal to 0 in the sth column of any of the matrices 30b-10 to 30b-80 can obtain the compensation matrix Hs of the matrix, where Offset s is greater than Or an integer equal to 0, 0 ⁇ s ⁇ 23.
- the offset values Offsets of one or more columns may be the same or different.
- the performance curves of the LDPC codes encoded based on the matrices 30b-10 to 30b-80 the abscissa indicates the length of the information bit sequence, the unit is the bit, and the ordinate is the symbol letter required to reach the corresponding BLER.
- the noise ratio (Es/N0) the two lines of each code rate correspond to the BLER of 0.01 and 0.0001 respectively. At the same code rate, 0.01 corresponds to the upper curve and 0.0001 corresponds to the lower curve.
- the curves are smooth, indicating that the matrix has superior performance over different block lengths.
- FIGS. 1 to 3a and 3b-1 to 3b-10 show the base diagram of the LDPC code and the structure of the base matrix.
- the design of the base map and/or the base matrix in the embodiments of the present invention it can be further illustrated by the following Table 2-10 to Table 2-11.
- the base map of 10a in Figure 1 is a matrix of 5 rows and 27 columns, and the parameters involved can be represented by Tables 2-10.
- the size of the base matrix shown in Fig. 1 is a matrix of 5 rows and 27 columns, and the parameters involved can be expressed by Table 2-11.
- matrix 30b-10 in Figure 3b-1 can be represented by Tables 3-10.
- matrix 30b-11 in Figure 3b-2 can be represented by Tables 3-11.
- matrix 30b-20 in Figure 3b-3 can be represented by Tables 3-20.
- matrix 30b-21 in Figure 3b-4 can be represented by Tables 3-21.
- the matrix 30b-30 of Figures 3b-5 can be represented by Tables 3-30.
- the matrix 30b-40 of Figures 3b-6 can be represented by Tables 3-40.
- the matrix 30b-50 of Figures 3b-7 can be represented by Tables 3-50.
- the matrix 30b-60 of Figures 3b-8 can be represented by Table 3-60.
- the matrix 30b-70 of Figures 3b-9 can be represented by Table 3-70.
- the matrix 30b-80 of Figures 3b-10 can be represented by Table 3-80.
- FIG. 1 to FIG. 3a, FIG. 3b-1 to FIG. 3b-10, and Table 2-10, Table 2-11, and Tables 3-10 to 3-80 are for understanding understanding of the design of the base map and the matrix, Its manifestation is not limited to the representations of Figures 1 to 3a, 3b-1 to 3b-10 or Tables 2-10, 2-11 and 3-10 to 3-80 above. Other possible variations may also be included.
- the parameter "row weight" in Tables 2-10, 2-11, and 3-10 to 3-80 above may also be omitted. You can know how many non-zero elements are in the row through a column with a non-zero element, so the row weight is known.
- the parameter values in the “column of non-zero elements” in Table 2-10, Table 2-11, and Tables 3-10 to 3-80 may also not be from small to large. The order is as long as the parameter value is indexed to the column in which the non-zero element is located.
- the parameter values in "non-zero element offset values" of Table 2-10, Table 2-11, Tables 3-10 to 3-80 are not necessarily arranged in the order of the columns, as long as “non-zero elements are biased"
- the parameter value in the "shift value” can be in one-to-one correspondence with the parameter value in the "column where the non-zero element is located".
- the position of non-zero elements of the base or base matrix in a relatively fixed structure can be calculated according to the position of the row and column, and the positions of these non-zero elements may not be saved.
- the sub-matrix E is a diagonal matrix, and there are only non-zero elements on the diagonal.
- the offset values of non-zero elements on these diagonals are all 0, and the column in which the non-zero elements are located can be calculated according to the line number.
- the position of the row where the non-zero element is located can also be calculated according to the column number, taking the matrix 30b-50 shown in FIG. 3b-7 as an example.
- m eth row m e ⁇ 4
- the double diagonal structure B′ in the sub-matrix B is located in the 0th to 3rd rows and the 23rd to 25th columns in the matrix 30b-50, and the position of the column in which the non-zero element is located may be calculated according to the line number, or may be The column number calculates the position of the row where the non-zero element is located.
- the position of the non-zero element in the row includes the m b + K b column, and the m b + K b +1 column
- the position of the non-zero element in the row includes the m b + K b column
- the parameters involved in each row of the matrix 30b-50 can save the position of the column where the non-zero elements in the 0th column to the 25th column are located, without saving the 26th column to the 68th column.
- the position of the column where the zero element is located that is, the column in which the non-zero element in the single-column re-column of the sub-matrix E and sub-matrix B is not saved:
- the parameters involved in each row of matrix 3b-50 can save the position of the column where the non-zero elements in columns 0 to 26 are located, without saving the 27th column to the 68th column.
- the position of the column in which the zero element is located that is, the column in which the non-zero element in sub-matrix E is not stored:
- the row weight is optional.
- the column where the row number and the non-zero element are located indicates the location of the non-zero element in each row, which is the information of the base map of the LDPC matrix.
- the base map and offset value information of the LDPC matrix can be saved in the manner of Tables 3-10 to 3-91.
- the offset values of the base map and the LDPC matrix of the LDPC matrix can be separately saved, and the offset value information of the LDPC matrix can be obtained by using the row number and the non-zero element offset value in Tables 3-10 to 3-91.
- the base map of the LDPC may be saved in various forms, for example, the matrix form of the base map 30a as shown in FIG. 3a, or the position of the row number and the non-zero element in Tables 3-10 to 3-91, or The base map is treated as a binary number according to 1 and 0 of each row or column. Saving in decimal or hexadecimal can save storage space.
- each row can store the position of the first 26 columns or the first 27 columns of non-zero elements in four hexadecimal numbers.
- the first 26 columns of the 0th row are 11110110 01111101 1011111100, which can be recorded as the 0th row.
- the position of the non-zero element is 0xF6, 0x7D, 0xBF, 0x00, that is, every 8 columns constitute a hexadecimal number.
- the corresponding hexadecimal number can be obtained by padding 0 to 8 bits. Other lines and so on, will not be described here.
- the offset value of the LDPC may also be saved by other transformed forms.
- the offset value may be saved in the column corresponding to the offset value.
- Figure 9 shows the converted values of the 0th to 4th rows and the 0th to the 26th columns in the matrix 3b-50. The illustrated example starts with the 0th line, and the 0th line has the same offset value.
- the offset value of the non-zero element in each row is the difference between the offset value of the same position in the matrix 30b-50 and the previous non-zero element in the column of the offset value, if the offset If there is no non-zero element before the row in the value column, the offset value does not change.
- the offset value of the first row and the 0th column in the matrix 30b-50 is 179
- the offset value of the first row and the 0th column in FIG. 9 is 179 and the difference between the previous offset value 211 in the 0th column is -32. Because the 0th row and the 4th column of FIG.
- the offset value of the first row and the fourth column is the same as the offset value of the first row and the fourth column of the matrix 30b-50; the second row and the third column in FIG. Zero element, the first row and the third column are non-zero elements, so the offset value of the third row and the third column is the offset value 166 of the matrix 30b-50, the third row and the third column, and the first row and the third column.
- the difference of the offset values is positive, indicating that the unit matrix is rotated rightward, and the difference is negative, indicating that the unit matrix is rotated to the left.
- the transformed offset value that is, the difference value of the offset value
- the transformed offset value can be saved at the non-zero element offset value in Tables 3-10 to 3-91 above. The above is only an example and is not limited thereto.
- Figure 5 shows the design of the process of processing data.
- the process of processing the data may be implemented by a communication device, which may be a base station, terminal or other entity, such as a communication chip, an encoder/decoder, and the like.
- Section 501 the input sequence is obtained.
- the encoded input sequence can be a sequence of information bits.
- the information bit sequence is sometimes also referred to as a code block, and may be, for example, an output sequence after code block division of the transport block.
- the input sequence may include at least one of the following: padding bits or cyclic redundancy check CRC bits.
- the padding of the information bit sequence can be implemented in code block partitioning or after code block partitioning.
- Null or a value of 0, or other system-prescribed values can be used as the value of the padding bits so that after padding, these padding bits can be identified and not transmitted.
- the invention is not limited thereto.
- the decoded input sequence may be a soft sequence of LDPC codes.
- the input sequence is encoded/decoded based on an LDPC matrix;
- the base matrix of the LDPC matrix may be any of the base matrices in the foregoing examples.
- the LDPC matrix H can be derived based on the spreading factor Z and the base matrix.
- related parameters of the LDPC matrix H may be saved, and the parameters include one or more of the following:
- the base matrix may be obtained based on the parameters; for example, the parameters may include one or more of the following: row number, row weight, The position of the non-zero element, the offset value in the base matrix, the non-zero element offset value and the corresponding position, the compensation value, the spreading factor, the base map, the code rate, and the like.
- any of the base matrix enumerated in each of the above implementation modes passes through at least one column of compensated compensation matrix Hs;
- the input sequence is encoded/decoded based on the low density parity check LDPC matrix, which may be performed in one or more of the following manners in the encoding/decoding process:
- the compensation matrix of the base matrix is encoded/decoded, or encoded/decoded based on the matrix of the matrix matrix obtained by the compensation matrix Hs.
- it may further include an extended matrix encoding/decoding based on an extension matrix of the base matrix or the compensation matrix Hs, or truncating or playing based on a base matrix or a compensation matrix.
- the base matrix or the compensation matrix Hs encoding/decoding optionally, it may further include an extended matrix encoding/decoding based on an extension matrix of the base matrix or the compensation matrix Hs, or truncating based on a base matrix or a compensation matrix or Matrix coding/decoding after puncturing;
- Figure 6 shows a design for the process of obtaining processed data, which can be used in section 502 of Figure 5.
- the spreading factor Z can be determined based on the length K of the input sequence. For example, it may be that in the set of supported extension factors, the smallest Z 0 is found as the size of the expansion factor Z, and Kb ⁇ Z 0 ⁇ K is satisfied. In one possible design, Kb can be the number of columns of information bits in the base matrix of the LDPC code.
- the set of spreading factors supported by the base map 30a is ⁇ 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60 , 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384 ⁇ .
- a specific information length K may also be used, for example, for 104 ⁇ K ⁇ 512, Z may be selected according to a system-defined rule, and K is other lengths according to any of the foregoing implementation manners. For example, the minimum Z 0 of Kb ⁇ Z 0 ⁇ K is satisfied, where Kb is 22 or is determined according to the threshold.
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Abstract
Description
Z | a=2 | a=3 | a=5 | a=7 | a=9 | a=11 | a=13 | a=15 |
j=0 | 2 | 3 | 5 | 7 | 9 | 11 | 13 | 15 |
j=1 | 4 | 6 | 10 | 14 | 18 | 22 | 26 | 30 |
j=2 | 8 | 12 | 20 | 28 | 36 | 44 | 52 | 60 |
j=3 | 16 | 24 | 40 | 56 | 72 | 88 | 104 | 120 |
j=4 | 32 | 48 | 80 | 112 | 144 | 176 | 208 | 240 |
j=5 | 64 | 96 | 160 | 224 | 288 | 352 | ||
j=6 | 128 | 192 | 320 | |||||
j=7 | 256 | 384 |
K的取值范围 | 扩展因子Z |
Claims (40)
- [0183]又一种可能的设计中,选择满足Kb·Z 0≥K的最小的Z 0,,其中104≤K≤512时,Kb的取值也可以根据K的取值变化,例如,如表4-2所示;K为其他长度时,根据上述任一实现方式选取,如Kb=22或者根据门限值确定:表4-2[0184]其中,扩展因子Z可以由通信装置根据输入序列的长度K来确定,也可以是由通信装置从其他实体(如处理器)获得。[0185]602部分,基于扩展因子和基矩阵获得LDPC矩阵。[0186]基矩阵是前述各实施方式中例举的任一基矩阵,或者,相对于前述例举的任一基矩阵中至少一列进行补偿得到的补偿矩阵,或者相对于前述例举的任一基矩阵或补偿矩阵而言行顺序发生变换、或者列顺序发生变换,或者行顺序和列顺序均发生变换的基矩阵,其基图至少包括子矩阵A和子矩阵B。可选的还可以包括子矩阵C、子矩阵D和子矩阵E,各部分可以参考前述各实施例中的描述,此处不再赘述。[0187]在一种可能的实现方式中,根据扩展因子Z确定对应的基矩阵,并且根据扩展因子Z对该基矩阵进行置换得到LDPC矩阵。[0188]在一种实现方式中,可以存储扩展因子与基矩阵的对应关系,601部分获得的扩展因子Z,确定对应的基矩阵。[0189]例如,Z为26,a=13,基矩阵可以包括矩阵30b-70中的第0至~4行以及第0至26列,或者,基矩阵包括矩阵30b-70中的第0~至4行以及第0至26列中的部分列,;进一步地,或者基矩阵还包括矩阵0至m行以及第0至n列,其中5≤m≤46,m为整数,27≤n≤68,n为整数,或者,基矩阵包括矩阵30b-70的第0至m行以及第0至n列,其中5≤m≤46,m为整数,27≤n≤68,n为整数30b-70的第5行至第45行中的行,以及第27列至第67列中的列。根据扩展因子Z对该基矩阵进行置换得到LDPC矩阵。[0190]需要说明的是,这里仅仅是以Z=26,a=13,图3b-7所示的矩阵为例说明。此处仅为举例,本发明不限于此。可以理解,扩展因子不同,则基矩阵也有所不同。[0191]一种可能的实现方式中,扩展因子与基矩阵的对应关系可以如表5所示,根据表5确定扩展因子对应的基矩阵索引。一种可能的设计,PCM1可以是如图3b-1所示的矩阵30b-10,或者如图3b-2所示的矩阵30b-11;PCM2可以是如图3b-3所示的矩阵30b-20,或者如图3b-4所示的矩阵30b-21;PCM3可以是如图3b-5所示的矩阵30b-30;PCM4可以是如图3b-6所示的矩阵30b-40;PCM5可以是如图3b-7所示的矩阵30b-50;PCM6可以是如图3b-8所示的矩阵30b-60;PCM7可以是如图3b-9所示的矩阵30b-70;PCM8可以是如图3b-8所示的矩阵30b-80。此处仅为举例,并不以此为限制。表5[0192]一种可能的设计中,如表6所示,将表5中8个扩展因子集合设置集合索引:表6[0193]每个集合索引与一个PCM对应,例如1对应PCM1,2对应PCM2,3对应PCM3,…,8对应PCM8,以此类推。[0194]可选地,在一种可能的设计中,对于扩展因子Z,其基矩阵中第i行第j列元素P i,j可以满足下述关系:[0196]其中,V i,j可以是扩展因子Z所在集合的基矩阵中第i行第j列的元素的偏移值,或者是扩展因子Z所在集合中最大扩展因子的基矩阵的第i行第j列的非零元素的偏移值。[0197]例如,以Z为13为例,其基矩阵中第i行第j列的元素P i,j满足[0199]其中,V i,j是PCM7,矩阵30b-70中第i行第j列的非零元素的偏移值。对于Z=13而言,需要将矩阵30b-70中第i行第j列的非零元素的偏移值V i,j对Z=13取模。[0200]需要说明的是,此处仅为举例,本发明不限于此。[0201]603部分,基于LDPC矩阵对输入序列进行编码/译码。[0202]在一种实现方式中,编码的输入序列可以是信息比特序列。在又一种实现方式中,译码的输入序列可以是LDPC码的软值序列,可以参照图5中的相关描述。[0203]在一种可能的实现方式中,编码的输入序列c={c 0,c 1,c 2,...,c K-1},输入序列c长度为K,输入序列c经过编码后得到的输出序列d={d 0,d 1,d 2,...,d N-1},K为大于0的整数,K可以是扩展因子Z的整数倍。[0205]其中,校验比特序列w和输入序列c满足公式(1):[0206]其中,c T=[c 0,c 1,c 2,...,c K-1] T,为输入序列中各比特组成的向量的转置向量, 为校验序列中各比特组成的向量的转置向量,0 T为列向量,其中所 有元素的值为0。[0207]其中H为基于前述各实施例中例举的任一基图或基矩阵得到的LDPC矩阵,H的基图大小为m行n列,可以是前述实施例中例举的任一基图,例如,基图30a。[0208]在一种设计中,H的基图中包括p列内置打孔列,p为大于或者等于0的整数,p列内置打孔列对应的信息比特不被输出,也输出序列中不包括p列内置打孔列对应的信息比特,则K 0=K-p·Z,例如,p=2,则K 0=K-2·Z,校验序列w的长度为N+2·Z-K。若p列内置打孔列参与编码,则K 0=K,校验序列w的长度为N-K。[0211]在一种可能的设计中, 为前述各实施例基图中子矩阵C, 为前述各实施例中子矩阵E,则 A,B和D分别为前述各实施例基图中子矩阵A、B和D,则m c=5,0≤n c≤41,H BG的行数小于或者等于46,且大于或者等于5,H BG的列数等于27。[0212]在又一种可能的设计中,由于第26列为一单列重列,且其中非零元素位于第5行,因此 也可以包括前述各实施例基图中第26列的前4行以及为前述各实施例中子矩阵C中的前4行, 也可以包括前述各实施例中基图子矩阵E以及第26列的第5至第46行和子矩阵C的最后1行,则m c=4,0≤n c≤42;H BG为前述各实施例基图中子矩阵A、B和D组成的部分去掉最后一列构成的矩阵,H BG的行数小于或者等于46,且大于或者等于5,H BG的列数等于26。可选地,如果需要进一步提高码率,H BG的行数可以为4行,也就是第0至3行。[0213]相应地,LDPC矩阵H可以表示成H=[H 1 H 2]。其中,[0214]H 1可以是将H BG中每个零元素替换成Z*Z大小的全零矩阵,每个非零元素替换成Z*Z大小的循环置换矩阵h i,j得到,其中循环置换矩阵h i,j是将Z*Z大小的单位矩阵循环右移P i,j得到的,有时也用I(P i,j)表示。其中,i是行号,j是列号,一种可能的设计中P i,j=mod(V i,j,Z),V i,j是Z对应的扩展因子集合索引i LS所对应的基矩阵中第i行第j列的非零元素。[0215]H 2可以是将H BG,EXT中每个零元素替换成Z*Z大小的全零矩阵,每个非零元素替换成Z*Z大小的单位矩阵得到。[0216]编码器可以采用多种方式进行编码并输出,下面以前述实施例中例举的基图30a以及基矩阵30b-50为例进行说明,其中基图和基矩阵行数最大为46行,列数最大为68列,包括2列内置打孔列,为了方便描述,在本发明中有时将行数最大且列数也最大的基图称为完整基图,行数最大且列数也最大的基矩阵称为完整基矩阵。[0217]方式一:[0218]基于完整基图或者完整基矩阵编码,从而获取到尽可能多的校验比特。此时,m=46,n=68,也就是上述基图30a的第0至第45行以及第0至第67列,或者,基矩阵30b-50中第0至第45行以及第0至第67列的偏移值。[0219]相应地,对于LDPC矩阵H,M=46·Z,如果输出序列包括内置打孔列对应的信息比特,则N=68·Z,如果输出序列不包括除内置打孔列对应的2·Z个信息比特,则N=66·Z。[0220]可以在后续处理环节中从编码器产生的输出序列中确定需要发送的信息比特和校验比特。[0221]方式二:[0222]基于完整基图或者完整基矩阵的部分行、列编码。可以根据需要发送的码率,或者,信息比特和校验比特数等从完整基图或基矩阵中选择行、列编码。[0223]例如,码率为8/9,m=5,n=27,也就是基于基图30a中第0至4行以及第0至26列的部分编码,或者基于基矩阵30b-50中第0至4行以及第0至26列的偏移值编码。[0224]相应地,对于LDPC矩阵H,M=5·Z,如果输出序列包括内置打孔列对应的信息比特,则N=27·Z,如果输出序列不包括内置打孔列对应的信息比特,则N=25·Z。[0225]又例如,码率为1/3,m=46,n=68。[0226]可见,这种方式下,H的基图或者基矩阵大小为,5≤m≤46,27≤n≤68,相应地对于LDPC矩阵H,5·Z≤M≤46·Z,27·Z≤N≤68·Z。[0227]一种可能的设计中,由于基图30a中第26列为单列重列,可以对核心矩阵中单列重列进行打孔,使得核心矩阵相应减少1行和1列,从而m为4,n=26,也就是基于上述基图30a或者基矩阵30b-50中第0至3行以及第0至25列的部分编码。这种方式可以获取到更高的码率。从而基图或基矩阵大小为,4≤m≤46,26≤n≤68,相应地对于LDPC矩阵H,4·Z≤M≤46·Z,26·Z≤N≤68·Z。[0228]由于译码是编码的逆过程,对LDPC矩阵H及其基图、基矩阵的描述可参见前述编码方法。在进行译码时也可以基于完整基图或者完整基矩阵进行译码,或者,基于完整基图或者完整基矩阵的部分行、列译码。[0229]对输入序列进行编码/译码时,可以根据Z对基矩阵进行扩展得到的LDPC矩阵H。对基矩阵中每一非零元素P i,j,确定Z*Z大小的循环置换矩阵h i,j,其中h i,j为单位矩阵经过P i,j次循环移位得到的循环置换矩阵,将h i,j替换非零元素P i,j,将Z*Z大小的全零矩阵替换基矩阵H B中的零元素,从而得到奇偶校验矩阵H。[0230]在一种可能的实现方式中,LDPC码的基矩阵可以是保存在存储器中,通信装置获取扩展因子Z对应的LDPC矩阵,从而对输入序列进行编码/译码。[0231]在一种可能的实现方式中,由于LDPC码的基矩阵有多个,按照矩阵结构保存会占用较大的存储空间,也可以将LDPC码的基图保存在存储器中,分别逐行或者逐列保存各基矩阵中非零元素的偏移值,然后根据基图和扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵。[0232]基图可以指示各基矩阵非零元素的位置,根据基图和扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵也可以是根据各非零元素的位置及扩展因子Z对应的基矩阵的偏移值得到LDPC矩阵。[0233]在又一种可能的实现方式中,保存基图可以是保存其中非零元素的位置。非零元素的位置可以通过非零元素所在的行和列指示,例如每一行中非零元素所在的列的位置,或者, 每一列中非零元素所在的行的位置。在又一种可能的实现方式中,保存基图也可以是保存其中零元素的位置,同样,也可以通过零元素所在的行和列指示。例如每一行中零元素所在的列的位置,或者每一行中零元素所在的行的位置,则相应的非零元素的位置可以通过排除零元素所在的位置得到。需要说明的是,此处仅为举例,本发明并不限于此。[0234]在一种可能的实现方式中,也可以按照表2-10,2-11,3-10至3-80以及3-90和3-91的方式保存各基矩阵中非零元素的偏移值,作为LDPC矩阵的参数,其中表2-10,2-11,3-10至3-80以及3-90和3-91中“行重”一列可选,也就是“行重”这列可以可选的保存或者不保存。通过一行非零元素所在的列,获知这一行有多少个非零元素,因此行重也就获知了。在一种可能的实现方式中,对于上述表2-10,2-11,3-10至3-80以及3-90和3-91中的“非零元素所在的列”中的参数值,也可以不按照由小到大的顺序排列,只要参数值索引到非零元素所在的列就行。此外,对于表2-10,2-11,3-10至3-80以及3-90和3-91中的“非零元素偏移值”中的参数值,也不一定按照列的顺序排列,只要“非零元素偏移值”中的参数值,与“非零元素所在的列”中的参数值一一对应,通信装置可获知非零元素偏移值是对应哪行哪一列的非零元素就性。例如:[0235]在一种可能的实现方式中,可以参照图5中的相关描述,对LDPC矩阵的相关参数保存。[0236]在一种可能的实现方式中,保存LDPC矩阵的相关的参数时,也可以不保存图1至图3a,3b-1至3b-10,或者表2-10,2-11,3-10至3-80以及3-90和3-91中所示矩阵的所有行,可以根据基矩阵中包括的行保存表格中相应的行所指示的参数。例如,可以保存上述实施例中所描述的LDPC矩阵的基矩阵所包括的行和列所构成的矩阵,或者所述行和列所构成的矩阵所涉及的相关参数。[0237]例如,如果基矩阵包括30b-10至30b-80以及3-90和3-91任一矩阵中的第0至4行以及第0至26列,则,可以保存所述第0至4行以及第0至26列所构成的矩阵,和/或保存第0至4行以及第0至26列所构成的矩阵的相关参数,可以参照表3-10至3-80以及3-90和3-91中所示的参数,以及上述部分描述。[0238]如果基矩阵包括30b-10至30b-80以及3-90和3-91任一矩阵中第0至(m-1)行以及第0至(n-1)列,其中5≤m≤46,m为整数,27≤n≤68,n为整数,则,可以保存所述第0至(m-1)行以及第0至(n-1)列所构成的矩阵,和/或者保存所述第0至(m-1)行以及第0至(n-1)列所构成的矩阵的相关参数,可以参照表3-10至3-80以及3-90和3-91中所示的参数以及上述部分的描述。[0239]在一种可能的实现方式中,可以对表3-10至3-80以及3-90和3-91任一表中至少一个“非零元素所在的列”中位置s指示的大于或等于0的各偏移值增加或减少补偿值Offset s。[0240]在一种可能的实现方式中,可以对表3-10至3-80以及3-90和3-91任一表中“非零元素偏移值”保存如前述实施例所述的变换后偏移值,如图9所示的偏移值。[0241]在又一种设计中,LDPC矩阵的基图和LDPC矩阵的偏移值可以分别保存,LDPC矩阵的偏移值信息可以通过表3-10至3-91中行号和非零元素偏移值来保存,LDPC的基图可以采用多种形式保存,例如,如图3a所示基图30a的矩阵形式,或者表3-10至表3-91中行号和非零元素所在的位置,或者,对于基图按照每一行或每一列的1和0视为2进制数,采用10进制或者16进制数保存可以节省存储空间。以基图30a为例,每行可以用4个16进制数 保存前26列或者前27列非零元素的位置,例如第0行前26列为11110110 01111101 10111111 00,则可以记为第0行非零元素的位置为0xF6,0x7D,0xBF,0x00,也就是每8列组成一个16进制数,对于其中最后2列或3列,可以通过填充0达到8位得到相应的16进制数,其他行以此类推,此处不再赘述。需要说明的是,此处均只是举例,并不以此为限制。[0242]以图1为例,确定出基矩阵H B后,可以先通过输入序列和基矩阵的第0至3行以及第0至第25列,也就是H core-dual部分得到第22至25列对应的校验比特;再根据输入序列和H core-dual对应的校验比特得到第26列,也就是单列重列对应的校验比特;然后根据输入序列以及第22至26列对应的校验比特和子矩阵D对应的部分编码得到子矩阵E部分对应的校验比特,从而完成编码。LDPC码的编码过程可以参考前述实现方式描述,此处不再赘述。[0243]在一种可能的实现方式中,LDPC矩阵H可以在编码前根据扩展因子Z对扩展因子进行展开,也就是根据偏移值替换相应的循环置换矩阵;[0244]在又一种可能的实现方式中,在进行编码时根据被编码的比特对应的非零元素的位置,获取相应的偏移值,对该非零元素替换相应的循环置换矩阵并处理;[0245]在又一种可能的实现方式中,LDPC矩阵H在使用过程中不直接展开,而根据偏移值计算等价矩阵行列间的连接关系对待输入序列中的比特进行处理;[0246]在又一种可能的实现方法中,可以采用QSN方法编码,对每个待处理的非零元素,根据该非零元素的偏移值,将与其对应的待编码比特段做移位操作;之后,对所有做过移位操作后的比特段直接进行编码运算。[0247]在又一种可能的实现方式中,也可以保存LDPC矩阵H的生成矩阵G,则输入序列c和输出序列d满足公式(2):d=c·G (2)[0248]若将LDPC矩阵H进行行列变换得到H’,其中H’右侧为单位矩阵I,左侧矩阵为P则H’=[P I],则其中生成矩阵G满足下述公式(3):G=[I P T] (3)[0249]需要说明的是,上述均为举例,本发明并不限于此。[0250]可选地,在通信系统中,可采用上述方法编码后得到LDPC码。获得LDPC码后,通信装置,还可以进行以下一个或多个操作:对LDPC码进行速率匹配;根据交织方案对速率匹配后的LDPC码进行交织;根据调制方案对交织后的LDPC码进行调制得到比特序列X;发送比特序列X。[0251]译码是编码的逆过程,译码过程使用的基矩阵与编码过程使用的的基矩阵具有相同的特征。LDPC码的编码过程可以参考前述实现方式描述,此处不再赘述。在一种实现方式中,在译码之前,通信装置还可以进行以下一个或多个操作:接收包含基于LDPC编码的信号,对信号进行解调,解交织以及解速率匹配得到LDPC码的软值序列,对LDPC码的软值序列进行译码。[0252]本申请中涉及的保存,可以是指的保存在一个或者多个存储器中。所述一个或者多个存储器,可以是单独的设置,也可以是集成在编码器或者译码器,处理器、芯片、通信装置、 或者终端。所述一个或者多个存储器,也可以是一部分单独设置,一部分集成在译码器、处理器、芯片、通信装置、或者终端中,存储器的类型可以是任意形式的存储介质,本申请并不对此限定。[0253]相应于图5,图6的给出的数据处理过程的设计,本发明实施例还提供了相应的通信装置,所述通信装置包括用于执行图5或图6中每个部分相应的模块。所述模块可以是软件,也可以是硬件,或者是软件和硬件结合。例如模块可以包括存储器,电子设备,电子部件,逻辑电路等,或上述任一组合。图7给出了一种通信装置700的结构示意图,装置700可用于实现上述方法实施例中描述的方法,可以参见上述方法实施例中的说明。所述通信装置700可以是芯片,基站,终端或者其他网络设备。[0254]所述通信装置700包括一个或多个处理器701。所述处理器701可以是通用处理器或者专用处理器等。例如可以是基带处理器、或中央处理器。基带处理器可以用于对通信协议以及通信数据进行处理,中央处理器可以用于对通信装置(如,基站、终端、或芯片等)进行控制,执行软件程序,处理软件程序的数据。[0255]在一种可能的涉及中,如5,图6中的一个或者多个模块可能由一个或者多个处理器来实现,或者一个或者多个处理器和存储器来实现。[0256]在一种可能的设计中,所述通信装置700包括一个或多个所述处理器701,所述一个或多个处理器701可实现上述编码/译码的功能,例如通信装置可以是编码器或者译码器。在另一种可能的设计中,处理器701除了实现编码/译码功能,还可以实现其他功能。[0257]所述通信装置700基于LDPC矩阵对输入序列进行编码/译码;该LDPC矩阵的基矩阵可以为前述示例中的任一基矩阵或者相对于前述例举的任一基矩阵而言行顺序发生变换、或者列顺序发生变换,或者行顺序和列顺序均发生变换的基矩阵,或者是基于前述例举的任一基矩阵截短或者打孔的基矩阵,或者是基于前述例举任一基矩阵扩展后的矩阵。关于编码或者/译码的处理可以参见图5和图6相关部分的描述,在此不再赘述。[0258]可选的,在一种设计中,处理器701可以包括指令703(有时也可以称为代码或程序),所述指令可以在所述处理器上被运行,使得所述通信装置700执行上述实施例中描述的方法。在又一种可能的设计中,通信装置700也可以包括电路,所述电路可以实现前述实施例中的编码/译码功能。[0259]可选的,在一种设计中,所述通信装置700中可以包括一个或多个存储器702,其上存有指令704,所述指令可在所述处理器上被运行,使得所述通信装置700执行上述方法实施例中描述的方法。[0260]可选的,所述存储器中还可以存储有数据。可选的处理器中也可以存储指令和/或数据。所述处理器和存储器可以单独设置,也可以集成在一起。[0261]可选的,上述实施例中所述的“保存”可以是保存存储器702中,也可以是保存在其他的外设的存储器或者存储设备中。[0262]例如,一个或多个存储702可以存储与上述列举的LDPC矩阵相关的参数,例如,基矩阵相关的参数,例如偏移值,基图,基于基图扩展到矩阵、基矩阵中的各行,扩展因子,基矩阵或者基于基矩阵扩展到矩阵等等。具体可以参见上述图5部分的相关描述。[0263]可选的,所述通信装置700还可以包括收发器705以及天线706。所述处理器701可以称为处理单元,对通信装置(终端或者基站)进行控制。所述收发器505可以称为收发单元、收发机、收发电路、或者收发器等,用于通过天线506实现通信装置的收发功能.[0264]可选的,所述通信装置700还可以包括用于产生传输块CRC的器件、用于码块分割和CRC校验的器件、用于交织的交织器、用于速率匹配的器件、或者用于调制处理的调制器等。可以通过一个或多个处理器701实现这些器件的功能。[0265]可选的,所述通信装置700还可以包括,用于解调操作的解调器、用于解交织的解交织器、用于解速率匹配的器件、或者用于码块级联和CRC校验的器件等等。可以通过一个或多个处理器701实现这些器件的功能。[0266]图8给出了一种通信系统800的示意图,通信系统800中包括通信设备80和通信设备81,其中,信息数据在通信设备80和通信设备81之间接收和发送。通信设备80和81可以是所述通信装装置700,或者通信设备备80和81分别包括通信装置700,对信息数据进行接收和/或发送。在一个例子中,通信设备80可以为终端,相应的通信设备81可以为基站;在另一个例子中,通信设备80为基站,相应的通信设备81可以为终端。[0267]本领域技术任何还可以了解到本发明实施例列出的各种说明性逻辑块(illustrative logical block)和步骤(step)可以通过电子硬件、电脑软件,或两者的结合进行实现。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用,可以使用各种方法实现所述的功能,但这种实现不应被理解为超出本发明实施例保护的范围。[0268]本申请所描述的技术可通过各种方式来实现。例如,这些技术可以用硬件、软件或者硬件结合的方式来实现。对于硬件实现,用于在通信装置(例如,基站,终端、网络实体、或芯片)处执行这些技术的处理单元,可以实现在一个或多个通用处理器、数字信号处理器(DSP)、数字信号处理器件(DSPD)、专用集成电路(ASIC)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、或其它可编程逻辑装置,离散门或晶体管逻辑,离散硬件部件,或上述任何组合中。通用处理器可以为微处理器,可选地,该通用处理器也可以为任何传统的处理器、控制器、微控制器或状态机。处理器也可以通过计算装置的组合来实现,例如数字信号处理器和微处理器,多个微处理器,一个或多个微处理器联合一个数字信号处理器核,或任何其它类似的配置来实现。[0269]本发明实施例中所描述的方法或算法的步骤可以直接嵌入硬件、处理器执行的指令、或者这两者的结合。存储器可以是RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域中其它任意形式的存储媒介。例如,存储器可以与处理器连接,以使得处理器可以从存储器中读取信息,并可以向存储器存写信息。可选地,存储器还可以集成到处理器中。处理器和存储器可以设置于ASIC中,ASIC可以设置于UE中。可选地,处理器和存储器也可以设置于UE中的不同的部件中。[0270]通过以上的实施方式的描述,所属领域的技术人员可以清楚地了解到本发明可以用硬件实现,或固件实现,或它们的组合方式来实现。当使用软件程序实现时,可以全部或部分地以计算机程序产品的形式实现,所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时,全部或部分地产生按照本发明实施例所述的流程或功能。 当使用软件程序实现时,也可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中,或者从一个计算机可读存储介质向另一计算机可读存储介质传输。计算机可读介质包括计算机存储介质和通信介质,其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于:计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如,如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的,那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定义中。如本发明所使用的,盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟,其中盘通常磁性的复制数据,而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。[0271]需要说明的是,本申请中的“/”表示和/或,例如“编码/译码(编码和/或译码),是指的编码、或者译码、或者编码和译码。[0272]总之,以上所述仅为本发明技术方案的较佳实施例而已,并非用于限定本发明的保护范围。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
- 一种编码方法,其特征在于,所述方法包括:使用低密度奇偶校验LDPC矩阵对输入序列进行编码;所述LDPC矩阵是基于扩展因子Z和基矩阵得到的,所述基矩阵包括以下所示矩阵:30b-10、30b-11、30b-20、30b-21、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列,或者,所述基矩阵包括以下所示矩阵:30b-10、30b-11、30b-20、30b-21、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列中的部分列。
- 一种译码方法,其特征在于,所述方法包括:使用低密度奇偶校验LDPC矩阵对输入序列进行译码;所述LDPC矩阵是基于扩展因子Z和基矩阵得到的,所述基矩阵包括以下所示矩阵:30b-10、30b-11、30b-20、30b-21、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列,或者,所述基矩阵包括以下所示矩阵:30b-10、30b-11、30b-20、30b-21、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0至4行以及第0至26列中的部分列。
- 根据权利要求1或2所述的方法,其特征在于,所述基矩阵还包括以下所示矩阵30b-10、30b-11、30b-20、30b-21、30b-30、30b-40、30b-50、30b-60、30b-70和30b-80之一中的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68。
- 根据权利要求1至3任一项所述的方法,其特征在于,所述扩展因子Z=a×2 j,0≤j<7,a∈{2,3,5,7,9,11,13,15},其中,a=2,所述基矩阵包括矩阵30b-10或30b-11中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-10或30b-11中的第0至4行以及第0至26列中的部分列;或者,a=3,所述基矩阵包括矩阵30b-20或30b-21中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-20或30b-21中的第0~4行以及第0至26列中的部分列;或者,a=5,所述基矩阵包括矩阵30b-30中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-30中的第0~4行以及第0至26列中的部分列;或者,a=7,所述基矩阵包括矩阵30b-40中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-40中的第0~4行以及第0至26列中的部分列;或者,a=9,所述基矩阵包括矩阵30b-50中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-50中的第0~4行以及第0至26列中的部分列;或者,a=11,所述基矩阵包括矩阵30b-60中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-60中的第0~4行以及第0至26列中的部分列;或者,a=13,所述基矩阵包括矩阵30b-70中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-70中的第0至4行以及第0至26列中的部分列;或者,a=15,所述基矩阵包括矩阵30b-80中的第0至4行以及第0至26列,或者,所述基矩阵包括矩阵30b-80中的第0至4行以及第0至26列中的部分列。
- 根据权利要求1至4任一项所述的方法所述的方法,其特征在于,a=2,所述基矩阵还包括矩阵30b-10或者30b-11的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68;或者,a=3,所述基矩阵还包括矩阵30b-20或者30b-21的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68;或者,a=5,所述基矩阵还包括矩阵30b-30的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68;或者,a=7,所述基矩阵还包括矩阵30b-40的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68;或者,a=9,所述基矩阵还包括矩阵30b-50的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68;或者,a=11,所述基矩阵还包括矩阵30b-60的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68;或者,a=13,所述基矩阵还包括矩阵30b-70的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68;或者,a=15,所述基矩阵还包括矩阵30b-80的第0行至第(m-1)行,以及第0列至第(n-1)列,其中5≤m≤46,27≤n≤68。
- 根据权利要求1至5任一项所述的方法,其特征在于,所述LDPC矩阵是基于所述扩展因子Z,和对所述基矩阵进行补偿后的矩阵Hs得到的,其中,所述矩阵Hs是对所述基矩阵中至少一列s中大于或等于0的各偏移值增加或减少补偿值Offset s得到的,其中,所述补偿值Offset s为大于或等于0的整数,0≤s<23。
- 根据权利要求1至6任一项所述的方法,其特征在于,所述LDPC矩阵是基于所述扩展因子Z,和所述基矩阵或者基矩阵的补偿矩阵Hs经过行交换、或者列交换、或者行交换和列交换后的矩阵得到的。
- 一种编码方法,其特征在于,所述方法包括:根据扩展因子Z和低密度奇偶校验LDPC矩阵的参数对输入序列进行编码;其中,所述LDPC矩阵的参数包括表3-10、表3-11、表3-20、表3-21、表3-30、表3-40、表3-50、表3-60、表3-70以及表3-80之一中行号为0至4对应的参数。
- 一种译码方法,其特征在于,所述方法包括:根据扩展因子Z和低密度奇偶校验LDPC矩阵的参数对输入序列进行译码;其中,所述LDPC矩阵的参数包括表3-10、表3-11、表3-20、表3-21、表3-30、表3-40、表3-50、表3-60、表3-70以及表3-80之一中行号为0至4对应的参数。
- 根据权利要求8或9所述的方法,其特征在于,所述LDPC矩阵的参数还包括 所述0至4之一中行号为5-45中的m D行对应的参数,其中0≤m D≤41。
- 根据权利要求8至10任一项所述的方法,其特征在于,所述扩展因子Z=a×2 j,0≤j<7,a∈{2,3,5,7,9,11,13,15},其中,a=2,所述LDPC矩阵的参数包括表3-10或者3-11中行号为0至4行所对应的参数;或者,a=3,所述LDPC矩阵的参数包括表3-20或者3-21中行号为0至4行所对应的参数;或者,a=5,所述LDPC矩阵的参数包括表3-30中行号为0至4行所对应的参数;或者,a=7,所述LDPC矩阵的参数包括表3-40中行号为0至4行所对应的参数;或者,a=9,所述LDPC矩阵的参数包括表3-50中行号为0至4行所对应的参数;或者,a=11,所述LDPC矩阵的参数包括表3-60中行号为0至4行所对应的参数;或者,a=13,所述LDPC矩阵的参数包括表3-70中行号为0至4行所对应的参数;或者,a=15,所述LDPC矩阵的参数包括表3-80中行号为0至4行所对应的参数。
- 根据权利要求11所述的方法,其特征在于,a=2,所述LDPC矩阵的参数包括表3-10或者3-11的行号为5至45中的m D行所对应的参数;或者,a=3,所述LDPC矩阵的参数包括表3-20或者3-21的行号为5至45中的m D行所对应的参数;或者,a=5,所述LDPC矩阵的参数包括表3-30的行号为5至45中的m D行所对应的参数;或者,a=7,所述LDPC矩阵的参数包括表3-40的行号为5至45中的m D行所对应的参数;或者,a=9,所述LDPC矩阵的参数包括表3-50的行号为5至45中的m D行所对应的参数;或者,a=11,所述LDPC矩阵的参数包括表3-60的行号为5至45中的m D行所对应的参数;或者,a=13,所述LDPC矩阵的参数包括表3-70的行号为5至45中的m D行所对应的参数;或者,a=15,所述LDPC矩阵的参数包括表3-80的行号为5至45中的m D行所对应的参数。
- 根据权利要求8至12任一项所述的方法,其特征在于,所述根据扩展因子Z和低密度奇偶校验LDPC矩阵的参数对输入序列进行编码,包括:根据扩展因子Z和对所述LDPC矩阵的参数进行补偿后的参数对输入序列进行编码;所述对所述LDPC矩阵的参数进行补偿,包括:对所述LDPC矩阵的参数中至少一个列位置s上的大于或等于0的各偏移值增加或 减少补偿值Offset s得到的,其中,所述补偿值Offset s为大于或等于0的整数,0≤s<23。
- 一种装置,用于执行如权利要求1至13项任一项所述的方法。
- 一种通信装置,其特征在于,所述通信装置包括处理器、存储器以及存储在存储器上并可在处理器上运行的指令,当所述指令被运行时,使得所述通信装置执行如权利要求1至13项任一项所述的方法。
- 一种终端,其特征在于,包括如权利要求14所述的装置或权利要求15所述的通信装置。
- 一种基站,其特征在于,包括如权利要求14所述的装置或权利要求15所述的通信装置。
- 一种通信系统,其特征在于包括如权利要求16所述的终端以及如权利要求17所述的基站。
- 一种计算机可读存储介质,包括指令,当其在计算机上运行时,使得计算机执行如权利要求1至13任一项所述的方法。
- 一种计算机程序产品,当其在计算机上运行时,使得计算机执行权利要求1至13任一项所述的方法。
- 一种编码方法,包括:基于低密度奇偶校验LDPC矩阵H对输入序列c进行编码;所述LDPC矩阵H的基矩阵包括非零元素(i,j),其中,i为行号,j为列号,所述非零元素(i,j)表示该元素被Z*Z大小的循环置换矩阵替换,所述循环置换矩阵对应于Z*Z大小的单位矩阵的向右P i,j次循环移位,P i,j=mod(V i,j,Z),Z为扩展因子,所述非零元素(i,j)及其对应的值V i,j如下:i=0,j=0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23,V i,j分别为211,198,188,186,219,4,29,144,116,216,115,233,144,95,216,73,261,1,0;i=1,j=0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24,V i,j分别为179,162,223,256,160,76,202,117,109,15,72,152,158,147,156,119,0,0;i=2,j=0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25,V i,j分别为258,167,220,133,243,202,218,63,0,3,74,229,0,216,269,200,234,0,0;i=3,j=0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25,V i,j分别为187,145,166,108,82,132,197,41,162,57,36,115,242,165,0,113,108,1,0;i=4,j=0,1,26,V i,j分别为246,235,0。
- 根据权利要求21所述的方法,其特征在于,所述基于低密度奇偶校验LDPC矩阵H对输入序列c进行编码,包括:对输入序列c={c 0,c 1,c 2,...,c K-1}进行编码得到输出序列d={d 0,d 1,d 2,...,d N-1},其中,K和N均为正整数;所述输出序列d包括所述输入序列c中K 0个比特和校验序列w中的校验比特,K 0为整数,且0<K 0≤K,校验序列w的长度为N-K 0;
- 根据权利要求22所述的方法,其特征在于,K 0=K-2·Z。
- 一种译码方法,包括:基于低密度奇偶校验LDPC矩阵H对LDPC码的软值序列进行译码得到信息序列;其中,所述H的基矩阵包括非零元素(i,j),其中,i为行号,j为列号,所述非零元素(i,j)表示该元素被Z*Z大小的循环置换矩阵替换,所述循环置换矩阵对应于Z*Z大小的单位矩阵的向右P i,j次循环移位,P i,j=mod(V i,j,Z),Z为扩展因子,所述非零元素(i,j)及其对应的值V i,j如下:i=0,j=0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23,V i,j分别为211,198,188,186,219,4,29,144,116,216,115,233,144,95,216,73,261,1,0;i=1,j=0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24,V i,j分别为179,162,223,256,160,76,202,117,109,15,72,152,158,147,156,119,0,0;i=2,j=0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25,V i,j分别为258,167,220,133,243,202,218,63,0,3,74,229,0,216,269,200,234,0,0;i=3,j=0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25,V i,j分别为187,145,166,108,82,132,197,41,162,57,36,115,242,165,0,113,108,1,0;i=4,j=0,1,26,V i,j分别为246,235,0。
- 根据权利要求21至24任一项所述的方法,其特征在于,所述H的基矩阵为m行n列的矩阵,m≤46,n≤68。
- 根据权利要求25所述的方法,其特性在于,所述H的基矩阵还包括以下非零元素(i,j),其对应的值V i,j如下:i=5,j=0,1,3,12,16,21,22,27,V i,j分别为261,181,72,283,254,79,144,0;i=6,j=0,6,10,11,13,17,18,20,28,V i,j分别为80,144,169,90,59,177,151,108,0;i=7,j=0,1,4,7,8,14,29,V i,j分别为169,189,154,184,104,164,0;i=8,j=0,1,3,12,16,19,21,22,24,30,V i,j分别为54,0,252,41,98,46,15,230,54,0;i=9,j=0,1,10,11,13,17,18,20,31,V i,j分别为162,159,93,134,45,132,76,209,0;i=10,j=1,2,4,7,8,14,32,V i,j分别为178,1,28,267,234,201,0;i=11,j=0,1,12,16,21,22,23,33,V i,j分别为55,23,274,181,273,39,26,0;i=12,j=0,1,10,11,13,18,34,V i,j分别为225,162,244,151,238,243,0;i=13,j=0,3,7,20,23,35,V i,j分别为231,0,216,47,36,0;i=14,j=0,12,15,16,17,21,36,V i,j分别为0,186,253,16,0,79,0;i=15,j=0,1,10,13,18,25,37,V i,j分别为170,0,183,108,68,64,0;i=16,j=1,3,11,20,22,38,V i,j分别为270,13,99,54,0,0;i=17,j=0,14,16,17,21,39,V i,j分别为153,137,0,0,162,0;i=18,j=1,12,13,18,19,40,V i,j分别为161,151,0,241,144,0;i=19,j=0,1,7,8,10,41,V i,j分别为0,0,118,144,0,0;i=20,j=0,3,9,11,22,42,V i,j分别为265,81,90,144,228,0;i=21,j=1,5,16,20,21,43,V i,j分别为64,46,266,9,18,0;i=22,j=0,12,13,17,44,V i,j分别为72,189,72,257,0;i=23,j=1,2,10,18,45,V i,j分别为180,0,0,165,0;i=24,j=0,3,4,11,22,46,V i,j分别为236,199,0,266,0,0;i=25,j=1,6,7,14,47,V i,j分别为205,0,0,183,0;i=26,j=0,2,4,15,48,V i,j分别为0,0,0,277,0;i=27,j=1,6,8,49,V i,j分别为45,36,72,0;i=28,j=0,4,19,21,50,V i,j分别为275,0,155,62,0;i=29,j=1,14,18,25,51,V i,j分别为0,180,0,42,0;i=30,j=0,10,13,24,52,V i,j分别为0,90,252,173,0;i=31,j=1,7,22,25,53,V i,j分别为144,144,166,19,0;i=32,j=0,12,14,24,54,V i,j分别为0,211,36,162,0;i=33,j=1,2,11,21,55,V i,j分别为0,0,76,18,0;i=34,j=0,7,15,17,56,V i,j分别为197,0,108,0,0;i=35,j=1,6,12,22,57,V i,j分别为199,278,0,205,0;i=36,j=0,14,15,18,58,V i,j分别为216,16,0,0,0;i=37,j=1,13,23,59,V i,j分别为72,144,0,0;i=38,j=0,9,10,12,60,V i,j分别为190,0,0,0,0;i=39,j=1,3,7,19,61,V i,j分别为153,0,165,117,0;i=40,j=0,8,17,62,V i,j分别为216,144,2,0;i=41,j=1,3,9,18,63,V i,j分别为0,0,0,183,0;i=42,j=0,4,24,64,V i,j分别为27,0,35,0;i=43,j=1,16,18,25,65,V i,j分别为52,243,0,270,0;i=44,j=0,7,9,22,66,V i,j分别为18,0,0,57,0;i=45,j=1,6,10,67,V i,j分别为168,0,144,0。
- 根据权利要求21至26任一项所述的方法,所述Z为9,18,36,72,144,288中之一。
- 一种装置,包括编码器和确定单元,所述确定单元用于确定对输入序列编码的扩展因子Z,所述编码器用于基于低密度奇偶校验LDPC矩阵H对所述输入序列进行编码得到LDPC码;其中,所述H的基矩阵包括非零元素(i,j),其中,i为行号,j为列号,所 述非零元素(i,j)表示该元素被Z*Z大小的循环置换矩阵替换,所述循环置换矩阵对应于Z*Z大小的单位矩阵的向右P i,j次循环移位,P i,j=mod(V i,j,Z),Z为扩展因子,所述非零元素(i,j)及其对应的值V i,j如下::i=0,j=0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23,V i,j分别为211,198,188,186,219,4,29,144,116,216,115,233,144,95,216,73,261,1,0;i=1,j=0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24,V i,j分别为179,162,223,256,160,76,202,117,109,15,72,152,158,147,156,119,0,0;i=2,j=0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25,V i,j分别为258,167,220,133,243,202,218,63,0,3,74,229,0,216,269,200,234,0,0;i=3,j=0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25,V i,j分别为187,145,166,108,82,132,197,41,162,57,36,115,242,165,0,113,108,1,0;i=4,j=0,1,26,V i,j分别为246,235,0。
- 根据权利要求28所述的装置,其中,所述编码器用于基于低密度奇偶校验LDPC矩阵H对所述输入序列进行编码得到LDPC码,包括:对输入序列c={c 0,c 1,c 2,...,c K-1}进行编码得到输出序列d={d 0,d 1,d 2,...,d N-1},其中,K和N均为正整数;所述输出序列d包括所述输入序列c中K 0个比特和校验序列w中的校验比特,K 0为整数,且0<K 0≤K,校验序列w的长度为N-K 0;
- 根据权利要求29所述的装置,其特征在于,K 0=K-2·Z。
- 一种装置,包括译码器和获取单元,所述获取单元用于获取低密度奇偶校验LDPC码的软值序列和扩展因子Z,所述译码器用于基于LDPC矩阵H对所述LDPC码进行译码得到信息比特序列;其中,所述H的基矩阵包括非零元素(i,j),其中,i为行号,j为列号,所述非零元素(i,j)表示该元素被Z*Z大小的循环置换矩阵替换,所述循环置换矩阵对应于Z*Z大小的单位矩阵的向右P i,j次循环移位,P i,j=mod(V i,j,Z),Z为扩展因子,所述非零元素(i,j)及其对应的值V i,j如下:i=0,j=0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23,V i,j分别为211,198,188,186,219,4,29,144,116,216,115,233,144,95,216,73,261,1,0;i=1,j=0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24,V i,j分别为179,162,223,256,160,76,202,117,109,15,72,152,158,147,156,119,0,0;i=2,j=0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25,V i,j分别为258,167,220,133,243,202,218,63,0,3,74,229,0,216,269,200,234,0,0;i=3,j=0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25,V i,j分别为187,145,166,108,82,132,197,41,162,57,36,115,242,165,0,113,108,1,0;i=4,j=0,1,26,V i,j分别为246,235,0。
- 根据权利要求28至31任一项所述的装置,其特征在于,所述H的基矩阵为m行n列的矩阵,m≤46,n≤68。
- 根据权利要求32所述的装置,其特性在于,所述H的基矩阵还包括以下非零元素(i,j),其对应的值V i,j如下:i=5,j=0,1,3,12,16,21,22,27,V i,j分别为261,181,72,283,254,79,144,0;i=6,j=0,6,10,11,13,17,18,20,28,V i,j分别为80,144,169,90,59,177,151,108,0;i=7,j=0,1,4,7,8,14,29,V i,j分别为169,189,154,184,104,164,0;i=8,j=0,1,3,12,16,19,21,22,24,30,V i,j分别为54,0,252,41,98,46,15,230,54,0;i=9,j=0,1,10,11,13,17,18,20,31,V i,j分别为162,159,93,134,45,132,76,209,0;i=10,j=1,2,4,7,8,14,32,V i,j分别为178,1,28,267,234,201,0;i=11,j=0,1,12,16,21,22,23,33,V i,j分别为55,23,274,181,273,39,26,0;i=12,j=0,1,10,11,13,18,34,V i,j分别为225,162,244,151,238,243,0;i=13,j=0,3,7,20,23,35,V i,j分别为231,0,216,47,36,0;i=14,j=0,12,15,16,17,21,36,V i,j分别为0,186,253,16,0,79,0;i=15,j=0,1,10,13,18,25,37,V i,j分别为170,0,183,108,68,64,0;i=16,j=1,3,11,20,22,38,V i,j分别为270,13,99,54,0,0;i=17,j=0,14,16,17,21,39,V i,j分别为153,137,0,0,162,0;i=18,j=1,12,13,18,19,40,V i,j分别为161,151,0,241,144,0;i=19,j=0,1,7,8,10,41,V i,j分别为0,0,118,144,0,0;i=20,j=0,3,9,11,22,42,V i,j分别为265,81,90,144,228,0;i=21,j=1,5,16,20,21,43,V i,j分别为64,46,266,9,18,0;i=22,j=0,12,13,17,44,V i,j分别为72,189,72,257,0;i=23,j=1,2,10,18,45,V i,j分别为180,0,0,165,0;i=24,j=0,3,4,11,22,46,V i,j分别为236,199,0,266,0,0;i=25,j=1,6,7,14,47,V i,j分别为205,0,0,183,0;i=26,j=0,2,4,15,48,V i,j分别为0,0,0,277,0;i=27,j=1,6,8,49,V i,j分别为45,36,72,0;i=28,j=0,4,19,21,50,V i,j分别为275,0,155,62,0;i=29,j=1,14,18,25,51,V i,j分别为0,180,0,42,0;i=30,j=0,10,13,24,52,V i,j分别为0,90,252,173,0;i=31,j=1,7,22,25,53,V i,j分别为144,144,166,19,0;i=32,j=0,12,14,24,54,V i,j分别为0,211,36,162,0;i=33,j=1,2,11,21,55,V i,j分别为0,0,76,18,0;i=34,j=0,7,15,17,56,V i,j分别为197,0,108,0,0;i=35,j=1,6,12,22,57,V i,j分别为199,278,0,205,0;i=36,j=0,14,15,18,58,V i,j分别为216,16,0,0,0;i=37,j=1,13,23,59,V i,j分别为72,144,0,0;i=38,j=0,9,10,12,60,V i,j分别为190,0,0,0,0;i=39,j=1,3,7,19,61,V i,j分别为153,0,165,117,0;i=40,j=0,8,17,62,V i,j分别为216,144,2,0;i=41,j=1,3,9,18,63,V i,j分别为0,0,0,183,0;i=42,j=0,4,24,64,V i,j分别为27,0,35,0;i=43,j=1,16,18,25,65,V i,j分别为52,243,0,270,0;i=44,j=0,7,9,22,66,V i,j分别为18,0,0,57,0;i=45,j=1,6,10,67,V i,j分别为168,0,144,0。
- 根据权利要求28至33任一项所述的装置,所述Z为9,18,36,72,144,288中之一。
- 根据权利要求28至30,32至34任一项所述的装置,还包括:用于对编码后得到的LDPC码进行速率匹配的器件;用于对所述速率匹配后的LDPC码进行交织的器件;用于对所述交织后的LDPC码进行调制的器件。
- 根据权利要求31至34任一项所述的装置,还包括:解调器,用于对信号进行解调;解交织器,用于对所述解调后的信号进行解交织;解速率匹配器,用于对所述解交织后的信号进行解速率匹配得到所述LDPC码的软值序列。
- 一种终端,其特征在于,包括如权利要求28至36任一项所述的装置以及收发机。
- 一种基站,其特征在于,包括如权利要求28至36任一项所述的装置以及收发机。
- 一种通信系统,其特征在于包括如权利要求37所述的终端以及如权利要求38所述的基站。
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