WO2019000903A1 - 显示装置以及供电电路和供电方法 - Google Patents

显示装置以及供电电路和供电方法 Download PDF

Info

Publication number
WO2019000903A1
WO2019000903A1 PCT/CN2018/072063 CN2018072063W WO2019000903A1 WO 2019000903 A1 WO2019000903 A1 WO 2019000903A1 CN 2018072063 W CN2018072063 W CN 2018072063W WO 2019000903 A1 WO2019000903 A1 WO 2019000903A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
delay
power supply
sub
voltage
Prior art date
Application number
PCT/CN2018/072063
Other languages
English (en)
French (fr)
Inventor
韩新斌
王欣
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/064,612 priority Critical patent/US11289020B2/en
Publication of WO2019000903A1 publication Critical patent/WO2019000903A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • Embodiments of the present disclosure relate to a display device and a power supply circuit and a power supply method.
  • the power-off protection is generally performed.
  • the display device can protect the data being processed from loss or function without damage by power-off protection.
  • this power-off protection may cause subsequent detection of the display device to be impossible.
  • At least one embodiment provides a power supply circuit including: a control sub-circuit configured to provide a first preset voltage and a second preset voltage, and output the first preset voltage To the first power supply end; the delay sub-circuit is configured to delay the second preset voltage, and output the delayed second preset voltage to the second power supply end.
  • control sub-circuit is a power chip
  • the power chip includes a first output end and a second output end, where the first output end is used to provide a first preset voltage, The second output terminal is configured to provide a second preset voltage, wherein the first output end is used as the first power supply end
  • the delay sub-circuit includes an input end and an output end, and the input end is The second output end of the power chip is connected, and the output end of the delay sub-circuit is connected to the second power supply end, and the second preset voltage provided by the power chip is delayed and output to the a second power supply end; wherein the first power supply end is connected to the first power receiving end of the display screen, and the second power supply end is connected to the second power receiving end of the display screen.
  • the delay sub-circuit includes: a first switch tube, a control end of the first switch tube is connected to an input end of the delay sub-circuit, the first switch tube The first end is grounded; the second switch is connected, the first end of the second switch is connected to the input end of the delay sub-circuit, and the second end of the second switch is connected to the delay sub-circuit The output ends are connected; the voltage dividing and delay sub-circuit, the first end of the voltage dividing and delay sub-circuit is connected to the input end of the delay sub-circuit, and the second part of the voltage dividing and delay sub-circuit The end is connected to the second end of the first switch tube, and the voltage dividing end of the voltage dividing and delay sub-circuit is connected to the control end of the second switch tube; the delay of the voltage dividing and delay sub-circuit The terminal is connected to the second end of the second switch and is connected to the output of the delay sub-circuit.
  • the first switching transistor is an NMOS transistor and the second switching transistor is a PMOS transistor.
  • the first switch in the second pre-
  • the voltage-dividing and delay sub-circuit is configured to divide the second preset voltage provided by the power chip after the first switch tube is turned on to generate a voltage divider Signaling, and outputting a voltage dividing signal to the second switching tube through the voltage dividing end to drive the second switching tube to be turned on; after the second switching tube is turned on, to the second preset voltage Delay output is performed.
  • the voltage dividing and delay sub-circuit includes: a first resistor, the first end of the first resistor is used as the second end of the voltage dividing and delay sub-circuit, a second end of the first resistor is connected to a voltage dividing end of the voltage dividing and delay sub-circuit; and a second resistor is used as the voltage dividing and delay sub-circuit of the second resistor The first end of the second resistor is connected to the voltage dividing end of the voltage dividing and delay sub-circuit.
  • the voltage dividing and delay sub-circuit further includes: a first capacitor, the first end of the first capacitor is connected to the voltage dividing end of the voltage dividing and delay sub-circuit The second end of the first capacitor is used as a delay end of the voltage dividing and delay sub-circuit.
  • the voltage dividing and delay sub-circuit further includes: a second capacitor, the first end of the second capacitor is connected to the first end of the second resistor, the A second end of the second capacitor is coupled to the second end of the second resistor.
  • the preset delay time of the delay sub-circuit is R1*C1*Ln((ELVDD_IN-ELVDD_OUT)/ELVDD_IN), where R1 is the first resistance The resistance value, C1 is the capacitance value of the second capacitor, ELVDD_IN is the voltage at the input end of the delay sub-circuit, ELVDD_OUT is the voltage at the output end of the delay sub-circuit, and Ln is the natural logarithm.
  • At least one embodiment further provides a display device including the above-described power supply circuit.
  • At least one embodiment further provides a power supply method, including: outputting a first preset voltage provided by a control sub-circuit to a first power supply terminal; and providing a second preset provided by the control sub-circuit The voltage is delayed by the delay sub-circuit to output the delayed second preset voltage to the second power supply end.
  • control sub-circuit is a power chip, wherein a first preset voltage is provided by the first output end of the power chip, and the first chip is provided by the power chip The preset voltage is output to the first power supply terminal; the second output terminal of the power chip is used to provide a second preset voltage, and the second preset voltage is outputted with a delay to output the delay The second preset voltage is output to the second power supply terminal.
  • the delay sub-circuit includes a first switch tube and a second switch tube, wherein delaying the second preset voltage provided by the control sub-circuit via the delay sub-circuit includes: Acquiring a second preset voltage provided by the control sub-circuit, wherein the first switch tube is turned on under the driving of the second preset voltage; after the first switch tube is turned on, The second preset voltage provided by the power chip is divided to generate a divided voltage signal, wherein the second switch tube is turned on under the driving of the divided voltage signal; after the second switch tube is turned on And delay outputting the second preset voltage.
  • FIG. 1 is a schematic diagram of a power supply circuit in accordance with an embodiment of the present disclosure:
  • FIG. 2 is a schematic diagram of a power supply circuit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a power supply circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a delay sub-circuit in accordance with an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a delay sub-circuit in accordance with an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a power supply circuit in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a waveform diagram of a first power source and a second power source of a power chip according to an embodiment of the present disclosure; wherein the second power source is pulled up to 0V or higher;
  • FIG. 8 is a schematic diagram of a power supply circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a flow chart of a power supply method in accordance with an embodiment of the present disclosure.
  • FIG. 10 is a time delay flowchart of a power supply method according to an embodiment of the present disclosure.
  • FIG. 11 is a time delay flowchart of a power supply method in accordance with an embodiment of the present disclosure.
  • a power supply circuit for a display screen is shown in FIG. 1 and includes a control sub-circuit, such as a power chip 101.
  • the power chip 101 generates a first predetermined voltage ELVDD' and a second predetermined voltage ELVSS' for driving respective pixel circuits in the display screen.
  • ELVSS' will be powered up after ELVDD' is powered up, but the power-on time of ELVDD' and ELVSS' is small.
  • the power chip will have two pulse currents during the voltage jump. Due to external interference, the two pulse currents may form a large pulse current; the ELVSS generated by the power chip will be Pull up to 0V or more. When a large current is generated in the power chip or ELVSS' is pulled up to 0V or higher, the power chip recognizes that it is abnormal, thereby performing power-off protection. However, the power-off protection during the power-on process may cause subsequent detection of the display to be impossible.
  • At least one embodiment of the present disclosure provides a schematic diagram of a power supply circuit as shown in FIG. 2, for example, for powering a display screen of a display device, such as an organic light emitting diode (OLED) display device, corresponding
  • the display is an OLED display (or display panel).
  • the power supply circuit includes a control sub-circuit 201 and a delay sub-circuit 202.
  • the control sub-circuit 201 is configured to provide a first preset voltage and a second preset voltage, and output the first preset voltage to the first power supply terminal P1;
  • the delay sub-circuit 202 is configured to be the second preset The voltage is delayed, and the delayed second preset voltage is output to the second power supply terminal P2.
  • control sub-circuit 201 may be implemented as a power chip, which may be a semiconductor integrated circuit chip.
  • the power chip 301 includes a first output terminal OUT1 and a second output terminal OUT2.
  • the first output terminal OUT1 is used to provide a first preset voltage
  • the second output terminal OUT2 is used to provide a second preset.
  • the delay sub-circuit includes an input terminal S1 and an output terminal S2, and the input terminal S1 thereof is connected to the second output terminal OUT2 of the power chip, and the delay sub-circuit
  • the output terminal S2 is connected to the second power supply terminal P2 to delay the second preset voltage provided by the power chip and output to the second power supply terminal P1.
  • the first power supply terminal P1 is connected to the first power receiving terminal X1 of the display screen 300, and the second power supply terminal P2 is connected to the second power receiving terminal X2 of the display screen 300.
  • the power supply circuit of the embodiment of the present disclosure can effectively avoid the power-off protection caused by the high current or the voltage being pulled up during the power-on process of the power chip, and prevent the power-off protection from being prevented while preventing the display screen from being damaged, so as to ensure the normal detection of the subsequent detection. get on.
  • the circuit has a simple structure and good compatibility.
  • the power chip 301 includes a first output terminal OUT1 and a second output terminal OUT2.
  • the power chip 301 provides a first preset voltage ELVSS through the first output terminal OUT1, and the power chip 301 is provided through the second output terminal OUT2.
  • a second preset voltage ELVDD wherein the first output terminal OUT1 of the power chip 301 is connected to the first power receiving terminal X1 of the display screen 300 to supply the first preset voltage ELVSS provided by the power chip 301 to the first power source
  • the time sub-circuit 202 is configured to delay output the second preset voltage ELVDD provided by the power chip 301 to delay the second preset voltage ELVDD provided by the power chip 301 for a preset delay time and then supply the second power receiving end.
  • the delay output sub-circuit 202 is connected between the second output terminal OUT2 of the power chip 301 and the second power receiving terminal X2 of the display screen 300, so that the second preset voltage ELVDD can be delayed by a preset delay time, for example, after 20 ms.
  • the second power supply terminal X2 of the display screen 300 is connected between the second output terminal OUT2 of the power chip 301 and the second power receiving terminal X2 of the display screen 300, so that the second preset voltage ELVDD can be delayed by a preset delay time, for example, after 20 ms.
  • the second preset voltage ELVDD can be powered on after the first preset voltage ELVSS is stabilized, that is, the second preset voltage ELVDD can be After the first preset voltage ELVSS provided to the first power receiving terminal X1 is smoothed, it is supplied to the second power receiving terminal X2, so that the power-on between the second preset voltage ELVDD and the first preset voltage ELVSS can be increased.
  • the time difference is to avoid the phenomenon that the power failure protection occurs due to the ELVSS being pulled high, and the power chip 301 is prevented from forming an excessive pulse current, and the power failure protection during the power-on process is prevented as much as possible to prevent the damage of the display screen, and the subsequent detection is ensured. Work properly.
  • the power chip 301 may further include a power conversion unit, and the power conversion unit may output the first preset voltage through the first output terminal OUT1 after converting the second preset voltage ELVDD to the first preset voltage ELVSS.
  • ELVSS further outputs a second preset voltage ELVDD through the second output terminal OUT2. Therefore, the second preset voltage ELVDD and the first preset voltage ELVSS may be sequentially generated, but since the conversion time of the power conversion unit is short, the second preset voltage ELVDD and the first preset voltage ELVSS may also be regarded as basic. Produced simultaneously.
  • the delay sub-circuit 202 includes a first switch tube 401, a second switch tube 402, a voltage dividing and delay sub-circuit 403.
  • the control end of the first switch 401 is connected to the input S1 of the delay sub-circuit 202, the first end of the first switch 401 is grounded; the first end of the second switch 402 and the input S1 of the delay sub-circuit 202 Connected, the second end of the second switch 402 is connected to the output S2 of the delay sub-circuit 202; the first end of the voltage dividing and delay sub-circuit 403 is connected to the input S1 of the delay sub-circuit 202, and the voltage divider is The second end of the delay sub-circuit 403 is connected to the second end of the first switch tube 401, and the voltage dividing end of the voltage dividing and delay sub-circuit 403 is connected to the control end of the second switch tube 402; the voltage divider and the delay period
  • the first switch tube includes three terminals, which are respectively a control end, a first end and a second end; the second switch tube also includes three terminals, which are respectively a control end, a first end and a second end;
  • the delay sub-circuit 403 includes four terminals, which are a first end, a second end, a voltage dividing end, and a delay end.
  • the delay sub-circuit 202 includes a first switch tube 401, a second switch tube 402, and a voltage dividing and delay sub-circuit 403.
  • the output terminal S2 of the delay sub-circuit 202 is connected to the second power receiving terminal X2 of the display screen 300, that is, the first switch tube.
  • the control end of the 401 is connected to the second output end OUT2 of the power chip 301, the first end of the first switch tube 401 is grounded; the first end of the second switch tube 402 is connected to the second output end OUT2 of the power chip 301;
  • the first end of the delay sub-circuit 403 is connected to the second output end OUT2 of the power chip 301, and the second end of the voltage dividing and delay sub-circuit 403 is connected to the second end of the first switch tube 401, and the voltage is divided and extended.
  • the voltage dividing end of the time sub-circuit 403 is connected to the control end of the second switch tube 402, and the delay end of the voltage dividing and delay sub-circuit 403 is connected to the second end of the second switch tube 402 for use with the display screen 300.
  • the second power receiving end X2 is connected.
  • the first switch 401 is turned on by the second preset voltage ELVDD, and the voltage dividing and delay sub-circuit 403 is configured to perform the second preset voltage ELVDD provided by the power chip 301 after the first switch 401 is turned on. Dividing to generate a divided voltage signal, and outputting a divided voltage signal to the second switching transistor 402 through the voltage dividing end to drive the second switching transistor 402 to be turned on, and to the second preset voltage ELVDD after the second switching transistor 402 is turned on Delay output is performed.
  • the voltage dividing and delay sub-circuit 403 includes a first resistor and a second resistor, and the first end of the first resistor serves as a second end of the voltage dividing and delay sub-circuit, the first resistor The second end is connected to the voltage dividing end of the voltage dividing and delay sub-circuit; the first end of the second resistor serves as the first end of the voltage dividing and delay sub-circuit, and the second end of the second resistor and the voltage dividing and delay The voltage dividing ends of the subcircuits are connected.
  • the first resistance is R1 and the second resistance is R2. That is, one end of the first resistor R1 is connected to the second end of the first switching transistor 401 (such as Q1); one end of the second resistor R2 is connected to the second output terminal OUT2 of the power chip 201, and the second resistor R2 is another. One end is connected to the other end of the first resistor R1 and has a first node, and the first node is connected to the control end of the second switch tube 402 (such as Q2).
  • the voltage dividing and delay sub-circuit 403 further includes a first capacitor and a second capacitor, the first end of the first capacitor is connected to the voltage dividing end of the voltage dividing and delay sub-circuit, and the second end of the first capacitor is used a delay end of the voltage dividing and delay sub-circuit; a first end of the second capacitor is coupled to the first end of the second resistor, and a second end of the second capacitor is coupled to the second end of the second resistor.
  • the first capacitor is C1
  • one end of the first capacitor C1 is connected to the other end of the first resistor R1
  • the other end of the first capacitor C1 is connected to the second end of the second switch transistor Q2 and has The second node is for connecting to the second power receiving end X2 of the display screen 300.
  • the second capacitor is C2, and the second capacitor C2 is connected in parallel with the second resistor R2.
  • the first resistor R1 and the second resistor R2 can divide the second preset voltage ELVDD, and the first resistor R1 and the first capacitor C1 can form an RC delay sub-unit to set the second preset voltage ELVDD. Delay preset time output.
  • the first switch tube Q1 may be an NMOS tube
  • the second switch tube Q2 may be a PMOS tube.
  • the implementation of the present disclosure is not limited thereto.
  • the second end of the first switch tube Q1 is the drain of the NMOS transistor, that is, the D pole
  • the first end of the first switch tube Q1 is the source of the NMOS tube, that is, the S pole
  • the control end of the first switch tube Q1 is the NMOS tube.
  • the gate is the G pole, the NMOS transistor can be turned on under the driving of the second preset voltage ELVDD; the control end of the second switching transistor Q2 is the gate of the PMOS transistor, that is, the G pole, and the first end of the second switching transistor Q2 is The source of the PMOS transistor is the S pole, and the second end of the second switching transistor Q2 is the drain of the PMOS transistor, that is, the D pole.
  • the preset delay time of the second preset voltage ELVDD delay output is related to the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1.
  • the preset delay time is R1*C1*Ln((ELVDD_IN-ELVDD_OUT)/ELVDD_IN), where R1 is the resistance value of the first resistor, C1 is the capacitance value of the first capacitor, and ELVDD_IN is the delay sub-circuit 403.
  • the voltage at the input terminal, ELVDD_OUT is the voltage at the output of delay sub-circuit 403, and Ln is the natural logarithm, that is, the logarithm of e.
  • the power supply chip 301 When the power supply chip 301 outputs the second preset voltage ELVDD through the second output terminal OUT2, if the first switch transistor Q1 is not turned on, the source voltage of the second switch transistor Q2 is equal to the second preset voltage ELVDD, and the second The gate voltage of the switching transistor Q2 is pulled up to the second predetermined voltage ELVDD by the second resistor R2, the gate voltage of the second switching transistor Q2 is equal to the source voltage, the second switching transistor Q2 is turned off, and the second switching transistor Q2 is The output of the drain delay sub-circuit 403 (such as Y2) has no output.
  • the drain delay sub-circuit 403 such as Y2
  • the gate voltage of the second switching transistor Q2 is smaller than the second voltage due to the voltage division of the second resistor R2 and the first resistor R1.
  • the source voltage of the switching transistor Q2 is turned on, and the second switching transistor Q2 is turned on.
  • the second preset voltage ELVDD is charged to the RC circuit formed by the first capacitor C1 and the first resistor R1 through the second switch Q2, and the drain of the second switch Q2 is filled when the RC circuit is full.
  • the output terminal (such as Y2) of the extreme delay sub-circuit 403 outputs a second preset voltage ELVDD to the second power receiving terminal X2 of the display screen 300.
  • the delay can be approximately R1*C1*Ln((ELVDD_IN-ELVDD_OUT)/ELVDD_IN).
  • the power-on time difference between the second preset voltage ELVDD and the first preset voltage ELVSS can be increased, thereby avoiding power-off due to the ELVSS being pulled high (the waveform of the ELVSS pull-up is as shown in FIG. 7) Protection phenomenon, and prevent the power chip from forming excessive pulse current, avoiding the power failure protection during the power-on process while preventing the display from being damaged, and ensuring the normal operation of the subsequent detection.
  • the power supply circuit of the display screen further includes a driving power supply chip 801, and the driving power supply chip 801 can output the driving power source VSP under the control of the driving enable signal VSP_EN to drive The power supply VSP supplies power to the drive chip 802 of the display.
  • the first output end of the power chip is connected to the first power receiving end of the display screen to supply the first preset voltage provided by the power chip to the first power receiving end
  • the second output end of the power chip The output end of the delay sub-circuit is connected to the second power receiving end of the display screen, so that the second preset voltage provided by the power chip is delayed for a preset delay time and then supplied to the second power receiving end, thereby effectively avoiding the power supply. Power-off protection caused by high current or voltage being pulled up during chip power-on, and to prevent damage to the display while avoiding power-off protection during power-on, ensuring normal operation of subsequent tests.
  • the circuit has a simple structure and good compatibility.
  • a display device comprising the power supply circuit of the above embodiment, such as an OLED display device, comprising a display screen comprising a plurality of sub-pixel units arranged in an array
  • Each of the sub-pixel units includes a pixel circuit
  • the pixel circuit includes an OLED device that is applied with the second predetermined voltage ELVDD and the first predetermined voltage ELVSS via the control of the pixel circuit, and emits light of a corresponding gray scale according to the data voltage.
  • the display device of the embodiment of the present disclosure can effectively avoid the power-off protection caused by the large current or the voltage being pulled up during the power-on process of the power chip, and prevent the display screen from being damaged while avoiding the occurrence of power-on. Power-off protection to ensure the normal operation of subsequent tests.
  • the embodiment of the present disclosure further provides a power supply method, for example, for powering the display screen.
  • the power supply circuit of the display screen provided by the embodiment of the present disclosure is corresponding to the power supply circuit of the display screen provided by the foregoing embodiment. Therefore, the implementation manner of the power supply circuit of the foregoing display screen is also applicable to the power supply method of the display screen provided by this embodiment. It will not be described in detail in this embodiment.
  • the power supply method includes the following steps:
  • Step S901 outputting a first preset voltage provided by the control sub-circuit to the first power supply end;
  • Step S902 the second preset voltage provided by the control sub-circuit is delayed by the delay sub-circuit to output the delayed second preset voltage to the second power supply end.
  • control sub-circuit is a power chip, wherein the first output terminal of the power chip is used to provide a first preset voltage, and the first preset voltage provided by the power chip is output to the first power supply terminal;
  • the output terminal provides a second preset voltage, and performs a delay output on the second preset voltage to output the second preset voltage after the delay output to the second power supply end.
  • the first preset voltage is provided by the first output end of the power chip, and the first preset voltage provided by the power chip is supplied to the first power receiving end of the display screen (step S1001);
  • the second output end of the power chip provides a second preset voltage, and delays output of the second preset voltage provided by the power chip (step S1002); delays the second preset voltage provided by the power chip by a preset delay After the time, the second power receiving end of the display screen is supplied (step S1003).
  • the delay output is performed by the delay sub-circuit 403, and the delay sub-circuit 403 includes a first switch tube and a second switch tube, as shown in FIG.
  • the preset voltage for delay output includes:
  • S1101 Obtain a second preset voltage provided by the control sub-circuit, wherein the first switch tube is turned on under the driving of the second preset voltage;
  • At least one embodiment of the present disclosure provides a first predetermined voltage through a first output end of the power chip, and supplies a first preset voltage provided by the power chip to the first power receiving end of the display screen, and passes through the power chip
  • the second output terminal provides a second preset voltage, and performs a delay output on the second preset voltage provided by the power chip to delay the second preset voltage provided by the power chip to the display screen after a preset delay time.
  • the second power receiving end can effectively avoid the power-off protection caused by the large current or the voltage being pulled up during the power-on process of the power chip, and prevent the power-off protection during the power-on process while preventing the display from being damaged, so as to ensure the normal detection of the subsequent detection. get on.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示装置以及供电电路（200）和供电方法。供电电路（200）包括控制子电路（201）和延时子电路（202）。控制子电路（201）被配置为提供第一预设电压（ELVSS）和第二预设电压（ELVDD），并将第一预设电压（ELVSS）输出至第一供电端（P1）；延时子电路（202）被配置为对第二预设电压（ELVDD）进行延时，并将延时后的第二预设电压（ELVDD）输出至第二供电端（P2）。

Description

显示装置以及供电电路和供电方法
本申请要求于2017年6月30日递交的中国专利申请第201710525756.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示装置以及供电电路和供电方法。
背景技术
显示装置发生漏电或短路故障时，一般会进行断电保护。显示装置可通过断电保护使得正在处理的数据不丢失或者功能不损坏。但是，该断电保护会导致后续对显示装置的检测无法进行。
发明内容
根据本公开的一方面，至少一个实施例提供了一种供电电路，包括：控制子电路，被配置为提供第一预设电压和第二预设电压，并将所述第一预设电压输出至第一供电端；延时子电路，被配置为对所述第二预设电压进行延时，并将延时后的所述第二预设电压输出至第二供电端。
此外，根据本公开的一个实施例，所述控制子电路为电源芯片，所述电源芯片包括第一输出端和第二输出端，所述第一输出端用于提供第一预设电压，所述第二输出端用于提供第二预设电压，其中，将所述第一输出端作为所述第一供电端；所述延时子电路包括输入端和输出端，所述输入端与所述电源芯片的第二输出端相连，所述延时子电路的输出端用于与所述第二供电端相连，以将所述电源芯片提供的所述第二预设电压延时后输出至第二供电端；其中，所述第一供电端与显示屏的第一电源接收端相连，所述第二供电端与显示屏的第二电源接收端相连。
此外，根据本公开的一个实施例，所述延时子电路包括：第一开关管，所述第一开关管的控制端与所述延时子电路的输入端相连，所述第一开关管的第一端接地；第二开关管，所述第二开关管的第一端与所述延时子电路的输入端相连，所述第二开关管的第二端与所述延时子电路的输出端相连；分 压及延时子电路，所述分压及延时子电路的第一端与所述延时子电路的输入端相连，所述分压及延时子电路的第二端与所述第一开关管的第二端相连，所述分压及延时子电路的分压端与所述第二开关管的控制端相连；所述分压及延时子电路的延时端与所述第二开关管的第二端相连后连接至所述延时子电路的输出端。
此外，根据本公开的一个实施例，所述第一开关管为NMOS管，所述第二开关管为PMOS管。
此外，根据本公开的一个实施例，在将所述控制子电路提供的第二预设电压输入至所述延时子电路的输入端的情况下，所述第一开关管在所述第二预设电压的驱动下导通；所述分压及延时子电路用于在所述第一开关管导通后对所述电源芯片提供的所述第二预设电压进行分压以生成分压信号，并通过所述分压端输出分压信号至所述第二开关管以驱动所述第二开关管导通；所述第二开关管在导通后，对所述第二预设电压进行延时输出。
此外，根据本公开的一个实施例，所述分压及延时子电路包括：第一电阻，将所述第一电阻的第一端作为所述分压及延时子电路的第二端，所述第一电阻的第二端与所述分压及延时子电路的分压端相连；第二电阻，将所述第二电阻的第一端作为所述分压及延时子电路的第一端，所述第二电阻的第二端与所述分压及延时子电路的分压端相连。
此外，根据本公开的一个实施例，所述分压及延时子电路还包括：第一电容，所述第一电容的第一端与所述分压及延时子电路的分压端相连，将所述第一电容的第二端作为所述分压及延时子电路的延时端。
此外，根据本公开的一个实施例，所述分压及延时子电路还包括：第二电容，所述第二电容的第一端与所述第二电阻的第一端连接，所述第二电容的第二端与所述第二电阻的第二端连接。
此外，根据本公开的一个实施例，其中，所述延时子电路的预设延时时间为R1*C1*Ln((ELVDD_IN-ELVDD_OUT)/ELVDD_IN)，其中，R1为所述第一电阻的电阻值，C1为所述第二电容的电容值，ELVDD_IN为所述延时子电路的输入端的电压，ELVDD_OUT为所述延时子电路的输出端的电压，Ln为自然对数。
根据本公开的另一方面，至少一个实施例还提供了一种显示装置，包括上述供电电路。
根据本公开的另一方面，至少一个实施例还提供了一种供电方法，包括：将控制子电路提供的第一预设电压输出至第一供电端；将控制子电路提供的第二预设电压经延时子电路进行延时，以将所述延时后的所述第二预设电压输出至第二供电端。
此外，根据本公开的一个实施例，所述控制子电路为电源芯片，其中，利用所述电源芯片的第一输出端提供第一预设电压，并将所述电源芯片提供的所述第一预设电压输出至所述第一供电端；利用所述电源芯片的第二输出端提供第二预设电压，并对所述第二预设电压进行延时输出，以将所述延时输出后的第二预设电压输出至第二供电端。
此外，根据本公开的一个实施例，所述延时子电路包括第一开关管和第二开关管，其中，将控制子电路提供的第二预设电压经延时子电路进行延时包括：获取所述控制子电路提供的第二预设电压，其中，所述第一开关管在所述第二预设电压的驱动下导通；在所述第一开关管导通后，对所述电源芯片提供的所述第二预设电压进行分压以生成分压信号，其中，所述第二开关管在所述分压信号的驱动下导通；所述第二开关管在导通后，对所述第二预设电压进行延时输出。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是根据本公开实施例的一种供电电路的示意图：
图2是根据本公开实施例的一种供电电路的示意图；
图3是根据本公开实施例的一种供电电路的示意图；
图4是根据本公开实施例的一种延时子电路的示意图；
图5是根据本公开实施例的一种延时子电路的示意图；
图6是根据本公开实施例的一种供电电路的示意图；
图7是根据本公开实施例的一种电源芯片的第一电源和第二电源的波形示意图；其中，第二电源被拉高至0V以上；
图8是根据本公开实施例的一种供电电路的示意图；
图9是根据本公开实施例的一种供电方法的流程图；
图10是根据本公开实施例的一种供电方法的延时流程图；以及
图11是根据本公开实施例的一种供电方法的延时流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，一种显示屏的供电电路如图1所示，其包括控制子电路，该控制子电路例如为电源芯片101。该电源芯片101产生第一预设电压ELVDD’和第二预设电压ELVSS’，用于驱动显示屏中的各个像素电路。根据电源芯片的设计原则，在ELVDD’上电后ELVSS’会上电，但ELVDD’与ELVSS’的上电时间相差很小。
在显示装置的显示屏上电过程中，电源芯片在电压跳变时会有两个脉冲电流，由于外界的干扰，两脉冲电流可能会形成一个大的脉冲电流；电源芯片产生的ELVSS’会被拉高至0V以上。当电源芯片出现大电流或者ELVSS’被拉高至0V以上时，电源芯片会识别判定为异常，从而进行断电保护。但是，该上电过程中的断电保护会导致后续对显示屏的检测无法进行。
下面参考附图来描述本公开实施例的显示装置以及供电电路和供电方法。
本公开的至少一个实施例提供了如图2所示的供电电路的示意图，该供 电电路200例如用于为显示装置的显示屏供电，该显示装置例如为有机发光二极管(OLED)显示装置，相应地其显示屏为OLED显示屏(或显示面板)。
如图2所示，该供电电路包括控制子电路201和延时子电路202。该控制子电路201被配置为提供第一预设电压和第二预设电压，并将第一预设电压输出至第一供电端P1；该延时子电路202被配置为对第二预设电压进行延时，并将延时后的第二预设电压输出至第二供电端P2。
这里，例如，控制子电路201可以实现为电源芯片，该电源芯片可以为半导体集成电路芯片。如图3所示，该电源芯片301包括第一输出端OUT1和第二输出端OUT2，其第一输出端OUT1用于提供第一预设电压，第二输出端OUT2用于提供第二预设电压，其中，将该第一输出端OUT1作为第一供电端P1；延时子电路包括输入端S1和输出端S2，其输入端S1与电源芯片的第二输出端OUT2相连，延时子电路的输出端S2用于与第二供电端P2相连，以将电源芯片提供的第二预设电压延时后输出至第二供电端P1。第一供电端P1与显示屏300的第一电源接收端X1相连，第二供电端P2与显示屏300的第二电源接收端X2相连。
通过本公开实施例的供电电路能够有效避免电源芯片在上电过程中大电流或者电压被拉高引起的断电保护，在防止显示屏损坏的同时尽量避免出现断电保护，确保后续检测的正常进行。该电路结构简单、具有很好的兼容性。
在一个具体的示例中，电源芯片301包括第一输出端OUT1和第二输出端OUT2，电源芯片301通过第一输出端OUT1提供第一预设电压ELVSS，电源芯片301通过第二输出端OUT2提供第二预设电压ELVDD，其中，电源芯片301的第一输出端OUT1用于与显示屏300的第一电源接收端X1相连，以将电源芯片301提供的第一预设电压ELVSS供给第一电源接收端X1；延时子电路202的输入端S1与电源芯片301的第二输出端OUT2相连，延时子电路202的输出端S2用于与显示屏300的第二电源接收端X2相连，延时子电路202用以对电源芯片301提供的第二预设电压ELVDD进行延时输出，以将电源芯片301提供的第二预设电压ELVDD延时预设延时时间后供给第二电源接收端X2。
例如，电源芯片301的第二输出端OUT2与显示屏300的第二电源接收端X2之间连接延时子电路202，从而第二预设电压ELVDD可延时预设延时时间例如20ms后供给显示屏300的第二电源接收端X2。由此，电源芯片301 在电源使能信号OLED_EN的控制下开始输出电源之后，第二预设电压ELVDD可在第一预设电压ELVSS上电平稳后再上电，即第二预设电压ELVDD可在提供至第一电源接收端X1的第一预设电压ELVSS平稳之后再提供至第二电源接收端X2，从而可加大第二预设电压ELVDD和第一预设电压ELVSS之间的上电时间差，避免因ELVSS被拉高而出现断电保护的现象，并防止电源芯片301形成过大的脉冲电流，在防止显示屏损坏的同时尽量避免上电过程中出现断电保护，确保后续检测的正常进行。
需要说明的是，电源芯片301还可包括电源转换单元，该电源转换单元可将第二预设电压ELVDD转换为第一预设电压ELVSS后，先通过第一输出端OUT1输出第一预设电压ELVSS，再通过第二输出端OUT2输出第二预设电压ELVDD。由此，第二预设电压ELVDD和第一预设电压ELVSS可先后产生，但由于电源转换单元进行转换的时间很短，第二预设电压ELVDD和第一预设电压ELVSS也可看作基本同时产生。
此外，根据本公开的一个实施例，如图4所示，延时子电路202包括：第一开关管401、第二开关管402、分压及延时子电路403。第一开关管401的控制端与延时子电路202的输入端S1相连，第一开关管401的第一端接地；第二开关管402的第一端与延时子电路202的输入端S1相连，第二开关管402的第二端与延时子电路202的输出端S2相连；分压及延时子电路403的第一端与延时子电路202的输入端S1相连，分压及延时子电路403的第二端与第一开关管401的第二端相连，分压及延时子电路403的分压端与第二开关管402的控制端相连；分压及延时子电路403的延时端与第二开关管402的第二端相连后连接至延时子电路202的输出端S2。
这里，第一开关管包括三个端子，分别为控制端、第一端和第二端；第二开关管也包括三个端子，分别为控制端、第一端和第二端；分压及延时子电路403包括四个端子，分别为第一端、第二端、分压端和延时端。例如，如图5所示，延时子电路202包括：第一开关管401、第二开关管402以及分压及延时子电路403。由于延时子电路202的输入端S1是与电源芯片301的第二输出端OUT2相连，延时子电路202的输出端S2与显示屏300的第二电源接收端X2相连，即第一开关管401的控制端与电源芯片301的第二输出端OUT2相连，第一开关管401的第一端接地；第二开关管402的第一端与电源芯片301的第二输出端OUT2相连；分压及延时子电路403的第一端与电源 芯片301的第二输出端OUT2相连，分压及延时子电路403的第二端与第一开关管401的第二端相连，分压及延时子电路403的分压端与第二开关管402的控制端相连，分压及延时子电路403的延时端与第二开关管402的第二端相连后用于与显示屏300的第二电源接收端X2相连。
第一开关管401在第二预设电压ELVDD的驱动下导通，分压及延时子电路403用于在第一开关管401导通后对电源芯片301提供的第二预设电压ELVDD进行分压以生成分压信号，并通过分压端输出分压信号至第二开关管402以驱动第二开关管402导通，以及在第二开关管402导通后对第二预设电压ELVDD进行延时输出。
在一个可选的实施例中，分压及延时子电路403包括第一电阻和第二电阻，第一电阻的第一端作为分压及延时子电路的第二端，第一电阻的第二端与分压及延时子电路的分压端相连；第二电阻的第一端作为分压及延时子电路的第一端，第二电阻的第二端与分压及延时子电路的分压端相连。
例如，在图6中，第一电阻为R1，第二电阻为R2。也就是说，第一电阻R1的一端与第一开关管401(如Q1)的第二端相连；第二电阻R2的一端与电源芯片201的第二输出端OUT2相连，第二电阻R2的另一端与第一电阻R1的另一端相连并具有第一节点，第一节点与第二开关管402(如Q2)的控制端相连。
这里，分压及延时子电路403还包括第一电容和第二电容，第一电容的第一端与分压及延时子电路的分压端相连，将第一电容的第二端作为分压及延时子电路的延时端；第二电容的第一端与第二电阻的第一端连接，第二电容的第二端与第二电阻的第二端连接。
例如，在图6中，该第一电容为C1，第一电容C1的一端与第一电阻R1的另一端相连，第一电容C1的另一端与第二开关管Q2的第二端相连并具有第二节点，第二节点用于与显示屏300的第二电源接收端X2相连。该第二电容为C2，第二电容C2与第二电阻R2并联连接。
也就是说，第一电阻R1和第二电阻R2可对第二预设电压ELVDD进行分压，第一电阻R1和第一电容C1可构成RC延时子单元，以将第二预设电压ELVDD延时预设时间输出。
可选的，在图6中的示例中，第一开关管Q1可为NMOS管，第二开关管Q2可为PMOS管，本公开的实施不限于此。第一开关管Q1的第二端为 NMOS管的漏极即D极，第一开关管Q1的第一端为NMOS管的源极即S极，第一开关管Q1的控制端为NMOS管的栅极即G极，NMOS管可在第二预设电压ELVDD的驱动下导通；第二开关管Q2的控制端为PMOS管的栅极即G极，第二开关管Q2的第一端为PMOS管的源极即S极，第二开关管Q2的第二端为PMOS管的漏极即D极。
由此可知，第二预设电压ELVDD延时输出的预设延时时间与第一电阻R1的电阻值和第一电容C1的电容值相关。其中，预设延时时间为R1*C1*Ln((ELVDD_IN-ELVDD_OUT)/ELVDD_IN)，其中，R1为第一电阻的电阻值，C1为第一电容的电容值，ELVDD_IN为延时子电路403的输入端的电压，ELVDD_OUT为延时子电路403的输出端的电压，Ln为自然对数、即是以e为底的对数。
下面结合图6，来阐述本公开上述实施例的延时子电路403的工作原理。
当电源芯片301通过第二输出端OUT2输出第二预设电压ELVDD时，第一开关管Q1未导通的情况下，第二开关管Q2的源极电压等于第二预设电压ELVDD，第二开关管Q2的栅极电压被第二电阻R2上拉至第二预设电压ELVDD，第二开关管Q2的栅极电压等于源极电压，第二开关管Q2关断，第二开关管Q2的漏极即延时子电路403的输出端(如Y2)无输出。
当第一开关管Q1的栅极的电压拉高使第一开关管Q1导通时，由于第二电阻R2和第一电阻R1的分压作用，第二开关管Q2的栅极电压小于第二开关管Q2的源极电压,第二开关管Q2开通。在第二开关管Q2开通后，第二预设电压ELVDD经过第二开关管Q2向第一电容C1和第一电阻R1构成的RC电路充电，当RC电路充满后，第二开关管Q2的漏极即延时子电路403的输出端(如Y2)输出第二预设电压ELVDD至显示屏300的第二电源接收端X2。由此，经过RC电路延时，可延时约为R1*C1*Ln((ELVDD_IN-ELVDD_OUT)/ELVDD_IN)。
由此，可加大第二预设电压ELVDD和第一预设电压ELVSS之间的上电时间差，从而避免因ELVSS被拉高(ELVSS拉高的波形图如图7所示)而出现断电保护的现象，并防止电源芯片形成过大的脉冲电流，在防止显示屏损坏的同时尽量避免上电过程中出现断电保护，确保后续检测的正常进行。
此外，根据本公开的一个实施例，如图8所示，显示屏的供电电路还包括驱动供电芯片801，驱动供电芯片801可在驱动使能信号VSP_EN的控制 下输出驱动电源VSP，以通过驱动电源VSP为显示屏的驱动芯片802供电。
通过本公开上述实施方式，电源芯片的第一输出端与显示屏的第一电源接收端相连，以将电源芯片提供的第一预设电压供给第一电源接收端，电源芯片的第二输出端通过延时子电路的输出端与显示屏的第二电源接收端相连，以将电源芯片提供的第二预设电压延时预设延时时间后供给第二电源接收端，从而能够有效避免电源芯片上电过程大电流或者电压被拉高引起的断电保护，并且在防止显示屏损坏的同时尽量避免上电过程中出现断电保护，确保后续检测的正常进行。该电路结构简单、具有很好的兼容性。
根据本公开至少一个实施例还提供了一种显示装置，包括上述实施例的供电电路，该显示装置例如为OLED显示装置，其包括显示屏，该显示屏包括多个排列为阵列的子像素单元，每个子像素单元包括像素电路，像素电路包括OLED器件，该OLED器件经由像素电路的控制被施加上述第二预设电压ELVDD和第一预设电压ELVSS，并且根据数据电压发出相应灰度的光。
通过上述的供电电路，本公开实施例的显示装置，能够有效避免电源芯片上电过程大电流或者电压被拉高引起的断电保护，并且在防止显示屏损坏的同时尽量避免上电过程中出现断电保护，确保后续检测的正常进行。
与上述实施例提供的显示屏的供电电路相对应，本公开的实施例还提供了一种供电方法，该用电方法例如用于为显示屏进行供电。由于本公开实施例提供的显示屏的供电方法与上述实施例提供的显示屏的供电电路相对应，因此在前述显示屏的供电电路的实施方式也适用于本实施例提供的显示屏的供电方法，在本实施例中不再详细描述。
根据本公开再一个实施例还提供了一种供电方法，可用于在本公开实施例的显示装置。如图9所示，该供电方法包括如下步骤：
步骤S901，将控制子电路提供的第一预设电压输出至第一供电端；
步骤S902，将控制子电路提供的第二预设电压经延时子电路进行延时，以将延时后的第二预设电压输出至第二供电端。
这里，控制子电路为电源芯片，其中，利用电源芯片的第一输出端提供第一预设电压，并将电源芯片提供的第一预设电压输出至第一供电端；利用电源芯片的第二输出端提供第二预设电压，并对第二预设电压进行延时输出，以将延时输出后的第二预设电压输出至第二供电端。
具体的，如图10所示，通过电源芯片的第一输出端提供第一预设电压， 并将电源芯片提供的第一预设电压供给显示屏的第一电源接收端(步骤S1001)；通过电源芯片的第二输出端提供第二预设电压，并对电源芯片提供的第二预设电压进行延时输出(步骤S1002)；将电源芯片提供的第二预设电压延时预设延时时间后供给显示屏的第二电源接收端(步骤S1003)。
此外，根据本公开的一个实施例，通过延时子电路403进行延时输出，延时子电路403包括第一开关管和第二开关管，如图11所示，对电源芯片提供的第二预设电压进行延时输出包括：
S1101：获取控制子电路提供的第二预设电压，其中，第一开关管在第二预设电压的驱动下导通；
S1102：在第一开关管导通后，对电源芯片提供的第二预设电压进行分压以生成分压信号，其中，第二开关管在分压信号的驱动下导通；
S1103：第二开关管在导通后，对第二预设电压进行延时输出。
本公开的至少一个实施例通过电源芯片的第一输出端提供第一预设电压，并将电源芯片提供的第一预设电压供给显示屏的第一电源接收端，并且，通过电源芯片的第二输出端提供第二预设电压，并对电源芯片提供的第二预设电压进行延时输出，以将电源芯片提供的第二预设电压延时预设延时时间后供给显示屏的第二电源接收端，从而能够有效避免电源芯片上电过程大电流或者电压被拉高引起的断电保护，在防止显示屏损坏的同时尽量避免上电过程中出现断电保护，确保后续检测的正常进行。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (13)

  1. 一种供电电路，包括：
    控制子电路，被配置为提供第一预设电压和第二预设电压，并将所述第一预设电压输出至第一供电端；
    延时子电路，被配置为对所述第二预设电压进行延时，并将延时后的所述第二预设电压输出至第二供电端。
  2. 根据权利要求1所述的供电电路，其中，所述控制子电路为电源芯片，
    所述电源芯片包括第一输出端和第二输出端，所述第一输出端用于提供第一预设电压，所述第二输出端用于提供第二预设电压，其中，将所述第一输出端作为所述第一供电端；
    所述延时子电路包括输入端和输出端，所述输入端与所述电源芯片的第二输出端相连，所述延时子电路的输出端用于与所述第二供电端相连，以将所述电源芯片提供的所述第二预设电压延时后输出至第二供电端；
    其中，所述第一供电端与显示屏的第一电源接收端相连，所述第二供电端与显示屏的第二电源接收端相连。
  3. 根据权利要求2所述的供电电路，所述延时子电路包括：
    第一开关管，所述第一开关管的控制端与所述延时子电路的输入端相连，所述第一开关管的第一端接地；
    第二开关管，所述第二开关管的第一端与所述延时子电路的输入端相连，所述第二开关管的第二端与所述延时子电路的输出端相连；
    分压及延时子电路，所述分压及延时子电路的第一端与所述延时子电路的输入端相连，所述分压及延时子电路的第二端与所述第一开关管的第二端相连，所述分压及延时子电路的分压端与所述第二开关管的控制端相连；所述分压及延时子电路的延时端与所述第二开关管的第二端相连后连接至所述延时子电路的输出端。
  4. 根据权利要求3所述的供电电路，其中，所述第一开关管为NMOS管，所述第二开关管为PMOS管。
  5. 根据权利要求3或4所述的供电电路，其中，在将所述控制子电路提供的第二预设电压输入至所述延时子电路的输入端的情况下，
    所述第一开关管在所述第二预设电压的驱动下导通；
    所述分压及延时子电路用于在所述第一开关管导通后对所述电源芯片提供的所述第二预设电压进行分压以生成分压信号，并通过所述分压端输出分压信号至所述第二开关管以驱动所述第二开关管导通；
    所述第二开关管在导通后，对所述第二预设电压进行延时输出。
  6. 根据权利要求3-5任一所述的供电电路，所述分压及延时子电路包括：
    第一电阻，将所述第一电阻的第一端作为所述分压及延时子电路的第二端，所述第一电阻的第二端与所述分压及延时子电路的分压端相连；
    第二电阻，将所述第二电阻的第一端作为所述分压及延时子电路的第一端，所述第二电阻的第二端与所述分压及延时子电路的分压端相连。
  7. 根据权利要求6所述的供电电路，所述分压及延时子电路还包括：
    第一电容，所述第一电容的第一端与所述分压及延时子电路的分压端相连，将所述第一电容的第二端作为所述分压及延时子电路的延时端。
  8. 根据权利要求6所述的供电电路，所述分压及延时子电路还包括：
    第二电容，所述第二电容的第一端与所述第二电阻的第一端连接，所述第二电容的第二端与所述第二电阻的第二端连接。
  9. 根据权利要求7所述的供电电路，其中，所述延时子电路的预设延时时间为R1*C1*Ln((ELVDD_IN-ELVDD_OUT)/ELVDD_IN)，其中，R1为所述第一电阻的电阻值，C1为所述第二电容的电容值，ELVDD_IN为所述延时子电路的输入端的电压，ELVDD_OUT为所述延时子电路的输出端的电压，Ln为自然对数。
  10. 一种显示装置，包括根据权利要求1-9中任一项所述的供电电路。
  11. 一种供电方法，包括：
    将控制子电路提供的第一预设电压输出至第一供电端；
    将控制子电路提供的第二预设电压经延时子电路进行延时，以将所述延时后的所述第二预设电压输出至第二供电端。
  12. 根据权利要求11所述的供电方法，所述控制子电路为电源芯片，其中，
    利用所述电源芯片的第一输出端提供第一预设电压，并将所述电源芯片提供的所述第一预设电压输出至所述第一供电端；
    利用所述电源芯片的第二输出端提供第二预设电压，并对所述第二预设电压进行延时输出，以将所述延时输出后的第二预设电压输出至第二供电端。
  13. 根据权利要求11所述的供电方法，所述延时子电路包括第一开关管和第二开关管，其中，将控制子电路提供的第二预设电压经延时子电路进行延时包括：
    获取所述控制子电路提供的第二预设电压，其中，所述第一开关管在所述第二预设电压的驱动下导通；
    在所述第一开关管导通后，对所述电源芯片提供的所述第二预设电压进行分压以生成分压信号，其中，所述第二开关管在所述分压信号的驱动下导通；
    所述第二开关管在导通后，对所述第二预设电压进行延时输出。
PCT/CN2018/072063 2017-06-30 2018-01-10 显示装置以及供电电路和供电方法 WO2019000903A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/064,612 US11289020B2 (en) 2017-06-30 2018-01-10 Display device, power supply circuit and power supply method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710525756.1A CN107103871B (zh) 2017-06-30 2017-06-30 显示装置以及显示屏的供电电路和供电方法
CN201710525756.1 2017-06-30

Publications (1)

Publication Number Publication Date
WO2019000903A1 true WO2019000903A1 (zh) 2019-01-03

Family

ID=59663621

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/072063 WO2019000903A1 (zh) 2017-06-30 2018-01-10 显示装置以及供电电路和供电方法

Country Status (3)

Country Link
US (1) US11289020B2 (zh)
CN (1) CN107103871B (zh)
WO (1) WO2019000903A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107103871B (zh) 2017-06-30 2019-11-22 京东方科技集团股份有限公司 显示装置以及显示屏的供电电路和供电方法
CN110544452B (zh) * 2018-05-28 2021-08-17 京东方科技集团股份有限公司 供电时序控制电路及控制方法、显示驱动电路、显示装置
CN110728961A (zh) * 2019-10-22 2020-01-24 南京熊猫电子制造有限公司 一种液晶显示器上电延时控制电路和控制方法
CN110827784A (zh) * 2019-10-24 2020-02-21 深圳市华星光电技术有限公司 一种驱动电路及其控制方法
CN113835503B (zh) * 2020-06-24 2024-04-12 北京小米移动软件有限公司 控制显示模式切换的方法及装置、电子设备、存储介质
CN112562564B (zh) * 2020-12-07 2022-07-08 湖北长江新型显示产业创新中心有限公司 一种显示装置
CN113889048A (zh) * 2021-09-24 2022-01-04 惠科股份有限公司 防闪屏电路、显示面板及显示器

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101110186A (zh) * 2006-07-17 2008-01-23 中华映管股份有限公司 显示驱动装置、显示器及显示器的驱动方法
CN101334969A (zh) * 2007-06-28 2008-12-31 中华映管股份有限公司 栅极驱动电路与电源控制电路
CN102110423A (zh) * 2009-12-28 2011-06-29 乐金显示有限公司 液晶显示器和初始化现场可编程门阵列的方法
US20110187337A1 (en) * 2010-02-03 2011-08-04 Beyond Innovation Technology Co., Ltd. Boost type power converting apparatus
US20110317317A1 (en) * 2010-06-23 2011-12-29 Liu dong-yi Method and Device for Delaying Activation Timing of Output Device
CN105469742A (zh) * 2016-01-15 2016-04-06 京东方科技集团股份有限公司 一种有机发光显示器及显示装置
CN106601207A (zh) * 2017-01-13 2017-04-26 京东方科技集团股份有限公司 控制电路、源极控制电路、驱动方法及显示装置
CN107103871A (zh) * 2017-06-30 2017-08-29 京东方科技集团股份有限公司 显示装置以及显示屏的供电电路和供电方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100747684B1 (ko) * 2001-08-14 2007-08-08 엘지.필립스 엘시디 주식회사 전원 시퀀스장치 및 그 구동방법
US7698573B2 (en) * 2002-04-02 2010-04-13 Sharp Corporation Power source apparatus for display and image display apparatus
KR100889690B1 (ko) * 2007-08-28 2009-03-19 삼성모바일디스플레이주식회사 Ｄｃ―ｄｃ 컨버터 및 이를 이용한 유기전계발광표시장치
KR20110133906A (ko) * 2010-06-07 2011-12-14 엘지이노텍 주식회사 인버터의 보호장치
CN205318129U (zh) * 2015-11-27 2016-06-15 孝感华工高理电子有限公司 一种延时控制电路
CN106817115B (zh) * 2017-03-24 2020-05-01 京东方科技集团股份有限公司 一种开机延时电路和方法
CN106787739B (zh) * 2017-03-28 2019-10-01 深圳Tcl新技术有限公司 产生时序的供电控制电路和电源电路

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101110186A (zh) * 2006-07-17 2008-01-23 中华映管股份有限公司 显示驱动装置、显示器及显示器的驱动方法
CN101334969A (zh) * 2007-06-28 2008-12-31 中华映管股份有限公司 栅极驱动电路与电源控制电路
CN102110423A (zh) * 2009-12-28 2011-06-29 乐金显示有限公司 液晶显示器和初始化现场可编程门阵列的方法
US20110187337A1 (en) * 2010-02-03 2011-08-04 Beyond Innovation Technology Co., Ltd. Boost type power converting apparatus
US20110317317A1 (en) * 2010-06-23 2011-12-29 Liu dong-yi Method and Device for Delaying Activation Timing of Output Device
CN105469742A (zh) * 2016-01-15 2016-04-06 京东方科技集团股份有限公司 一种有机发光显示器及显示装置
CN106601207A (zh) * 2017-01-13 2017-04-26 京东方科技集团股份有限公司 控制电路、源极控制电路、驱动方法及显示装置
CN107103871A (zh) * 2017-06-30 2017-08-29 京东方科技集团股份有限公司 显示装置以及显示屏的供电电路和供电方法

Also Published As

Publication number Publication date
CN107103871A (zh) 2017-08-29
CN107103871B (zh) 2019-11-22
US20210210015A1 (en) 2021-07-08
US11289020B2 (en) 2022-03-29

Similar Documents

Publication Publication Date Title
WO2019000903A1 (zh) 显示装置以及供电电路和供电方法
JP7092665B2 (ja) 画素駆動回路およびその補償方法、表示パネル、ならびに表示装置
JP7114461B2 (ja) 画素回路、表示パネル、および駆動方法
TWI591609B (zh) 級電路及包含該級電路之有機發光顯示器
KR102061256B1 (ko) 스테이지 회로 및 이를 이용한 유기전계발광 표시장치
US9620061B2 (en) Gate driver circuit, gate driving method, gate-on-array circuit, display device, and electronic product
US9583041B2 (en) Pixel circuit and driving method thereof, display panel, and display device
US9087480B2 (en) Scan lines driver and organic light emmiting display device using the same
US9536476B2 (en) Gate driver circuit, gate driving method, gate-on-array circuit, display device, and electronic product
WO2016058352A1 (zh) 栅极驱动电路、显示电路及驱动方法和显示装置
US10665170B2 (en) Display device
WO2018171137A1 (zh) Goa单元及其驱动方法、goa电路、显示装置
US20070258557A1 (en) Shift register circuit and pull high element thereof
US8450942B2 (en) Light emitting diode driving apparatus
WO2018014645A1 (zh) 像素电路、其驱动方法及显示面板
US10885846B2 (en) Pixel driving circuit, display device and driving method
JP2020502549A (ja) Ｏｌｅｄ画素回路及びその駆動方法、表示装置
KR20170091828A (ko) 정전 방지 회로 및 이를 포함하는 표시 장치
US10008154B2 (en) Gate driving circuit and OLED display device
TW201638916A (zh) 畫素電路
US20160232847A1 (en) Scan Control Line Driving Module and Display Device Including Same
TW201535945A (zh) 電源轉換系統
TW201431290A (zh) 輸出緩衝器
TW201315284A (zh) 發光元件驅動電路
US10650777B2 (en) Display device having an inactive mode

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18824510

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18824510

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28.05.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18824510

Country of ref document: EP

Kind code of ref document: A1