WO2018233270A1

WO2018233270A1 - Z-direction interconnected circuit board and manufacturing method thereof

Info

Publication number: WO2018233270A1
Application number: PCT/CN2017/120092
Authority: WO
Inventors: 廉泽阳; 吴森; 李艳国; 陈蓓
Original assignee: 广州兴森快捷电路科技有限公司; 深圳市兴森快捷电路科技股份有限公司; 宜兴硅谷电子科技有限公司
Priority date: 2017-06-20
Filing date: 2017-12-29
Publication date: 2018-12-27
Also published as: CN107155266B; CN107155266A

Abstract

Disclosed are a Z-direction interconnected circuit board and manufacturing method thereof, the method comprising the following steps: S10, manufacturing daughter boards (100), wherein at least two daughter boards (100) are sequentially provided from top to bottom, a surface of each of the daughter boards (100) facing a neighboring daughter board has a pad layer provided thereon, and each pad layer is provided with a conductive pad in one-to-one correspondence with a conducting through hole (130) on the daughter board where the pad layer is located; S20, on two neighboring daughter boards (100), manufacturing an insulating dielectric layer (200) covering the pad layer of at least one of the daughter boards (100); S30, manufacturing a receiving hole (210) on the insulating dielectric layer (200), wherein the receiving hole (210) is in one-to-one correspondence with the conducting through hole (130) on the daughter board (100) where the receiving hole (210) is located; S40, filling the receiving hole (210) with a conductive medium (220); and S50, laminating all of the daughter boards (100) to form a mother board, wherein the pad on each of the daughter boards (100) is conductively connected to the pad on the neighboring daughter board (100) via the conductive medium (220). The method can be used to effectively lower filling difficulty, and reduce defects such as bubbles and holes produced during the laminating process, thereby ensuring stronger adhesion between neighboring daughter boards.

Description

Z-direction interconnected circuit board and manufacturing method thereof

Technical field

The invention relates to the technical field of printed circuit boards, in particular to a Z-direction interconnected circuit board and a manufacturing method thereof.

Background technique

With the development and construction of the communications industry, high-level backplanes have gradually been applied. With the increase of various networked consumer products in the future, it will certainly require greater capacity and higher speed for information transmission. In the future, 5G network construction will inevitably need to support more sub-boards, smaller signal loss and higher reliability backplanes. The manufacturing technology of ultra-high density and higher number of backplanes will be a development direction of the printed circuit industry in the future.

The Via bond process is a Z-direction inter-layer random interconnect technique. It is to press the first prepared sub-board to achieve the high-level number, and the interconnection is connected by a conductive medium. The advantage of this technology is that it is simple to make and can be used to make super high-rise boards. However, in order to prevent the conductive medium from being squeezed and dissipated, the prepreg of the intermediate receiving layer can generally only be used with low fluidity. At the same time, in the process of making POFV (plated on filled via), the outer layer of the sub-board has a thick copper thickness, which causes the copper and copper-free areas on the sub-board to have large fluctuations, and the low-lying copper-free area is filled with glue. Difficulties, defects such as bubbles and voids are easily generated during the lamination process, which in turn affects the quality problems such as bond strength and reliability between the daughter boards.

Summary of the invention

Based on the above, the present invention overcomes the defects of the prior art, and provides a Z-direction interconnected circuit board and a manufacturing method thereof, which can effectively reduce the difficulty of filling, reduce defects such as bubbles and holes generated during the lamination process, and ensure the defects. Bond strength between adjacent daughter boards.

Its technical solutions are as follows:

A method for manufacturing a Z-direction interconnected circuit board, comprising the steps of: preparing a daughter board, the number of the daughter boards being at least two, and at least two of the daughter boards are sequentially arranged from top to bottom, wherein the One side of each of the sub-boards facing the adjacent one of the sub-boards is provided with a pad layer, and the pad layer is provided with pads that are in one-to-one correspondence with the conductive vias on the sub-boards on which the sub-boards are located Forming an insulating dielectric layer for press-bonding on at least one of the two sub-boards adjacent to the two of the sub-boards, the insulating dielectric layer covering the pad layer; a receiving hole is formed in the insulating medium layer, and the receiving hole has a one-to-one correspondence with the conductive through hole of the sub-board; the conductive medium is filled in the receiving hole; and all the sub-boards are laminated to form a mother board, wherein The pads on each of the daughter boards are electrically conducted through the conductive medium to pads on the adjacent one of the daughter boards.

A method for fabricating a Z-direction interconnected circuit board according to an embodiment of the present invention, wherein a pad layer is disposed on each of the sub-boards to be bonded, and each layer of each sub-board extends through the conductive via to the solder The pads on the disk layer are then electrically conducted through the conductive medium on the insulating spacer layer to the respective layer lines on the other daughter board. In the process of pressing, the insulating dielectric layer bonds the two sub-plates adjacent to each other. Since the upper and lower sides of the insulating dielectric layer are butted against the pad layer of the sub-board, the pad layer has only pads (wireless paths), and the rest are copper-free regions, thereby reducing the residual copper ratio, thereby reducing the difficulty of filling and enhancing The bonding strength between the sub-boards avoids the delamination caused by the insufficient bonding of the sub-board wiring layer directly to the insulating dielectric layer. In addition, the present invention also effectively prevents the pad from being directly added to the original design circuit layer, thereby avoiding the alignment space between the conductive medium on one of the daughter boards and the pad on the other of the daughter boards during the docking process of the daughter board. Insufficient is easy to cause short circuit of the circuit board.

The above technical solutions are further described below:

In one embodiment, at least two of the sub-boards are sequentially arranged from top to bottom to form a sub-board group, the sub-board group includes two end sub-boards at both ends, and the step of fabricating the sub-board includes a production end The step of manufacturing the tip sub-board includes the steps of: preparing two copper foils, a plurality of copper clad laminates, and a plurality of first prepregs, each of the two opposite sides of the copper clad plate being provided with a circuit layer; Forming a pre-pressing plate in the order of copper foil, a plurality of copper clad laminates, and copper foil, wherein at least one of the first prepreg is disposed between two adjacent copper clad laminates, and two of the copper foils are At least one of the first prepregs is also disposed between the copper clad plates; the pre-pressing plates are pressed together to form a plywood; conductive through holes are formed on the plywood; and a line is etched on one of the copper foils A surface wiring layer is formed, and a pad is etched on another copper foil to form the pad layer, and the fabrication of the terminal sub-board is completed.

As can be seen from the above, the number of copper foil layers (including the number of circuit layers and the number of pad layers) on each of the terminal sub-boards is even, so that the laminated structure of the sub-board is symmetrical to avoid warping.

In one embodiment, the number of the daughter boards is at least three, the daughter board group further includes an intermediate daughter board between the two end daughter boards, and the step of fabricating the daughter board further includes making a middle child a step of fabricating the intermediate sub-board, comprising the steps of: preparing two copper foils, a plurality of copper clad laminates, and a plurality of first prepregs, each of the opposite sides of the copper clad plate being provided with a circuit layer; a copper foil, a plurality of copper clad laminates, and a copper foil are sequentially laminated to form a pre-pressing plate, wherein at least one of the first prepreg is disposed between two adjacent copper clad plates, and the two copper foils are At least one of the first prepregs is also disposed between the copper clad plates; the pre-pressing plates are pressed together to form a plywood; conductive through holes are formed on the plywood; and the copper foil is etched on both of the copper foils The pad forms the pad layer, completing the fabrication of the intermediate daughter board.

Similarly, the number of copper foil layers on each of the intermediate sub-boards is even, so that the laminated structure of the sub-boards is symmetrical to avoid warping. At the same time, the pad layer is disposed on both sides of the middle sub-board, so as to ensure the difficulty of filling the glue when docking with the two sub-boards on the upper and lower sides.

In one embodiment, in the step of forming an insulating dielectric layer on at least one of the daughter boards, the insulating dielectric layer comprises a second prepreg and a protective film disposed on the second prepreg; The step of forming the receiving holes on the insulating dielectric layer and the step of laminating all of the sub-boards further include the step of removing the protective film.

The protective film is provided to prevent the insulating dielectric layer from being melted by heat in the subsequent fabrication of the receiving hole.

In one embodiment, the aperture of the receiving hole is smaller than or equal to the aperture of the conductive through hole of two adjacent sub-boards, and the impedance of the signal transmission process is reduced by providing a receiving hole of a smaller aperture. Reduce fluctuations and losses during signal transmission.

In one of the embodiments, the insulating dielectric layer comprises a low flow prepreg to prevent the conductive medium from being squeezed and dissipated.

In one embodiment, the conductive medium is a conductive resin, and the conductive resin contains a metal alloy containing particles of copper, tin, antimony, etc., and the metal tin and antimony particles are melted by heat to melt the metal copper during lamination heating. The particles and the pads are soldered together to achieve conduction and fixed connection of the two adjacent sub-boards.

In one embodiment, the step of forming a receiving hole on the insulating dielectric layer is specifically: drilling the receiving hole on the insulating dielectric layer by laser drilling. Guaranteed drilling accuracy and speed are conducive to high-density group hole machining.

The technical solution also provides a Z-direction interconnect circuit board, comprising an insulating dielectric layer and at least two sub-boards, at least two of which are sequentially stacked from top to bottom, and two adjacent sub-boards are arranged. The insulating dielectric layer is disposed, and one side of each of the sub-boards facing the adjacent one of the sub-boards is provided with a pad layer, and the pad layer is provided with a conductive path with the sub-board a pad corresponding to the hole and having a conductive medium, wherein the insulating medium layer is provided with a conductive medium, and the pad on each of the sub-boards is guided by the conductive medium and the pad on the adjacent other sub-board The sub-board and the insulating dielectric layer are of a press-composite structure.

In the embodiment of the present invention, by providing a pad layer on the mating surface of the sub-board, the filling difficulty can be effectively reduced, the bonding strength between the sub-boards can be enhanced, and the bonding of the sub-board wiring layer directly to the insulating dielectric layer can be avoided. The stratification caused by insufficient glue. In addition, the present invention also effectively prevents the pad from being directly added to the original design circuit layer, thereby avoiding the short circuit between the conductive medium and the pad due to insufficient alignment space.

DRAWINGS

1 is a flowchart of a method for fabricating a Z-direction interconnected circuit board according to an embodiment of the present invention;

2 is a flow chart of fabricating a daughter board according to an embodiment of the present invention;

3 is a flowchart of fabricating a header sub-board according to an embodiment of the present invention;

4 is a flowchart of manufacturing a middle sub-board according to an embodiment of the present invention;

FIG. 5 is a schematic exploded view of a Z-direction interconnected circuit board according to an embodiment of the invention; FIG.

6 is a schematic structural diagram of a Z-direction interconnected circuit board according to an embodiment of the present invention;

FIG. 7 is a schematic exploded view of a Z-direction interconnected circuit board according to another embodiment of the present invention.

Description of the reference signs:

100, daughter board, 110, copper clad board, 120, first prepreg, 130, conductive through hole, 200, dielectric layer, 210, receiving hole, 220, conductive medium.

Detailed ways

The present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the scope of the invention.

As shown in FIG. 1 , FIG. 5 , FIG. 6 and FIG. 7 , a method for manufacturing a Z-direction interconnected circuit board according to the present invention includes the following steps:

S100, the daughter board 100 is fabricated. The number of the daughter boards 100 is at least two, and at least two daughter boards 100 are sequentially disposed from top to bottom. Wherein, each of the fabricated sub-boards 100 is provided with a pad layer on one side of the adjacent other sub-board 100 (padslayer1, padslayer2, padslayer3, padslayer4, and padslayer5 shown in FIG. 5 and FIG. 7), and each sub-board The conductive vias 130 are disposed on the first two sub-boards 100, and the conductive vias 130 on the adjacent two sub-boards 100 are in one-to-one correspondence and are vertically opposed. The pad layer is provided with pads that are in one-to-one correspondence with the conductive vias 130 on the sub-board on which they are placed.

In addition, in conjunction with FIG. 5 and FIG. 7, at least two sub-boards 100 are sequentially disposed from top to bottom to form a sub-board group. When the number of the daughter boards 100 is two, the daughter board group includes two end daughter boards 100 at both ends, as shown in FIG. 5; when the number of the daughter boards 100 is more than two, the daughter board group Also included is at least one intermediate daughter board 100 between the two end daughter boards 100, as shown in FIG. When the daughter board 100 is the terminal daughter board 100, the pad layer is only located on one of the faces of the daughter board 100, and the other side of the daughter board 100 is the surface circuit layer (L1, L18, and attached as shown in FIG. 5). L1, L34) shown in Fig. 7. When the daughter board 100 is the intermediate daughter board 100, its pad layer is located on the upper and lower opposite sides of the daughter board 100.

S200, in the adjacent two sub-boards 100, an insulating dielectric layer 200 is formed on at least one of the sub-boards 100, and the insulating dielectric layer 200 covers the pad layer on the sub-board 100.

Specifically, a certain insulating dielectric layer 200 is attached to the sub-board 100.

S300, a receiving hole 210 is formed on the insulating dielectric layer 200, and the receiving hole 210 is in one-to-one correspondence with the conductive through hole 130 of the sub-board 100 where it is located, and is vertically opposed.

Specifically, the receiving hole 210 is drilled on the insulating dielectric layer 200 by means of laser drilling to ensure drilling accuracy and speed, and is advantageous for realizing high-density group hole processing.

S400, filling the conductive hole 220 in the receiving hole 210.

Specifically, the conductive medium 220 is a conductive resin, and the conductive resin contains a metal alloy containing particles of copper, tin, antimony or the like. During the lamination heating process, the metal tin and antimony particles are melted by heat to weld the metal copper particles and the metal. The disks and the like are welded together to realize the conduction and fixed connection of the two adjacent sub-boards 100 up and down. The invention can also select other conductive materials according to actual needs.

At S500, all of the daughter boards 100 are laminated to form a mother board as shown in FIG. Wherein, the pads on each of the sub-boards 100 are electrically connected to the pads on the adjacent other sub-board 100 through the conductive medium 220.

A method for fabricating a Z-direction interconnected circuit board according to an embodiment of the present invention, wherein a pad layer is disposed on each of the sub-boards 100 to be bonded, and each layer of each of the sub-boards 100 passes through the conductive vias 130. The pads are extended to the pads on the pad layer and then electrically connected to the respective layers on the other daughter board 100 via the conductive medium 220 on the insulating spacer. In the process of pressing, the insulating dielectric layer 200 bonds the two sub-boards 100 adjacent to each other. Since the upper and lower sides of the insulating dielectric layer 200 are butted to the pad layer of the sub-board 100, the pad layer has only pads (wireless paths), and the rest are copper-free regions, thereby reducing the residual copper ratio and thereby reducing the difficulty of filling the glue. The bonding strength between the reinforcing sub-boards 100 is prevented, and the delamination caused by the insufficient bonding of the bonding layer of the sub-board 100 directly to the insulating dielectric layer 200 is avoided. In addition, the present invention also effectively prevents the pad from being directly added to the original design circuit layer, thereby avoiding the interconnection between the conductive medium 220 on one of the sub-boards 100 and the pad on the other sub-board 100 during the docking process of the sub-board 100. Because of the aligning space (the aligning space refers to the space that can be displaced between adjacent two sub-boards 100 in the case of ensuring normal conduction), the short circuit of the circuit board is easily caused. Because there is a line on the original design circuit layer, the misalignment of the sub-board 100 is easy to conduct with the line, causing a short circuit.

In one of the embodiments, when the total number of all the sub-boards 100 is two, step S100 includes only step S110 of fabricating the header sub-board 100. As shown in FIG. 3 and FIG. 5, step S110 specifically includes the following steps:

S111, two copper foils, a plurality of copper clad plates 110 and a plurality of first prepregs 120 are prepared, and each of the upper and lower sides of the copper clad laminate 110 is provided with a circuit layer, as shown in FIG. 5 (L2, L3). And (L4, L5) and so on.

S112, a pre-pressing plate is formed by sequentially stacking copper foil, a plurality of copper clad plates 110, and copper foils from top to bottom, wherein at least one of the first prepregs 120 is disposed between two adjacent copper clad laminates 110, At least one of the first prepregs 120 is also disposed between the two copper foils and the copper clad laminate 110.

S113, pressing the pre-pressing plate to form a pressure-bonding plate.

S114, forming a conductive via 130 on the plywood, including two process steps of drilling and plating.

S115, etching a line on one of the copper foils to form a surface wiring layer (L1 or L18 as shown in FIG. 5), and etching a pad on the other copper foil to form the pad layer (as shown in FIG. 5, shown by padslayer1 or padslayer2), to complete the production of the terminal sub-board. It should be noted that, during the pressing between the respective sub-boards 100, the two end sub-boards 100 are symmetrically disposed, that is, the pad layers on the two end sub-boards 100 are oppositely disposed.

As can be seen from the above, the number of copper foil layers (including the number of circuit layers (L1-L9 or L10-L18) and the number of pad layers) on the terminal sub-board 100 in the embodiment of the present invention is an even number, thereby making the sub-board 100 The laminated structure is symmetrical to avoid warping.

In addition, in another embodiment, when the total number of all the sub-boards 100 is more than two, step S100 includes not only step S110 but also step S120 of making the intermediate sub-board 100. As shown in FIG. 4 and FIG. 7 , step S120 specifically includes the following steps:

S121, two copper foils, a plurality of copper clad plates 110 and a plurality of first prepregs 120 are prepared, and each of the upper and lower sides of the copper clad laminate 110 is provided with a circuit layer, as shown in FIG. 7 (L10, L11). And (L12, L13) and so on.

S122, a pre-pressing plate is formed by sequentially stacking copper foil, a plurality of copper clad plates 110, and copper foils from top to bottom, wherein at least one of the first prepregs 120 is disposed between two adjacent copper clad laminates 110, At least one of the first prepregs 120 is also disposed between the two copper foils and the copper clad laminate 110.

S123, pressing the pre-pressing plate to form a pressure-bonding plate.

S124, forming a conductive via 130 on the plywood, including two process steps of drilling and plating.

S125, etching a pad on the two pieces of the copper foil to form the pad layer (padslayer2, padslayer3 or padslayer4, padslayer5 as shown in FIG. 7), and completing the fabrication of the intermediate sub-board.

Similarly, the number of copper foil layers (including the circuit layer and the pad layer) on the intermediate sub-board 100 in the embodiment of the present invention is also an even number, so that the laminated structure of the sub-board 100 is symmetrical to avoid warping. At the same time, the pad layer is disposed on both sides of the intermediate sub-board 100, so as to ensure the difficulty of filling the glue when docking with the two sub-boards 100 on the upper and lower sides.

It should be noted that the present invention does not limit the ordering between step S110 and step S120, and can be performed by any person skilled in the art according to actual needs.

In addition, before step S100, a step may be further included: symmetrically splitting the target circuit board according to the drill tape and the number of layers of the target order, thereby determining the number of the daughter boards 100. This step can be used to determine the total number of daughter boards 100 to be pressed, so that the design of the daughter board 100 is simpler and only needs to be symmetrically split according to the original design of the customer.

In this embodiment, in step S300, the insulating dielectric layer 200 includes a second prepreg and a protective film disposed on the second prepreg. Also, between step S400 and step S600, a step of removing the protective film is further included. It is only necessary to attach a protective film before drilling the receiving hole 210 to prevent damage to the insulating dielectric layer 200 during drilling. The protective film is then torn off during lamination.

Wherein, the second prepreg is a low flow pp prepreg, thereby preventing the conductive medium 220 from being squeezed and washed away. In the embodiment of the present invention, since the defect of the rubber filling can be effectively solved, the pp prepreg with a small fluidity can also meet the filling requirement. The flowability of the low flow prepreg is less than or equal to 150 mi. The present invention can also select prepregs of other fluidity according to actual needs. In addition, the present invention does not limit the fluidity of the first prepreg 120.

In this embodiment, the aperture of the receiving hole 210 is smaller than or equal to the aperture of the conductive via 130 of the two adjacent sub-boards 100. The impedance of the signal transmission process is reduced by setting the receiving hole 210 of the smaller aperture, and the fluctuation and loss during signal transmission are reduced.

As shown in FIG. 6, the present invention further provides a Z-direction interconnected circuit board fabricated by the above manufacturing method, comprising an insulating dielectric layer 200 and at least two sub-boards 100, at least two of which are composed of Stack settings in order from top to bottom. The insulating dielectric layer 200 is disposed between two adjacent sub-boards 100, and one side of each of the sub-boards 100 facing the adjacent one of the sub-boards 100 is provided with a pad layer. The pad layer is provided with pads that are in one-to-one correspondence with the conductive vias 130 of the sub-board 100. The insulating medium layer 200 is provided with a conductive medium 220, and the pads on each of the sub-boards 100 are electrically connected to the pads on the adjacent other sub-board 100 through the conductive medium 220. The sub-board 100 and the insulating dielectric layer 200 are of a press-composite structure. By providing a pad layer on the abutting surface of the sub-board 100, the invention can effectively reduce the difficulty of filling the glue, strengthen the bonding strength between the sub-boards 100, and avoid the bonding of the circuit layer of the sub-board 100 directly to the insulating dielectric layer 200. Stratification due to insufficient filling. In addition, the present invention also effectively prevents the pad from being directly added to the original design circuit layer, thereby avoiding the short circuit between the conductive medium 220 and the pad due to insufficient alignment space.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

A method for manufacturing a Z-direction interconnected circuit board, comprising the steps of:

Making a daughterboard, the number of the daughterboards being at least two, at least two of the daughterboards being disposed in order from top to bottom, wherein each of the fabricated daughterboards faces an adjacent one of the other daughterboards One of the pads is provided with a pad layer, and the pad layer is provided with a pad which is in one-to-one correspondence with the conductive via on the sub-board on which the sub-board is located;

An insulating dielectric layer for press-bonding is formed on at least one of the two sub-boards, and the insulating dielectric layer covers the pad layer;

Forming a receiving hole on the insulating dielectric layer, wherein the receiving hole has a one-to-one correspondence with the conductive through hole of the sub-board;

Filling the receiving hole with a conductive medium;

All of the daughter boards are laminated to form a mother board, wherein pads on each of the daughter boards are electrically conducted through the conductive medium to pads on the adjacent one of the daughter boards.
The method of fabricating a Z-direction interconnected circuit board according to claim 1, wherein at least two of the sub-boards are arranged in order from top to bottom to form a sub-board group, wherein the sub-board group comprises two at two ends The terminal sub-board, the step of fabricating the sub-board includes the steps of fabricating the end sub-board, and the step of fabricating the end sub-board includes the following steps:

Preparing two copper foils, a plurality of copper clad laminates and a plurality of first prepregs, each of the opposite sides of the copper clad laminate having a circuit layer;

Forming a pre-pressing plate in the order of copper foil, a plurality of copper clad laminates, and copper foil, wherein at least one of the first prepreg is disposed between two adjacent copper clad laminates, and two of the copper foils are At least one of the first prepregs is also disposed between the copper clad plates;

Pressing the pre-pressing plate to form a pressure plate;

Making a conductive via on the plywood;

A wiring is formed on one of the copper foils to form a surface wiring layer, and a pad is formed on the other copper foil to form the pad layer, thereby completing the fabrication of the terminal sub-board.
The method of fabricating a Z-direction interconnected circuit board according to claim 2, wherein the number of the sub-boards is at least three, and the sub-board group further comprises a middle sub-block between the two end sub-boards. The step of fabricating the daughterboard further includes the step of fabricating the intermediate daughterboard, and the step of fabricating the intermediate daughterboard includes the following steps:

Preparing two copper foils, a plurality of copper clad laminates and a plurality of first prepregs, each of the opposite sides of the copper clad laminate having a circuit layer;

Forming a pre-pressing plate in the order of copper foil, a plurality of copper clad laminates, and copper foil, wherein at least one of the first prepreg is disposed between two adjacent copper clad laminates, and two of the copper foils are At least one of the first prepregs is also disposed between the copper clad plates;

Pressing the pre-pressing plate to form a pressure plate;

Making a conductive via on the plywood;

A pad is etched on both of the copper foils to form the pad layer, and the fabrication of the intermediate sub-board is completed.
The method of fabricating a Z-direction interconnected wiring board according to claim 1, wherein in the step of forming an insulating dielectric layer on at least one of the daughter boards, the insulating dielectric layer comprises a second prepreg And a protective film disposed on the second prepreg;

And the step of forming a receiving hole on the insulating dielectric layer and the step of laminating all the sub-boards further comprises the following steps:

The protective film is removed.
The method of fabricating a Z-direction interconnected circuit board according to claim 1, wherein the aperture of the receiving hole is smaller than or equal to the aperture of the conductive via of two adjacent sub-boards.
The method of fabricating a Z-direction interconnected wiring board according to any one of claims 1 to 5, wherein the insulating dielectric layer comprises a low-flow prepreg.
The method of fabricating a Z-direction interconnected wiring board according to any one of claims 1 to 5, wherein the conductive medium is a conductive resin.
The method for fabricating a Z-interconnected wiring board according to any one of claims 1 to 5, wherein the step of forming a receiving hole on the insulating dielectric layer is specifically:

The receiving hole is drilled in the insulating medium layer by means of laser drilling.
A Z-direction interconnecting circuit board, comprising: an insulating dielectric layer and at least two sub-boards, at least two of which are sequentially stacked from top to bottom, and two adjacent sub-boards are disposed between The insulating dielectric layer is provided with a pad layer on one side of each of the adjacent sub-boards facing the adjacent one of the sub-boards, and the pad layer is provided with a conductive via hole corresponding to the sub-board a corresponding and conductive pad, the insulating medium layer is provided with a conductive medium, and the pads on each of the sub-boards are electrically connected to the pads on the adjacent other sub-board through the conductive medium, The daughter board and the insulating dielectric layer are of a press-composite structure.