WO2018223497A1 - 一种阵列基板及其制作方法、液晶显示面板 - Google Patents

一种阵列基板及其制作方法、液晶显示面板 Download PDF

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Publication number
WO2018223497A1
WO2018223497A1 PCT/CN2017/093822 CN2017093822W WO2018223497A1 WO 2018223497 A1 WO2018223497 A1 WO 2018223497A1 CN 2017093822 W CN2017093822 W CN 2017093822W WO 2018223497 A1 WO2018223497 A1 WO 2018223497A1
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Prior art keywords
metal layer
layer
array substrate
metal
gate
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French (fr)
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甘启明
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/739,712 priority Critical patent/US10824031B2/en
Publication of WO2018223497A1 publication Critical patent/WO2018223497A1/zh
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0005Production of optical devices or components in so far as characterised by the lithographic processes or materials used therefor
    • G03F7/0007Filters, e.g. additive colour filters; Components for display devices
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136231Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a liquid crystal display panel.
  • the display industry has always improved display quality and reduced production costs as a key factor in winning. And with the development of technology, various process technologies are constantly improving, and the degree of fineness of the processes that can be performed is also higher and higher, which is reflected in the fact that the key dimensions of the pixels can be made smaller and smaller. And people have a certain change in the pursuit of display quality, no longer simply pursue high brightness ratio, but pay more attention to perspective and color space.
  • VA Vertical Alignment, vertical alignment is undoubtedly a very good choice.
  • the traditional VA pixel process has relatively many processes, and at least four processes are required, including M1 (first metal layer) and active. Layer (active layer) and M2 (second metal layer), PV (organic layer) and pixel electrode.
  • M1 first metal layer
  • M2 second metal layer
  • PV organic layer
  • pixel electrode For high-volume production, the cost is relatively high. If semiconductor display technology reduces process passes, it can relatively reduce production costs.
  • the technical problem to be solved by the present invention is to provide an array substrate, a manufacturing method thereof, and a liquid crystal display panel, which can only require two masks in the manufacturing process of the array substrate, thereby improving production efficiency and reducing the cost of product production.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, the method comprising: fabricating a first metal layer on a substrate; and performing a first metal layer on the first metal layer Etching process to form a gate; sequentially forming a gate insulating layer, an active layer and a second metal layer on the first metal layer; and etching the second metal layer and the active layer by using a second mask A source, a drain, and a pixel electrode are formed.
  • an array substrate including a first metal layer, a gate insulating layer, an active layer, and a second metal layer which are sequentially stacked;
  • the first metal layer includes a gate
  • the second metal layer includes a source, a drain, and a pixel electrode.
  • a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate, wherein the array The substrate is produced by the above manufacturing method, or the array substrate as above, and a common electrode is disposed on the color filter substrate.
  • the method for fabricating the array substrate of the present invention comprises: forming a first metal layer on the substrate; and etching the first metal layer by using the first photomask Forming a gate electrode; sequentially forming a gate insulating layer, an active layer and a second metal layer on the first metal layer; etching the second metal layer and the active layer by using a second mask to form a source, Drain and pixel electrodes.
  • the manufacturing process of the entire array substrate requires only two masks, which improves the production efficiency and reduces the cost of production.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate provided by the present invention.
  • FIG. 2 is a schematic flow chart of an embodiment of a method for fabricating an array substrate provided by the present invention
  • 3-6 are schematic structural diagrams of steps S21-S22 in an embodiment of the method for fabricating an array substrate provided by the present invention.
  • step S23 is a schematic structural view of step S23 in an embodiment of a method for fabricating an array substrate provided by the present invention.
  • FIG. 8 to FIG. 13 are schematic structural diagrams of step S24 in an embodiment of a method for fabricating an array substrate according to the present invention.
  • FIG. 14 is a top plan view showing an embodiment of a method for fabricating an array substrate provided by the present invention.
  • FIG. 15 is a schematic structural view of an embodiment of a liquid crystal display panel provided by the present invention.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate according to the present invention.
  • the array substrate includes a first metal layer 11, a gate insulating layer 12, an active layer and a second metal layer which are sequentially stacked on the substrate 10. 15.
  • the active layer includes a semiconductor layer 13 and an ion implantation layer 14.
  • the first metal layer 11 includes a gate 111
  • the second metal layer 15 includes a source 151, a drain 152, and a pixel electrode 153.
  • the first metal layer 11 is etched under the first mask to form the gate 111
  • the second metal layer 15 is etched under the second mask to form the source 151, the drain 152 and the pixel electrode 153.
  • the second metal layer 15 is an anti-oxidation metal layer, and the second metal layer 15 is exposed in the liquid crystal layer between the array substrate and the color filter substrate.
  • the method for fabricating the array substrate includes:
  • the substrate 10 may be a transparent glass substrate or a transparent plastic substrate; the first metal layer may be one or more of Pt, Ru, Au, Ag, Mo, Cr, Al, Ta, Ti or W. An alloy of metals.
  • a layer of metal may be deposited on the substrate 10 by physical vapor deposition or chemical vapor deposition, and specifically, one of physical sputtering, spin coating, inkjet, slit coating, or photolithography may be used.
  • the present embodiment is not limited.
  • the photoresist 31 is coated on the first metal layer 11, and the photoresist 31 is exposed and developed using the first photomask 32.
  • the first metal layer is then etched to form a structure as shown in FIG. 5, and finally the photoresist 31 is stripped to form a gate as shown in FIG. Extreme 111.
  • the gate electrode 111 is made of the same metal layer (ie, the first metal layer 11), and only one reticle is used for patterning.
  • S23 sequentially forming a gate insulating layer, an active layer, and a second metal layer on the first metal layer.
  • a gate insulating layer 12 is formed on the first metal layer 11; a semiconductor layer 13 is formed on the gate insulating layer 12, and ion implantation is performed on the surface of the semiconductor layer 13 to form an ion implantation.
  • Layer 14; a second metal layer 15 is formed on the ion implantation layer 14.
  • the gate insulating layer 12 may be SiOx, SiNx or a mixture thereof; the semiconductor layer 13 may be made of Si, Ge or GaAs, etc., in this embodiment, may be made of As; the ion implantation layer 14 may also be called an ion doping layer. Different ions can be implanted according to the specific function of the TFT. If an N-type semiconductor is to be formed, phosphorus can be implanted. To form a P-type semiconductor, boron or gallium can be implanted.
  • the second metal layer 15 is exposed to directly contact the liquid crystal. Therefore, the second metal layer 15 needs to use a metal that is difficult to oxidize, such as Ag or Ag, Mo combination. A multilayered metal formed.
  • S24 etching the second metal layer and the active layer by using a second mask to form a source, a drain, and a pixel electrode.
  • the photoresist 33 is coated on the second metal layer 15; the photolithography 33 is exposed and developed by using the second mask 34; FIG. 9 is the exposure and development of the photoresist 33. Schematic.
  • the second metal layer 15, the semiconductor layer 13, and the ion implantation layer 14 are then etched to form source, drain, and pixel electrodes.
  • the second metal layer 15, the semiconductor layer 13, and the ion implantation layer 14 not covered by the photoresist 33 are etched to expose the region not covered by the photoresist 33. Pole insulating layer 12.
  • wet etching may be employed, and when the semiconductor layer 13 and the ion implantation layer 14 are etched, dry etching may be performed.
  • a hole is then formed in the photoresist 33 to form a via 331 to expose a portion of the second metal layer 15 covered by the photoresist 33, specifically, a portion corresponding to the exposed gate 111;
  • the exposed second metal layer 15 is further etched as shown in FIG. 12 to expose the ion implantation layer 14; the exposed ion implantation layer 14 is etched to expose the semiconductor layer 13.
  • the photoresist on the second metal layer 15 is peeled off to form an array substrate, wherein the second metal layer 15 forms a source electrode 151, a drain electrode 152, and a pixel electrode 153 in the above etching process. .
  • the source 151, the drain 152 and the pixel electrode 153 are made of the same metal layer (ie, the second metal layer 15), and only one reticle is used for patterning.
  • the method for fabricating the array substrate includes: forming a first metal layer on the substrate; and etching the first metal layer by using the first mask to form a gate; A gate insulating layer, an active layer and a second metal layer are sequentially formed on the metal layer; the second metal layer and the active layer are etched by a second mask to form source, drain and pixel electrodes.
  • the manufacturing process of the entire array substrate requires only two masks, which improves the production efficiency and reduces the cost of production.
  • FIG. 15 is a schematic structural diagram of an embodiment of a liquid crystal display panel according to the present invention.
  • the liquid crystal display panel includes an array substrate 40, a color filter substrate 50, and a liquid crystal layer 60 between the array substrate 40 and the color filter substrate 50.
  • the array substrate 40 is an array substrate as provided in the above embodiment, wherein the second metal layer (including the source, the drain, and the pixel electrode) is exposed in the liquid crystal layer 60, so the second metal layer needs to be difficult to be oxidized.
  • the metal material is made of, for example, a multilayer structure metal formed by a combination of Ag or Ag and Mo.
  • a photoresist and a common electrode are disposed in the color filter substrate 50.
  • the photoresist may include RGB three-color photoresist, and an electric field is formed between the common electrode and the pixel electrode in the array substrate to control deflection of the liquid crystal molecules.
  • the liquid crystal display panel is a VA type liquid crystal display panel.
  • the present invention can also provide a VA type liquid crystal display, including a liquid crystal display panel and a backlight, wherein the liquid crystal display panel is the same as above, and the structure thereof is the same, and details are not described herein again.
  • the first metal layer in the array substrate is etched under the first mask to form a gate
  • the second metal layer is etched under the second mask to form a source
  • the drain and the pixel electrode so only two masks are used in the process, which increases the production efficiency and reduces the cost of production.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板及其制作方法、液晶显示面板,该阵列基板的制作方法包括:在基板(10)上制作第一金属层(11);采用第一张光罩(32)对第一金属层进行刻蚀工艺以形成栅极(111);在第一金属层上依次制作栅极绝缘层(12)、有源层(13和14)和第二金属层(15);采用第二张光罩(34)对第二金属层和有源层进行刻蚀工艺以形成源极(151)、漏极(152)和像素电极(153)。通过上述方式,能够在阵列基板的制作制程中只需要两道光罩,提高了生产效率,降低了产品生产的成本。

Description

一种阵列基板及其制作方法、液晶显示面板
【技术领域】
本发明涉及显示技术领域,特别是涉及一种阵列基板及其制作方法、液晶显示面板。
【背景技术】
显示行业一直将提高显示品质,降低生产成本作为制胜的关键因素。并且随着技术的发展,各种工艺技术也在不断的提高,所能进行的工艺精细程度也越来越高,这体现在像素的关键尺寸可以越做越小。并且人们追求显示品质也有了一定的改变,不再单纯追求高亮度高度比,而对视角、色彩空间加更注重。
在这些显示技术中,VA(Vertical Alignment,垂直配向)无疑是一个非常好的选择。但是传统的VA像素工艺制程相对比较多,至少需要四道制程,包括M1(第一金属层)、active layer(有源层)与M2(第二金属层)、PV(有机层)及像素电极。这对于大量生产来说,成本也就相对比较高。半导体显示技术如果减少制程道次,相对来说就能降低生产成本。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及其制作方法、液晶显示面板,能够在阵列基板的制作制程中只需要两道光罩,提高了生产效率,降低了产品生产的成本。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种阵列基板的制作方法,该制作方法包括:在基板上制作第一金属层;采用第一张光罩对第一金属层进行刻蚀工艺以形成栅极;在第一金属层上依次制作栅极绝缘层、有源层和第二金属层;采用第二张光罩对第二金属层和有源层进行刻蚀工艺以形成源极、漏极和像素电极。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种阵列基板,该阵列基板包括依次层叠形成的第一金属层,栅极绝缘层、有源层以及第二金属层;其中,第一金属层包括栅极,第二金属层包括源极、漏极和像素电极。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种液晶显示面板,该液晶显示面板包括阵列基板、彩膜基板以及阵列基板和彩膜基板之间的液晶层,其中,阵列基板是采用如上的制作方法制得,或是如上的阵列基板,彩膜基板上设置有公共电极。
本发明的有益效果是:区别于现有技术的情况,本发明的阵列基板的制作方法包括:在基板上制作第一金属层;采用第一张光罩对第一金属层进行刻蚀工艺以形成栅极;在第一金属层上依次制作栅极绝缘层、有源层和第二金属层;采用第二张光罩对第二金属层和有源层进行刻蚀工艺以形成源极、漏极和像素电极。通过上述方式,整个阵列基板的制作制程只需要两道光罩,提高了生产效率,降低了产品生产的成本。
【附图说明】
图1是本发明提供的阵列基板一实施例的结构示意图;
图2是本发明提供的阵列基板的制作方法一实施例的流程示意图;
图3-图6是本发明提供的阵列基板的制作方法一实施例中步骤S21-S22的结构示意图;
图7是本发明提供的阵列基板的制作方法一实施例中步骤S23的结构示意图;
图8-图13是本发明提供的阵列基板的制作方法一实施例中步骤S24的结构示意图;
图14是本发明提供的阵列基板的制作方法一实施例的俯视结构示意图;
图15是本发明提供的液晶显示面板一实施例的结构示意图。
【具体实施方式】
参阅图1,图1是本发明阵列基板一实施例的结构示意图,该阵列基板包括依次层叠设置在基板10上的第一金属层11、栅极绝缘层12、有源层以及第二金属层15。
其中,有源层包括半导体层13以及离子注入层14。
其中,第一金属层11包括栅极111,第二金属层15包括源极151、漏极152和像素电极153。
具体地,第一金属层11在第一张光罩下被刻蚀形成栅极111,第二金属层15在第二张光罩下被刻蚀形成源极151、漏极152和像素电极153。
其中,第二金属层15为抗氧化金属层,且第二金属层15裸露在阵列基板与彩膜基板之间的液晶层中。
下面参阅图2的流程示意图以及图3-图13的结构示意图,对上述阵列基板的制作方法进行详细说明。
如图2所示,该阵列基板的制作方法包括:
S21:在基板上制作第一金属层。
S22:采用第一张光罩对第一金属层进行刻蚀工艺以形成栅极。
基板10可以是透明的玻璃基板,也可以是透明的塑料基板;第一金属层可以采用Pt、Ru、Au、Ag、Mo、Cr、Al、Ta、Ti或W中的一种金属或多种金属的合金。
具体地,可以采用物理气相沉积或化学气相沉积的方式在基板10上沉积一层金属,具体可以采用物理溅射、旋涂、喷墨、狭缝涂布或者光刻工艺等方法中的一种或多种,本实施例不作限定。
如图3所示,在金属沉积之后,在第一金属层11上涂覆光刻胶31,采用第一张光罩32对光刻胶31进行曝光显影。曝光显影后的光刻胶如图4所示,然后对第一金属层进行刻蚀,形成如图5所示的结构,最后对光刻胶31进行剥离,以形成如图6所示的栅极111。
值得注意的是,在上述制程中,栅极111采用同一金属层(即第一金属层11)制作,在图形化时,仅使用一道光罩。
S23:在第一金属层上依次制作栅极绝缘层、有源层和第二金属层。
具体地,如图7所示,在第一金属层11上制作栅极绝缘层12;在栅极绝缘层12上制作半导体层13,并在半导体层13的表面进行离子注入,以形成离子注入层14;在离子注入层14上制作第二金属层15。
其中,栅极绝缘层12可以是SiOx、SiNx或其混合物;半导体层13可以采用Si、Ge或GaAs等,在本实施例中,可以采用As制作;离子注入层14也可以叫做离子掺杂层,可以根据TFT的具体功能而注入不同的离子,若要形成N型半导体,可以注入磷,若要形成P型半导体,可以注入硼、镓。
其中,由于在阵列基板和彩膜基板对盒形成液晶盒时,第二金属层15裸露出来直接与液晶接触,因此,第二金属层15需要采用难以氧化的金属,例如Ag或Ag、Mo组合形成的多层结构金属。
S24:采用第二张光罩对第二金属层和有源层进行刻蚀工艺以形成源极、漏极和像素电极。
具体地,如图8所示,在第二金属层15上涂覆光刻胶33;采用第二张光罩34对光刻33胶进行曝光显影;图9为光刻胶33曝光显影后的结构示意图。
然后对第二金属层15、半导体层13以及离子注入层14进行刻蚀,以形成源极、漏极以及像素电极。
具体地,如图10所示,对未被光刻胶33覆盖的第二金属层15、半导体层13以及离子注入层14进行刻蚀,以使未被光刻胶33覆盖的区域裸露出栅极绝缘层12。可选的,在对第二金属层15进行刻蚀时,可以采用湿法刻蚀,在对半导体层13以及离子注入层14进行刻蚀时,可以才是干法刻蚀。
如图11所示,然后在光刻胶33上挖孔,形成过孔331,以使光刻胶33覆盖的第二金属层15部分裸露,具体地,是裸露出栅极111对应的部分;如图12所示再对裸露的第二金属层15进行刻蚀,以裸露出离子注入层14;对裸露的离子注入层14进行刻蚀,以裸露出半导体层13。
如图13所示,最后对第二金属层15上面的光刻胶进行剥离,形成阵列基板,其中,第二金属层15在上述刻蚀过程中形成源极151、漏极152以及像素电极153。
值得注意的是,在上述制程中,源极151、漏极152以及像素电极153采用同一金属层(即第二金属层15)制作,在图形化时,仅使用一道光罩。
如图14所示,其中,竖线填充区域表示第一金属层11的图案,横线填充区域表示第二金属层15的图案。
区别于现有技术,本实施方式提供的阵列基板的制作方法包括:在基板上制作第一金属层;采用第一张光罩对第一金属层进行刻蚀工艺以形成栅极;在第一金属层上依次制作栅极绝缘层、有源层和第二金属层;采用第二张光罩对第二金属层和有源层进行刻蚀工艺以形成源极、漏极和像素电极。通过上述方式,整个阵列基板的制作制程只需要两道光罩,提高了生产效率,降低了产品生产的成本。
参阅图15,图15是本发明提供的液晶显示面板一实施例的结构示意图,该液晶显示面板包括阵列基板40、彩膜基板50以及阵列基板40和彩膜基板50之间的液晶层60。
其中,阵列基板40是如上述实施方式中所提供的阵列基板,其中的第二金属层(包括源极、漏极以及像素电极)裸露在液晶层60中,因此第二金属层需要采用难以氧化的金属材料制得,例如Ag或Ag、Mo组合形成的多层结构金属。
彩膜基板50中设置有光阻和公共电极,具体地,光阻可以包括RGB三色光阻,公共电极与阵列基板中的像素电极之间形成电场以控制液晶分子的偏转。
具体地,该液晶显示面板为VA型液晶显示面板。
另外,本发明还可以提供一种VA型液晶显示器,包括液晶显示面板以及背光,其中,该液晶显示面板是如上的面板,其结构相同,这里不再赘述。
在本发明提供的液晶显示面板中,由于阵列基板中第一金属层在第一张光罩下被刻蚀形成栅极,第二金属层在第二张光罩下被刻蚀形成源极、漏极和像素电极,因此在制程中只使用两道光罩,提高了生产效率,降低了产品生产的成本。
以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板,其中,包括依次层叠形成的第一金属层,栅极绝缘层、有源层以及第二金属层;
    其中,所述第一金属层包括栅极,所述第二金属层包括源极、漏极和像素电极;
    其中,所述第一金属层采用Pt、Ru、Au、Ag、Mo、Cr、Al、Ta、Ti或W中的一种金属或多种金属的合金制得,所述第二金属层采用抗氧化金属材料制得,且所述第二金属层裸露在所述阵列基板与彩膜基板之间的液晶层中。
  2. 根据权利要求1所述的阵列基板,其中,
    所述第一金属层在第一张光罩下被刻蚀形成所述栅极,所述第二金属层在第二张光罩下被刻蚀形成所述源极、漏极和像素电极。
  3. 根据权利要求1所述的阵列基板,其中,
    所述第二金属层为抗氧化金属层,且所述第二金属层裸露在所述阵列基板与彩膜基板之间的液晶层中。
  4. 一种阵列基板的制作方法,其中,包括:
    在基板上制作第一金属层;
    采用第一张光罩对所述第一金属层进行刻蚀工艺以形成栅极;
    在所述第一金属层上依次制作栅极绝缘层、有源层和第二金属层;
    采用第二张光罩对所述第二金属层和所述有源层进行刻蚀工艺以形成源极、漏极和像素电极。
  5. 根据权利要求4所述的制作方法,其中,
    所述第二金属层采用抗氧化金属材料制得,且所述第二金属层裸露在所述阵列基板与彩膜基板之间的液晶层中。
  6. 根据权利要求4所述的制作方法,其中,
    所述采用第一张光罩对所述第一金属层进行刻蚀工艺以形成栅极,包括:
    在所述第一金属层上涂覆光刻胶;
    采用第一张光罩对所述光刻胶进行曝光显影;
    对所述第一金属层进行刻蚀,以形成栅极。
  7. 根据权利要求4所述的制作方法,其中,
    所述在所述第一金属层上依次制作栅极绝缘层、有源层和第二金属层,包括:
    在所述第一金属层上制作栅极绝缘层;
    在所述栅极绝缘层上制作半导体层,并在所述半导体层的表面进行离子注入,以形成离子注入层;
    在所述离子注入层上制作第二金属层。
  8. 根据权利要求7所述的制作方法,其中,
    所述采用第二张光罩对所述第二金属层和所述有源层进行刻蚀工艺以形成源极、漏极和像素电极,包括:
    在所述第二金属层上涂覆光刻胶;
    采用第二张光罩对所述光刻胶进行曝光显影;
    对所述第二金属层、所述半导体层以及所述离子注入层进行刻蚀,以形成源极、漏极以及像素电极。
  9. 根据权利要求8所述的制作方法,其中,
    所述曝光显影后的光刻胶覆盖对应所述栅极;
    所述对所述第二金属层、所述半导体层以及所述离子注入层进行刻蚀,以形成源极、漏极以及像素电极,包括:
    对所述第二金属层、所述半导体层以及所述离子注入层进行刻蚀,以使未被所述光刻胶覆盖的区域裸露出所述栅极绝缘层;
    在所述光刻胶上挖孔,以使所述光刻胶覆盖的第二金属层部分裸露;
    对裸露的第二金属层进行刻蚀,以裸露出离子注入层;
    对裸露的离子注入层进行刻蚀,以裸露出半导体层。
  10. 根据权利要求9所述的制作方法,其中,
    所述对所述第二金属层、所述半导体层以及所述离子注入层刻蚀,以使未被所述光刻胶覆盖的区域裸露出所述栅极绝缘层,包括:
    对所述第二金属层进行湿法刻蚀,以裸露出离子注入层;
    对离子注入层以及半导体层进行干法刻蚀,以裸露出栅极绝缘层。
  11. 一种液晶显示面板,包括阵列基板、彩膜基板以及所述阵列基板和所述彩膜基板之间的液晶层,其中,
    所述阵列基板包括依次层叠形成的第一金属层,栅极绝缘层、有源层以及第二金属层;其中,所述第一金属层包括栅极,所述第二金属层包括源极、漏极和像素电极;或
    所述阵列基板采用以下的方法制得:
    在基板上制作第一金属层;
    采用第一张光罩对所述第一金属层进行刻蚀工艺以形成栅极;
    在所述第一金属层上依次制作栅极绝缘层、有源层和第二金属层;
    采用第二张光罩对所述第二金属层和所述有源层进行刻蚀工艺以形成源极、漏极和像素电极。
  12. 根据权利要求11所述的液晶显示面板,其中,
    所述第一金属层在第一张光罩下被刻蚀形成所述栅极,所述第二金属层在第二张光罩下被刻蚀形成所述源极、漏极和像素电极。
  13. 根据权利要求11所述的液晶显示面板,其中,
    所述第二金属层为抗氧化金属层,且所述第二金属层裸露在所述阵列基板与彩膜基板之间的液晶层中。
PCT/CN2017/093822 2017-06-05 2017-07-21 一种阵列基板及其制作方法、液晶显示面板 Ceased WO2018223497A1 (zh)

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