WO2018222915A1 - Formation de motif bidimensionnel de couche de circuit intégré par implantation ionique inclinée - Google Patents

Formation de motif bidimensionnel de couche de circuit intégré par implantation ionique inclinée Download PDF

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Publication number
WO2018222915A1
WO2018222915A1 PCT/US2018/035461 US2018035461W WO2018222915A1 WO 2018222915 A1 WO2018222915 A1 WO 2018222915A1 US 2018035461 W US2018035461 W US 2018035461W WO 2018222915 A1 WO2018222915 A1 WO 2018222915A1
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hard mask
mask layer
pattern
substrate
substructure
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PCT/US2018/035461
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English (en)
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Tsu-Jae King Liu
Fei Ding
Yi-Ting Wu
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The Regents Of The University Of California
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/05—Arrays
    • B81B2207/056—Arrays of static structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation

Definitions

  • the field of currently claimed embodiments of this invention relates to integrated circuits and methods of producing integrated circuits, and more particularly to integrated circuits produced and methods of production using tilted ion implantation techniques.
  • Photolithography uses light to transfer a geometric pattern from a photomask to the surface of a silicon (Si) wafer substrate comprising multiple chips.
  • the size of the features on the mask is larger than that of the features on the wafer, by the demagnification factor (typically 4-5) of the optical projection system, which provides for lower mask cost.) "Blurring" of the pattern on the wafer produced by the
  • a hard (inorganic) mask material is used rather than photoresist to pattern the IC layer with better etch selectivity; in this case, extra processes are required to deposit the hard mask layer prior to photoresist coating, to etch the hard mask layer, and to remove the hard mask layer after it is used to pattern the IC layer, i.e., 7 processes are needed.
  • the minimum pitch (J ) of features defined by photolithography is limited by diffraction and is proportional to the wavelength of light, ⁇ :
  • P mitl 2 /n. s ii, ⁇
  • ⁇ is the propagation angle of the projection lens system (typically -70°)
  • m is the lowest index of refraction of the propagation medium.
  • J n is twice the lithographic resolution limit.
  • the second technique is referred to as “spacer lithography” or “self-aligned double patterning (SADP)” and is illustrated in FIGS. 2A-2J. It involves even more processes than the litho-etch-litho-etch technique and also requires extra lithography and etch processes to eliminate the portions of the spacers located at the ends of the sacrificial linear features (called “mandrels”); otherwise, the spacers formed along the sidewalls of the same mandrel feature may be interconnected.
  • spacer lithography or “self-aligned double patterning
  • DSA directed self-assembly of a diblock copolymer film: the film is coated onto a wafer with lithographically defined features on its surface, which serve as a guide for the formation of the sub- lithographic features; self-assembly (phase separation) occurs upon heating to form features as small as a few nanometers, depending on the degree of polymerization (number of monomer repeats in the chain) and the block-block interaction parameter.
  • Drawbacks of this technique include a limited range of feature sizes and pitches for a given diblock copolymer material formulation, and feature-edge roughness which does not scale well with the feature size. Therefore, a need remains for improved methods of producing integrated circuits and the improved integrated circuits.
  • An aspect of the present disclosure is to provide a method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two- dimensional pattern.
  • the method includes providing a substrate comprising a
  • substructure and a hard mask layer formed on the substructure performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer; selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two- dimensional pattern in the hard mask layer; and selectively etching the substructure of the substrate in exposed regions to transfer the two-dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two- dimensional structure therein.
  • a further aspect of the present disclosure is to produce a device according to the above method.
  • the device produced according to the above method may include a two-dimensional (2D) pattern, the two-dimensional pattern having a minimum feature pitch smaller than a minimum pitch of a photolithographic process and having a minimum feature size smaller than a photolithographic resolution limit that is achieved solely by using a photolithographic process without using ion implantation.
  • Another aspect of the present disclosure is to provide a structure for producing a device having sub-lithographic two-dimensional structures comprising a substrate comprising a substructure and a hard mask layer formed on the substructure.
  • the hard mask layer defines a two-dimensional pattern therein that exposes the substructure of the substrate according to the two-dimensional pattern.
  • FIG. 1 A is a schematic illustration of a cross-section illustrating the
  • double exposure double etch technique, where the IC layer to be patterned is coated with a hard mask layer
  • FIG. IB is a schematic illustration of the cross-section, where a first layer of light-sensitive "photoresist" is coated onto the hard mask layer;
  • FIG. 1C is a schematic illustration of the cross-section, where
  • photolithography light exposure through a mask, followed by immersion in a chemical developer solution to remove photoresist in regions exposed to light
  • photoresist layer is used to print features in the photoresist layer (note that these features usually are "trimmed" to become narrower than the lithographic resolution limit);
  • FIG. ID is a schematic illustration of the cross-section, where an etch process is used to remove regions of the hard mask layer in regions not protected by the etch-resistant photoresist;
  • FIG. IE is a schematic illustration of the cross-section, where photoresist is selectively removed
  • FIG. IF is a schematic illustration of the cross-section, a second layer of photoresist is coated thereon;
  • FIG. 1G is a schematic illustration of the cross-section, where
  • FIG. 1H is a schematic illustration of the cross-section, where an etch process is used to remove regions of the IC layer not protected by either the hard mask or photoresist;
  • FIG. II is a schematic illustration of the cross-section, where hard mask and photoresist layers are selectively removed.
  • FIG. 2A is a schematic illustration of a cross-section illustrating the self- aligned double patterning technique, where the IC layer to be patterned is coated with a sacrificial layer;
  • FIG. 2B is a schematic illustration of the cross-section, where photoresist is coated onto the sacrificial layer
  • FIG. 2C is a schematic illustration of the cross-section, where
  • photolithography is used to print features in the photoresist layer
  • FIG. 2D is a schematic illustration of the cross-section, where an etch process is used to remove regions of the sacrificial layer in regions not protected by the photoresist;
  • FIG. 2E is a schematic illustration of the cross-section, where photoresist is selectively removed
  • FIG. 2F is a schematic illustration of the cross-section, where a relatively thin hard mask layer is conformally deposited
  • FIG. 2G is a schematic illustration of the cross-section, where an anisotropic etch process is used to form hard-mask "spacers" along the sidewalls of the "mandrel” sacrificial layer features (note that the width of these spacers is correlated with the thickness of the deposited hard mask layer, and can be much smaller than the lithographic resolution limit);
  • FIG. 2H is a schematic illustration of the cross-section, where the sacrificial layer is selectively removed
  • FIG. 21 is a schematic illustration of the cross-section, where an etch process is used to remove regions of the IC layer not protected by the spacers;
  • FIG. 2J is a schematic illustration of the cross-section, where the spacers are selectively removed.
  • FIG. 3 A is a schematic illustration of a cross-section illustrating how a sub-lithographic feature is created in a hard mask layer using a sequence of
  • photolithography and tilted ion implantation processes where photoresist features (formed using a photolithography process) serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin hard mask layer on the surface of the IC substrate, according to an embodiment of the present disclosure
  • FIG. 4A is a schematic plan view showing a first exemplary 2D IC -layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present disclosure
  • FIG. 4B is a schematic plan view showing ID patterns (labeled A, B, C,
  • FIG. 4C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the four ID patterns A, B, C, D, according to an embodiment of the present disclosure
  • FIG. 5A is a schematic plan view showing a second example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
  • FIG. 5B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form the 2D pattern, according to an embodiment of the present disclosure
  • FIG. 5C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • FIG. 6A is a schematic plan view showing a third example of a 2D IC- layer pattern according to another embodiment of the current invention with sub- lithographic features and feature pitch, according to an embodiment of the present disclosure
  • FIG. 6B is a schematic plan view showing ID patterns labeled A, B, C, D which when overlaid form the 2D pattern, according to an embodiment of the present disclosure
  • FIG. 6C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • FIG.7A is a schematic plan view showing a fourth example of a 2D IC- layer pattern according to another embodiment of the current invention with sub- lithographic features and feature pitch, according to an embodiment of the present disclosure
  • FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure
  • FIG.7C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns, according to an embodiment of the present disclosure
  • FIG. 8A is a schematic plan view showing a fifth example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
  • FIG. 8B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure
  • FIG. 8C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • FIG. 9A is a schematic plan view showing a sixth example of a 2D IC- layer pattern with sub-lithographic features and feature pitch, according to an
  • FIG. 9B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present disclosure.
  • FIG. 9C is a schematic plan view showing a corresponding set of dark- field lithographic mask features that can be used in conjunction with tilted ion
  • An IC manufacturing method for achieving a two-dimensional (2D) pattern with minimum feature pitch smaller than the minimum pitch of the photolithographic process (J n) and with minimum feature size smaller than the lithographic resolution limit (.Pmin/2) is disclosed.
  • This new method uses multiple lithography processes, each followed by a tilted ion implantation (TII) process, to create a latent 2D pattern in a hard mask layer.
  • TII tilted ion implantation
  • the 2D pattern in the hard mask is "developed” by etching the hard mask material either selectively in the implanted regions or selectively in the non-implanted regions.
  • the 2D pattern is transferred to an underlying IC layer by an etch process.
  • FIGS. 3A-3B illustrate how a latent sub-lithographic pattern is created in a hard mask layer on the surface of an IC substrate, using a sequence of photolithography and TII processes ("litho-TII" for short), according to an embodiment of the present disclosure.
  • FIG. 3A is a schematic illustration of a cross-section illustrating how a sub- lithographic feature is created in a hard mask layer using a sequence of photolithography and tilted ion implantation processes (litho-TII) [S.W. Kim et al., Journal of Vacuum Science and Technology B, vol.
  • photoresist features formed using a photolithography process serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin hard mask layer on the surface of the IC substrate.
  • Ion implantation is a relatively simple process as compared to lithography, deposition and etch processes, as it does not require steps to pre-coat, pre-clean, or pre- bake the wafer. It is used in IC manufacturing to introduce impurity atoms in precise amounts (dose in the range from I0 n /cm 2 to 10 16 /cni 2 ) into the surface region of the wafer, over a range of depths ("projected range" determined by the implant energy, which can range from ⁇ 1 keV to 60 keV in common ini planters). The implantation tilt angle can be readily adjusted in the range from -60° to +60°.
  • the implanted species can be inert species such as argon (Ar) or xenon (Xe), or other inert species.
  • the implanted species can also be oxygen (O), nitrogen (N), or silicon (Si) depending on the hard mask material (silicon oxide, silicon nitride, SiOxNy, SiOxCy, etc.).
  • the atoms e.g., Ar, Xe, O, N, Si, etc.
  • the ions are then neutralized with an electron gun once the ions hit the target.
  • the implant dose can be in the range from 1E14 to 1E15 per square centimeter, with less than +/- 5% variation across the wafer.
  • FIGS. 4A-4C show plan-view schematics of a first exemplary 2D pattern, how it can be formed as a composite of overlaid ID patterns, and a corresponding set of dark-field lithographic mask features ⁇ i.e., corresponding to the rectangular regions from which photoresist is to be removed in developer solution) that can be used to define the ID patterns via multiple litho-TII sequences.
  • FIG. 4A is a schematic plan view showing a 2D IC -layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present disclosure.
  • FIG. 4B is a schematic plan view showing ID patterns (labeled A, B, C, D) which when overlaid form the 2D pattern shown in FIG.
  • FIG. 4C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the four ID patterns A, B, C, D, according to an embodiment of the present disclosure.
  • t e lithographic resolution limit is indicated as Pm 2.
  • the ion trajectory direction is indicated by the dashed arrows (shown in
  • FIG. 4C according to the line type for each dark-field mask feature.
  • a hard mask layer is deposited onto the IC layer; then litho-TII is performed using each of the four masks in sequence; afterwards the hard mask is selectively etched to form the composite 2D pattern, after which the 2D pattern is transferred to the IC layer by a selective etch process.
  • the constituent orthogonal ID pattern features overlap.
  • the degree of overlap in each direction can be adjusted in practice to minimize unwanted blurring or bloating while ensuring a continuous bend.
  • the resultant 2D pattern is "dark-field.”
  • the unimplanted regions of the hard mask layer are subsequently selectively etched away (i.e., implantation serves to retard the etch rate of the hard mask material), then the resultant 2D pattern is "bright-field.”
  • litho-TII lithographic tilted ion implantation
  • the features of the lithographic masks can be automatically generated by first decomposing each 2D feature into a minimum number of horizontal and vertical overlapping ID features (see, FIG. 4B), then apportioning all of the ID features of the decomposed pattern across multiple masks as needed to comply with lithographic design rules (similarly as is done today for the conventional LELE method), and finally generating for each I D feature a rectangular mask feature that circumscribes three sides of the ID feature - corresponding to the region to be implanted - and that complies with the resolution limit (Pmm/2), as illustrated in FIG. 4C.
  • FIG. 9A-9C show various rectangular mask features and configurations that could be used to form other 213 patterns using this method according to some embodiments of the current invention.
  • FIG. 5A is a schematic plan view showing a second example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 5B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form the 2D pattern, according to an embodiment of the present invention.
  • FIG. 5C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to generate the three ID patterns A, B and C, according to an embodiment of the present invention.
  • FIG. 5A is a schematic plan view showing a second example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 5B is a schematic plan view showing ID patterns labeled A
  • FIG. 6A is a schematic plan view showing a third example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 6B is a schematic plan view showing ID patterns labeled A, B, C, D which when overlaid form the 2D pattern, according to an embodiment of the present invention.
  • FIG. 6C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the four ID patterns A, B, C and D, according to an embodiment of the present invention.
  • FIG.7A is a schematic plan view showing a fourth example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention.
  • FIG.7C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention.
  • FIG.7A is a schematic plan view showing a fourth example of a 2D IC-layer pattern according to another embodiment of the current invention with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG.7B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the
  • FIG. 8A is a schematic plan view showing a fifth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 8B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention.
  • FIG. 8C is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention.
  • FIG. 9A is a schematic plan view showing a sixth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 9A is a schematic plan view showing a sixth example of a 2D IC-layer pattern with sub-lithographic features and feature pitch, according to an embodiment of the present invention.
  • FIG. 9B is a schematic plan view showing ID patterns labeled A, B, C which when overlaid form a 2D pattern, according to an embodiment of the present invention.
  • FIG. 9A is a schematic plan view showing a corresponding set of dark-field lithographic mask features that can be used in conjunction with tilted ion implantation to define the three ID patterns A, B and C, according to an embodiment of the present invention.
  • a minimum feature size of each of the mask patterns can be less than or equal to the lithographic resolution limit .Pmin/2, for example.
  • an embodiment of the present invention provides a method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two-dimensional pattern.
  • the method includes providing a substrate comprising a substructure and a hard mask layer formed on the substructure.
  • the method further includes performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer.
  • the method also includes selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two-dimensional pattern in the hard mask layer.
  • the method further includes etching the substructure of the substrate in exposed regions to transfer the two- dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two-dimensional structure therein.
  • the angle a may be equal to substantially 90 degrees.
  • the method further includes removing remaining portions of the hard mask from the substructure of the substrate.
  • the performing the plurality of sequential photolithographic and tilted ion implantation processes includes resolving the sub- lithographic two-dimensional pattern as a plurality of linear patterns for performing a plurality of sequential photolithographic and tilted ion implantation processes.
  • the method may further includes performing additional processing steps such that the method is a method of producing an integrated microsystem.
  • the method may also include performing additional processing steps such that the method is a method of producing a micro-electro-mechanical (MEM) or nano- electro-mechanical (NEM) device.
  • providing the substrate may include forming the hard mask layer on the substructure of the substrate.
  • providing the substrate comprises forming the hard mask layer on the substructure of the substrate. In an embodiment, providing the substrate comprises providing a substrate having a semiconductor layer. In an embodiment, the method may further include forming the hard mask layer on the substructure, the hard mask layer comprising an oxide layer.
  • the oxide layer may include silicon oxide (Si0 2 ).
  • performing the tilted ion implantation processes includes introducing impurity atoms in precise amounts into a selected surface region of the hard mask layer.
  • the impurity atoms may be introduced over a range of depths depending upon an energy of incident ions on the surface, for example.
  • the implantation tilt angle can also be adjusted in a range from -60° to +60° depending on desired implantation configuration, for example.
  • Another embodiment of the present invention is to produce a device according to the above described method.
  • the device includes a two-dimensional pattern having a minimum feature pitch smaller than a minimum pitch of a photolithographic process and having a minimum feature size smaller than a photolithographic resolution limit that is achieved solely by using a photolithographic process without using ion implantation.
  • Another embodiment of the present invention is to provide a structure for producing a device having sub-lithographic two-dimensional structures.
  • the device includes a substrate having a substructure and a hard mask layer formed on the substructure.
  • the hard mask layer defines a two-dimensional pattern therein that exposes the substructure of the substrate according to the two-dimensional pattern.
  • sub-lithographic is intended to refer to feature sizes and/or spacing between features that are smaller than that which can be achieved with a corresponding photolithographic process itself.
  • the "pitch" of linear features is defined as the distance between their centerlines. For the case in which a patterning process produces the smallest feature size and/or pitch that is possible with a single photolithographic exposure step at the time (i.e., at the resolution limit of photolithography), a sub-lithographic process produces feature sizes and/or achieves feature pitches that are even smaller.
  • the broad concepts of methods according to some embodiments of the current invention are not limited to only this example. In some cases, it may be desirable to use methods in accordance with some embodiments of the current invention in combination with feature and/or pitch sizes that are larger than the resolution limit of the photolithographic process.
  • photolithography is intended to refer to any lithographic processes that use "light” (i.e., electromagnetic radiation) of any wavelength including, but not limited to, visible light, ultraviolet light, deep ultraviolet light, and extreme ultraviolet light, for example.
  • photolithographic process is intended to have a broad definition that can include multiple steps such as, but not limited to, forming a layer of photoresist, exposing the photoresist layer to a pattern of light, and developing the photoresist layer to remove one of regions exposed to the light or regions unexposed to the light. It can also include additional deposition and processing steps, including, but not limited to multiple photolithographic processes.
  • ion implantation process is intended to refer to any process by which ions are impacted into a solid to change the physical, chemical, or electrical properties of the solid.
  • tiltted ion implantation is intended to refer to an ion implantation process in which the trajectory of the ions is not substantially orthogonal to the surface of the solid.
  • linear pattern or "one-dimensional pattern” is intended to mean a pattern with one or more features that each extends in only one direction, with a substantially uniform width along its length, as is understood within the art.
  • two-dimensional pattern is intended to mean a pattern having features that extend in two orthogonal directions.
  • two-dimensional structure is intended to mean a structure having features that extend in two orthogonal directions within the same layer.
  • a two-dimensional pattern can be resolved as a combination of a plurality of linear patterns that can be defined sequentially.
  • the broad concepts of the current invention are not limited to only two- dimensional patterns that can be resolved as a combination of linear features.
  • ion implant defined pattern is intended to refer to a pattern that is defined by one or more ion implantation processes. Regions outside of the ion implant defined pattern may or may not have been subjected to an ion implantation process.
  • the term "hard mask layer” is intended to refer to a material layer that is patterned according to one or more processes and that is subsequently used as a mask to transfer its pattern to an underlying material layer.
  • the processes can include ion implantation processes using embodiments of the current invention either with or without other conventional processes in the same layer in some embodiments.
  • substrate' is intended to have a broad definition which can include a simple structure such as, but not limited to, a semiconductor wafer with a hard mask layer, but can in other embodiments be a more complex structure in itself having one or more additional layers of materials and/or other previously produced substructures.
  • the semiconductor wafer can be, but is not limited to, a silicon wafer, for example.

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

L'invention concerne un procédé de production d'un micro-dispositif ou d'un nano-dispositif ayant au moins une couche avec un motif bidimensionnel sous-lithographique. Le procédé consiste à : fournir un substrat comprenant une sous-structure et une couche de masque dur formée sur la sous-structure; réaliser une pluralité de procédés de photolithographie séquentielle et d'implantation ionique inclinée pour produire un motif de régions à implantation ionique dans la couche de masque dur; graver sélectivement au moins une des régions à implantation ionique dans la couche de masque dur pour exposer la sous-structure afin de produire un motif bidimensionnel dans la couche de masque dur; et graver sélectivement la sous-structure du substrat dans des régions exposées pour transférer le motif bidimensionnel dans la couche de masque dur à la sous-structure du substrat de façon à produire une structure bidimensionnelle sous-lithographique à l'intérieur de celle-ci.
PCT/US2018/035461 2017-05-31 2018-05-31 Formation de motif bidimensionnel de couche de circuit intégré par implantation ionique inclinée WO2018222915A1 (fr)

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CN111640654A (zh) * 2019-03-01 2020-09-08 中芯国际集成电路制造(上海)有限公司 图形化方法及图形化结构
CN111933525A (zh) * 2020-09-22 2020-11-13 南京晶驱集成电路有限公司 刻蚀方法
CN113539794A (zh) * 2020-04-22 2021-10-22 芯恩（青岛）集成电路有限公司 半导体结构及其制备方法

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111640654A (zh) * 2019-03-01 2020-09-08 中芯国际集成电路制造(上海)有限公司 图形化方法及图形化结构
CN111640654B (zh) * 2019-03-01 2023-07-14 中芯国际集成电路制造(上海)有限公司 图形化方法及图形化结构
CN113539794A (zh) * 2020-04-22 2021-10-22 芯恩（青岛）集成电路有限公司 半导体结构及其制备方法
CN113539794B (zh) * 2020-04-22 2024-06-04 芯恩（青岛）集成电路有限公司 半导体结构及其制备方法
CN111933525A (zh) * 2020-09-22 2020-11-13 南京晶驱集成电路有限公司 刻蚀方法

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