WO2018219195A1 - 一种译码方法及译码器 - Google Patents

一种译码方法及译码器 Download PDF

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Publication number
WO2018219195A1
WO2018219195A1 PCT/CN2018/088113 CN2018088113W WO2018219195A1 WO 2018219195 A1 WO2018219195 A1 WO 2018219195A1 CN 2018088113 W CN2018088113 W CN 2018088113W WO 2018219195 A1 WO2018219195 A1 WO 2018219195A1
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bit group
bms
path
paths
group
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PCT/CN2018/088113
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English (en)
French (fr)
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张涛
郑征
杜政
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华为技术有限公司
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Priority to US16/695,835 priority Critical patent/US20200106462A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
    • H03M13/3927—Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3961—Arrangements of methods for branch or transition metric calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3784—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 for soft-output decoding of block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Definitions

  • the present application relates to the field of communications, and in particular, to a decoding method and a decoder.
  • Polarization code is based on channel polarization theory. It is considered that after channel combination, N times transmission of the same channel will cause channel polarization, so that the capacity of a part of channels is close to 1, and the capacity of a part of channels is close to 0, and N The larger the ratio of the two parts of the channel, the higher the ratio, which is considered to be a coding scheme that can theoretically prove that the channel capacity is reachable.
  • the effective decoding algorithm of the Polar code is a Successive Cancellation (SC) algorithm, that is, the estimated value of the next bit of the block to be coded can be estimated according to the received signal and the existing bit.
  • SC Successive Cancellation
  • the sequence is determined one by one by calculating the transition probability of the channel with the next bit of 0 or 1. Since the communication rate is improved, the performance of the simple SC algorithm cannot meet the decoding requirement.
  • SC Successive Cancellation
  • continuous A Successive Cancellation List (SCL) algorithm that saves L bits from a preferred path of the next bit or group of bits by saving the L bit metrics of the current bit or group of bits. The basic path is split and sorted to select the optimal path.
  • the embodiment of the present application provides a decoding method and a decoder to solve the problem of high decoding and low decoding efficiency brought about by the SCL algorithm decoding process.
  • a first aspect of the embodiments of the present application provides a decoding method, in which a log likelihood ratio of a first bit group is first calculated according to a path selection result of a second bit group in a currently decoded code block.
  • Log Likelihood Ration, LLR for short and calculating a branch metric (Branch Metric, BM for short) of the first bit group according to the LLR, wherein the BM includes L group BM, and the L group BM has one-to-one correspondence with L paths.
  • the number of BMs in each group of BMs is 1/L of the total number of BMs, and then for each of the L paths, at least L BMs are selected from a group of BMs corresponding to each path, respectively.
  • PM a Metric
  • the BM of the first bit group obtained directly from the second bit group of the Kth bit group located before the first bit group is equivalent to the path of the previous bit group without considering the first bit group.
  • the BM of the first bit group is calculated, and then, after obtaining the path selection result of the previous bit group, only the path selection result according to the previous bit group of the first bit group and The selected BM can determine the PM, that is, the PM of the previous bit group of the first bit group plus the BM calculated by the first bit group can obtain the PM of the first bit group, thereby being able to determine the path selection according to the PM.
  • each of the bit groups includes M bits, and M is an integer greater than or equal to 1, thereby calculating LLRs of the first bit group in the code block to respectively calculate that the first bit group corresponds to 2 KM-K LLRs of each of the L paths, where L is 2 N , where N is an integer greater than or equal to 0; and calculating the BM of the first bit group according to the LLR is variable Calculating L*2 KM-K BMs of the first bit group according to the 2 KM-K LLRs corresponding to each of the L paths. It can be seen that when calculating the BM, for each branch, the default is to eliminate half of the number, thus reducing the amount of calculation and improving the execution efficiency.
  • selecting at least L BMs from a group of BMs corresponding to each path may be for each of the L paths And selecting at least L BMs according to a preset rule from 2 KM-K BMs corresponding to each path. It can be seen that in order to calculate L optimal PMs, at least L PMs need to be calculated for each path, so that L optimal ones of the finally obtained PMs can be guaranteed.
  • selecting at least L BMs according to a preset rule from 2 KM-K BMs corresponding to each path may be Each of the L paths respectively sorts the absolute values of 2 KM-K BMs or 2 KM-K BMs corresponding to the paths by numerical presets, from the sorted 2 KM-K In the BM, L BMs are selected according to a preset rule.
  • each path corresponds to 2 KM-K BMs, but only L BMs can be selected therefrom, which can reduce the calculation amount and improve the execution efficiency. .
  • the PM may be that, for any of the L paths, the PM of the path is added to at least L BMs corresponding to the path to obtain at least L PMs; and at least L rows corresponding to the L paths In the L*L PMs, L PMs are selected as the PM of the first bit group according to a preset preset rule. Therefore, when actually selecting, it is only necessary to select the largest L PMs among at least L*L PMs, thereby ensuring that the selected L PMs are the optimal L of at least L*L PMs.
  • the manner of selecting the largest L PMs from the L*L PMs may be as follows. Specifically, the largest L PMs are selected from the L*L PMs of the L paths.
  • the PM of the current bit group includes: firstly, the L paths are divided into X groups of path groups, and each group of the path groups respectively performs PM comparison to obtain L PMs, and each group of the path groups includes 2 Y paths.
  • the Y is an integer greater than or equal to 0; the largest L PMs are selected from the obtained (L/2 Y )*L PMs as the PM of the current bit group. It can be seen that this method firstly groups L*L PMs and then further selects them from the packets, and the grouping manner is a multiple of 2.
  • the preset rule may be: selecting the L objects having the largest value from the object value set; or selecting the L objects having the smallest value from the object set; or selecting the largest absolute value from the object set L objects; or, select L objects with the smallest absolute value from the object set; wherein the object is BM or PM. It can be seen that the preset rule actually includes four cases, that is, selecting a large, small, large absolute value, and a small absolute value, and the four types can respectively correspond to different algorithms, thereby enhancing the solution of the embodiment of the present application. Scalability.
  • the second bit group is a starting bit group in the coded block, and calculating a path selection result of the second bit group may be first calculating an LLR of the second special group; The LLR of the second bit group calculates the BM of the second bit group; after that, L BMs are selected from the calculated BM of the second bit group; and the second bit group is further calculated according to the selected L BMs PM; finally, determining a path selection result of the second bit group according to the PM of the second bit group.
  • the path selection result of the first N bit groups is not required because of the particularity of the first bit group.
  • the second bit group is not needed.
  • the path selection result of the first N bit groups that is, the first bit group and the second bit group can be decoded in parallel.
  • a second aspect of the embodiments of the present application further provides a decoder, the apparatus comprising at least one unit for performing the decoding method provided in the first aspect or any one of the implementations of the first aspect.
  • the third aspect of the embodiment of the present application further provides a communication device, which includes a processor, a transceiver, a memory, and a decoder in the second aspect of the embodiment of the present application.
  • Yet another aspect of the present application provides a computer readable storage medium having stored therein instructions that, when executed on a decoder, cause the decoder to perform the methods described in the above aspects .
  • Yet another aspect of the present application provides a computer program product comprising instructions that, when executed on a decoder, cause the decoder to perform the methods described in the various aspects above.
  • 1 is a schematic diagram of channel combination of two channels
  • FIG. 5 is a diagram of an embodiment of a decoding method according to an embodiment of the present application.
  • FIG. 6 is a diagram of an embodiment of a decoding method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the sorting process in the list and the sorting between the lists in FIG. 6;
  • FIG. 8 is a diagram of an embodiment of a decoder in an embodiment of the present application.
  • FIG. 9 is a diagram of an embodiment of a communication device according to an embodiment of the present application.
  • the embodiment of the present application provides a decoding method, which performs serial execution on a part of a decoding process, thereby greatly reducing decoding delay and improving decoding efficiency.
  • the set (s 1 , s 2 , s 3, ..., s N ) becomes a set of v N (s 1 , s 3 , ..., s N-1 , s 2 , s 4 , ..., s N ).
  • the current node is the first node and the third node of the second level
  • the next level of the first node of the second node is first calculated.
  • the BM of the node, for the first node of the second level, the possible next level node is the BM of the first node of the third level and the BM of the second node of the third level, and then the third level is calculated.
  • the PM of the fifth node of the third level is calculated to be 0.27, and the PM of the sixth node of the third level is 0.03, and two nodes are also reserved, and two nodes with larger PMs are selected from the four nodes as path selection. , which is The fifth node and the second node of the third three-level hierarchy.
  • the number of PMs of the nodes of the next level that need to be calculated each time is 2 a , where a represents the number of bits in the bit group.
  • the LLR is a signed number
  • the BM based on the LLR calculation also has positive numbers and negative numbers.
  • FIG. 5 is a diagram of an embodiment of a decoding method according to an embodiment of the present application.
  • the method may include:
  • the second bit group is the Kth bit group in the code block before the first bit group, the K is an integer greater than or equal to 2, and the path selection result includes L paths, where L is greater than An integer equal to 1. That is, the first bit group of the present application is actually the first N bit groups of the first bit group, and according to the strength of the decoder performance and the decoding efficiency, the first N bits may be specifically determined.
  • the LLR refers to the ratio of the probability that the node is 0 is correct for any node and the probability that the node is 1 is correct, and then the LLR is obtained by taking the ratio as a logarithm.
  • the first bit group can calculate the different number of the first bit group according to the position of the first bit group in the decoded block without considering the path selection result of the previous bit group of the first bit group.
  • BM which corresponds to the BM of all possible visited nodes of the first bit group in the binary tree structure in the SCL algorithm.
  • the path selection result is actually selecting an optimal path according to the PM.
  • the path selection result is as indicated by the arrow in FIG.
  • the path of the node, that is, the result of the path selection is L branches of various branches of the binary tree in SCL or similar algorithms.
  • the BM can be calculated.
  • two BMs that is, two branches of 0 and 1 can be calculated.
  • the BM includes an L group BM, and the L group BM has a one-to-one correspondence with the L paths, and the number of BMs in each group BM is 1/L of the total number of BMs, that is, the number of BMs of the first bit group. It is obtained by adding the BMs corresponding to the L paths respectively.
  • the calculated number of BMs varies according to the number of paths and the number of bits included in each bit group. If the first bit group and the previous bit group of the first bit group both contain M bits, the path The LLR of the first bit group in the code block may be calculated by calculating the 2 KM-K LLRs of the first bit group corresponding to each of the L paths. Where L is 2 N , where N is an integer greater than or equal to zero.
  • calculating the BM of the first bit group according to the LLR may specifically calculate L*2 KM-K BMs of the first bit group according to the 2 KM-K LLRs, that is, calculate The first bit group has a total of L*2 KM-K BMs, that is, it can correspond to L*2 KM-K nodes.
  • PSUM is the hard value of the intermediate node
  • LLR refers to the log likelihood ratio corresponding to all possible outcomes of the end bits
  • PSUM refers to the hard value corresponding to each LLR.
  • the hard value is determined by the soft value such as LLR, that is, the original may be 0 may be determined as one of them. It can be known from the above formula that for different BMs of the same path, the M symbol can be selected according to the sign positions of PSUM and LLR. /2 paths.
  • the selection process of the BM can be performed, in order to ensure that the optimal L BMs are selected to be finally desired, specifically, in the case of L paths, corresponding to each path, It is necessary to select at least L of the BM groups calculated from each path, so as to ensure that the BM corresponding to one path that is likely to occur calculates the optimal L PMs of all the first bit groups instead of corresponding to multiple paths.
  • the BM calculates the optimal L PMs respectively.
  • the manner of selecting at least L BMs according to a preset rule from 2 KM-K BMs corresponding to each path may be preset.
  • the rules may be directly selected, or may be sorted first, and then selected by a preset rule, whichever method is selected, is the optimal L BMs when the adopted algorithm corresponds to the preset rule.
  • the process may be: selecting at least L BMs from the 2 KM-K BMs of the first bit group corresponding to each of the L paths according to a preset preset rule.
  • an X object is selected according to a preset rule from the object set, and X is an integer greater than or equal to 1.
  • the preset rule may be in the object set.
  • the X objects with the largest value of the object may also be the X objects with the smallest value of the object in the object set.
  • the X object with the largest absolute value of the object value, and the absolute value of the value of the object may be the smallest.
  • the X object of course, the object can be BM or PM. Which one can be used depends on the algorithm.
  • the largest L BMs may be selected; and if, for example, the algorithm is specifically the smallest BM is optimal, then the smallest L BMs may be selected.
  • the algorithm is specifically that the BM with the largest absolute value is optimal, then the L BMs with the largest absolute value may be selected.
  • the absolute value is the smallest. L BM can be.
  • selecting L BM modes according to the sorting manner may be, for any one of the L paths, respectively, 2 KM-K BMs or 2 KM-K of the first bit groups corresponding to the paths.
  • the absolute value of the BM is preset, and after the preset sorting is completed, one of the preset rules required by the specific algorithm may be selected from the preset sorting of the 2 KM-K BMs arranged in order. Select L BMs.
  • the selected node of the current bit group can be determined. Specifically, taking the first bit group as a bit as an example, the node corresponding to the previous bit of the first bit group splits two nodes. Since all the BMs are sorted before, the two nodes are also Sorting is performed. In this case, the larger one of the nodes can be directly selected, and then the PM of the node corresponding to the previous bit is added to the BM of the selected node to obtain the PM of the selected node, that is, the current bit group. One bit of PM in.
  • the calculated BM is a multi-bit BM corresponding to the bit group, instead of the BM of each bit of the multiple bits in the first bit group, and the specific BM calculation method
  • the specific BM calculation method refer to the description of step 502, and details are not described herein again.
  • determining the selected L paths according to the path selection result of the previous bit group of the first bit group that is, determining L end nodes of the previous bit group; and then, for any path of the L paths, the path is
  • the PM is added to the BM of the first bit group corresponding to the path to obtain L PMs; then, L PMs are selected as preset PMs from at least L*L PMs of the L paths as the first bit group.
  • the process of selecting the largest L PMs from the at least L*L PMs of the L paths as the PM of the first bit group may be:
  • the L paths are divided into X groups of path groups, and each group of path groups respectively obtains PM PMs after PM comparison, and each group of the path groups includes 2 Y paths, and the Y is greater than or equal to 0. Integer
  • the largest L PMs are selected from the obtained (L/2 Y )*L PMs as the PM of the current bit group.
  • L is 8
  • Y is 1, and 8 paths are grouped into two groups, which are divided into four groups, and (8/2 1 )*8, that is, 32 from 8*8 PMs. PM, and then select the largest 8 PMs from 32 PMs.
  • 8/2 1 )*8
  • the specific calculation method may be different according to the actual calculation requirements. For example, when L is small, L*L may be directly sorted. For example, when L is large, the data is sorted first, and then combined and sorted.
  • the path selection of the current bit group can be performed, because the PM includes the BM corresponding to the M bits of the current bit group and the corresponding corresponding to the current bit group.
  • the path of one bit group therefore, according to the PM, a new path selection can be performed, and after the L paths are all selected, the path selection result of the current bit group can be obtained.
  • each PM in the first List is compared with a corresponding PM in the second List.
  • the PM in each List is also already sorted.
  • a double-tone sorting algorithm is generally adopted, that is, the first algorithm for the inter-list algorithm is needed. List and the first List, if the first List is monotonically increasing, the second List is monotonically decreasing, or if the first List is monotonically decreasing, the second List is monotonically increasing. Therefore, in this comparison process, the first PM of the first List is compared with the last PM of the second List, and the second PM of the first List is compared with the second PM of the second List. And so on, the last PM of the first List is compared with the first PM of the second List.
  • the sorted first List and the first L PMs in the second List are selected for sorting.
  • This step needs to be sorted, and the sorting includes three steps, and the first step is to The first PM is compared with the fifth PM, the second PM is compared with the sixth PM, the third PM is compared with the seventh PM, and the fourth PM is compared with the eighth PM; then the second step Comparing the first PM after the first step with the third PM, comparing the second PM with the fourth PM, comparing the fifth PM with the seventh PM, the sixth PM and the eighth PM comparison; finally, the second PM is compared with the first PM and the second PM, the third PM is compared with the fourth PM, and the fifth PM is compared with the sixth PM, the seventh The PM is compared with the 8th PM to complete the ordering of 8 PMs.
  • the path of the current bit group can be selected according to the sort result.
  • FIG. 6 is a diagram of an embodiment of a decoding method in the embodiment of the present application
  • the process of sorting in List is explained.
  • This step includes a total of six steps, with the first List as an example:
  • Step 3 Compare the first BM after sorting in step 2 with the second BM, compare the third BM with the fourth BM, compare the fifth BM with the sixth BM, and the seventh BM and the eighth
  • Step 4 Comparing the first BM sorted in step 3 with the eighth BM, comparing the second BM with the seventh BM, comparing the third BM with the sixth BM, and the fourth BM and the fifth
  • Step 5 Comparing the first BM sorted in step 4 with the third BM, comparing the second BM with the fourth BM, comparing the fifth BM with the seventh BM, and the sixth BM and the eighth
  • B 13 0.05
  • B 15 0.03
  • B 16 0.08
  • B 14 0.09
  • B 11 0.11
  • B 18 0.12
  • B 17 0.14
  • B 12 0.21.
  • Step 6 comparing the first BM sorted in step 5 with the second BM, comparing the third BM with the fourth BM, comparing the fifth BM with the sixth BM, and the seventh BM and the eighth
  • two Lists have a total of 16 PMs, that is, the first PM is compared with the 16th PM, and the second PM is compared with the 15th PM, and the third PM is compared with the 14th PM. 4 PM vs. 13th PM, 5th PM vs. 12th PM, 6th PM vs. 11th PM, 7th PM vs. 10th PM, 8th PM and 9 PM comparisons, so that the 8 PMs of the top 8 of the two lists are ranked in the first 8 positions of the sequence.
  • the sorting consists of three steps:
  • Step 1 Compare the first PM with the fifth PM, compare the second PM with the sixth PM, compare the third PM with the seventh PM, and compare the fourth PM with the eighth PM;
  • Step 2 Compare the first PM after the comparison with the third PM, compare the second PM with the fourth PM, compare the fifth PM with the seventh PM, and the sixth PM and the third 8 PM comparisons;
  • Step 3 Compare the first PM after the second step with the second PM, compare the third PM with the fourth PM, compare the fifth PM with the sixth PM, and the seventh PM and the third 8 PM comparisons, finishing 8 PM sorts.
  • FIG. 8 is a schematic diagram of a decoder according to an embodiment of the present application, where The decoder is applied to polarization code decoding, and the decoder includes:
  • the calculating module 801 calculates an LLR of the first bit group in the code block according to a path selection result of the second bit group in the currently coded code block, where the second bit group is in the code block a K-th bit group located before the first bit group, where K is an integer greater than or equal to 2, the path selection result includes L paths, and L is an integer greater than or equal to 1; the calculation module 801 is further configured to Calculating, by the LLR, the BM of the first bit group, where the BM includes an L group BM, the L group BM is in one-to-one correspondence with the L paths, and the number of BMs in each group BM is 1/L of the total number of BMs; the processing module 802 is configured to select at least L BMs from a group of BMs corresponding to each path for each of the L paths; the processing module 802 And determining, according to a path selection result of each of the L paths, and a previous bit group of the first bit group, a path metric value PM of the
  • the calculation module 801 directly obtains the BM of the first bit group obtained from the second bit group of the Kth bit group located before the first bit group, that is, the previous bit of the first bit group is not considered.
  • the BM of the first bit group is calculated, and then, after the processing module 802 acquires the path selection result of the previous bit group, only the previous bit of the first bit group needs to be used.
  • the path selection result of the group and the selected BM can determine the PM, that is, the PM of the previous bit group of the first bit group plus the BM calculated by the first bit group can obtain the PM of the first bit group, thereby being able to The PM determines the path selection result.
  • each bit group in the code block includes M bits, and the M is an integer greater than or equal to 1.
  • the calculation module 801 is specifically configured to calculate a path corresponding to each of the L paths. 2 KM-K LLRs of the first bit group, where L is 2N, where N is an integer greater than or equal to 0; calculating L*2 KM of the first bit group according to the 2 KM-K LLRs - K BM.
  • BM For the specific method of calculating the BM, refer to the description of the step 502 in the embodiment shown in FIG. 5, and details are not described herein again.
  • the processing module 802 is specifically configured to: select, for each of the L paths, at least L BMs according to a preset rule from 2 KM-K BMs corresponding to each path.
  • select, for each of the L paths at least L BMs according to a preset rule from 2 KM-K BMs corresponding to each path.
  • the calculating module 801 is specifically configured to: for each path in the L paths, respectively, 2 KM-K BMs or 2 KM-K BMs of the first bit group corresponding to the path
  • the absolute values are sorted by default, and L BMs are selected according to a preset rule from the preset ordering of the 2 KM-K BMs.
  • L BMs are selected according to a preset rule from the preset ordering of the 2 KM-K BMs.
  • the processing module 802 is specifically configured to: add, to any one of the L paths, the PM of the path to at least L BMs corresponding to the path to obtain at least L PMs; Among the at least L*L PMs corresponding to the strip path, L PMs are selected as the PM of the first bit group according to a preset preset rule. Specifically, for the manner of selecting at least L PMs, refer to the description of step 504 in the embodiment shown in FIG. 5, and details are not described herein again.
  • the processing module 802 is specifically configured to divide the L*L path into X groups of path groups, and each group of the path groups respectively performs PM comparison and obtains L PMs according to preset preset rules.
  • the group of the path group includes 2 Y paths, and the Y is an integer greater than or equal to 0; selecting L PMs as the first bit from the obtained (L/2 Y )*L PMs according to a preset preset rule Group of PM.
  • selecting at least L PMs refer to the description of step 504 in the embodiment shown in FIG. 5, and details are not described herein again.
  • selecting X objects according to the preset rule from the object set includes: selecting a maximum of X objects from the object value set; or selecting a minimum X objects from the object set; Or, select X objects having the largest absolute value from the object set; or select X objects having the smallest absolute value from the object set; wherein the object is BM or PM, and the X is an integer greater than or equal to 1.
  • selecting X objects according to the preset rule from the object set includes: selecting a maximum of X objects from the object value set; or selecting a minimum X objects from the object set; Or, select X objects having the largest absolute value from the object set; or select X objects having the smallest absolute value from the object set; wherein the object is BM or PM, and the X is an integer greater than or equal to 1.
  • the second bit group is a starting bit group in the code block, where the starting bit group is the first bit group in the code block, in this case, the specific second bit group
  • the path selection result is calculated as follows: First, the calculation module 801 calculates the LLR of the second bit group; then, the calculation module 801 calculates the BM of the second bit group according to the LLR of the second bit group; The processing module 802 selects L BMs from the BM of the second bit group to be calculated; and the processing module 802 calculates the PM of the second bit group according to the selected L BMs; finally, the processing module 802 is configured according to The PM of the second bit group determines a path selection result of the second bit group.
  • a functional module such as a computing module and a processing module of the decoder may be a large-scale integrated circuit (LSI).
  • the decoder is implemented in various ways by the LSI, such as a digital signal processing (DSP) method and a Field Programmable Gate Array (FPGA) method.
  • DSP digital signal processing
  • FPGA Field Programmable Gate Array
  • the calculation module and processing can be fabricated as separate or separate chips.
  • the two functional modules can also be fabricated as separate chips containing the two functional modules or more functional modules.
  • the LSI may be referred to as an integrated circuit (IC), a system-level LSI, a very large-scale LSI, or a very large-scale LSI based on integration.
  • FIG. 9 is a schematic diagram of a communication device according to an embodiment of the present application, where the communication device 9 is applied.
  • Polarized code decoding the communication device 9 includes a decoder 901 and a transceiver 902 in the embodiment shown in FIG. 8, wherein the transceiver 902 is configured to receive a code stream; and the decoder 901 is configured to acquire a code stream.
  • the code block and the parameters of the code block; the decoder 901 can then decode according to the parameters of the code block and the code block to generate a decoding result; finally, the decoder 901 outputs the decoding result.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • wire eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be stored by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a Solid State Disk, SSD for short).
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in the embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • a computer readable storage medium A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

本申请涉及通信领域，具体涉及一种译码方法及译码器。该译码方法包括根据当前被译码的码块内的第二比特组的路径选择结果，计算码块内的第一比特组的LLR；路径选择结果包含L条路径；根据LLR计算第一比特组的BM；对于L条路径中的每一条路径，选择至少L个BM；根据至少L个BM和第一比特组的前一个比特组的路径选择结果，确定第一比特组的PM；根据PM确定第一比特组的路径选择结果。本申请的整个译码过程中无需进行PM排序，在进行第一比特组的译码时，只需要在当前比特组的PM计算阶段时，能够获取到上一比特组的路径选择结果即可，从而能够使得在译码过程中，在PM计算阶段之前的其他阶段均可并行，从而大大降低译码时延，提高译码效率。

Description

一种译码方法及译码器
本申请要求于2017年5月27日提交中国专利局、申请号为201710391333.5、发明名称为“一种译码方法及译码器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，具体涉及一种译码方法及译码器。
背景技术
极化(Polar)码基于信道极化理论，认为信道组合后，同一个信道的N次传输，将会发生信道极化，使得一部分信道的容量接近1，而一部分信道的容量接近0，且N越大，这两部分信道的比例越高，被认为是可以在理论上证明是信道容量可达的编码方案。
由于Polar码结构化的编码方式，Polar码的有效译码算法是连续消除(Successive Cancellation，简称SC)算法，即对待译码块的下一比特的估计值可以根据接收信号和已有的比特估计序列通过计算下一比特为0或为1的信道的转移概率进行逐个判决，由于通讯速率的提高，单纯的SC算法的性能已无法满足译码需求，在此SC算法的基础上，产生了连续消除列表(Successive Cancellation List，简称SCL)算法，该算法通过保存当前比特或比特组的L个度量值较优的比特序列路径，在下一比特或比特组译码的优选路径从保存的L个比特序列路径上基础进行分裂并排序选取较优路径。
然而，在SCL算法译码过程中，每次选取下一比特或比特组的序列路径需要依赖当前比特或比特组的序列路径的分裂后的排序结果，即需要依赖上一比特或比特组的选择结果，所以需要依次串行处理所有比特或比特组，从而形成关键路径，其译码时延较高，导致译码效率低。
发明内容
本申请实施例提供了一种译码方法及译码器来解决SCL算法译码过程中带来的译码高，译码效率低的问题。
本申请实施例的第一方面提供一种译码方法，该方法中，首先会根据当前被译码的码块内的第二比特组的路径选择结果计算第一比特组的对数似然比(Log Likelihood Ration，简称LLR)以及根据该LLR计算第一比特组的分支度量值(Branch Metric，简称BM)，其中，该BM中包括L组BM，L组BM与L条路径一一对应，且每组BM中的BM的数量均为BM的总数的1/L，接着对于L条路径中的每条路径，分别从与每条路径相对应的一组BM中，选择至少L个BM，根据为L条路径中每条路径分别对应的所述至少L个BM，和，所述第一比特组的前一个比特组的路径选择结果，确定所述第一比特组的路径度量值(Path Metric，简称PM)，L条路径分别对应的至少L个BM和所述第一比特组的前一个比特组的路径选择结果，确定所述第一比特组的路径度量值PM,最后，按照该PM确定当前比特组的路径选择结果。
可以看出，由于直接根据位于第一比特组之前的第K个比特组的第二比特组得到的第 一比特组的BM，即相当于在不考虑第一比特组的前一个比特组的路径选择结果的情况下，将该第一比特组的BM均计算出来，接着，在获取到上一比特组的路径选择结果后，仅需要根据第一比特组的前一个比特组的路径选择结果和选择出的BM即可确定出PM，即第一比特组的前一个比特组的PM加上第一比特组计算的BM即可得到第一比特组的PM，从而能够根据该PM确定出路径选择结果，可见，整个译码过程中无需进行PM排序，在进行第一比特组的译码时，也无需等待第一比特组的前一个比特组的路径选择完成，只需要在当前比特组的PM计算阶段时，能够获取到上一比特组的路径选择结果即可，从而能够使得在译码过程中，在PM计算阶段之前的其他阶段均可并行，从而大大降低译码时延，提高译码效率。
在一些实施例中，每个所述比特组包含M个比特，M为大于等于1的整数，从而计算所述码块内的第一比特组的LLR为分别计算所述第一比特组对应于所述L条路径中每一条路径的2 KM-K个LLR，其中，L为2 N，其中N为大于等于0的整数；并且根据所述LLR计算所述第一比特组的BM则可变为根据所述L条路径中每一条路径对应的所述2 KM-K个LLR计算所述第一比特组的L*2 KM-K个BM。可以看出，在计算BM时，对于每个分支，实际上默认是淘汰掉其中一半的数量，如此，可减小计算量，提高执行效率。
在一些实施例中，对于所述L条路径中的每条路径，分别从与每条路径相对应的一组BM中，选择至少L个BM可以是对于所述L条路径中的每条路径，分别从与每条路径相对应的2 KM-K个BM中，按照预设规则选择至少L个BM。可见，为了计算得到L个最优的PM，需要对每条路径均计算出至少L个PM，从而能够保证最终得到的PM中L个最优的。
在一些实施例中，对于所述L条路径中的每条路径，分别从与每条路径相对应的2 KM-K个BM中，按照预设规则选择至少L个BM可以是，对于所述L条路径中每条路径，均分别对所述路径对应的2 KM-K个BM或者2 KM-K个BM的绝对值进行按照数值预设进行排序，从排序后的所述2 KM-K个BM中按照预设规则选取L个BM。为了进一步减小后续的计算量，在具有L条路径时，实际上每条路径对应的2 KM-K个BM，但是仅从其中选取L个BM即可，可减小计算量，提高执行效率。
在一些实施例中，根据为所述L条路径中每条路径分别选择的至少L个BM，和，所述第一比特组的前一个比特组的路径选择结果，确定所述第一比特组的PM可以是，对所述L条路径中任一路径，均分别将所述路径的PM加上对应所述路径的至少L个BM得到至少L个PM；从所述L条路径对应的至少L*L个PM中按照预设的预设规则选择L个PM作为所述第一比特组的PM。从而在实际进行选择时，仅仅是在至少L*L个PM中选最大的L个PM即可，从而能够保证选的L个PM是至少L*L个PM中最优的L个。
在一些实施例中，从L*L个PM中选择最大的L个PM的方式可以是如下方式，具体的，从所述L条路径的L*L个PM中选择最大的L个PM作为所述当前比特组的PM包括：首先将所述L条路径分为X组路径组，每组所述路径组分别进行PM对比后分别得到L个PM，每组所述路径组包含2 Y个路径，所述Y为大于等于0的整数；从得到的(L/2 Y)*L个PM中选择最大的L个PM作为当前比特组的PM。可以看出，此方式是先将L*L个PM进行分组，而后从分组中再进一步选取，分组的方式为2的倍数。
在一些实施例中，预设规则可以是，从对象值集合中选择数值最大的L个对象；或，从对象集合中选择数值最小的L个对象；或，从对象集合中选择绝对值最大的L个对象； 或，从对象集合中选择绝对值最小的L个对象；其中，所述对象为BM或者PM。可以看出，该预设规则实际包括四种情况，即选取大的，小的、绝对值大的和绝对值小的，四种可分别对应到不同的算法，从而能够增强本申请实施例方案的可扩展性。
在一些实施例中，第二比特组为被译码块中起始比特组，计算该第二比特组的路径选择结果可以是首先计算所述第二特组的LLR；接着，根据所述第二比特组的LLR计算所述第二比特组的BM；之后，从计算出的所述第二比特组的BM中选取L个BM；再根据选取的L个的BM计算所述第二比特组的PM；最后，根据所述第二比特组的PM确定所述第二比特组的路径选择结果。可见，对于被译码块中的第一个比特组由于其排在第一个的特殊性，无需前N个比特组的路径选择结果，当然本申请实施例中，第二个比特组也无需前N个比特组的路径选择结果，即，第一个比特组和第二个比特组是可以并行执行译码的。
本申请实施例第二方面还提供一种译码器，该装置包括用于执行第一方面或第一方面的任一种实现方式中提供的译码方法的至少一个单元。
本申请实施例第三方面还提供一种通信设备，该通信设备包括处理器、收发器、存储器和本申请实施例第二方面中的译码器。
本申请的又一方面提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在译码器上运行时，使得译码器执行上述各方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在译码器上运行时，使得译码器执行上述各方面所述的方法。
附图说明
图1是两个信道的信道组合示意图；
图2是两个独立的W N信道进行组合示意图；
图3是SCL算法的流程示意图；
图4是SCL算法的一个实施例图；
图5是本申请实施例的译码方法的实施例图；
图6是本申请实施例的译码方法一个实施例图；
图7是图6中List内排序过程和List间排序示意图；
图8是本申请实施例的译码器的实施例图；
图9是本申请实施例的通信设备的实施例图。
具体实施方式
本申请实施例提供了一种译码方法，该方法通过对译码过程中的部分阶段进行串行执行，从而大大降低译码时延，提高译码效率。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例进行描述。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这 里图示或描述的内容以外的顺序实施。此外，术语“包括”或“具有”及其任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
信道极化是N个独立的信道变换为宽度为N的集合信道的过程，其中，N＝2 n，n≥0，这个过程中包括两个部分，即信道组合(Channel Combining)和信道拆分(Channel Splitting)，当N的值越大，信道对称容量(Symmetric Capacity)越趋于0或者1。如图1所示，图1为两个信道的信道组合示意图，对两个独立的信道W进行组合，得到信道W 2：X 2→Y 2，其中x 1＝u 1⊕u 2且x 2＝u 2。在此基础上，请参阅图2，图2是两个独立的W N信道进行组合示意图，若两个独立的W N信道进行组合产生一个W 2N信道，W 2N的输入向量u 2N首先转换成s 2N，对于任意1≦i≦N，存在s 2i-1＝u 2i-1⊕u 2i且s 2i＝u 2i，图2所示的H 2N是一个置换操作，其作者用是将s N集合(s 1，s 2，s 3，…，s N)变成v N集合(s 1，s 3，…，s N-1，s 2，s 4，…，s N)。
下面以List＝2，即L＝2，L为List的数量，为例对译码过程进行说明，译码按照逐比特进行译码，SCL算法的过程请参阅图3，图3是SCL算法的流程示意图，具体的，首先进行LLR计算以及BM计算，接着根据BM进行PM计算，再对PM进行排序，最后作出路径选择，并按照此选择结果进行下一轮的LLR和BM的计算，如此往复循环，完成译码过程。其中处理过程可参阅图4所示，图4为SCL算法的一个实施例图，其中，箭头方向表示路径选择过程，其中，填充节点表示被访问的节点，未填充节点，表示未访问节点，每个节点上的数字表示PM，除了根节点之外，在译码过程中，以当前比特为第二层级的第一节点和第三节点，首先计算第二层级第一节点的下一级可能的节点的BM，对于第二层级的第一节点来说，可能的下一级节点为第三层级的第一节点的BM和第三层级的第二节点的BM，再计算得到第三层级的第一节点的PM则为0.08，第三层级的第二节点的PM则为0.25，由于L＝2，因此无需进行排除，两个节点都予以保留，接着再针对第二层级的第二节点计算，计算得到第三层级的第五节点的PM为0.27，第三层级的第六节点的PM为0.03，同样保留两个节点，再从这四个节点中选取两个PM较大的节点作为路径选择，即第三层级的第二节点和第三层级的第五节点。同理，当采逐比特组进行译码时，每次需要计算的下一层级的节点的PM数量为2 a，其中a表示比特组内的比特数量。
需要说明的是，两条路径最终进行选择时，是按照所有分支的PM结果进行选择的，因此，可能出现被选择的两条路径的上一比特节点是同一个。
需要说明的是，由于LLR是有符号数，因此有正数也有负数，而基于LLR计算的BM同样也是有正数也有负数。
可以看出，上述方式，需要对L条路径的所有分裂情况的PM进行排序，只有经过优选的路径才能作为下一比特译码时的路径，且对每个比特译码都需要对路径进行排序，而正是由于此排序计算延时限制了Polar码SCL译码器的吞吐率的提升。
有鉴于此，本申请实施例提供一种译码方法，该译码方法是在SCL算法的基础上进行的改进，将原本SCL算法只能进行顺序执行改为可以并行执行，从而提高译码效率，具体的，请参阅图5，图5是本申请实施例的译码方法的实施例图，该方法可包括：
501、根据当前被译码的码块内的第二比特组的路径选择结果，计算码块内的第一比特组的对数似然比LLR。
其中，第二比特组为所述码块中位于所述第一比特组之前的第K个比特组，所述K为大于等于2的整数，所述路径选择结果包含L条路径，L为大于等于1的整数。即本申请的第一比特组实际是第一比特组的前N个比特组，按照译码器性能的强弱以及译码效率，可以具体确定到前N个即可。
需要说明的是，LLR指的是对于任意节点来说，判断该节点为0是正确的概率以及判断该节点为1是正确的概率进行比值，而后在将该比值取对数即得到LLR。
其中，第一比特组在不考虑第一比特组的前一比特组的路径选择结果的情况下，根据第一比特组位于被译码块中的位置，可以计算出第一比特组的不同数量的BM，该BM即对应SCL算法中二叉树结构中第一比特组的所有可能的访问的节点的BM。
需要说明的是，路径选择结果实际上是根据PM选择最优的路径，具体可参见图4，该路径选择结果，若按照L为2的情况下，路径选择结果为图4中箭头所示的节点的路径，即该路径选择结果是SCL或类似算法中的二叉树的各种不同分支中L个分支。
502、根据LLR计算第一比特组的BM。
可以看出，在完成LLR的计算后，即可计算BM，对于任意一个LLR，可以计算出两个BM，即0和1两个分支。
其中，BM中包括L组BM，所述L组BM与L条路径一一对应，且每组BM中的BM的数量均为BM的总数的1/L，即第一比特组的BM的数量是由L条路径分别对应计算的BM相加得到的。
其中，计算出的BM的数量，根据路径的数量以及每比特组包含的比特数量的不同有所不同，若第一比特组和第一比特组的前一比特组均包含M个比特，路径的数量为L，则计算所述码块内的第一比特组的LLR具体可以是，计算所述L条路径中每条所述路径对应的所述第一比特组的2 KM-K个LLR，其中，L为2 N，其中N为大于等于0的整数。在此情形下，根据所述LLR计算所述第一比特组的BM具体可以为根据所述2 KM-K个LLR计算所述第一比特组的L*2 KM-K个BM，即计算出的第一比特组一共有L*2 KM-K个BM，即能够对应到L*2 KM-K个节点。
需要说明的是，在比特组为多比特情况下的BM计算中，即当前比特组的可能结果的计算中，能够去掉其中一半的可能结果，即若当前比特组为M个比特，则当前比特组的所有可能结果为2 M/2，即2 M-1。下面对产生此情形的原因进行说明，下面是此情形下的多比特的BM计算公式：
Figure PCTCN2018088113-appb-000001
其中，M表示比特组中比特数，PSUM表示中间节点的硬值，以M＝4为例，LLR指末端比特的所有可能结果对应的对数似然比，PSUM指每个LLR对应硬值，该硬值即将LLR这类软值进行确定，即将原来可能为0可能为1确定为其中一个，由上述公式可知，对于同一条路径的不同BM，可以根据PSUM和LLR的符号位，筛选出M/2条路径。
503、对于L条路径中的每条路径，分别从与每条路径相对应的一组BM中，选择至少 L个BM。
其中，在完成BM的计算后，即可进行BM的选择过程，为了保证选择到最终想要的最优的L个BM，具体的，在L条路径的情况下，对应到每一条路径，均需要从每一条路径计算出的BM组中选出至少L个，从而确保有可能出现的一条路径对应的BM计算出所有的第一比特组的最优的L个PM而不是从多条路径对应的BM分别计算出最优的L个PM。
需要说明的是，对于所述L条路径中的每条路径，分别从与每条路径相对应的2 KM-K个BM中，按照预设规则选择至少L个BM的方式可以是按照预设规则直接选取，也可以是先进行排序，而后再通过预设规则进行选取，不论哪一种方式选取，均是选择所采用算法对应到预设规则时的最优的L个BM。具体的，该过程具体可以是从所述L条路径中的每一条路径对应的所述第一比特组的2 KM-K个BM中按照预设的预设规则分别选择至少L个BM。其中，预设规则有多种情况，根据采用算法的不同而有所不同，例如，从对象集合中按照预设规则选择X对象，X为大于等于1的整数，该预设规则可以对象集合中对象的值最大的X个对象，也可以是对象集合中对象的值最小的X个对象，当然还可以是对象的值的绝对值最大的X对象，以及还可以是对象的值的绝对值最小的X对象，当然，该对象可以是BM也可以是PM。而具体按照哪一种情形则可以根据算法的不同而有所不同。例如算法上具体为值最大的BM是最优的，则选择最大的L个BM即可；又例如算法上具体为最小的BM是最优的，则选择最小的L个BM即可。当然若算法上具体是绝对值最大的BM是最优的，则选择绝对值最大的L个BM即可，当然若算法上具体是绝对值最小的BM是最优的，则选择绝对值最小的L个BM即可。
此外，按照排序的方式选择L个BM方式可以是，对于L条路径中任一路径，均分别对所述路径对应的所述第一比特组的2 KM-K个BM或者2 KM-K个BM的绝对值进行预设排序，在完成预设排序后，即可从排好序的所述2 KM-K个BM的预设排序中按照具体的算法所要求的预设规则中的一种选取L个BM即可。
504、根据为L条路径中每条路径分别选择的至少L个BM，和，第一比特组的前一个比特组的路径选择结果，确定第一比特组的路径度量值PM。
其中，由于BM的排序结果能够反映出当前比特组的节点选择，再结合第一比特组的前一比特组的路径选择结果进行定位，即可确定出当前比特组的选择节点。具体来说，以第一比特组为一个比特为例，第一比特组的前一比特对应的节点会分裂出两个节点，由于之前对所有的BM均进行了排序，因此该两个节点也进行了排序，此时，直接选取其中较大的一个节点即可，而后将该上一比特对应的节点的PM加上选择出的节点的BM即可得到被选择节点的PM，即当前比特组中的一个比特的PM。当然，若是第一比特组为多比特的情况，则计算的BM是对应该比特组的多比特的BM，而非第一比特组中多个比特中每个比特的BM，具体的BM计算方式可参见步骤502的说明，此处不再赘述。
下面对具有L条路径的情况进行说明，其中，L的值为2的幂次方，则上述描述为比特组中仅包含一个比特且L为1的情况的说明，下面对L大于等于2且比特组包含M个比特的情况下，计算当前比特组PM的过程：
首先根据第一比特组的前一比特组的路径选择结果确定已选择的L条路径，即确定出前一比特组的L个末端节点；接着，对L条路径中任一路径，将该路径的PM加上对应该路径的 第一比特组的BM，得到L个PM；之后，从L条路径的至少L*L个PM中按照预设选取L个PM作为所述第一比特组的PM。
其中，可选的，从L条路径的至少L*L个PM中选择最大的L个PM作为所述第一比特组的PM的过程可以是：
首先，将所述L条路径分为X组路径组，每组路径组分别进行PM对比后分别得到L个PM，每组所述路径组包含2 Y个路径，所述Y为大于等于0的整数；
接着，从得到的(L/2 Y)*L个PM中选择最大的L个PM作为当前比特组的PM。
举例来说，L为8，Y为1，即将8条路径两两分为一组，共分为四组，从8*8个PM中计算出(8/2 1)*8，即32个PM，再从32个PM中选择出最大的8个PM，当然，选择此8个最大的PM的方式有多种，例如，再对四组各自的8个PM两两进行对比，得到16个PM，再对16个PM进行排序，得到最终8个PM，也可以直接对32个PM进行排序，选择其中最大的8个PM。具体的计算方式可根据实际的计算需求的不同有所不同，如，L较小时，可直接将L*L进行排序，如，L较大时，先分组进行排序，再进行结合排序。
505、根据PM确定所述当前比特组的路径选择结果。
可以看出，在步骤504中确定出了L条路径的PM之后，便可进行当前比特组的路径选择，由于PM包含了当前比特组的M个比特对应的BM以及该当前比特组对应的上一比特组的路径，因此，根据该PM即可进行新的路径选择，将L条路径均选择完毕，即可得到当前比特组的路径选择结果。
下面，以两个List为例，说明List间的PM排序过程：
首先，将第一List中的每个PM与所述第二List中的对应PM进行对比。
其中，由于之前BM阶段已经进行排序，因此在PM计算后，每个List内的PM也是已经排序好的，在SCL算法中，一般采用双调排序算法，即对于需要进行List间算法的第一List和第而List，若第一List是单调增排列，则第二List为单调减排列，或者若第一List是单调减排列，则第二List为单调增排列。因此，在此比对过程中，将第一List的第1个PM与第二List的最后1个PM进行对比，第一List的第2个PM与第二List的倒数第2个PM进行对比，依此类推，第一List的最后1个PM与第二List的第1个PM进行对比。
接着，选取排序后的第一List和第二List中的前L个PM进行排序。
其中，前述步骤相当于选取了第一List和第二List中的前L个PM，以L＝8为例，此步骤则需要对其进行排序，该排序包含三个步骤，第一步骤是将第1个PM与第5个PM对比，第2个PM与第6个PM对比，将第3个PM与第7个PM对比，第4个PM与第8个PM对比；接着第二个步骤，将第一步骤比对后的第1个PM与第3个PM对比，第2个PM与第4个PM对比，将第5个PM与第7个PM对比，第6个PM与第8个PM对比；最后，将第二步骤比对后的第1个PM与第2个PM对比，第3个PM与第4个PM对比，将第5个PM与第6个PM对比，第7个PM与第8个PM对比，完成8个PM的排序。
在完成8个PM的排序后，即可按照排序结果选择当前比特组的路径。
下面通过一个具体的例子对本申请实施例的List内的BM排序和List间的PM排序进行说明，根据所述PM确定所述当前比特组的路径选择结果的过程可采用Bitonic双调排序算法， 请参阅图6和图7，图6是本申请实施例的译码方法一个实施例图，图7是图6中List内排序过程和List间排序过程，其中，List内排序为BM排序过程，以BM为8路输入，List＝8为例，以两个List内排序，其后的List间排序的过程为PM的排序，首先对List内排序的过程进行说明，其中第一List的BM分别为B 11＝0.11,B 12＝0.21,B 13＝0.05,B 14＝0.09,B 15＝0.03,B 16＝0.08,B 17＝0.12,B 18＝0.14：第二List的BM分别为B 21＝0.26,B 22＝0.01,B 23＝0.33,B 24＝0.15,B 25＝0.23,B 26＝0.35,B 27＝0.13,B 28＝0.18。
a、对第一List和第二List中的L个BM分别进行排序。
该步骤共包含6个步骤，以第一List为例进行说明：
步骤1：首先将第一List中的8个BM按照每两个一组，且相邻的两个组排序相反，即，将第1个BM与第2个BM对比，第3个BM与第4个BM对比，将第5个BM与第6个BM对比，第7个BM与第8个BM对比，即得到B 11＝0.11，B 12＝0.21；B 14＝0.09，B 13＝0.05；B 15＝0.03，B 16＝0.08；B 18＝0.14，B 17＝0.12。
步骤2：将步骤1排序后的将第1个BM与第4个BM对比，第2个BM与第3个BM对比，将第5个BM与第8个BM对比，第6个BM与第7个BM对比，即得到B 13＝0.05，B 14＝0.09；B 12＝0.21，B 11＝0.11；B 15＝0.03，B 16＝0.08；B 18＝0.14，B 17＝0.12。
步骤3：将步骤2排序后的第1个BM与第2个BM对比，第3个BM与第4个BM对比，将第5个BM与第6个BM对比，第7个BM与第8个BM对比，即得到B 13＝0.05，B 14＝0.09；B 12＝0.21，B 11＝0.11；B 15＝0.03，B 16＝0.08；B 17＝0.14，B 18＝0.12。
步骤4，将步骤3排序后的第1个BM与第8个BM对比，第2个BM与第7个BM对比，将第3个BM与第6个BM对比，第4个BM与第5个BM对比，即得到B 13＝0.05,B 14＝0.09；B 16＝0.08,B 15＝0.03；B 11＝0.11,B 12＝0.21；B 17＝0.14,B 18＝0.12。
步骤5，将步骤4排序后的第1个BM与第3个BM对比，第2个BM与第4个BM对比，将第5个BM与第7个BM对比，第6个BM与第8个BM对比，即得到B 13＝0.05，B 15＝0.03；B 16＝0.08，B 14＝0.09；B 11＝0.11，B 18＝0.12；B 17＝0.14，B 12＝0.21。
步骤6，将步骤5排序后的第1个BM与第2个BM对比，第3个BM与第4个BM对比，将第5个BM与第6个BM对比，第7个BM与第8个BM对比，即得到B 15＝0.03，B 13＝0.05；B 16＝0.08，B 14＝0.09；B 11＝0.11，B 18＝0.12；B 17＝0.14，B 12＝0.21。
同理，按照上述6个步骤对第二List进行排序，可得到B 26＝0.35，B 23＝0.33，B 21＝0.26，B 25＝0.23，B 28＝0.18，B 24＝0.15，B 27＝0.13，B 22＝0.01。
b、将排序后的第一List中的每个PM与所述第二List中的对应PM进行比对。
其中，该步骤中，两个List共16个PM，即将第1个PM与第16个PM对比，第2个PM与第15个PM对比，将第3个PM与第14个PM对比，第4个PM与第13个PM对比，第5个PM与第12个PM对比，第6个PM与第11个PM对比，将第7个PM与第10个PM对比，第8个PM与第9个PM对比，使得两个List中大小排前8的8个PM排在序列的前8个位置。
c、选取排序后的第一List和第二List中的前L个PM进行排序。
其中，该排序包含三个步骤：
步骤1：将第1个PM与第5个PM对比，第2个PM与第6个PM对比，将第3个PM与 第7个PM对比，第4个PM与第8个PM对比；
步骤2：将步骤1比对后的第1个PM与第3个PM对比，第2个PM与第4个PM对比，将第5个PM与第7个PM对比，第6个PM与第8个PM对比；
步骤3：将步骤2比对后的第1个PM与第2个PM对比，第3个PM与第4个PM对比，将第5个PM与第6个PM对比，第7个PM与第8个PM对比，完成8个PM的排序。
d、按照前L个PM的排序结果选择当前比特组的路径。
上面对本申请实施例的极化码译码方法进行了说明，下面对本申请实施例的译码器进行说明，请参阅图8，图8是本申请实施例的译码器的一个示意图，其中，译码器应用于极化码译码，所述译码器包括：
计算模块801根据当前被译码的码块内的第二比特组的路径选择结果，计算所述码块内的第一比特组的LLR，其中，所述第二比特组为所述码块中位于所述第一比特组之前的第K个比特组，所述K为大于等于2的整数，所述路径选择结果包含L条路径，L为大于等于1的整数；计算模块801还用于根据所述LLR计算所述第一比特组的BM，其中，所述BM中包括L组BM，所述L组BM与所述L条路径一一对应，且每组BM中的BM的数量均为所述BM的总数的1/L；处理模块802用于对于所述L条路径中的每一条路径，分别从与每条路径相对应的一组BM中，选择至少L个BM；处理模块802还根据为所述L条路径中每条路径，和，所述第一比特组的前一个比特组的路径选择结果，确定所述第一比特组的路径度量值PM；处理模块802还根据所述PM确定所述第一比特组的路径选择结果。
可以看出，由于计算模块801直接根据位于第一比特组之前的第K个比特组的第二比特组得到的第一比特组的BM，即相当于在不考虑第一比特组的前一个比特组的路径选择结果的情况下，将该第一比特组的BM均计算出来，接着，在处理模块802获取到上一比特组的路径选择结果后，仅需要根据第一比特组的前一个比特组的路径选择结果和选择出的BM即可确定出PM，即第一比特组的前一个比特组的PM加上第一比特组计算的BM即可得到第一比特组的PM，从而能够根据该PM确定出路径选择结果，可见，整个译码过程中无需进行PM排序，在进行当前比特组的译码时，也无需等待上一比特组的译码完成，只需要在当前比特组的PM计算阶段时，能够获取到上一比特组的路径选择结果即可，从而能够使得在译码过程中，在PM计算阶段之前的其他阶段均可并行，从而大大降低译码时延，提高译码效率。
可选的，所述码块中的每个比特组均包含M个比特，所述M为大于等于1的整数，计算模块801具体用于计算所述L条路径中每条所述路径对应的所述第一比特组的2 KM-K个LLR，其中，L为2N，其中N为大于等于0的整数；根据所述2 KM-K个LLR计算所述第一比特组的L*2 KM-K个BM。具体的计算BM的方式可参见图5所示实施例中针对步骤502的说明，此处不再赘述。
可选的，处理模块802具体用于对于所述L条路径中的每条路径，分别从与每条路径相对应的2 KM-K个BM中，按照预设规则选择至少L个BM。具体的，选择至少L个BM的方式可参见图5所示实施例中的步骤503的说明，此处不再赘述。
可选的，计算模块801具体用于对于所述L条路径中每条路径，均分别对所述路径对应的所述第一比特组的2 KM-K个BM或者2 KM-K个BM的绝对值进行预设排序，从所述2 KM-K个BM 的预设排序中按照预设规则选取L个BM。具体的，选择至少L个BM的方式可参见图5所示实施例中的步骤503的说明，此处不再赘述。
可选的，处理模块802具体用于对所述L条路径中任一路径，均分别将所述路径的PM加上对应所述路径的至少L个BM得到至少L个PM；从所述L条路径对应的至少L*L个PM中按照预设的预设规则选择L个PM作为所述第一比特组的PM。具体的，选择至少L个PM的方式可参见图5所示实施例中的步骤504的说明，此处不再赘述。
可选的，处理模块802具体用于将所述L*L条路径分为X组路径组，每组所述路径组分别进行PM对比后按照预设的预设规则分别得到L个PM，每组所述路径组包含2 Y个路径，所述Y为大于等于0的整数；从得到的(L/2 Y)*L个PM中按照预设的预设规则选择L个PM作为第一比特组的PM。具体的，选择至少L个PM的方式可参见图5所示实施例中的步骤504的说明，此处不再赘述。
可选的，对于预设规则，从对象集合中按照所述预设规则选取X个对象包括：从对象值集合中选择最大的X个对象；或，从对象集合中选择最小的X个对象；或，从对象集合中选择绝对值最大的X个对象；或，从对象集合中选择绝对值最小的X个对象；其中，所述对象为BM或者PM，所述X为大于等于1的整数。具体可参见图5所示实施例中步骤503的说明，此处不再赘述。
可选的，所述第二比特组为码块中起始比特组，该起始比特组即为该码块中排序第一的比特组，在这种情况下，具体的第二比特组的路径选择结果通过如下方式计算，首先，计算模块801计算所述第二比特组的LLR；接着，计算模块801根据所述第二比特组的LLR计算所述第二比特组的BM；接下来，处理模块802从将计算出的所述第二比特组的BM中选取L个BM；再由处理模块802根据选取的L个的BM计算所述第二比特组的PM；最后，处理模块802根据所述第二比特组的PM确定所述第二比特组的路径选择结果。
需要说明的是，本申请实施例也可以包括这样一个例子，该例中，译码器的计算模块和处理模块这类功能模块可以由大规模集成电路(Large-scale integrated circuit，简称LSI)，译码器通过LSI有多种方式实施，如数字信号处理(Digital Signal Processing，简称DSP)方式和现场可编程逻辑门阵列(Field Programmable Gate Array，简称FPGA)方式等，此外，该计算模块以及处理模块等这些功能模块可以分别制作成单独的或者是分离的芯片，当然，这两个功能模块也可以被制作成包含该两个功能模块或者更多功能模块的单独的芯片。其中，该LSI可以称之为集成电路(Integrated Circuit，简称IC)、系统级LSI、超大规模LSI或者基于集成度的甚大规模LSI。
上面对本申请实施例的译码器进行了说明，下面对本申请实施例的通信设备进行说明，请参阅图9，图9是本申请实施例的通信设备的一个示意图，其中，通信设备9应用于极化码译码，所述通信设备9包括图8所示实施例中的译码器901和收发器902，其中，该收发器902用于接收码流；译码器901则获取码流中的码块和码块的参数；译码器901接着可以根据码块的参数和码块进行译码，生成译码结果；最后译码器901输出所述译码结果。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk，简称SSD)等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (19)

  1. 一种极化码译码方法，其特征在于，包括：
    根据当前被译码的码块内的第二比特组的路径选择结果，计算所述码块内的第一比特组的对数似然比LLR，其中，所述第二比特组为所述码块中位于所述第一比特组之前的第K个比特组，所述K为大于等于2的整数，所述路径选择结果包含L条路径，L为大于等于1的整数；
    根据所述LLR计算所述第一比特组的分支度量值BM，其中，所述BM中包括L组BM，所述L组BM与所述L条路径一一对应，且每组BM中的BM的数量均为所述BM的总数的1/L；
    对于所述L条路径中的每条路径，分别从与每条路径相对应的一组BM中，选择至少L个BM；
    根据为所述L条路径中每条路径分别选择的所述至少L个BM，和，所述第一比特组的前一个比特组的路径选择结果，确定所述第一比特组的路径度量值PM；
    根据所述PM确定所述第一比特组的路径选择结果。
  2. 根据权利要求1所述的极化码译码方法，其特征在于，所述码块中的每个比特组均包含M个比特，所述M为大于等于1的整数，所述计算所述码块内的第一比特组的LLR包括：
    分别计算所述第一比特组对应于所述L条路径中每一条路径的2 KM-K个LLR，其中，L为2 N，其中N为大于等于0的整数；
    所述根据所述LLR计算所述第一比特组的BM包括：
    根据所述L条路径中每一条路径对应的2 KM-K个LLR，计算所述第一比特组的L*2 KM-K个BM。
  3. 根据权利要求2所述的极化码译码方法，其特征在于，对于所述L条路径中的每条路径，分别从与每条路径相对应的一组BM中，选择至少L个BM包括：
    对于所述L条路径中的每条路径，分别从与每条路径相对应的2 KM-K个BM中，按照预设规则选择至少L个BM。
  4. 根据权利要求3所述的极化码译码方法，其特征在于，所述对于所述L条路径中的每条路径，分别从与每条路径相对应的2 KM-K个BM中，按照预设规则选择至少L个BM包括：
    对于所述L条路径中每条路径，均分别对所述路径对应的2 KM-K个BM或者2 KM-K个BM的绝对值按照数值大小进行排序，从排序后的所述2 KM-K个BM中按照所述预设规则选取L个BM。
  5. 根据权利要求1所述的极化码译码方法，其特征在于，所述根据为所述L条路径中每条路径分别选择的所述至少L个BM，和，所述第一比特组的前一个比特组的路径选择结果，确定所述第一比特组的PM包括：
    对所述L条路径中任一路径，均分别将所述路径的PM加上对应所述路径的至少L个BM得到至少L个PM；从所述L条路径对应的至少L*L个PM中按照预设的预设规则选择L个PM作为所述第一比特组的PM。
  6. 根据权利要求5所述的极化码译码方法，其特征在于，所述从所述L条路径对应的至少L*L个PM中按照预设的预设规则选择L个PM作为所述第一比特组的PM包括：
    将所述至少L*L条路径分为X组路径组，每组所述路径组分别进行PM对比后按照预设 的预设规则分别得到L个PM，每组所述路径组包含2 Y个路径，所述Y为大于等于0的整数；
    从得到的(L/2 Y)*L个PM中按照预设的预设规则选择L个PM作为第一比特组的PM。
  7. 根据权利要求3至6中任一项所述的极化码译码方法，其特征在于，所述预设规则包括：
    从对象集合中选择数值最大的L个对象；或，
    从对象集合中选择数值最小的L个对象；或，
    从对象集合中选择绝对值最大的L个对象；或，
    从对象集合中选择绝对值最小的L个对象；其中，所述对象为BM或者PM。
  8. 根据权利要求1至7中任一项所述的极化码译码方法，其特征在于，当所述第二比特组为所述码块中的起始比特组时，所述第二比特组的路径选择结果通过如下方式计算：
    计算所述第二比特组的LLR；
    根据所述第二比特组的LLR计算所述第二比特组的BM；
    从计算出的所述第二比特组的BM中选取L个BM；
    根据选取的L个的BM计算所述第二比特组的PM；
    根据所述第二比特组的PM确定所述第二比特组的路径选择结果。
  9. 一种应用于极化码译码的译码器，其特征在于，所述译码器包括：
    计算模块，用于根据当前被译码的码块内的第二比特组的路径选择结果，计算所述码块内的第一比特组的对数似然比LLR，其中，所述第二比特组为所述码块中位于所述第一比特组之前的第K个比特组，所述K为大于等于2的整数，所述路径选择结果包含L条路径，L为大于等于1的整数；
    所述计算模块还用于根据所述LLR计算所述第一比特组的分支度量值BM，其中，所述BM中包括L组BM，所述L组BM与所述L条路径一一对应，且每组BM中的BM的数量均为所述BM的总数的1/L；
    处理模块，用于对于所述L条路径中的每一条路径，分别从与每条路径相对应的一组BM中，选择至少L个BM；
    所述处理模块还用于根据为所述L条路径中每条路径分别选择的所述至少L个BM，和，所述第一比特组的前一个比特组的路径选择结果，确定所述第一比特组的路径度量值PM；
    所述处理模块还用于根据所述PM确定所述第一比特组的路径选择结果。
  10. 根据权利要求9所述的译码器，其特征在于，所述码块中的每个比特组均包含M个比特，所述M为大于等于1的整数，所述计算模块具体用于：
    分别计算所述第一比特组对应于所述L条路径中每一条路径的2 KM-K个LLR，其中，L为2 N，其中N为大于等于0的整数；
    根据所述2 KM-K个LLR计算所述第一比特组的L*2 KM-K个BM。
  11. 根据权利要求10所述的译码器，其特征在于，所述处理模块具体用于：
    对于所述L条路径中的每条路径，分别从与每条路径相对应的2 KM-K个BM中，按照预设规则选择至少L个BM。
  12. 根据权利要求11所述的译码器，其特征在于，所述计算模块具体用于：
    对于所述L条路径中每条路径，均分别对所述路径对应的所述第一比特组的BM中的 2 KM-K个BM或者2 KM-K个BM的绝对值进行预设排序，从所述2 KM-K个BM的预设排序中按照所述预设规则选取L个BM。
  13. 根据权利要求9所述的译码器，其特征在于，所述处理模块具体用于：
    对所述L条路径中任一路径，均分别将所述路径的PM加上对应所述路径的至少L个BM得到至少L个PM；从所述L条路径对应的至少L*L个PM中按照预设的预设规则选择L个PM作为所述第一比特组的PM。
  14. 根据权利要求13所述的译码器，其特征在于，所述处理模块具体用于：
    将所述至少L*L条路径分为X组路径组，每组所述路径组分别进行PM对比后按照预设的预设规则分别得到L个PM，每组所述路径组包含2 Y个路径，所述Y为大于等于0的整数；
    从得到的(L/2 Y)*L个PM中按照预设的预设规则选择L个PM作为第一比特组的PM。
  15. 根据权利要求11至14中任一项所述的译码器，其特征在于，所述预设规则包括：
    从对象集合中选择数值最大的L个对象；或，
    从对象集合中选择数值最小的L个对象；或，
    从对象集合中选择绝对值最大的L个对象；或，
    从对象集合中选择绝对值最小的L个对象；其中，所述对象为BM或者PM。
  16. 根据权利要求9至15中任一项所述的译码器，其特征在于，当所述第二比特组为所述码块中的起始比特组时，所述第二比特组的路径选择结果通过如下方式计算：
    所述计算模块用于计算所述第二比特组的LLR；
    所述计算模块还用于根据所述第二比特组的LLR计算所述第二比特组的BM；
    所述处理模块用于从将计算出的所述第二比特组的BM中选取L个BM；
    所述处理模块还用于根据选取的L个的BM计算所述第二比特组的PM；
    所述处理模块还用于根据所述第二比特组的PM确定所述第二比特组的路径选择结果。
  17. 一种通信设备，其特征在于，所述通信设备包括收发器和权利要求9至权利要求16中任一项所述的译码器；
    所述收发器用于接收码流；
    所述译码器获取所述码流中的码块和所述码块的参数；
    所述译码器根据所述码块的参数和所述被译码块进行译码，生成译码结果；
    所述译码器输出所述译码结果。
  18. 一种计算机可读存储介质，其特征在于，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1-8中任意一项所述的方法。
  19. 一种包含指令的计算机程序产品，其特征在于，当其在计算机上运行时，使得计算机执行如权利要求1-8中任意一项所述的方法。
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