WO2018218898A1 - 一种抗单粒子瞬态时钟树结构 - Google Patents

一种抗单粒子瞬态时钟树结构 Download PDF

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Publication number
WO2018218898A1
WO2018218898A1 PCT/CN2017/113269 CN2017113269W WO2018218898A1 WO 2018218898 A1 WO2018218898 A1 WO 2018218898A1 CN 2017113269 W CN2017113269 W CN 2017113269W WO 2018218898 A1 WO2018218898 A1 WO 2018218898A1
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nmos transistor
pmos transistor
clock
transistor
gate
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PCT/CN2017/113269
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English (en)
French (fr)
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王丹
王福庆
岳素格
赵元富
王亮
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北京时代民芯科技有限公司
北京微电子技术研究所
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Publication of WO2018218898A1 publication Critical patent/WO2018218898A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15066—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using bistable devices

Definitions

  • the invention relates to the field of clock reinforcement, in particular to a single-particle transient clock tree structure, and belongs to the technical field of anti-irradiation design.
  • the radiation generated by high-energy protons or high-energy neutrons striking the nucleus and the heavy nuclei in the cosmic rays can cause changes in the state of the circuit, such as transients in combinatorial logic, bit flipping of memory cells, etc.
  • the result is often referred to as the single particle effect.
  • SEU single-event upset
  • SET single-event transient
  • the critical charge Q'crit of SET without attenuation propagation is also reduced.
  • the SET can occur at any node of the circuit and propagates through a series of combined circuits to the input of the sequential circuit causing error flipping of the storage logic.
  • the error rate of SET even exceeds the error rate of SEU, which becomes the main source of soft errors.
  • the clock As a global signal of an integrated circuit, the clock has a special influence on the timing of the circuit, a wide distribution of nodes, and a high frequency.
  • the clock tree is usually designed in the form of a clock tree.
  • the clock tree has a balanced tree and an H-tree.
  • X-tree, etc. regardless of the structure, is designed to allow the designer to align the clock edges or to move the clock forward or backward through a flexible design approach, thereby increasing the effective window of the data.
  • the clock buffer (BUFFER) and the inverter (INV) are the necessary components of the clock tree.
  • the clock tree root node clock unit drives a certain number of clock buffers/inverters to finally implement the cascaded clock tree.
  • the clock tree is spread throughout the layout of the integrated circuit, when heavy ions, protons, neutron space particles bombard the sensitive nodes of an inverter/buffer in the clock tree
  • an incorrect clock SET pulse is introduced.
  • the SET transient pulse propagates in the clock tree to the clock signal port of a large number of timing units driven by the leaf node, and the error data is sampled.
  • SEU single event flip
  • SET-induced soft errors on clock tree networks are even as high as 90%.
  • the main methods to eliminate the suppression of SET pulses on the clock tree network are redundancy techniques and filtering techniques.
  • Time redundancy uses the signal levels before and after the transient pulse to occur as two sources of signal normality. With proper delay and sampling, the majority vote is used to determine the final correct output. The time redundancy must have three or more.
  • the latch unit is redundant and brings additional speed overhead.
  • the filtering technique is selected. Compared with the redundancy technology, the method of filtering the single-particle pulse by filtering technology introduces relatively less overhead.
  • the specific implementation method is a sensitive port inside the timing unit, and by adding a filtering circuit, Transient pulses above a certain width ( ⁇ t) are filtered out on the input signal, but it is worth noting that in the prior art, the filter circuit itself used in the timing unit is susceptible to SET damage, and the use of filters introduces additional Sensitive body, when the SET pulse generated by the particle bombardment to the filter output node propagates to the internal storage circuit, causing the error flipping of the stored data, this method avoids the global signal (such as the clock) in the single-particle transient reinforcement.
  • the timing unit clock signal SET hardening method increases the area of one filter per area of the timing unit, and the power consumption overhead caused by the reinforcement increases sharply with the increase of the frequency. These overheads are for performance (low power consumption). , high speed) advanced process node integrated circuits are intolerable.
  • the technical solution of the present invention solves the problem of overcoming the deficiencies of the prior art and provides a single-particle transient clock tree structure, which can suppress the generation and propagation of single-event transient pulses on a clock signal with a small circuit overhead.
  • the technical solution of the present invention is: an anti-single-particle transient clock tree structure, including a root node a clock driving unit, a sub-node clock driving unit, and a leaf node clock driving unit;
  • the root node clock driving unit is a clock node source starting node driving unit, and the child node clock driving unit is a lower clock driving unit of the root node clock driving unit, the number of stages is N level, N is an integer;
  • the leaf node clock driving unit is a clock node end leaf node driving unit; an output end of the root node clock driving unit is connected to an input end of the sub node clock driving unit, and an output end of the sub node clock unit is connected to an input end of the leaf node clock driving unit, and each leaf node clock driving unit outputs Two clock signals for connecting a certain number of dual clock anti-single-particle timing units.
  • the circuit form of the root node clock driving unit and the sub-node clock driving unit is a clock inverter circuit or a clock buffer circuit.
  • the clock inverter circuit includes a PMOS transistor and an NMOS transistor.
  • the gate of the PMOS transistor is connected to the gate of the NMOS transistor.
  • As the input terminal I, the drain of the PMOS transistor is connected with the drain of the NMOS transistor.
  • the output terminal ZN; the source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transistor is grounded.
  • the clock buffer circuit comprises a PMOS transistor, an NMOS transistor, a PMOS transistor and an NMOS transistor.
  • the gate of the PMOS transistor is connected to the gate of the NMOS transistor.
  • the drain of the PMOS transistor is connected to the drain of the NMOS transistor. After that, it is connected to the gate of the PMOS transistor and the gate of the NMOS transistor at the same time.
  • the drain of the PMOS transistor and the drain of the NMOS transistor are connected together as the output terminal ZN; the source of the PMOS transistor and the source of the PMOS transistor are connected.
  • the power supply VDD, the source of the NMOS transistor, and the source of the NMOS transistor are both grounded.
  • Each of the leaf node clock driving units is a two-way filter.
  • the two-way filter is composed of a first delay unit, a second delay unit, a PMOS transistor, a PMOS transistor, an NMOS transistor, an NMOS transistor, a PMOS transistor, a PMOS transistor, an NMOS transistor, and an NMOS transistor; wherein, the PMOS transistor, the PMOS transistor, The NMOS transistor and the NMOS transistor are sequentially connected in series to form a first dual input inverter, and the first dual input inverter and the first delay unit 1 form a first filter. road;
  • the PMOS transistor, the PMOS transistor, the NMOS transistor, and the NMOS transistor are sequentially connected in series to form a second dual input inverter, and the second dual input inverter and the second delay unit constitute another filtering circuit;
  • the source of the PMOS transistor and the source of the PMOS transistor are connected to the power supply VDD, the source of the NMOS transistor and the source of the NMOS transistor are grounded; the gates of the PMOS transistor, the NMOS transistor, the PMOS transistor, and the NMOS transistor are connected together with the first delay
  • the unit is connected to the input of the second delay unit.
  • the gate of the PMOS transistor and the gate of the NMOS transistor are connected to the output terminal Z1 of the first delay unit, and the drain of the PMOS transistor and the drain of the NMOS transistor are connected.
  • the gate of the PMOS transistor and the gate of the NMOS transistor are connected to the output terminal Z2 of the second delay unit, and the drain of the PMOS transistor is connected to the drain of the NMOS transistor As the second output terminal Y2 of the two-way filter.
  • the separation distance of the two filtering circuits is equal to the minimum distance L between adjacent drain terminals of the MOS tube, L is greater than or equal to D, and D is a single particle that can affect the circuit under the specific manufacturing process. Physical size.
  • the two-way filter is composed of a third delay unit, a PMOS transistor, an NMOS transistor, a PMOS transistor, a PMOS transistor, an NMOS transistor, and an NMOS transistor.
  • the PMOS transistor and the NMOS transistor are connected in series to form an inverter, and the source of the PMOS transistor is connected.
  • the power supply VDD, the source of the NMOS transistor is grounded; the PMOS transistor, the PMOS transistor, the NMOS transistor, and the NMOS transistor are sequentially connected in series to form a third dual input inverter, the source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transistor is grounded; the PMOS transistor The gate is connected to the gate of the NMOS transistor and connected to the input terminal of the third delay unit. As the input of the double filter A, the output Z of the third delay unit is simultaneously connected to the gate of the PMOS transistor and the gate of the NMOS transistor. The gate of the PMOS transistor and the gate of the NMOS transistor are connected.
  • the drain of the PMOS transistor After the drain of the PMOS transistor is connected to the drain of the NMOS transistor, the drain of the PMOS transistor and the drain of the NMOS transistor are used as the first output terminal Y1 of the two-way filter. After the pole is connected, it acts as the second output Y2 of the two-way filter.
  • the circuit in which the inverter composed of the PMOS transistor and the NMOS transistor are connected in series with the third delay unit is separated from the third dual input inverter, and the separation distance is equal to the adjacent MOS transistor.
  • the minimum distance L between the drain ends, L is greater than or equal to D, and D is the physical size at which individual particles can affect the circuit in a particular manufacturing process.
  • the first delay unit, the second delay unit and the third delay unit have the same circuit structure, and are composed of two inverters INV1 and INV2, and the input end of the INV1 is connected to the output end of the INV2 to form the input terminal A of the delay unit.
  • the output terminal of INV1 is connected to the input terminal of INV2 to form the output terminal Z of the delay unit.
  • the present invention has the following beneficial effects:
  • the present invention achieves effective reinforcement against single-particle transients.
  • the invention is suitable for the characteristics of the advanced process node circuit with small size, narrow pitch and low critical charge Qcrit of the circuit flipping. Considering the sensitivity problem of the introduced filter circuit itself, not only the circuit implementation is considered. Radiation particles cause single-event transient problems in a single node, and single-event transient pulses in multiple nodes are also considered to induce single-event up-turning of sequential elements.
  • the clock tree structure design based on two-way filter ensures that the single-element is guaranteed.
  • the present invention effectively reduces the probability of generating a single-event transient pulse on each clock node after the clock tree network is bombarded by the radiation particles.
  • the traditional reinforcement method is usually a reinforcement circuit that increases the anti-single-particle transient in the sensitive port inside the timing unit.
  • the area of each timing unit is increased by one filter. Area, in particular, when the filter is placed at the clock-sensitive end of the sequential circuit, the power consumption increases dramatically with increasing frequency, making the power consumption of the integrated circuit extremely expensive.
  • the invention proposes that in the clock tree structure, the leaf node clock driving unit adopts a two-way filter, and the two-way filter drives a plurality of dual-clock anti-single-particle timing units, and the clock-sensitive end of the timing unit itself does not need to introduce a redundant circuit, only the clock leaf node
  • the clock drive unit adopts anti-single-particle transient reinforcement circuit.
  • the number of anti-single-particle transient reinforcement circuits is much smaller than the traditional reinforcement design, and has low power consumption, high speed and small area.
  • the conventional delay unit adopts an inverter cascade.
  • an inverter of a larger size transistor is generally used in the inverter cascade, and the delay unit of the present invention can adopt a smaller-sized transistor to form an INV.
  • the delay characteristics are realized, and the area and performance overhead are small, which is more suitable for the clock tree structure design requirement, thereby further reducing the power consumption and area of the clock tree structure.
  • the present invention provides two types of two-way filter structures. Compared with the conventional single-particle transient filter, the two-way filter itself has good immunity to single-event transients and occurs in the structure.
  • the single-event transient pulse of any internal node can not disturb the two outputs at the same time to ensure that the whole circuit has extremely high single-particle transient capability, which can effectively eliminate the occurrence of the input signal pulse width less than the delay unit delay and occur in the unit. Internal single particle pulse.
  • the first two-way filter circuit has a higher resistance to single-event transients than the second filter circuit, and the second two-way filter circuit, when the radiation particles are bombarded to the input A, the third When any one of the delay unit, the output terminal Y1 or the output terminal Y2, a single-event transient disturbance occurs in one of the outputs, and the first two-way filter circuit only bombards the output Y1 or the output from the radiation particles.
  • the single-particle transient disturbance occurs at the end Y2, and the reliability is higher. Therefore, the first two-way filter circuit structure is more suitable for complex single-particle effects (such as single-particle transient re-convergence, single-particle transient broadening).
  • the advanced process node circuit design is more suitable for complex single-particle effects (such as single-particle transient re-convergence, single-particle transient broadening).
  • FIG. 1 is a schematic diagram of a structure of a single-particle transient clock tree according to the present invention
  • FIG. 2 is a clock inverter circuit and a clock in a single-particle transient clock tree structure of the present invention
  • a schematic diagram of a buffer circuit wherein (a) is a clocked inverter circuit, and (b) is a clock buffer circuit;
  • FIG. 3 is a schematic diagram of an implementation circuit of a two-way filter according to the present invention.
  • FIG. 4 is a schematic diagram of another implementation circuit of the dual filter of the present invention.
  • FIG. 5 is a schematic diagram of implementation of a delay unit in a two-way filter according to the present invention.
  • FIG. 6 is a schematic diagram of an implementation circuit of a dual clock anti-single-particle transient timing unit according to the present invention.
  • FIG. 7 is a schematic diagram of layout separation of a two-way filter and a dual-clock anti-single-particle transient timing unit according to the present invention.
  • Figure 8 is a schematic diagram of the connection of a two-way filter to a dual-clock anti-single-particle transient timing unit.
  • the anti-single-particle transient clock tree structure of the present invention includes a root node clock driving unit 11, a sub-node clock driving unit 12, and a leaf node clock driving unit 13.
  • the output of the root node clock drive unit 11 is connected to the input of the child node clock drive unit 12, and the child node clock unit 12 outputs the connection leaf node clock drive unit 13 input.
  • the output of the leaf node clock drive unit 13 is connected to a dual clock anti-single-particle timing unit.
  • the sub-node clock driving unit 12 is a lower-level clock driving unit of the clock root node clock driving unit 11, and the number of stages is N, and N is an integer. The specific number depends on the complexity of the design circuit and the clock design adopted.
  • the number of child node clock drive units 12 connected to the root node clock drive unit 11 in the clock tree, the number of leaf node clock drive units 13 connected at the end of the clock tree, and the dual clock anti-single particles connected to each leaf node clock drive unit The number of timing units is entirely determined by the specific drive capability and circuit timing constraints of the design unit.
  • a clock tree of an H-type structure is used.
  • the present invention is also applicable to various forms of clock tree structures such as a balanced tree and an X-tree.
  • the first output terminal Y1 of the dual filter is connected to the CK1 terminal of the dual clock anti-single-particle timing unit 14, and the second output terminal Y2 of the dual filter is connected to the CK2 of the dual-clock anti-single-particle timing unit 14. end.
  • the circuit form of the root node clock driving unit 11 is a clock inverter circuit or a clock buffer circuit
  • the circuit form of the child node clock driving unit 12 is a clock inverter circuit or a clock buffer circuit. Which circuit is specifically used according to the specific timing logic requirements of the design circuit and the Depending on the clock design.
  • the clock inverter circuit includes a PMOS transistor 21 and an NMOS transistor 22 as shown in FIG. 2(a).
  • the gate of the PMOS transistor 21 is connected to the gate of the NMOS transistor 22 as an input terminal I, and the PMOS transistor 21
  • the drain is connected to the drain of the NMOS transistor 22 as an output terminal ZN.
  • the source of the PMOS transistor 21 is connected to the power supply VDD, and the source of the NMOS transistor 22 is grounded.
  • the clock buffer circuit includes a PMOS transistor 23, an NMOS transistor 24, a PMOS transistor 25, and an NMOS transistor 26.
  • the gate of the PMOS transistor 23 is connected to the gate of the NMOS transistor 24 as an input terminal.
  • the drain of the PMOS transistor 23 is connected to the drain of the NMOS transistor 24, and is connected to the gate of the PMOS transistor 25 and the gate of the NMOS transistor 26.
  • the drain of the PMOS transistor 25 and the drain of the NMOS transistor 26 are connected together.
  • the output ZN The sources of the PMOS transistor 23 and the PMOS transistor 25 are connected to the power supply VDD, and the sources of the NMOS transistor 24 and the NMOS transistor 26 are grounded.
  • the leaf node clock driving unit 12 in the anti-single-particle transient clock tree structure is a two-way filter structure, and the input signal passes through the filtering circuit to output two signals that do not interfere with each other.
  • the NMOS transistor 38 is composed of.
  • the PMOS transistor 31, the PMOS transistor 32, the NMOS transistor 33, and the NMOS transistor 34 are sequentially connected in series to form a first dual input inverter, the PMOS transistor 31 source is connected to the power supply VDD, and the NMOS transistor 34 is grounded to the ground, and the first dual input is inverted.
  • the first delay unit constitutes a filter circuit, and the PMOS transistor 35, the PMOS transistor 36, the NMOS transistor 37, and the NMOS transistor 38 are sequentially connected in series to form a second dual input inverter.
  • the PMOS transistor 35 is connected to the power supply VDD, and the NMOS transistor 38 is connected.
  • the second double input inverter and the second delay unit form another filter circuit, and the gate of the PMOS transistor 31, the gate of the NMOS transistor 34, the gate of the PMOS transistor 35, and the gate of the NMOS transistor 38 are connected.
  • the gate of the PMOS transistor 32, the gate of the NMOS transistor 33 is connected to the output terminal Z1 of the first delay unit, and the PMOS transistor 32
  • the drain is connected to the drain of the NMOS transistor 33 as the first output terminal Y1
  • the gate of the PMOS transistor 36 and the gate of the NMOS transistor 37 are connected to the output terminal Z2 of the delay unit 2, and the drain and NMOS transistor of the PMOS transistor 36.
  • the second output terminal Y2 After the drain of 37 is connected, It is the second output terminal Y2.
  • the pulse width is smaller than the delay of the delay unit
  • the pulse on the delayed input signal (ie, Z1 point, Z2 point) and the input A original signal after the delay unit are passed.
  • the upper pulses do not overlap and reach the input terminals of the first dual input inverter and the second dual input inverter. Since Z1 and Z2 are different from the signals transmitted by input A, the previous state is maintained, and the output of both filter circuits is There is no interference to subsequent circuits.
  • the two-way filter output (ie, the Y1 and Y2 points) also has a single-particle radiation bombardment while generating a pulse, so in the dual-filter layout layout, according to the separation requirements of the sensitive nodes in the single-particle reinforcement circuit,
  • the two-way filter circuit is separated, and the separation distance is defined as the minimum distance L between the drain ends of adjacent MOS tubes, L is greater than or equal to D, and D is the physical size that a single particle can affect in the circuit under a specific manufacturing process, thereby obtaining two
  • the output signals of the roads do not interfere with each other, ensuring that single-particle bombardment can only affect one of the two-way filter output Y1 or Y2, ensuring that at least one of the filter circuit output signals is output resistant to single-event transients.
  • the two filter circuits have the same logic and have a filtering function, which can eliminate single-event transient pulses whose pulse width on the input signal is smaller than the delay time set inside the filter, and the same input signal passes.
  • the two filter circuits output two output signals.
  • FIG. 4 shows another circuit form of the leaf node clock driving unit 12 in the anti-single-particle transient clock tree structure, and the third delay unit, the PMOS transistor 41, the NMOS transistor 42, the PMOS transistor 43, and the PMOS transistor 44.
  • the NMOS transistor 45 and the NMOS transistor 46 are formed.
  • the PMOS transistor 41 and the NMOS transistor 42 are connected in series to form an inverter.
  • the PMOS transistor 41 has a source connected to the power supply VDD, and the NMOS transistor 42 has a source grounded.
  • the PMOS transistor 43 and the PMOS transistor 44 and the NMOS transistor are used.
  • the tube 45 and the NMOS transistor 46 are sequentially connected in series to form a third dual input inverter.
  • the source of the PMOS transistor 43 is connected to the power supply VDD, the source of the NMOS transistor 46 is grounded, the gate of the PMOS transistor 43, the gate of the NMOS transistor 46, and the input of the delay unit.
  • the terminal is connected as the input terminal A of the dual filter, and the output terminal Z of the third delay unit is simultaneously connected to the gate of the PMOS transistor 41, the gate of the NMOS transistor 42, the gate of the PMOS transistor 44, and the gate of the NMOS transistor 45.
  • the PMOS transistor 41 is connected to the drain of the NMOS transistor 42 as the first output terminal Y1 of the two-way filter, and the drain of the PMOS transistor 44 is connected to the drain of the NMOS transistor 45 as a two-way filter. Second output Y2.
  • the circuit in which the inverter composed of the PMOS transistor 41 and the NMOS transistor 42 is connected in series with the third delay unit is The PMOS transistor 43, the PMOS transistor 44, the NMOS transistor 45, and the NMOS transistor 46 are sequentially connected in series to form a third dual input inverter for separation.
  • the separation distance is defined as the minimum distance L between the drain terminals of adjacent MOS transistors. L is greater than or equal to D, D is the physical size of a single particle that can affect the circuit in a particular manufacturing process.
  • the single-event transient pulse occurring at any node affects at most one output (Y1 or Y2) of the circuit, ensuring that at least one of the filtering circuit outputs is anti-single-particle transient. Output.
  • the first output terminal Y1 of the inverter formed by the PMOS transistor 41 and the NMOS transistor 42 still propagates a single-event transient pulse.
  • the pulse on the delayed input signal (ie, the Z-point output) after the delay unit does not overlap with the pulse on the original signal and reaches the input of the dual-input inverter unit.
  • the logic is different at the pulse, the third pair The second output Y2 of the input inverter will remain in the previous state, and Y2 will produce an output that is resistant to single-event transients.
  • the first delay unit, the second delay unit and the third delay unit circuit have the same composition, as shown in FIG. 5 is the implementation circuit of the delay unit in the dual filter circuit of FIG. 3 and FIG. 4, which is composed of two inverters (INV1 and INV2), the input terminal of INV1 is connected to the output terminal of INV2, constitutes the input terminal A of the delay unit, and the output terminal of INV1 is connected to the input terminal of INV2, which constitutes the output terminal Z of the delay unit, which is used in comparison with the inverter cascade.
  • the delay time of the inverter itself is recursed to form a certain delay time circuit.
  • the delay unit of the present invention can form a INV by using a transistor of a smaller size, and realizes a delay characteristic by a latched logic structure, and has a small area and performance overhead.
  • the circuit form of the dual-clock anti-single-particle timing unit in the anti-single-particle transient clock tree structure is to control the storage structure with redundant nodes by two identical clock signals, and the sensitivity in the single-particle reinforcement circuit in the layout layout.
  • the separation requirement of the node separates the logic circuits of the two clocks to ensure that a single clock signal caused by particle bombardment in the timing unit does not cause single-event flipping of the storage structure of the sequential unit when the single-event transient occurs, and the timing unit type includes the lock. Register, trigger Device.
  • Figure 6 shows a circuit form of a dual-clock anti-single-particle timing unit in a single-particle transient clock tree structure, that is, a dual-clock anti-single-particle timing unit using a two-mode memory structure (DMR), and CK1 is connected in two stages.
  • the inverter provides a clock reverse CKN1 and a clock CKNN1 signal.
  • the clocks CK1 and CK2 are identical.
  • the outputs CKN1 and CKNN1 of CK1 and the outputs CKN2 and CKNN2 of CK2 are respectively connected to the dual mode memory structure and the data input clock control terminal.
  • the circuits of CK1 and CK2 need to be physically separated. As shown in Fig.
  • the separation distance of the sensitive nodes of the layout of the first clock 71 and the second clock 72 is greater than the specific spacing L. (Defined as the minimum distance between the drain terminals of adjacent MOS tubes), L is greater than or equal to D, and D is the physical size that a single particle can affect in the circuit under a specific manufacturing process. Ensure that single-event transients generated by any one of the output on the clock tree structure do not cause single-event flipping of the memory structure in the timing unit, and that single-event transient pulses on either node of the timing unit clock signal are not guaranteed. A single-event flip that causes the timing unit to appear in the storage structure.
  • the minimum distance L between the drain terminals of adjacent MOS tubes satisfies the L ⁇ D requirement.
  • the larger the D value the better.
  • the larger D value can better ensure that the sensitive nodes are not affected by single particles at the same time. If the physical size D of a single particle that can affect the circuit in a process size is 2.5 um, the distance between sensitive nodes is required to be L ⁇ 2.5 um, that is, when laying out the layout of the underlying module, it is necessary to ensure that the distance between the sensitive nodes is greater than 2.5um.
  • the working process of the anti-single particle transient clock tree structure of the present invention is as follows:
  • each clock node on the clock tree is bombarded by space particles and has the following events that may generate single-event transient pulses: 1.
  • the root node clock drive unit uses a clock inverter circuit, the clock inverter The NMOS tube leakage end is bombarded by the radiating particles to generate a single-event transient pulse;
  • the root node clock driving unit uses the clock buffer circuit, the first-stage NMOS transistor or the second-stage PMOS drain terminal of the buffer is subjected to radiation particles. Bombardment Single-event transient pulse; 2.
  • the sub-node clock drive unit uses a clock inverter circuit or a clock buffer circuit
  • the corresponding off-state NMOS tube or PMOS tube drain region is bombarded by radiation particles to generate a single-event transient pulse.
  • the single-event transient pulse generated on the above clock network node will eventually propagate along the clock network to the input end of the leaf node clock drive unit two-way filter, and the filter is set according to the characteristics of the single-event transient pulse under the specific process node.
  • the delay time inside the circuit, the two-way filter can eliminate the single-event transient pulse that occurs on the input signal with a pulse width smaller than the delay time set inside the filter.
  • the single-event transient generated by event 1 or event 2 above The pulse is eventually filtered out by the two-way filter so that it does not affect all of the large number of timing elements connected to the leaf node clock drive unit.
  • the third possible event is when the radiation particles are bombarded to the internal sensitive node of the two-way filter or the output node of the two-way filter. Since the two-way filter of the present invention has two output logics that do not interfere with each other, and two In the physical layout, the path logic completes the physical separation of the sensitive nodes according to the separation requirements of the sensitive nodes in the single-particle reinforcement circuit. Therefore, when the radiation particles are incident on the sensitive nodes in the two-way filter, there is only one redundancy.
  • the single-event transient pulse appears in the output of the filter circuit Y1 or Y2, and the other is still the normal clock signal 0.
  • the dual-filter is driven by the dual-clock anti-single-particle timing unit, and the two clocks are respectively controlled with redundant nodes.
  • the storage structure, the two-way clock also completes the separation of sensitive nodes in the physical layout, so only the single-event transient pulse appearing in one Y1 or Y2 propagates to the clock port CK1 or CK2 of the dual-clock anti-single-particle sequential unit, and A normal clock signal of 0 ensures that the timing unit memory structure does not have an event of latching erroneous data, thus ensuring timing.
  • the accuracy of metadata is required to be used to the timing unit memory structure.
  • the invention can eliminate single-event transient pulses whose pulse width on the input signal is smaller than the delay time set inside the filter, and the same input signal outputs two output signals that do not interfere with each other.
  • the dual-channel filtering unit acts as a leaf node clock driving unit, and according to the specific driving load constraint of the circuit, connects a certain number of dual-clock anti-single-particle timing units that can be driven, and the timing unit having the characteristics of two-way clock reinforcing structure can be applied to the present invention.
  • Anti-single-particle transient clock tree structure is a leaf node clock driving unit
  • the invention achieves effective reinforcement against single-particle transients. Correct Compared with the traditional filter reinforcement method, consider the sensitivity problem of the introduced single-particle reinforcement circuit itself, and ensure that the single-event transient pulse caused by the radiation particle bombardment of any node of the clock tree network will not cause the wrong data lock of the clock unit of the timing unit. The event is in accordance with the characteristics of small size, narrow pitch and low critical charge Qcrit of the circuit of the advanced process node.
  • the present invention effectively reduces the clock
  • the probability of a single-event transient pulse on each clock node after the tree network is bombarded by the radiating particles significantly improves the ability of the clock signal distribution network to resist single-event transients.
  • the traditional reinforcement method it is usually a reinforcement circuit that increases the anti-single-particle transient in the sensitive port inside the timing unit.
  • the area of each timing unit increases the area of one filter, especially Therefore, the power consumption increases sharply with the increase of the frequency, so that the power consumption of the integrated circuit is extremely large.
  • the present invention proposes that in the clock tree structure, the leaf node clock driving unit adopts a two-way filter, and the two-way filter drives multiple Dual clock anti-single-particle timing unit, the timing unit itself does not need to introduce redundant circuits on the clock end, only the clock leaf node clock drive unit adopts anti-single-particle transient reinforcement circuit, and for the circuit, anti-single-particle transient reinforcement circuit (number of transistors) The number of introductions is much smaller than the traditional reinforcement design, and has low power consumption and low overhead.

Abstract

一种抗单粒子瞬态时钟树结构，包括根节点时钟驱动单元、子节点时钟驱动单元以及叶节点时钟驱动单元，根节点时钟驱动单元和子节点时钟驱动单元均为时钟反相器或者缓冲器，而叶节点时钟驱动单元为双路滤波器，双路滤波器可以消除发生于输入信号上的脉冲宽度小于滤波器内部设定的延迟时间的单粒子瞬态脉冲，且同一输入信号输出两路互不干扰的输出信号。每个双路滤波器驱动一定数量的双时钟抗单粒子时序单元。本发明显著提高时钟树网络抗单粒子瞬态的能力，有效降低时钟树网络受到辐射粒子轰击时，任意时钟节点以及多个时钟树节点上产生单粒子瞬态脉冲的概率，且相对于时序单元单粒子瞬态加固方式实现的集成电路，具有功耗低、速度快、面积小的特点。

Description

一种抗单粒子瞬态时钟树结构 技术领域
本发明涉及时钟加固领域，尤其涉及一种抗单粒子瞬态时钟树结构，属于抗辐照设计技术领域。
背景技术
高能质子或高能中子撞击原子核产生的辐射以及宇宙射线中的重核粒子都能引起电路状态的改变，如组合逻辑中的瞬变、存储类单元的位翻转等，这种效应是单个粒子作用的结果，通常称为单粒子效应。对于先进纳米工艺节点，抗单粒子加固技术研究更为关注的是所凸显的单粒子翻转(SEU)、单粒子瞬态(SET)单粒子软错误事件，特别是SET事件，伴随着器件间距的缩小，最直接的影响就是由单个粒子轰击会造成多个敏感节点产生瞬态脉冲，与此同时，由于电路翻转的临界电荷Qcrit的降低，SET能无衰减传播的临界电荷Q′crit也在降低，SET可以发生在电路的任意节点，经过一系列组合电路传播到时序电路的输入端而造成存储逻辑的错误翻转。在纳米级集成电路的辐照试验数据中可明显观测到SET的错误率甚至超过SEU的错误率，成为主要的软错误来源。
时钟作为集成电路的全局性信号，由于该信号对电路时序影响大、节点分布广、频率高等特点，通常以时钟树形式进行时钟分布网络的特殊设计，时钟树的结构有平衡树、H树、X树等，无论是哪种结构，其目的都是通过灵活多变的设计方法使得设计者可以对齐时钟边沿，或者使时钟前移或后移，从而增大数据的有效窗口。众多结构中时钟缓冲器(BUFFER)和反相器(INV)为时钟树的必要组成单元，由时钟树根节点时钟单元驱动一定数量的时钟缓冲器/反相器最终实现级连式的时钟树设计，时钟树遍布在整个集成电路的版图中，当重离子、质子、中子空间粒子轰击到时钟树的某个反相器/缓冲器的敏感节点 时，收集的电荷会引发时钟跳变到错误的状态，引入一个错误的时钟SET脉冲，该SET瞬态脉冲在时钟树传播开到叶节点驱动的大量时序单元的时钟信号端口，会采样错误数据，从而造成大量时序单元发生由SET引起的单粒子翻转(SEU)事件。对于非加固的纳米级电路设计，时钟树网络上的SET诱发的软错误甚至高达90％。
消除抑制时钟树网络上的SET脉冲的主要方法有冗余技术和滤波技术。时间冗余利用瞬态脉冲发生之前和之后的信号电平作为信号正常状态的两个来源，通过恰当的延迟和采样，利用多数表决判断出最终正确的输出，时间冗余要有三路或更多的锁存单元冗余，且带来额外的速度开销。通常的SET加固方式会选用滤波技术，相对于冗余技术，采用滤波技术滤除单粒子脉冲的方法引入的开销相对较少，具体实现方式为在时序单元内部的敏感端口，通过增加滤波电路，将输入信号上将一定宽度(Δt)以下的瞬态脉冲过滤掉，但是值得注意的是现有技术中，在时序单元中所应用的滤波器电路本身容易受到SET损伤，采用滤波器会引入额外的敏感体，当粒子轰击到滤波器输出节点所产生的SET脉冲传播至内部存储电路，引发存储数据的错误翻转，此种方法在单粒子瞬态加固方面虽然避免了由全局性信号(例如时钟信号)单粒子瞬态所引发的多单元单粒子翻转事件，但是由于所引入的额外敏感体，也增加了单个时序单元出现单粒子翻转的概率。此外，时序单元时钟信号SET加固方式使得每时序单元的面积会增加一个滤波器的面积，加固所带来的功耗开销会随着频率的提高而剧增，这些开销对于追求性能(低功耗、高速)的先进工艺节点集成电路是不可忍受的。
发明内容
本发明的技术解决问题是:克服现有技术的不足，提供一种抗单粒子瞬态时钟树结构，能够以较小的电路开销实现抑制时钟信号上单粒子瞬态脉冲产生和传播的目的。
本发明的技术解决方案是：一种抗单粒子瞬态时钟树结构，包括根节点 时钟驱动单元、子节点时钟驱动单元以及叶节点时钟驱动单元；
其中根节点时钟驱动单元为时钟树源端起始节点驱动单元，子节点时钟驱动单元为根节点时钟驱动单元的下级时钟驱动单元，级数为N级，N为整数；叶节点时钟驱动单元为时钟树末端叶节点驱动单元；根节点时钟驱动单元的输出端连接子节点时钟驱动单元的输入端，子节点时钟单元输出端连接叶节点时钟驱动单元的输入端，每一个叶节点时钟驱动单元输出两路时钟信号，用于连接一定数量的双时钟抗单粒子时序单元。
所述根节点时钟驱动单元和子节点时钟驱动单元的电路形式为时钟反相器电路或者时钟缓冲器电路。
所述时钟反相器电路包括PMOS管和NMOS管，PMOS管的栅极与NMOS管的栅极连接在一起，作为输入端I，PMOS管的漏极与NMOS管的漏极连接在一起，作为输出端ZN；PMOS管的源极接电源VDD，NMOS管的源极接地。
所述时钟缓冲器电路包括PMOS管、NMOS管、PMOS管和NMOS管，PMOS管的栅极与NMOS管的栅极接一起，作为输入端I，PMOS管的漏极与NMOS管的漏极连接后，再同时与PMOS管的栅极和NMOS管的栅极连接，PMOS管的漏极和NMOS管的漏极接一起，作为输出端ZN；PMOS管的源极和PMOS管的源极均接电源VDD，NMOS管的源极和NMOS管的源极均接地。
所述每个叶节点时钟驱动单元为双路滤波器。
所述双路滤波器由第一延迟单元、第二延迟单元、PMOS管、PMOS管、NMOS管、NMOS管、PMOS管、PMOS管、NMOS管以及NMOS管组成；其中，PMOS管、PMOS管、NMOS管、NMOS管依次串联构成第一双输入反相器，第一双输入反相器与第一延迟单元1构成一路滤波电 路；
PMOS管、PMOS管、NMOS管、NMOS管依次串联构成第二双输入反相器，第二双输入反相器与第二延迟单元组成另一路滤波电路；
PMOS管的源极和PMOS管的源极接电源VDD，NMOS管的源极和NMOS管的源极接地；PMOS管、NMOS管、PMOS管、NMOS管的栅级连接一起，并与第一延迟单元和第二延迟单元的输入相连，作为输入端A，PMOS管的栅极和NMOS管的栅极连接到第一延迟单元的输出端Z1，PMOS管的漏极和NMOS管的漏极连接在一起，作为双路滤波器的第一输出端Y1；PMOS管的栅极和NMOS管的栅极连接到第二延迟单元的输出端Z2，PMOS管的漏极和NMOS管的漏极连接在一起，作为双路滤波器的第二输出端Y2。
在双路滤波器版图布局中，两路滤波电路分离距离等于相邻MOS管漏端之间的最小距离L，L大于或等于D，D为具体制造工艺下单个粒子能在电路中造成影响的物理尺寸。
所述双路滤波器由第三延迟单元、PMOS管、NMOS管、PMOS管、PMOS管、NMOS管、NMOS管组成，其中，PMOS管与NMOS管串联构成反相器，PMOS管的源极接电源VDD，NMOS管的源极接地；PMOS管、PMOS管、NMOS管、NMOS管依次串联构成第三双输入反相器，PMOS管的源极接电源VDD，NMOS管的源极接地；PMOS管的栅极和NMOS管的栅级连接后与第三延迟单元的输入端连接，作为双路滤波器输入端A，第三延迟单元的输出Z同时与PMOS管的栅极、NMOS管的栅极、PMOS管的栅极、NMOS管的栅极连接，PMOS管的漏极与NMOS管的漏极连接后，作为双路滤波器的第一输出端Y1，PMOS管的漏极与NMOS管的漏极连接后，作为双路滤波器的第二输出端Y2。
在双路滤波器版图布局中，将PMOS管与NMOS管串联构成的反相器与第三延迟单元连接后的电路，与第三双输入反相器进行版图分离，分离距离等于相邻MOS管漏端之间的最小距离L，L大于或等于D，D为具体制造工艺下单个粒子能在电路中造成影响的物理尺寸。
所述第一延迟单元、第二延迟单元和第三延迟单元电路结构相同，均由两个反相器INV1和INV2组成，INV1的输入端与INV2的输出端连接，构成延迟单元的输入端A，INV1的输出端接INV2的输入端，构成延迟单元的输出端Z。
与现有技术相比，本发明具有如下有益效果：
(1)本发明相对于传统的时钟树结构，实现了抗单粒子瞬态的有效加固。对比传统的滤波加固方法，本发明契合先进工艺节点电路的尺寸小、间距窄、电路翻转的临界电荷Qcrit低的特点，考虑引入的滤波器电路本身的敏感性问题，在电路实现时不仅考虑了辐射粒子所引起单个节点单粒子瞬态问题，而且也考虑了多个节点出现单粒子瞬态脉冲从而引发时序单元的单粒子翻转问题，通过基于双路滤波器的时钟树结构设计，保证在单粒子轰击时，至少有一路滤波后的时钟信号工作正常，确保辐射粒子轰击时钟树网络的任意节点所引发的单粒子瞬态脉冲都不会引起时序单元时钟端的错误数据锁存事件，使得由时钟树网络上产生的单粒子瞬态导致时序单元发生单粒子翻转事件的概率为零，因此，本发明有效降低了时钟树网络受到辐射粒子轰击后各个时钟节点上产生单粒子瞬态脉冲的概率，显著提高了时钟信号分布网络抗单粒子瞬态的能力。
(2)传统加固方法，通常为在时序单元内部敏感端口增加抗单粒子瞬态的加固电路，基于抗单粒子加固时序电路所实现的集成电路，每个时序单元的面积会增加一个滤波器的面积，特别是，当滤波器放置在时序电路的时钟敏感端，功耗会随着频率的提高而剧增，使得集成电路的功耗开销极大， 本发明提出在时钟树结构中叶节点时钟驱动单元采用双路滤波器，由双路滤波器驱动多个双时钟抗单粒子时序单元，时序单元本身时钟敏感端无需引入冗余电路，仅时钟树叶节点时钟驱动单元采用抗单粒子瞬态加固电路，对于电路，抗单粒子瞬态加固电路(晶体管数量)的引入数量上要远小于传统加固设计，具有功耗低、速度快、面积小的低开销特点，满足先进工艺节点集成电路需求。
(3)传统延迟单元采用反相器级连，为实现一定延迟时间，反相器级连中通常会采用倒比管较大尺寸晶体管，而本发明延迟单元可采用较小尺寸的晶体管形成INV，通过锁存的逻辑结构，实现延迟特性，具有面积和性能开销小的特点，更契合时钟树结构设计需求，从而进一步降低了时钟树结构的功耗和面积。
(4)本发明给出了两种双路滤波器的结构形式，与传统的抗单粒子瞬态滤波器相比，双路滤波器本身对单粒子瞬态具有良好的免疫力，发生在结构内部任意节点的单粒子瞬态脉冲都不能使两路输出同时发生扰动确保整个电路具有极高的抗单粒子瞬态能力，可以有效消除发生在输入信号脉宽小于延迟单元延迟的以及发生在单元内部的单粒子脉冲。尤其是第一种双路滤波器电路，相对于第二种滤波器电路，具备更高的抗单粒子瞬态能力，第二种双路滤波器电路，当辐射粒子轰击到输入A、第三延迟单元、输出端Y1或者输出端Y2其中任意一处时，均会出现其中一路输出发生单粒子瞬态扰动的现象，而第一种双路滤波器电路只有在辐射粒子轰击到输出Y1或者输出端Y2时才会发生单粒子瞬态扰动，可靠性更高，因此第一种双路滤波器电路结构更适合于具有复杂单粒子效应(例如单粒子瞬态重汇聚、单粒子瞬态展宽)的先进工艺节点电路设计中。
附图说明
图1为本发明抗单粒子瞬态时钟树结构示意图；
图2为本发明抗单粒子瞬态时钟树结构中的时钟反相器电路以及时钟 缓冲器电路示意图，其中(a)为时钟反相器电路，(b)为时钟缓冲器电路；
图3为本发明双路滤波器的一种实现电路示意图；
图4为本发明双路滤波器的另一种实现电路示意图；
图5为本发明双路滤波器中的延迟单元实现示意图；
图6为本发明双时钟抗单粒子瞬态时序单元的一种实现电路示意图；
图7为本发明中双路滤波器以及双时钟抗单粒子瞬态时序单元的版图分离示意图；
图8为双路滤波器与双时钟抗单粒子瞬态时序单元连接示意图。
具体实施方式
本发明抗单粒子瞬态时钟树结构包括根节点时钟驱动单元11、子节点时钟驱动单元12和叶节点时钟驱动单元13。根节点时钟驱动单元11的输出连接子节点时钟驱动单元12的输入，子节点时钟单元12输出连接叶节点时钟驱动单元13输入。叶节点时钟驱动单元13的输出连接双时钟抗单粒子时序单元。子节点时钟驱动单元12为时钟树根节点时钟驱动单元11的下级时钟驱动单元，级数为N级，N为整数，具体级数依据设计电路的复杂度及其采用的时钟设计方案而定。时钟树中的根节点时钟驱动单元11所连接的子节点时钟驱动单元数目12、时钟树末端连接的叶节点时钟驱动单元13的数目以及每个叶节点时钟驱动单元所连接的双时钟抗单粒子时序单元的数目完全由设计单元具体的驱动能力和电路时序约束而定。
如图1所示为一种H型结构的时钟树，事实上，本发明也适用于平衡树、X树等多种形式的时钟树结构。如图8所示，双路滤波器的第一输出端Y1连接双时钟抗单粒子时序单元14的CK1端，双路滤波器的第二输出端Y2连接双时钟抗单粒子时序单元14的CK2端。
根节点时钟驱动单元11的电路形式为时钟反相器电路或者时钟缓冲器电路，子节点时钟驱动单元12的电路形式为时钟反相器电路或者时钟缓冲器电路。具体采用哪种电路依据设计电路的具体时序逻辑要求及其所采用的 时钟设计方案而定。其中时钟反相器电路如图2中(a)所示，包括PMOS管21和NMOS管22，PMOS管21的栅极与NMOS管22的栅极接一起，作为输入端I，PMOS管21的漏极与NMOS管22的漏极接一起，作为输出端ZN。PMOS管21的源极连接电源VDD，NMOS管22的源极接地。
时钟缓冲器电路如图2中(b)所示，包括PMOS管23、NMOS管24、PMOS管25以及NMOS管26，PMOS管23的栅极与NMOS管24的栅极接一起，作为输入端I，PMOS管23的漏极与NMOS管24的漏极接一起后，连至PMOS管25的栅极和NMOS管26的栅极，PMOS管25的漏极和NMOS管26漏极接一起，作为输出端ZN。PMOS管23和PMOS管25的源极连接电源VDD，NMOS管24和NMOS管26的源极接地。
本发明中，抗单粒子瞬态时钟树结构中的叶节点时钟驱动单元12为双路滤波器结构，由输入信号通过滤波电路输出两路互不干扰的信号。其中一种实现形式如图3所示，由第一延迟单元、第二延迟单元、PMOS管31、PMOS管32、NMOS管33、NMOS管34、PMOS管35、PMOS管36、NMOS管37、NMOS管38组成。其中，PMOS管31、PMOS管32、NMOS管33、NMOS管34依次串联构成第一双输入反相器，PMOS管31源极连接电源VDD，NMOS管34源极接地，第一双输入反相器与第一延迟单元构成一路滤波电路，PMOS管35、PMOS管36、NMOS管37、NMOS管38依次串联构成第二双输入反相器，PMOS管35源极连接电源VDD，NMOS管38源极接地，第二双输入反相器与第二延迟单元组成另一路滤波电路，PMOS管31的栅级、NMOS管34的栅级、PMOS管35的栅级、NMOS管38的栅级连接在一起后，与第一延迟单元和第二延迟单元的输入相连，作为输入端A，PMOS管32的栅级、NMOS管33的栅极连接到第一延迟单元的输出端Z1，PMOS管32的漏极与NMOS管33的漏极连接后作为第一输出端Y1，PMOS管36的栅极与NMOS管37的栅极连接到延迟单元2的输出端Z2，PMOS管36的漏极与NMOS管37的漏极连接后，作 为第二输出端Y2。首先，当输入信号A受到单粒子辐射而产生脉冲，且此脉冲宽度小于延迟单元的延迟时，通过延迟单元后的延时输入信号(即Z1点、Z2点)上的脉冲与输入A原信号上的脉冲不重叠的到达第一双输入反相器和第二双输入反相器的输入端，由于Z1与Z2与输入A所传输信号不同，因此保持之前的状态，两路滤波电路输出均不会对后续电路产生干扰。再者，双路滤波器输出(即Y1、Y2点)也存在单粒子辐射轰击同时产生脉冲的情况，因此在双路滤波器版图布局中根据抗单粒子加固电路中敏感节点的分离要求，将两路滤波电路分离，分离距离定义为相邻MOS管漏端之间的最小距离L，L大于或等于D，D为具体制造工艺下单个粒子能在电路中造成影响的物理尺寸，从而获得两路互不干扰的输出信号，确保单粒子轰击只可影响双路滤波器输出输出Y1或者Y2其中一路，保证至少一路滤波电路输出信号为抗单粒子瞬态的输出。图3的电路形式中，两路滤波电路逻辑完全相同，都具备滤波功能，可以消除发生于输入信号上的脉冲宽度小于滤波器内部设定的延迟时间的单粒子瞬态脉冲，同一输入信号通过两路滤波电路输出两个输出信号。
如图4所示为抗单粒子瞬态时钟树结构中的叶节点时钟驱动单元12的另一种电路形式，由第三延迟单元、PMOS管41、NMOS管42、PMOS管43、PMOS管44、NMOS管45、NMOS管46组成，其中，PMOS管41与NMOS管42串联构成反相器，PMOS管41源极连接电源VDD，NMOS管42源极接地，PMOS管43、PMOS管44、NMOS管45、NMOS管46依次串联构成第三双输入反相器，PMOS管43源极连接电源VDD，NMOS管46源极接地，PMOS管43的栅极、NMOS管46栅级以及延迟单元的输入端连接，作为双路滤波器输入端A，第三延迟单元的输出端Z同时接PMOS管41的栅极、NMOS管42的栅极、PMOS管44的栅极以及NMOS管45的栅极，PMOS管41与NMOS管42的漏极相连，作为双路滤波器第一输出端Y1，PMOS管44的漏极与NMOS管45的漏极相连，作为双路滤波 器第二输出端Y2。在该种双路滤波器的版图布局中，根据抗单粒子加固电路中敏感节点的分离要求，将PMOS管41与NMOS管42串联构成的反相器与第三延迟单元连接后的电路、与PMOS管43、PMOS管44、NMOS管45、NMOS管46依次串联所构成的第三双输入反相器进行版图分离，分离距离定义为相邻MOS管漏端之间的最小距离L。L大于或等于D，D为具体制造工艺下单个粒子能在电路中造成影响的物理尺寸。由于在版图布局上进行敏感路径的有效分离，发生在任一节点上的单粒子瞬态脉冲至多影响本电路的一个输出(Y1或者Y2)，保证至少一路滤波电路输出信号为抗单粒子瞬态的输出。当输入信号A受到单粒子辐射而产生脉冲时，且此脉冲宽度小于延迟单元的延迟，PMOS管41与NMOS管42构成的反相器的第一输出端Y1仍会传播单粒子瞬态脉冲，但通过延时单元后的延时输入信号(即Z点输出)上的脉冲与原信号上的脉冲不重叠的到达双输入反相器单元的输入，在脉冲处两者逻辑不同，第三双输入反相器的第二输出端Y2会保持之前的状态，Y2会产生抗单粒子瞬态的输出。
第一延迟单元、第二延迟单元和第三延迟单元电路组成相同，如图5所示为图3、图4双路滤波器电路中延迟单元的实现电路，由两个反相器(INV1和INV2)组成，INV1的输入端接INV2的输出端，构成延迟单元的输入端A，INV1的输出端接INV2的输入端，构成延迟单元的输出端Z，相比于采用反相器级连利用反相器本身的延迟时间递推形成一定延迟时间电路实现的方式，本发明延迟单元可采用较小尺寸的晶体管形成INV，通过锁存的逻辑结构，实现延迟特性，具有面积和性能开销小的特点。
抗单粒子瞬态时钟树结构中的双时钟抗单粒子时序单元的电路形式为由两路完全相同时钟信号分别控制具有冗余节点的存储结构，在版图布局中根据抗单粒子加固电路中敏感节点的分离要求，将两路时钟的逻辑电路分离，确保时序单元中某一路时钟信号由粒子轰击导致出现单粒子瞬态时不会引起时序单元的存储结构出现单粒子翻转，时序单元类型包含锁存器、触发 器。
图6所示为抗单粒子瞬态时钟树结构中的双时钟抗单粒子时序单元的一种电路形式，即采用两模存储结构(DMR)的双时钟抗单粒子时序单元，CK1连接两级反相器，提供时钟反向CKN1与时钟同向CKNN1信号，时钟CK1与CK2电路完全相同，CK1的输出CKN1与CKNN1以及CK2的输出CKN2与CKNN2分别连接双模存储结构以及数据输入时钟控制端。在版图布局中需要将CK1与CK2的电路进行物理分离，如图7所示，在布局过程中要保障版图第一路时钟71、第二路时钟72电路版图的敏感节点分离距离大于特定间距L(定义为相邻MOS管漏端之间的最小距离)，L大于或等于D，D为具体制造工艺下单个粒子能在电路中造成影响的物理尺寸。确保由时钟树结构上任意一路输出所产生的单粒子瞬态脉冲不会引起时序单元出现存储结构的单粒子翻转，也同时保证了时序单元时钟信号任一节点上的单粒子瞬态脉冲不会引起时序单元出现存储结构的单粒子翻转。
本发明中，相邻MOS管漏端之间的最小距离L满足L≥D要求。在综合考虑版图面积的前提下，D值越大越好，较大D值可更好的保证敏感节点不会同时受到单粒子的影响。假如某工艺尺寸下单个粒子能在电路中造成影响的物理尺寸D为2.5um，要求敏感节点间距L≥2.5um，即在对底层模块版图进行布局时，需要保证各个敏感节点之间的距离大于2.5um。
本发明抗单粒子瞬态时钟树结构的工作过程如下：
以图1所示的H型时钟树结构抗单粒子瞬态时钟树结构为例来说明本发明的具体应用。假设时钟输入clk为0，时钟树上各个时钟节点受空间粒子轰击后有以下可能产生单粒子瞬态脉冲的事件：1、当根节点时钟驱动单元采用时钟反相器电路时，时钟反相器的NMOS管漏端受到辐射粒子的轰击会产生单粒子瞬态脉冲；当根节点时钟驱动单元采用时钟缓冲器电路时，缓冲器的第一级NMOS管或者第二级PMOS漏端受到辐射粒子的轰击会产 生单粒子瞬态脉冲；2、子节点时钟驱动单元采用时钟反相器电路或者时钟缓冲器电路时，相应的关态NMOS管或者PMOS管漏区受到辐射粒子的轰击会产生单粒子瞬态脉冲；上述时钟网络节点上所产生的单粒子瞬态脉冲会最终沿时钟网络传播至叶节点时钟驱动单元双路滤波器的输入端，根据具体的工艺节点下单粒子瞬态脉冲的特征，设置滤波电路内部的延迟时间，双路滤波器可以消除发生于输入信号上的脉冲宽度小于滤波器内部设定的延迟时间的单粒子瞬态脉冲，上述的事件1或事件2所产生的单粒子瞬态脉冲最终都会被双路滤波器滤除，从而不会影响到叶节点时钟驱动单元所连接的全部大量的时序单元。第3种可能事件，是辐射粒子轰击到双路滤波器内部敏感节点或者双路滤波器的输出节点时的情况，由于本发明的双路滤波器有两路互不干扰的输出逻辑，且两路逻辑在物理版图布局中根据抗单粒子加固电路中敏感节点的分离要求完成了敏感节点物理分离，因此，当辐射粒子入射轰击到双路滤波器里的敏感节点时，至多仅有一路冗余滤波电路输出Y1或者Y2会出现单粒子瞬态脉冲，另一路仍为正常的时钟信号0，双路滤波器后面所驱动的为双时钟抗单粒子时序单元，两路时钟分别控制具有冗余节点的存储结构，两路时钟同样在物理布局中完成了敏感节点分离，因此仅一路Y1或者Y2所出现的单粒子瞬态脉冲传播至双时钟抗单粒子时序单元的时钟端口CK1或者CK2中，另一路的正常时钟信号0确保了时序单元存储结构不会出现锁存错误数据的事件，从而保证了时序单元数据的正确性。
本发明可以消除发生于输入信号上的脉冲宽度小于滤波器内部设定的延迟时间的单粒子瞬态脉冲，且同一输入信号输出两路互不干扰的输出信号。双路滤波单元作为叶节点时钟驱动单元，按照电路具体驱动负载约束，连接可驱动的一定数量的双时钟抗单粒子时序单元，具有两路时钟加固结构特点的时序单元均可应用到本发明的抗单粒子瞬态时钟树结构中。
本发明相对于传统的时钟树结构，实现了抗单粒子瞬态的有效加固。对 比传统的滤波加固方法，考虑引入的抗单粒子加固电路本身的敏感性问题，确保辐射粒子轰击时钟树网络的任意节点所引发的单粒子瞬态脉冲都不会引起时序单元时钟端的错误数据锁存事件，契合先进工艺节点电路的尺寸小、间距窄、电路翻转的临界电荷Qcrit低的特点，在电路实现时不仅考虑了辐射粒子所引起单个节点单粒子瞬态问题，而且也考虑了多个节点出现单粒子瞬态脉冲从而引发时序单元的单粒子翻转问题，使得由时钟树网络上产生的单粒子瞬态导致时序单元发生单粒子翻转事件的概率为零，因此，本发明有效降低了时钟树网络受到辐射粒子轰击后各个时钟节点上产生单粒子瞬态脉冲的概率，显著提高了时钟信号分布网络抗单粒子瞬态的能力。
对比传统加固方法，通常为在时序单元内部敏感端口增加抗单粒子瞬态的加固电路，基于抗单粒子加固时序电路所实现的集成电路，每时序单元的面积会增加一个滤波器的面积，特别是，功耗会随着频率的提高而剧增，使得集成电路的功耗开销极大，本发明提出在时钟树结构中叶节点时钟驱动单元采用双路滤波器，由双路滤波器驱动多个双时钟抗单粒子时序单元，时序单元本身时钟端无需引入冗余电路，仅时钟树叶节点时钟驱动单元采用抗单粒子瞬态加固电路，对于电路，抗单粒子瞬态加固电路(晶体管数量)的引入数量上要远小于传统加固设计，具有功耗低、面积小的低开销特点。
本说明书中未作详细描述的内容属本领域专业技术人员的公知技术。

Claims (10)

  1. 一种抗单粒子瞬态时钟树结构，其特征在于：包括根节点时钟驱动单元(11)、子节点时钟驱动单元(12)以及叶节点时钟驱动单元(13)；
    其中根节点时钟驱动单元(11)为时钟树源端起始节点驱动单元，子节点时钟驱动单元(12)为根节点时钟驱动单元(11)的下级时钟驱动单元，级数为N级，N为整数；叶节点时钟驱动单元(13)为时钟树末端叶节点驱动单元；根节点时钟驱动单元(11)的输出端连接子节点时钟驱动单元(12)的输入端，子节点时钟单元(12)输出端连接叶节点时钟驱动单元(13)的输入端，每一个叶节点时钟驱动单元(13)输出两路时钟信号，用于连接一定数量的双时钟抗单粒子时序单元。
  2. 根据权利要求1所述的一种抗单粒子瞬态时钟树结构，其特征在于：所述根节点时钟驱动单元(11)和子节点时钟驱动单元(12)的电路形式为时钟反相器电路或者时钟缓冲器电路。
  3. 根据权利要求2所述的一种抗单粒子瞬态时钟树结构，其特征在于：所述时钟反相器电路包括PMOS管(21)和NMOS管(22)，PMOS管(21)的栅极与NMOS管(22)的栅极连接在一起，作为输入端I，PMOS管(21)的漏极与NMOS管(22)的漏极连接在一起，作为输出端ZN；PMOS管(21)的源极接电源VDD，NMOS管(22)的源极接地。
  4. 根据权利要求2所述的一种抗单粒子瞬态时钟树结构，其特征在于：所述时钟缓冲器电路包括PMOS管(23)、NMOS管(24)、PMOS管(25)和NMOS管(26)，PMOS管(23)的栅极与NMOS管(24)的栅极接一起，作为输入端I，PMOS管(23)的漏极与NMOS管(24)的漏极连接后，再同时与PMOS管(25)的栅极和NMOS管(26)的栅极连接，PMOS管(25)的漏极和NMOS管(26)的漏极接一起，作为输出端ZN； PMOS管(23)的源极和PMOS管(25)的源极均接电源VDD，NMOS管(24)的源极和NMOS管(26)的源极均接地。
  5. 根据权利要求1所述的一种抗单粒子瞬态时钟树结构，其特征在于：所述每个叶节点时钟驱动单元(13)为双路滤波器。
  6. 根据权利要求5所述的一种抗单粒子瞬态时钟树结构，其特征在于：所述双路滤波器由第一延迟单元、第二延迟单元、PMOS管(31)、PMOS管(32)、NMOS管(33)、NMOS管(34)、PMOS管(35)、PMOS管(36)、NMOS管(37)以及NMOS管(38)组成；其中，PMOS管(31)、PMOS管(32)、NMOS管(33)、NMOS管(34)依次串联构成第一双输入反相器，第一双输入反相器与第一延迟单元1构成一路滤波电路；
    PMOS管(35)、PMOS管(36)、NMOS管(37)、NMOS管(38)依次串联构成第二双输入反相器，第二双输入反相器与第二延迟单元组成另一路滤波电路；
    PMOS管(31)的源极和PMOS管(35)的源极接电源VDD，NMOS管(34)的源极和NMOS管(38)的源极接地；PMOS管(31)、NMOS管(34)、PMOS管(35)、NMOS管(38)的栅级连接一起，并与第一延迟单元和第二延迟单元的输入相连，作为输入端A，PMOS管(32)的栅极和NMOS管(33)的栅极连接到第一延迟单元的输出端Z1，PMOS管(32)的漏极和NMOS管(33)的漏极连接在一起，作为双路滤波器的第一输出端Y1；PMOS管(36)的栅极和NMOS管(37)的栅极连接到第二延迟单元的输出端Z2，PMOS管(36)的漏极和NMOS管(37)的漏极连接在一起，作为双路滤波器的第二输出端Y2。
  7. 根据权利要求6所述的一种抗单粒子瞬态时钟树结构，其特征在于：在双路滤波器版图布局中，两路滤波电路分离距离等于相邻MOS管漏端之 间的最小距离L，L大于或等于D，D为具体制造工艺下单个粒子能在电路中造成影响的物理尺寸。
  8. 根据权利要求5所述的一种抗单粒子瞬态时钟树结构，其特征在于：所述双路滤波器由第三延迟单元、PMOS管(41)、NMOS管(42)、PMOS管(43)、PMOS管(44)、NMOS管(45)、NMOS管(46)组成，其中，PMOS管(41)与NMOS管(42)串联构成反相器，PMOS管(41)的源极接电源VDD，NMOS管(42)的源极接地；PMOS管(43)、PMOS管(44)、NMOS管(45)、NMOS管(46)依次串联构成第三双输入反相器，PMOS管(43)的源极接电源VDD，NMOS管(46)的源极接地；PMOS管(43)的栅极和NMOS管(46)的栅级连接后与第三延迟单元的输入端连接，作为双路滤波器输入端A，第三延迟单元的输出Z同时与PMOS管(41)的栅极、NMOS管(42)的栅极、PMOS管(44)的栅极、NMOS管(45)的栅极连接，PMOS管(41)的漏极与NMOS管(42)的漏极连接后，作为双路滤波器的第一输出端Y1，PMOS管(44)的漏极与NMOS管(45)的漏极连接后，作为双路滤波器的第二输出端Y2。
  9. 根据权利要求8所述的一种抗单粒子瞬态时钟树结构，其特征在于：在双路滤波器版图布局中，将PMOS管(41)与NMOS管(42)串联构成的反相器与第三延迟单元连接后的电路，与第三双输入反相器进行版图分离，分离距离等于相邻MOS管漏端之间的最小距离L，L大于或等于D，D为具体制造工艺下单个粒子能在电路中造成影响的物理尺寸。
  10. 根据权利要求6或8所述的一种抗单粒子瞬态时钟树结构，其特征在于：所述第一延迟单元、第二延迟单元和第三延迟单元电路结构相同，均由两个反相器INV1和INV2组成，INV1的输入端与INV2的输出端连接，构成延迟单元的输入端A，INV1的输出端接INV2的输入端，构成延迟单元的输出端Z。
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CN108199698A (zh) * 2017-12-13 2018-06-22 北京时代民芯科技有限公司 一种双时钟抗单粒子锁存器
CN109976503A (zh) * 2017-12-28 2019-07-05 炬芯（珠海）科技有限公司 一种芯片多源时钟树的主干网络
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