WO2018216251A1 - Circuit d'attaque de gâchette - Google Patents

Circuit d'attaque de gâchette Download PDF

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Publication number
WO2018216251A1
WO2018216251A1 PCT/JP2017/045072 JP2017045072W WO2018216251A1 WO 2018216251 A1 WO2018216251 A1 WO 2018216251A1 JP 2017045072 W JP2017045072 W JP 2017045072W WO 2018216251 A1 WO2018216251 A1 WO 2018216251A1
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Prior art keywords
switching element
semiconductor switch
period
gate
terminal
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PCT/JP2017/045072
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English (en)
Japanese (ja)
Inventor
陽平 丹
航平 恩田
亮太 近藤
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三菱電機株式会社
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Priority to JP2018520204A priority Critical patent/JP6370524B1/ja
Publication of WO2018216251A1 publication Critical patent/WO2018216251A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to a gate drive circuit for driving on / off a semiconductor switch to be controlled.
  • the first switching element connected in series between the positive terminal of the DC power supply and the first node, and the first connected in series between the first node and the negative electrode of the DC power supply.
  • the first node is connected to the gate terminal of the semiconductor switch to be driven and the negative electrode of the DC power supply is connected to the source terminal of the semiconductor switch, so that the accumulated charge of the input capacitance of the semiconductor switch So as to power regenerated to the DC power supply side, to reduce the loss of the gate driving circuit, there is a method to reduce the size of the circuit (for example, see Patent Document 1 below).
  • Patent Document 1 when the power regeneration type gate drive technology of a single power source disclosed in Patent Document 1 is used for an inverter composed of a half-bridge or full-bridge circuit composed of semiconductor switches of a high-voltage side arm and a low-voltage side arm, When the semiconductor switch of the high-voltage side arm is turned on, the voltage between the drain terminal and the source terminal of the semiconductor switch of the low-voltage side arm rises, whereby the voltage between the gate terminal and the source terminal of the semiconductor switch of the low-voltage side arm This causes a malfunction that causes the malfunction of the semiconductor switch of the low-voltage side arm that is lifted and turned off.
  • the present invention has been made to solve the above-described problems, and in a conventional single power supply power regeneration type gate drive circuit, a negative voltage is applied between the gate terminal and the source terminal of the corresponding semiconductor switch.
  • the purpose is to prevent malfunction of the semiconductor switch.
  • the gate drive circuit is: A DC circuit is connected in parallel with a series circuit composed of a first switching element and a second switching element, and a series circuit composed of a third switching element and a fourth switching element, A first node that is a connection point between the first switching element and the second switching element, and a second node that is a connection point between the third switching element and the fourth switching element. Connect a reactor between the node and Connecting the first node to a gate terminal of a semiconductor switch to be driven and controlled; A diode is connected between the second switching element and the negative terminal of the DC power supply; A switching control circuit for controlling the on / off operation of each of the first, second, third, and fourth switching elements is provided.
  • the gate drive circuit of the present invention when the semiconductor switch to be driven is turned off, the accumulated charge of the input capacitance of the semiconductor switch is regenerated to the power source side by the reactor, and the gate of the semiconductor switch It becomes possible to apply a negative voltage between the sources. Therefore, even in a conventional single power source power regeneration type gate drive circuit, it is possible to reliably prevent malfunction of the semiconductor switch.
  • FIG. 1 is a circuit diagram showing a configuration of a gate drive circuit according to a first embodiment of the present invention.
  • FIG. 6 is a timing chart showing the operation of the first to fourth switching elements of the gate drive circuit according to the first embodiment of the present invention.
  • FIG. 3 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements shown in FIG.
  • FIG. 3 is a current path diagram in one operation period shown in FIG. 2.
  • FIG. 3 is a current path diagram in one operation period shown in FIG. 2.
  • FIG. 3 is a current path diagram in one operation period shown in FIG. 2.
  • It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 1 of this invention.
  • FIG. 10 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fifth switching elements shown in FIG. 9;
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 2 of this invention.
  • It is a circuit diagram which shows the structure of the gate drive circuit by Embodiment 3 of this invention.
  • 14 is a timing chart showing operations of first to fourth switching elements of a gate drive circuit according to Embodiment 3 of the present invention.
  • FIG. 23 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fourth switching elements shown in FIG. 22;
  • FIG. 23 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fourth switching elements shown in FIG. 22;
  • FIG. 23 is an operation
  • FIG. 23 is a current path diagram in one operation period shown in FIG. 22.
  • FIG. 23 is a current path diagram in one operation period shown in FIG. 22.
  • FIG. 23 is a current path diagram in one operation period shown in FIG. 22.
  • It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 3 of this invention.
  • 14 is a timing chart showing first to fourth switching operations of a gate drive circuit according to a fourth embodiment of the present invention.
  • FIG. 29 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of each of the first to fourth switching elements shown in FIG.
  • FIG. 29 is a current path diagram in one operation period shown in FIG. 28.
  • FIG. 1 is a circuit diagram showing a configuration of a gate drive circuit according to the first embodiment.
  • the gate drive circuit 100 according to the first embodiment uses a voltage-driven semiconductor switch 9 having an input capacitor 10 as a drive control target and drives the semiconductor switch 9 on and off with a single DC power supply 7. .
  • a series circuit including a first switching element 1 and a second switching element 2, and a third switching element 3 and a fourth switching element with respect to the DC power supply 7. 4 series circuits are connected together in parallel.
  • the reactor 6 is connected between the two nodes 12 and the first node 11 is connected to the gate terminal of the semiconductor switch 9 to be driven and controlled.
  • a diode 8 is connected between the second switching element 2 and the negative terminal of the DC power supply 7.
  • a switching control circuit 50 that controls the on / off operations of the first, second, third, and fourth switching elements 1, 2, 3, and 4 is provided.
  • the DC voltage of the DC power supply 7 (hereinafter referred to as power supply voltage) is Vdc
  • the current flowing through the reactor 6 (hereinafter referred to as reactor current) is iL
  • the current flowing through the input capacitor 10 of the semiconductor switch 9 is ig
  • the semiconductor A voltage applied between the gate terminal and the source terminal via the input capacitor 10 of the switch 9 (hereinafter referred to as a gate-source voltage) is VgsL
  • a voltage applied between the drain terminal and the source terminal of the semiconductor switch 9 (hereinafter referred to as “voltage”).
  • VsL) the current flowing through the drain terminal of the semiconductor switch 9 is idL.
  • the driving signal for the first switching element 1 is Q1
  • the driving signal for the second switching element 2 is Q2
  • the driving signal for the third switching element 3 is Q3
  • the driving signal for the fourth switching element 4 is Q4.
  • the inductance value of the reactor 6 is L
  • the capacitance value of the input capacitor 10 is Ciss. If the resonance period determined by the reactor 6 and the input capacitor 10 is T, the resonance period T can be expressed by the following (formula 1).
  • the first to fourth switching elements 1 to 4 are MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) each including a parasitic diode as an example here.
  • MOSFETs Metal-Oxide-Semiconductor Field Effect Transistors
  • a configuration in which a diode and an IGBT (Insulated Gate Bipolar Transistor) are connected in parallel may be used.
  • a thyristor or a GTO (Gate Turn-Off thyristor) in which diodes are connected in parallel may be used.
  • the first to fourth switching elements 1 to 4 are regarded as MOSFETs, and the forward voltage of the parasitic diode and the diode 8 is regarded as zero.
  • FIG. 2 is a timing chart showing the operations of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 in accordance with the on / off operation of the semiconductor switch 9 to be driven.
  • the semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the semiconductor switch 9 is turned on within the period from the period T4 to the period T6.
  • the six periods T1 to T6 are defined as follows.
  • Period T1 Excitation period of the reactor 6
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • Period T3 Semiconductor switch 9 off Fixed duration (4)
  • Period T4 Reactor 6 excitation period (5)
  • Period T5 Positive voltage application period to the gate of the semiconductor switch 9 (6)
  • Period T6 Semiconductor switch 9 on-fixed duration
  • FIG. 3 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG. 4 to 6 show current paths in the above-described periods T1 to T3.
  • FIGS. 3 the principle of operation will be described with reference to FIGS.
  • Period T1 Excitation period of the reactor 6 In this period T1, the first switching element 1 is on, the second, third, and fourth switching elements 2, 3, and 4 are all off, and the semiconductor switch From the state in which 9 is fixed to ON, the first switching element 1 is turned off and the fourth switching element 4 is turned on for a predetermined time ta. Then, as shown in FIG. 4, the current flows from the input capacitor 10 to the node 11, flows into the fourth switching element 4 through the reactor 6 and the node 12, and returns to the input capacitor 10.
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • the fourth switching element 4 is turned off, and the first time period tb is reached. 2 switching element 2 is turned off.
  • the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 is conducted, flows into the positive electrode of the DC power supply 7, and returns to the input capacitor 10.
  • a part of the excitation energy of the reactor 6 is regenerated to the DC power source 7 and the remainder of the excitation energy flows from the negative electrode of the DC power source 7 to the input capacitor 10, so that the gate-source voltage VgsL is directed toward the negative electrode.
  • the current iL increases toward the positive electrode. Therefore, a negative voltage is applied to the gate of the semiconductor switch 9.
  • Period T3 Fixed off duration of semiconductor switch 9 In this period T3, the second switching element 2 is turned on. At this time, as shown in FIG. 3, since the gate-source voltage VgsL is a negative voltage and the reactor current iL is zero, the parasitic diode of the fourth switching element 4 becomes conductive. As a result, as shown in FIG. 6, current flows from the input capacitor 10 to the node 12 via the parasitic diode of the fourth switching element 4. Thereafter, the current flows from the node 12 through the reactor 6 to the node 11 and returns to the input capacitor 10.
  • the gate-source voltage VgsL is increased toward the positive electrode.
  • the diode 8 causes the semiconductor switch 9.
  • the gate-source voltage VgsL is clamped to zero and the semiconductor switch 9 continues to be turned off. Needless to say, the change in the gate-source voltage VgsL from the negative electrode to the positive electrode is suppressed by the reactor 6.
  • Period T4 Excitation period of the reactor 6
  • the third switching element 3 is turned on.
  • the current flows from the positive electrode of the DC power supply 7 to the node 12 via the third switching element 3.
  • the current flows from the node 12 to the cathode of the diode 8 through the reactor 6 and the second switching element 2, and returns to the negative electrode of the DC power supply 7. Since the reactor 6 is excited by this current path, the reactor current iL increases to the positive electrode.
  • Period T5 Positive voltage application period to the gate of the semiconductor switch 9 In this period T5, the second switching element 2 is turned off. In this case, the reactor current iL continuously flows through the reactor 6 and charges the input capacitor 10. As a result, the gate-source voltage VgsL increases toward the positive electrode.
  • Period T6 On-fixing continuation period of the semiconductor switch 9 In this period T6, the first switching element 1 is turned on. Then, the current forms a path for returning from the positive electrode of the DC power source 7 to the negative electrode of the DC power source 7 via the first switching element 1 and the input capacitor 10. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
  • the gate driving circuit 100 when the semiconductor switch 9 is turned off, a part of the accumulated charge Ciss of the input capacitor 10 is regenerated to the DC power source 7 side by the reactor 6, and the input capacitor 10 The remainder of the accumulated charge Ciss can be applied as a negative voltage between the gate and source of the semiconductor switch 9. Therefore, it is possible to reliably prevent the malfunction of the semiconductor switch 9 without providing a negative power supply as in the prior art, and to obtain the gate drive circuit 100 that is simple and can be miniaturized.
  • the gate-source voltage VgsL and the reactor current iL at this time ta can be expressed by a trigonometric function as shown in the following (Expression 2) and (Expression 3).
  • the predetermined time ta is set to be longer than a quarter of the resonance period T determined by the reactor 6 and the input capacity 10 and shorter than a half of the resonance period T determined by the reactor 6 and the input capacity 10.
  • the gate-source voltage VgsL and the reactor current iL have negative values, and a period during which a negative voltage is applied as the voltage VgsL between the gate terminal and the source terminal of the semiconductor switch 9 can be provided in a part of the period T1. .
  • the negative voltage application period is increased, there is an advantage that the turn-on timing setting of a high voltage side arm (not shown) connected in series to the semiconductor switch 9 can be facilitated.
  • reactor current iL is a negative value, reactor 6 is excited and it goes without saying that the excitation energy is regenerated to DC power supply 7 in period T2.
  • a predetermined time tb for turning off the second switching element 2 described in the period T2 will be described.
  • This time tb is assumed to be when the gate-source voltage VgsL is less than or equal to zero. In other words, when the gate-source voltage VgsL is a negative value, the second switching element 2 is turned on.
  • an increase in the gate-source voltage VgsL to the positive electrode due to the current through the parasitic diode of the fourth switching element 4 can be prevented, and malfunction of the semiconductor switch 9 can be suppressed.
  • FIG. 7 shows a modification of the gate drive circuit shown in FIG. 1, and the same reference numerals are given to components corresponding to or corresponding to FIG.
  • FIG. 7 differs from the configuration of FIG. 1 in that the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the semiconductor switch 9.
  • the cathode terminal of the first Zener diode 31 is connected to the gate terminal of the semiconductor switch 9.
  • the cathode terminal of the second Zener diode 32 is connected to the source terminal of the semiconductor switch 9. Further, the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other.
  • a first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistor 42 is connected between the second switching element 2 and the first node 11. (Roff) is connected.
  • the input capacitance of the semiconductor switch 9 can be increased. Therefore, for example, when a high-voltage side arm (not shown) connected in series to the semiconductor switch 9 is turned on, the voltage VdsL between the drain terminal and the source terminal of the semiconductor switch 9 serving as the low-voltage side arm increases. Lifting of the gate-source voltage VgsL to the positive electrode side can be suppressed. Therefore, malfunction of the semiconductor switch 9 can be suppressed.
  • the second Zener diode 32 provides an effect of preventing a negative overvoltage from being applied between the gate terminal and the source terminal of the semiconductor switch 9 in the period T1 to the period T3.
  • the first Zener diode 31 provides an effect of preventing a positive overvoltage from being applied between the gate terminal and the source terminal of the semiconductor switch 9 when, for example, the semiconductor switch 9 is fixed on after the period T4.
  • the first resistor 41 provides an effect of preventing an inrush current based on a potential difference between the gate-source voltage VgsL and the power supply voltage Vdc when the semiconductor switch 9 is fixed on from the period T3, for example.
  • the second resistor 42 provides an effect of preventing an inrush current based on a potential difference between the gate-source voltage VgsL and the forward voltage of the diode 8 when clamping the gate-source voltage VgsL in the period T3.
  • the first resistor 41 may not be provided separately and the internal resistance of the first switching element 1 may be used. Similarly, the internal resistance of the second switching element 2 may be used without providing the second resistor 42 separately.
  • the other configuration and operational effects of the gate drive circuit 100 shown in FIG. 7 are the same as those of the configuration shown in FIG.
  • Embodiment 2 when the semiconductor switch 9 is turned off, a part of the stored charge Ciss of the input capacitor 10 is regenerated to the DC power supply 7 side by the reactor 6 and the remaining stored charge Ciss of the input capacitor 10 is transferred to the semiconductor switch. 9 is applied as a negative voltage between the gate terminal and the source terminal.
  • the gate-source voltage VgsL when the gate-source voltage VgsL is a negative value, the current flows into the input capacitor 10 via the parasitic diode of the fourth switching element 4, and the gate-source voltage VgsL is charged toward the positive electrode. Due to this charging, loss of the gate driving circuit 100 occurs.
  • FIG. 8 is a circuit diagram showing a configuration of the gate drive circuit according to the second embodiment of the present invention, and components corresponding to or corresponding to the configuration shown in FIG. 1 are denoted by the same reference numerals.
  • the gate drive circuit 100 according to the second embodiment is different from the circuit configuration according to the first embodiment (FIG. 1) in that the fifth switching element 5 is provided between the fourth switching element 4 and the negative terminal of the DC power source 7. They are connected in series. A first capacitor 21 is connected in parallel to the anode terminal and the cathode terminal of the diode 8. Further, the switching control circuit 50 is additionally provided with a drive signal Q5 for driving the fifth switching element 5.
  • FIG. 9 is a timing chart showing the operation of the first to fifth switching elements 1 to 5 of the gate drive circuit 100 in accordance with the on / off operation of the semiconductor switch 9 to be driven and controlled.
  • the semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the semiconductor switch 9 is turned on within the period from the period T4 to the period T9.
  • the nine periods T1 to T9 are defined as follows.
  • Period T1 Excitation period of the reactor 6
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitance 10 and negative voltage application period to the gate of the semiconductor switch 9
  • Period T3 Semiconductor switch 9 OFF fixed continuation period (4) period
  • T4 power regeneration period of charge accumulated by the input capacitor 10 and the first capacitor 21 and excitation period (5)
  • period of the reactor 6 T5: charge injection period (6) period to the input capacitor 10
  • Period T6 Period of recirculation to reactor 6
  • Period T7 Power regeneration period to DC power supply 7 by exciting current of reactor 6
  • Period T8 Power regeneration continuation period to DC power supply 7 by exciting current of reactor 6 ( 9)
  • Period T9 On-fixed duration of semiconductor switch 9
  • FIG. 10 is an operation waveform diagram showing changes in the current and voltage of each part accompanying the operation of each of the first to fifth switching elements 1 to 5 based on FIG.
  • FIGS. 11 to 19 show current paths in the operation periods T1 to T9.
  • the operation principle will be described with reference to FIGS.
  • Period T1 Excitation period of the reactor 6
  • the first switching element 1 is turned on, and the second, third, fourth, and fifth switching elements 2, 3, 4, and 5 are all turned off.
  • the first switching element 1 is turned off, and the fourth and fifth switching elements 4 and 5 are turned on for a predetermined time ta.
  • the current flows from the input capacitor 10 to the node 11, flows into the fourth and fifth switching elements 4 and 5 through the reactor 6 and the node 12, and returns to the input capacitor 10.
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • the fourth switching element 4 is turned off, and the period of time is predetermined. 2 switching element 2 is turned off.
  • the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 becomes conductive and flows into the positive electrode of the DC power supply 7.
  • One of the currents is fed back to the reactor 6 through the first capacitor 21 and the parasitic diode of the second switching element 2, and the other of the currents is fed back to the reactor 6 through the input capacitor 10.
  • the gate-source voltage VgsL increases to the negative electrode.
  • the voltage applied to the first capacitor 21 is not shown, it goes without saying that the voltage increases to the negative electrode similarly to the gate-source voltage VgsL. Thereafter, the value of the reactor current iL approaches zero, and the gate-source voltage VgsL becomes a certain negative voltage value.
  • Period T3 Fixed off duration of semiconductor switch 9 In this period T3, the second switching element 2 is turned on. At this time, the gate-source voltage VgsL and the applied voltage of the first capacitor 21 are both negative voltages. However, since the capacitance of the first capacitor 21 is generally larger than the input capacitance 10 of the semiconductor switch 9, A voltage difference is generated between the gate-source voltage VgsL and the voltage applied to the first capacitor 21.
  • the current flows from the first capacitor 21 to the input capacitor 10 via the second switching element 2 as shown in FIG. 13, and charges the input capacitor 10.
  • the first capacitor 21 may be charged by the input capacitor 10.
  • the semiconductor switch 9 is fixed to the off state.
  • Period T4 Power regeneration period of stored charges by the input capacitor 10 and the first capacitor 21 and the excitation period of the reactor 6
  • the second switching element 2 and the semiconductor switch 9 are turned on.
  • the third switching element 3 is turned on for a predetermined time tc.
  • one of the currents is fed back from the first node 11 to the negative electrode of the DC power supply 7 via the second switching element 2 and the first capacitor 21.
  • the other current is fed back from the first node 11 to the negative electrode of the DC power supply 7 through the input capacitor 10.
  • both the input capacitor 10 and the first capacitor 21 are discharged, and the gate-source voltage VgsL approaches zero from the negative voltage value.
  • the electric charges stored in the input capacitor 10 and the first capacitor 21 are regenerated in the reactor 6.
  • Period T5 Charge injection period to the input capacitor 10 In this period T5, the second switching element 2 is turned off. In that case, as shown in FIG. 15, since the reactor 6 continuously flows the reactor current iL, the current flows from the reactor 6 toward the first node 11, the input capacitor 10, and the negative electrode of the DC power source 7, Charge the capacity 10.
  • the input capacitor 10 is charged by this current path, and the gate-source voltage VgsL approaches the power supply voltage Vdc from zero. Thereafter, when the gate-source voltage VgsL reaches the power supply voltage Vdc, the parasitic diode of the first switching element 1 becomes conductive. Even in that case, since the reactor 6 continuously flows the reactor current iL, the current path is not shown, but the first node 11, the parasitic diode of the first switching element 1, the third switching element 3 from the reactor 6. , And flows toward the second node 12. That is, the reactor 6 is performing a reflux operation.
  • Period T6 Return Period to Reactor 6 In this period T6, the first switching element 1 is turned on. Also in this case, since the reactor 6 continuously flows the reactor current iL, the current flows from the reactor 6 to the first node 11, the first switching element 1, the third switching element 3, and the second as shown in FIG. It flows toward the node 12. That is, since the reactor 6 continues the reflux operation, the value of the reactor current iL does not change.
  • Period T7 Power regeneration period to the DC power source 7 by the exciting current of the reactor 6
  • the fifth switching element 5 is turned on and the third switching element 3 is turned off.
  • the reactor 6 continuously flows the reactor current iL, so that the current flows from the reactor 6 to the positive electrode of the DC power supply 7 via the first node 11 and the first switching element 1 as shown in FIG. Furthermore, it returns to the reactor 6 from the negative electrode of the DC power source 7 through the fifth switching element 5 and the parasitic diode of the fourth switching element 4. Due to this current path, the exciting power of the reactor 6 is regenerated to the DC power source 7, so that the reactor current iL gradually approaches zero from the positive electrode.
  • Period T8 Power regeneration continuation period to the DC power supply 7 by the exciting current of the reactor 6
  • the fourth switching element 4 is turned on.
  • the reactor 6 continuously flows the reactor current iL, so that the current flows from the reactor 6 to the positive electrode of the DC power supply 7 via the first node 11 and the first switching element 1 as shown in FIG.
  • the feedback is made from the negative electrode of the DC power source 7 to the reactor 6 through the fifth switching element 5 and the fourth switching element 4. Due to this current path, the exciting power of the reactor 6 is regenerated to the DC power source 7, so that the reactor current iL approaches zero from the positive electrode.
  • Period T9 On-fixing continuation period of semiconductor switch 9 In this period T9, the fifth switching element 5 is turned off. Then, as shown in FIG. 19, a current path that returns from the positive electrode of the DC power source 7 to the negative electrode of the DC power source 7 through the first switching element 1 and the input capacitor 10 is formed. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
  • the gate-source voltage VgsL can be held at a negative voltage value during the off-fixed duration T3 of the semiconductor switch 9. Thereafter, during the turn-on period of the semiconductor switch 9 (period T4 to period T9), the charge stored in the input capacitor 10 and the first capacitor 21 is regenerated in the reactor 6, so that the gate drive circuit 100 is compared with the first embodiment. Loss can be reduced, and a small gate driving circuit 100 can be obtained.
  • the gate-source voltage VgsL has a negative voltage value.
  • the accumulated charge Ciss of the input capacitor 10 can be regenerated during the turn-on period of the semiconductor switch 9.
  • the gate-source voltage VgsL cannot be held at a negative voltage value during the fixed off duration T3 of the semiconductor switch 9. That is, the gate-source voltage VgsL finally becomes zero at the end of the OFF fixed duration T3.
  • the gate-source voltage VgsL can be reliably held at a negative voltage value during the off-fixed duration T3.
  • the negative voltage application period is increased from that in the first embodiment, and there is an advantage that the turn-on timing setting of the semiconductor switch of the high-voltage side arm (not shown) connected in series to the semiconductor switch 9 can be facilitated.
  • the predetermined period tc described in the period T4 is set so that the voltage applied to the first capacitor 21 becomes zero. Until this applied voltage reaches zero, a current can flow through the reactor 6, so that the accumulated charge Ciss of the input capacitor 10 connected in parallel to the first capacitor 21 can be efficiently regenerated into the reactor 6. It becomes possible.
  • the semiconductor switch 9 When the semiconductor switch 9 is fixed to OFF, the input capacitor 10 and the first capacitor 21 are connected in parallel when viewed from the gate terminal of the semiconductor switch 9. That is, the input capacity of the semiconductor switch 9 can be increased. Therefore, it goes without saying that the malfunction of the semiconductor switch 9 can be suppressed as described in the first embodiment.
  • the drive signal Q4 of the fourth switching element 4 and the drive signal Q5 of the fifth switching element 5 are set to different signals as shown in FIGS. In this way, the timings at which the fourth and fifth switching elements 4 and 5 are turned on can be shifted from each other, so that a function of reducing overcurrent failure is provided.
  • FIG. 20 shows a modification of the gate drive circuit shown in FIG. 8, and the same reference numerals are given to components corresponding to or corresponding to FIG.
  • the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the semiconductor switch 9.
  • the cathode terminal of the first Zener diode 31 is connected to the gate terminal of the semiconductor switch 9, and the cathode terminal of the second Zener diode 32 is connected to the source terminal of the semiconductor switch 9. Further, the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other.
  • a first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistor is connected between the second switching element 2 and the first node 11. (Roff) 42 is connected.
  • FIG. 20 the operational effect obtained by providing the second capacitor 22, the first and second Zener diodes 31, 32, and the first and second resistors 41, 42 is the same as that of the first embodiment. Since it is similar, detailed description is omitted here. 20 is the same as that of the configuration shown in FIG. 8, and thus detailed description thereof is omitted here.
  • FIG. FIG. 21 is a circuit diagram showing the configuration of the gate drive circuit according to the third embodiment of the present invention, and components corresponding to or corresponding to the configuration shown in FIG.
  • the gate drive circuit 100 having the configuration shown in FIG. 21 is connected to a pair of semiconductor switches 60 connected in series to the semiconductor switch 9 and the connection point thereof with respect to the circuit configuration of FIG. 1 described in the first embodiment.
  • An inductive load 70 is additionally provided.
  • the semiconductor switch serving as the low-voltage side arm is the first semiconductor switch 9 and the semiconductor switch serving as the high-voltage side arm paired therewith is the second semiconductor switch 60.
  • the voltage applied between the drain terminal and the source terminal of the second semiconductor switch 60 (hereinafter referred to as the second drain-source voltage) is VdsH
  • the voltage between the drain terminal and the source terminal of the first semiconductor switch 9 A voltage applied to (hereinafter referred to as a first drain-source voltage) is VdsL.
  • FIG. 22 is a timing chart showing the operation of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 in accordance with the on / off operation of the first and second semiconductor switches 9 and 60 to be driven and controlled. It is.
  • the first semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the first semiconductor switch 9 is turned on from the period T4 to the period T6. Within the period.
  • the six periods T1 to T6 are defined as follows.
  • Period T1 Excitation period of the reactor 6
  • Period T2 Generation period of self-turn-on of the first semiconductor switch 9
  • Period T3 Fixed off duration of the first semiconductor switch 9
  • period T4 Reactor 6 excitation period
  • period T5 Positive voltage application period to the gate of the first semiconductor switch 9
  • period T6 On-fixed duration of the first semiconductor switch 9
  • FIG. 23 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG. 24 to 26 show current paths in the operation periods T1 to T3.
  • FIGS. 23 will be described with reference to FIGS.
  • Period T1 Excitation period of the reactor 6 In this period T1, the first switching element 1 is turned off and the fourth switching element 4 is determined in advance from the state where the first semiconductor switch 9 is fixed on. It turns on only for the time. The predetermined time is set such that the first semiconductor switch 9 is turned on by turning on the second semiconductor switch 60.
  • the current flows from the input capacitor 10 to the first node 11, flows into the fourth switching element 4 via the reactor 6 and the second node 12, and returns to the input capacitor 10.
  • Form a pathway Due to this current path, a resonant operation occurs between the reactor 6 and the input capacitor 10, the gate-source voltage VgsL decreases from the power supply voltage Vdc, and the current ig flowing through the input capacitor 10 increases from zero to the negative electrode.
  • Period T2 Self-turn-on period of the first semiconductor switch 9
  • the fourth switching element 4 is turned off, and the second switching element 2 is turned off for a predetermined time.
  • the gate-source voltage VgsL is set to zero or less.
  • the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 becomes conductive.
  • the current flows into the DC power source 7 and returns to the input capacitor 10.
  • the gate-source voltage VgsL increases to the negative electrode when current flows from the negative electrode of the DC power supply 7 to the input capacitor 10.
  • the semiconductor switch 9 is set to self-turn on during this period T1
  • the value of the gate-source voltage VgsL is the same between the gate and source described in the first and second embodiments. It is close to zero compared to the value of the voltage VgsL.
  • the first semiconductor switch 9 After the first semiconductor switch 9 is switched from on to off and the paired second semiconductor switch 60 is switched from off to on, the first semiconductor switch 9 is self-turned on. This is because the gate-source voltage VgsL is increased by increasing the drain-source voltage VdsL. With this self-turn-on, a current idL flows from the drain terminal to the source terminal of the first semiconductor switch 9, so that the recovery surge voltage Vrs of the semiconductor switch 9 is indicated by the hatched portion with respect to the drain-source voltage VdsL in FIG. Is reduced.
  • Period T3 OFF fixed continuation period of the first semiconductor switch 9
  • the second switching element 2 is turned on.
  • the diode 8 becomes conductive.
  • the current flows from the input capacitor 10 to the first node 11 and returns to the input capacitor 10 via the second switching element 2 and the diode 8.
  • the gate-source voltage VgsL of the first semiconductor switch 9 is clamped to zero by the diode 8 and continues to be turned off.
  • Period T4 Excitation period of the reactor 6
  • the third switching element 3 is turned on.
  • the current flows from the positive electrode of the DC power supply 7 to the second node 12 via the third switching element 3.
  • the second node 12 flows into the first node 11 through the reactor 6.
  • the current flows from the first node 11 to the cathode of the diode 8 via the second switching element 2 and returns to the negative electrode of the DC power supply 7.
  • the reactor 6 is excited by this current path.
  • Period T5 Positive voltage application period to the gate of the first semiconductor switch 9 In this period T5, the second switching element 2 is turned off. In this case, since the current continuously flows through the reactor 6, the input capacitor 10 is charged. As a result, the gate-source voltage VgsL increases to the positive electrode.
  • Period T6 On-fixing continuation period of the first semiconductor switch 9 In this period T6, the first switching element 1 is turned on. Then, a path is formed in which the current returns from the positive electrode of the DC power supply 7 to the negative electrode of the DC power supply 7 via the first switching element 1 and the input capacitor 10. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
  • the turn-on time of the paired second semiconductor switch 60 is generally delayed, but the switching loss of the second semiconductor switch 60 increases.
  • the second semiconductor switch 60 is turned on by self-turning on the first semiconductor switch 9 when the second semiconductor switch 60 is turned on.
  • the recovery surge voltage Vrs can be reduced without increasing the switching loss. Therefore, the effect of simultaneously reducing the loss of the paired second semiconductor switch 60 while suppressing the occurrence of a failure due to the overvoltage of the first semiconductor switch 9 can be obtained.
  • FIG. 8 described in the second embodiment may be used. Needless to say.
  • FIG. 27 shows a gate drive circuit 100 showing a modified example of the configuration shown in FIG. 21.
  • Components corresponding to or corresponding to those in FIG. 21 are denoted by the same reference numerals.
  • FIG. 27 is different from the configuration of FIG. 21 in that the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the first semiconductor switch 9.
  • the cathode terminal of the first Zener diode 31 is connected to the gate terminal of the first semiconductor switch 9.
  • the cathode terminal of the second Zener diode 32 is connected to the source terminal of the first semiconductor switch 9.
  • the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other.
  • a first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistance is connected between the second switching element 2 and the first node 11.
  • a resistor (Roff) 42 is connected.
  • Embodiment 4 the turn-off loss of the semiconductor switch 9 is reduced compared to the first embodiment by adding a period during which the first switching element 1 is turned on to the period T1 in the first embodiment.
  • the contents will be specifically described below.
  • FIG. 28 is a timing chart showing the operations of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 accompanying the turn-off operation of the semiconductor switch 9 to be driven.
  • the turn-off of the semiconductor switch 9 to be driven and controlled will be described in the period from the period T1 to the period T4. Since the operation within the period when the semiconductor switch 9 is turned on is the same as that of the first embodiment, the detailed description is omitted.
  • the four periods from the period T1 to the period T4 are defined as follows.
  • Period T1 Initial excitation period of the reactor 6
  • Period T2 Excitation period of the reactor 6
  • Period T3 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage to the gate of the semiconductor switch 9
  • Application period (4) period T4 OFF fixed continuation period of the semiconductor switch 9
  • FIG. 29 is an operation waveform diagram showing changes in the current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG.
  • broken lines in FIG. 29 are current and voltage waveform diagrams of the respective parts based on the timing chart of the first embodiment (FIG. 2).
  • FIG. 30 shows a current path in an operation period T1 different from that in the first embodiment. Since the current path from the period T2 to the period T4 is the same as that in the first embodiment (FIGS. 4 to 6), detailed description is omitted here.
  • Period T1 Initial Excitation Period of Reactor 6
  • T1 the state where the first switching element 1 is on is continued.
  • the time for which the first switching element 1 is kept on is set to be shorter than the predetermined time ta for the fourth switching element 4.
  • the current flows from the DC power source 7 to the first node 11, flows into the fourth switching element 4 via the reactor 6 and the second node 12, and returns to the DC power source 7. To do.
  • the reactor current iL increases from zero to the negative electrode.
  • the reactor 6 is initially excited by the power supply voltage Vdc of the DC power supply 7.
  • Period T2 Excitation period of the reactor 6
  • the first switching element 1 is turned off, and the fourth switching element 4 is kept on for a predetermined time ta. Then, since reactor current iL continuously flows through reactor 6, the current flows as shown in FIG. At this time, since the reactor 6 is initially excited, the current value becomes larger than the reactor current iL (broken line) of the first embodiment as shown in FIG.
  • Period T3 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • the fourth switching element 4 is turned off and only for a predetermined time tb.
  • the second switching element 2 is turned off. Then, current flows as shown in FIG. At this time, since the reactor 6 is initially excited, the current value becomes larger than the reactor current iL (broken line) of the first embodiment as shown in FIG.
  • Period T4 Fixed off duration of semiconductor switch 9
  • the second switching element 2 is turned on.
  • current flows as shown in FIG. As a result, the gate-source voltage VgsL increases toward the positive electrode as shown in FIG. 29.
  • the gate-source voltage VgsL of the semiconductor switch 9 is zero by the diode 8. The semiconductor switch 9 continues to be turned off.
  • the current value of the reactor current iL is set to the first embodiment by providing a period during which the first switching element 1 and the fourth switching element 4 are simultaneously turned on. Can be larger. Therefore, the turn-off loss can be reduced as compared with the first embodiment, and the cooler of the semiconductor switch 9 can be downsized.
  • FIG. 8 described in the second embodiment can also be used. Needless to say, it is good.
  • the example in which the gate drive circuit of the first to fourth embodiments is applied to the first semiconductor switch 9 constituting the low voltage side arm has been described. It goes without saying that the same effect can be obtained even if the gate driving circuits of the first to fourth embodiments are applied to the second semiconductor switch 60 to be configured.
  • the present invention is not limited to the configurations of the first to fourth embodiments described above, and some of the configurations of the first to fourth embodiments may be changed without departing from the spirit of the present invention. Or the configuration thereof can be omitted, and the configurations of Embodiments 1 to 4 can be combined as appropriate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

L'invention concerne un circuit série comprenant des premier et deuxième éléments de commutation (1, 2), et un circuit en série comprenant des troisième et quatrième éléments de commutation (3, 4) qui sont branchés en parallèle à une alimentation en courant continu (7). Une bobine de réactance (6) est reliée entre un premier nœud (11), c'est-à-dire un point de connexion entre les premier et deuxième éléments de commutation (1, 2), et un deuxième nœud (12), c'est-à-dire un point de connexion entre les troisième et quatrième éléments de commutation (3, 4). Le premier nœud (11) est relié à une borne de gâchette d'un commutateur à semi-conducteur (9), une diode (8) est reliée entre le deuxième élément de commutation (2) et la borne d'électrode négative de l'alimentation en courant continu (7), et un circuit de commande de commutation (50) commande les opérations marche/arrêt des premier à quatrième éléments de commutation (1-4).
PCT/JP2017/045072 2017-05-24 2017-12-15 Circuit d'attaque de gâchette WO2018216251A1 (fr)

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JP2017102513 2017-05-24

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077462A (ja) * 2009-10-02 2011-04-14 Hitachi Ltd 半導体駆動回路、及びそれを用いた半導体装置
JP2015119625A (ja) * 2013-11-15 2015-06-25 パナソニックＩｐマネジメント株式会社 駆動装置、電力変換装置
JP2016040967A (ja) * 2014-08-12 2016-03-24 ニチコン株式会社 ゲート駆動回路
JP2016123199A (ja) * 2014-12-25 2016-07-07 パナソニックＩｐマネジメント株式会社 駆動装置、電力変換装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077462A (ja) * 2009-10-02 2011-04-14 Hitachi Ltd 半導体駆動回路、及びそれを用いた半導体装置
JP2015119625A (ja) * 2013-11-15 2015-06-25 パナソニックＩｐマネジメント株式会社 駆動装置、電力変換装置
JP2016040967A (ja) * 2014-08-12 2016-03-24 ニチコン株式会社 ゲート駆動回路
JP2016123199A (ja) * 2014-12-25 2016-07-07 パナソニックＩｐマネジメント株式会社 駆動装置、電力変換装置

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