WO2018216251A1 - Gate drive circuit - Google Patents

Gate drive circuit Download PDF

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Publication number
WO2018216251A1
WO2018216251A1 PCT/JP2017/045072 JP2017045072W WO2018216251A1 WO 2018216251 A1 WO2018216251 A1 WO 2018216251A1 JP 2017045072 W JP2017045072 W JP 2017045072W WO 2018216251 A1 WO2018216251 A1 WO 2018216251A1
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WIPO (PCT)
Prior art keywords
switching element
semiconductor switch
period
gate
terminal
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Application number
PCT/JP2017/045072
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French (fr)
Japanese (ja)
Inventor
陽平 丹
航平 恩田
亮太 近藤
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2018520204A priority Critical patent/JP6370524B1/en
Publication of WO2018216251A1 publication Critical patent/WO2018216251A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to a gate drive circuit for driving on / off a semiconductor switch to be controlled.
  • the first switching element connected in series between the positive terminal of the DC power supply and the first node, and the first connected in series between the first node and the negative electrode of the DC power supply.
  • the first node is connected to the gate terminal of the semiconductor switch to be driven and the negative electrode of the DC power supply is connected to the source terminal of the semiconductor switch, so that the accumulated charge of the input capacitance of the semiconductor switch So as to power regenerated to the DC power supply side, to reduce the loss of the gate driving circuit, there is a method to reduce the size of the circuit (for example, see Patent Document 1 below).
  • Patent Document 1 when the power regeneration type gate drive technology of a single power source disclosed in Patent Document 1 is used for an inverter composed of a half-bridge or full-bridge circuit composed of semiconductor switches of a high-voltage side arm and a low-voltage side arm, When the semiconductor switch of the high-voltage side arm is turned on, the voltage between the drain terminal and the source terminal of the semiconductor switch of the low-voltage side arm rises, whereby the voltage between the gate terminal and the source terminal of the semiconductor switch of the low-voltage side arm This causes a malfunction that causes the malfunction of the semiconductor switch of the low-voltage side arm that is lifted and turned off.
  • the present invention has been made to solve the above-described problems, and in a conventional single power supply power regeneration type gate drive circuit, a negative voltage is applied between the gate terminal and the source terminal of the corresponding semiconductor switch.
  • the purpose is to prevent malfunction of the semiconductor switch.
  • the gate drive circuit is: A DC circuit is connected in parallel with a series circuit composed of a first switching element and a second switching element, and a series circuit composed of a third switching element and a fourth switching element, A first node that is a connection point between the first switching element and the second switching element, and a second node that is a connection point between the third switching element and the fourth switching element. Connect a reactor between the node and Connecting the first node to a gate terminal of a semiconductor switch to be driven and controlled; A diode is connected between the second switching element and the negative terminal of the DC power supply; A switching control circuit for controlling the on / off operation of each of the first, second, third, and fourth switching elements is provided.
  • the gate drive circuit of the present invention when the semiconductor switch to be driven is turned off, the accumulated charge of the input capacitance of the semiconductor switch is regenerated to the power source side by the reactor, and the gate of the semiconductor switch It becomes possible to apply a negative voltage between the sources. Therefore, even in a conventional single power source power regeneration type gate drive circuit, it is possible to reliably prevent malfunction of the semiconductor switch.
  • FIG. 1 is a circuit diagram showing a configuration of a gate drive circuit according to a first embodiment of the present invention.
  • FIG. 6 is a timing chart showing the operation of the first to fourth switching elements of the gate drive circuit according to the first embodiment of the present invention.
  • FIG. 3 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements shown in FIG.
  • FIG. 3 is a current path diagram in one operation period shown in FIG. 2.
  • FIG. 3 is a current path diagram in one operation period shown in FIG. 2.
  • FIG. 3 is a current path diagram in one operation period shown in FIG. 2.
  • It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 1 of this invention.
  • FIG. 10 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fifth switching elements shown in FIG. 9;
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • FIG. 10 is a current path diagram in one operation period shown in FIG. 9.
  • It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 2 of this invention.
  • It is a circuit diagram which shows the structure of the gate drive circuit by Embodiment 3 of this invention.
  • 14 is a timing chart showing operations of first to fourth switching elements of a gate drive circuit according to Embodiment 3 of the present invention.
  • FIG. 23 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fourth switching elements shown in FIG. 22;
  • FIG. 23 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fourth switching elements shown in FIG. 22;
  • FIG. 23 is an operation
  • FIG. 23 is a current path diagram in one operation period shown in FIG. 22.
  • FIG. 23 is a current path diagram in one operation period shown in FIG. 22.
  • FIG. 23 is a current path diagram in one operation period shown in FIG. 22.
  • It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 3 of this invention.
  • 14 is a timing chart showing first to fourth switching operations of a gate drive circuit according to a fourth embodiment of the present invention.
  • FIG. 29 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of each of the first to fourth switching elements shown in FIG.
  • FIG. 29 is a current path diagram in one operation period shown in FIG. 28.
  • FIG. 1 is a circuit diagram showing a configuration of a gate drive circuit according to the first embodiment.
  • the gate drive circuit 100 according to the first embodiment uses a voltage-driven semiconductor switch 9 having an input capacitor 10 as a drive control target and drives the semiconductor switch 9 on and off with a single DC power supply 7. .
  • a series circuit including a first switching element 1 and a second switching element 2, and a third switching element 3 and a fourth switching element with respect to the DC power supply 7. 4 series circuits are connected together in parallel.
  • the reactor 6 is connected between the two nodes 12 and the first node 11 is connected to the gate terminal of the semiconductor switch 9 to be driven and controlled.
  • a diode 8 is connected between the second switching element 2 and the negative terminal of the DC power supply 7.
  • a switching control circuit 50 that controls the on / off operations of the first, second, third, and fourth switching elements 1, 2, 3, and 4 is provided.
  • the DC voltage of the DC power supply 7 (hereinafter referred to as power supply voltage) is Vdc
  • the current flowing through the reactor 6 (hereinafter referred to as reactor current) is iL
  • the current flowing through the input capacitor 10 of the semiconductor switch 9 is ig
  • the semiconductor A voltage applied between the gate terminal and the source terminal via the input capacitor 10 of the switch 9 (hereinafter referred to as a gate-source voltage) is VgsL
  • a voltage applied between the drain terminal and the source terminal of the semiconductor switch 9 (hereinafter referred to as “voltage”).
  • VsL) the current flowing through the drain terminal of the semiconductor switch 9 is idL.
  • the driving signal for the first switching element 1 is Q1
  • the driving signal for the second switching element 2 is Q2
  • the driving signal for the third switching element 3 is Q3
  • the driving signal for the fourth switching element 4 is Q4.
  • the inductance value of the reactor 6 is L
  • the capacitance value of the input capacitor 10 is Ciss. If the resonance period determined by the reactor 6 and the input capacitor 10 is T, the resonance period T can be expressed by the following (formula 1).
  • the first to fourth switching elements 1 to 4 are MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) each including a parasitic diode as an example here.
  • MOSFETs Metal-Oxide-Semiconductor Field Effect Transistors
  • a configuration in which a diode and an IGBT (Insulated Gate Bipolar Transistor) are connected in parallel may be used.
  • a thyristor or a GTO (Gate Turn-Off thyristor) in which diodes are connected in parallel may be used.
  • the first to fourth switching elements 1 to 4 are regarded as MOSFETs, and the forward voltage of the parasitic diode and the diode 8 is regarded as zero.
  • FIG. 2 is a timing chart showing the operations of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 in accordance with the on / off operation of the semiconductor switch 9 to be driven.
  • the semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the semiconductor switch 9 is turned on within the period from the period T4 to the period T6.
  • the six periods T1 to T6 are defined as follows.
  • Period T1 Excitation period of the reactor 6
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • Period T3 Semiconductor switch 9 off Fixed duration (4)
  • Period T4 Reactor 6 excitation period (5)
  • Period T5 Positive voltage application period to the gate of the semiconductor switch 9 (6)
  • Period T6 Semiconductor switch 9 on-fixed duration
  • FIG. 3 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG. 4 to 6 show current paths in the above-described periods T1 to T3.
  • FIGS. 3 the principle of operation will be described with reference to FIGS.
  • Period T1 Excitation period of the reactor 6 In this period T1, the first switching element 1 is on, the second, third, and fourth switching elements 2, 3, and 4 are all off, and the semiconductor switch From the state in which 9 is fixed to ON, the first switching element 1 is turned off and the fourth switching element 4 is turned on for a predetermined time ta. Then, as shown in FIG. 4, the current flows from the input capacitor 10 to the node 11, flows into the fourth switching element 4 through the reactor 6 and the node 12, and returns to the input capacitor 10.
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • the fourth switching element 4 is turned off, and the first time period tb is reached. 2 switching element 2 is turned off.
  • the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 is conducted, flows into the positive electrode of the DC power supply 7, and returns to the input capacitor 10.
  • a part of the excitation energy of the reactor 6 is regenerated to the DC power source 7 and the remainder of the excitation energy flows from the negative electrode of the DC power source 7 to the input capacitor 10, so that the gate-source voltage VgsL is directed toward the negative electrode.
  • the current iL increases toward the positive electrode. Therefore, a negative voltage is applied to the gate of the semiconductor switch 9.
  • Period T3 Fixed off duration of semiconductor switch 9 In this period T3, the second switching element 2 is turned on. At this time, as shown in FIG. 3, since the gate-source voltage VgsL is a negative voltage and the reactor current iL is zero, the parasitic diode of the fourth switching element 4 becomes conductive. As a result, as shown in FIG. 6, current flows from the input capacitor 10 to the node 12 via the parasitic diode of the fourth switching element 4. Thereafter, the current flows from the node 12 through the reactor 6 to the node 11 and returns to the input capacitor 10.
  • the gate-source voltage VgsL is increased toward the positive electrode.
  • the diode 8 causes the semiconductor switch 9.
  • the gate-source voltage VgsL is clamped to zero and the semiconductor switch 9 continues to be turned off. Needless to say, the change in the gate-source voltage VgsL from the negative electrode to the positive electrode is suppressed by the reactor 6.
  • Period T4 Excitation period of the reactor 6
  • the third switching element 3 is turned on.
  • the current flows from the positive electrode of the DC power supply 7 to the node 12 via the third switching element 3.
  • the current flows from the node 12 to the cathode of the diode 8 through the reactor 6 and the second switching element 2, and returns to the negative electrode of the DC power supply 7. Since the reactor 6 is excited by this current path, the reactor current iL increases to the positive electrode.
  • Period T5 Positive voltage application period to the gate of the semiconductor switch 9 In this period T5, the second switching element 2 is turned off. In this case, the reactor current iL continuously flows through the reactor 6 and charges the input capacitor 10. As a result, the gate-source voltage VgsL increases toward the positive electrode.
  • Period T6 On-fixing continuation period of the semiconductor switch 9 In this period T6, the first switching element 1 is turned on. Then, the current forms a path for returning from the positive electrode of the DC power source 7 to the negative electrode of the DC power source 7 via the first switching element 1 and the input capacitor 10. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
  • the gate driving circuit 100 when the semiconductor switch 9 is turned off, a part of the accumulated charge Ciss of the input capacitor 10 is regenerated to the DC power source 7 side by the reactor 6, and the input capacitor 10 The remainder of the accumulated charge Ciss can be applied as a negative voltage between the gate and source of the semiconductor switch 9. Therefore, it is possible to reliably prevent the malfunction of the semiconductor switch 9 without providing a negative power supply as in the prior art, and to obtain the gate drive circuit 100 that is simple and can be miniaturized.
  • the gate-source voltage VgsL and the reactor current iL at this time ta can be expressed by a trigonometric function as shown in the following (Expression 2) and (Expression 3).
  • the predetermined time ta is set to be longer than a quarter of the resonance period T determined by the reactor 6 and the input capacity 10 and shorter than a half of the resonance period T determined by the reactor 6 and the input capacity 10.
  • the gate-source voltage VgsL and the reactor current iL have negative values, and a period during which a negative voltage is applied as the voltage VgsL between the gate terminal and the source terminal of the semiconductor switch 9 can be provided in a part of the period T1. .
  • the negative voltage application period is increased, there is an advantage that the turn-on timing setting of a high voltage side arm (not shown) connected in series to the semiconductor switch 9 can be facilitated.
  • reactor current iL is a negative value, reactor 6 is excited and it goes without saying that the excitation energy is regenerated to DC power supply 7 in period T2.
  • a predetermined time tb for turning off the second switching element 2 described in the period T2 will be described.
  • This time tb is assumed to be when the gate-source voltage VgsL is less than or equal to zero. In other words, when the gate-source voltage VgsL is a negative value, the second switching element 2 is turned on.
  • an increase in the gate-source voltage VgsL to the positive electrode due to the current through the parasitic diode of the fourth switching element 4 can be prevented, and malfunction of the semiconductor switch 9 can be suppressed.
  • FIG. 7 shows a modification of the gate drive circuit shown in FIG. 1, and the same reference numerals are given to components corresponding to or corresponding to FIG.
  • FIG. 7 differs from the configuration of FIG. 1 in that the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the semiconductor switch 9.
  • the cathode terminal of the first Zener diode 31 is connected to the gate terminal of the semiconductor switch 9.
  • the cathode terminal of the second Zener diode 32 is connected to the source terminal of the semiconductor switch 9. Further, the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other.
  • a first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistor 42 is connected between the second switching element 2 and the first node 11. (Roff) is connected.
  • the input capacitance of the semiconductor switch 9 can be increased. Therefore, for example, when a high-voltage side arm (not shown) connected in series to the semiconductor switch 9 is turned on, the voltage VdsL between the drain terminal and the source terminal of the semiconductor switch 9 serving as the low-voltage side arm increases. Lifting of the gate-source voltage VgsL to the positive electrode side can be suppressed. Therefore, malfunction of the semiconductor switch 9 can be suppressed.
  • the second Zener diode 32 provides an effect of preventing a negative overvoltage from being applied between the gate terminal and the source terminal of the semiconductor switch 9 in the period T1 to the period T3.
  • the first Zener diode 31 provides an effect of preventing a positive overvoltage from being applied between the gate terminal and the source terminal of the semiconductor switch 9 when, for example, the semiconductor switch 9 is fixed on after the period T4.
  • the first resistor 41 provides an effect of preventing an inrush current based on a potential difference between the gate-source voltage VgsL and the power supply voltage Vdc when the semiconductor switch 9 is fixed on from the period T3, for example.
  • the second resistor 42 provides an effect of preventing an inrush current based on a potential difference between the gate-source voltage VgsL and the forward voltage of the diode 8 when clamping the gate-source voltage VgsL in the period T3.
  • the first resistor 41 may not be provided separately and the internal resistance of the first switching element 1 may be used. Similarly, the internal resistance of the second switching element 2 may be used without providing the second resistor 42 separately.
  • the other configuration and operational effects of the gate drive circuit 100 shown in FIG. 7 are the same as those of the configuration shown in FIG.
  • Embodiment 2 when the semiconductor switch 9 is turned off, a part of the stored charge Ciss of the input capacitor 10 is regenerated to the DC power supply 7 side by the reactor 6 and the remaining stored charge Ciss of the input capacitor 10 is transferred to the semiconductor switch. 9 is applied as a negative voltage between the gate terminal and the source terminal.
  • the gate-source voltage VgsL when the gate-source voltage VgsL is a negative value, the current flows into the input capacitor 10 via the parasitic diode of the fourth switching element 4, and the gate-source voltage VgsL is charged toward the positive electrode. Due to this charging, loss of the gate driving circuit 100 occurs.
  • FIG. 8 is a circuit diagram showing a configuration of the gate drive circuit according to the second embodiment of the present invention, and components corresponding to or corresponding to the configuration shown in FIG. 1 are denoted by the same reference numerals.
  • the gate drive circuit 100 according to the second embodiment is different from the circuit configuration according to the first embodiment (FIG. 1) in that the fifth switching element 5 is provided between the fourth switching element 4 and the negative terminal of the DC power source 7. They are connected in series. A first capacitor 21 is connected in parallel to the anode terminal and the cathode terminal of the diode 8. Further, the switching control circuit 50 is additionally provided with a drive signal Q5 for driving the fifth switching element 5.
  • FIG. 9 is a timing chart showing the operation of the first to fifth switching elements 1 to 5 of the gate drive circuit 100 in accordance with the on / off operation of the semiconductor switch 9 to be driven and controlled.
  • the semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the semiconductor switch 9 is turned on within the period from the period T4 to the period T9.
  • the nine periods T1 to T9 are defined as follows.
  • Period T1 Excitation period of the reactor 6
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitance 10 and negative voltage application period to the gate of the semiconductor switch 9
  • Period T3 Semiconductor switch 9 OFF fixed continuation period (4) period
  • T4 power regeneration period of charge accumulated by the input capacitor 10 and the first capacitor 21 and excitation period (5)
  • period of the reactor 6 T5: charge injection period (6) period to the input capacitor 10
  • Period T6 Period of recirculation to reactor 6
  • Period T7 Power regeneration period to DC power supply 7 by exciting current of reactor 6
  • Period T8 Power regeneration continuation period to DC power supply 7 by exciting current of reactor 6 ( 9)
  • Period T9 On-fixed duration of semiconductor switch 9
  • FIG. 10 is an operation waveform diagram showing changes in the current and voltage of each part accompanying the operation of each of the first to fifth switching elements 1 to 5 based on FIG.
  • FIGS. 11 to 19 show current paths in the operation periods T1 to T9.
  • the operation principle will be described with reference to FIGS.
  • Period T1 Excitation period of the reactor 6
  • the first switching element 1 is turned on, and the second, third, fourth, and fifth switching elements 2, 3, 4, and 5 are all turned off.
  • the first switching element 1 is turned off, and the fourth and fifth switching elements 4 and 5 are turned on for a predetermined time ta.
  • the current flows from the input capacitor 10 to the node 11, flows into the fourth and fifth switching elements 4 and 5 through the reactor 6 and the node 12, and returns to the input capacitor 10.
  • Period T2 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • the fourth switching element 4 is turned off, and the period of time is predetermined. 2 switching element 2 is turned off.
  • the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 becomes conductive and flows into the positive electrode of the DC power supply 7.
  • One of the currents is fed back to the reactor 6 through the first capacitor 21 and the parasitic diode of the second switching element 2, and the other of the currents is fed back to the reactor 6 through the input capacitor 10.
  • the gate-source voltage VgsL increases to the negative electrode.
  • the voltage applied to the first capacitor 21 is not shown, it goes without saying that the voltage increases to the negative electrode similarly to the gate-source voltage VgsL. Thereafter, the value of the reactor current iL approaches zero, and the gate-source voltage VgsL becomes a certain negative voltage value.
  • Period T3 Fixed off duration of semiconductor switch 9 In this period T3, the second switching element 2 is turned on. At this time, the gate-source voltage VgsL and the applied voltage of the first capacitor 21 are both negative voltages. However, since the capacitance of the first capacitor 21 is generally larger than the input capacitance 10 of the semiconductor switch 9, A voltage difference is generated between the gate-source voltage VgsL and the voltage applied to the first capacitor 21.
  • the current flows from the first capacitor 21 to the input capacitor 10 via the second switching element 2 as shown in FIG. 13, and charges the input capacitor 10.
  • the first capacitor 21 may be charged by the input capacitor 10.
  • the semiconductor switch 9 is fixed to the off state.
  • Period T4 Power regeneration period of stored charges by the input capacitor 10 and the first capacitor 21 and the excitation period of the reactor 6
  • the second switching element 2 and the semiconductor switch 9 are turned on.
  • the third switching element 3 is turned on for a predetermined time tc.
  • one of the currents is fed back from the first node 11 to the negative electrode of the DC power supply 7 via the second switching element 2 and the first capacitor 21.
  • the other current is fed back from the first node 11 to the negative electrode of the DC power supply 7 through the input capacitor 10.
  • both the input capacitor 10 and the first capacitor 21 are discharged, and the gate-source voltage VgsL approaches zero from the negative voltage value.
  • the electric charges stored in the input capacitor 10 and the first capacitor 21 are regenerated in the reactor 6.
  • Period T5 Charge injection period to the input capacitor 10 In this period T5, the second switching element 2 is turned off. In that case, as shown in FIG. 15, since the reactor 6 continuously flows the reactor current iL, the current flows from the reactor 6 toward the first node 11, the input capacitor 10, and the negative electrode of the DC power source 7, Charge the capacity 10.
  • the input capacitor 10 is charged by this current path, and the gate-source voltage VgsL approaches the power supply voltage Vdc from zero. Thereafter, when the gate-source voltage VgsL reaches the power supply voltage Vdc, the parasitic diode of the first switching element 1 becomes conductive. Even in that case, since the reactor 6 continuously flows the reactor current iL, the current path is not shown, but the first node 11, the parasitic diode of the first switching element 1, the third switching element 3 from the reactor 6. , And flows toward the second node 12. That is, the reactor 6 is performing a reflux operation.
  • Period T6 Return Period to Reactor 6 In this period T6, the first switching element 1 is turned on. Also in this case, since the reactor 6 continuously flows the reactor current iL, the current flows from the reactor 6 to the first node 11, the first switching element 1, the third switching element 3, and the second as shown in FIG. It flows toward the node 12. That is, since the reactor 6 continues the reflux operation, the value of the reactor current iL does not change.
  • Period T7 Power regeneration period to the DC power source 7 by the exciting current of the reactor 6
  • the fifth switching element 5 is turned on and the third switching element 3 is turned off.
  • the reactor 6 continuously flows the reactor current iL, so that the current flows from the reactor 6 to the positive electrode of the DC power supply 7 via the first node 11 and the first switching element 1 as shown in FIG. Furthermore, it returns to the reactor 6 from the negative electrode of the DC power source 7 through the fifth switching element 5 and the parasitic diode of the fourth switching element 4. Due to this current path, the exciting power of the reactor 6 is regenerated to the DC power source 7, so that the reactor current iL gradually approaches zero from the positive electrode.
  • Period T8 Power regeneration continuation period to the DC power supply 7 by the exciting current of the reactor 6
  • the fourth switching element 4 is turned on.
  • the reactor 6 continuously flows the reactor current iL, so that the current flows from the reactor 6 to the positive electrode of the DC power supply 7 via the first node 11 and the first switching element 1 as shown in FIG.
  • the feedback is made from the negative electrode of the DC power source 7 to the reactor 6 through the fifth switching element 5 and the fourth switching element 4. Due to this current path, the exciting power of the reactor 6 is regenerated to the DC power source 7, so that the reactor current iL approaches zero from the positive electrode.
  • Period T9 On-fixing continuation period of semiconductor switch 9 In this period T9, the fifth switching element 5 is turned off. Then, as shown in FIG. 19, a current path that returns from the positive electrode of the DC power source 7 to the negative electrode of the DC power source 7 through the first switching element 1 and the input capacitor 10 is formed. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
  • the gate-source voltage VgsL can be held at a negative voltage value during the off-fixed duration T3 of the semiconductor switch 9. Thereafter, during the turn-on period of the semiconductor switch 9 (period T4 to period T9), the charge stored in the input capacitor 10 and the first capacitor 21 is regenerated in the reactor 6, so that the gate drive circuit 100 is compared with the first embodiment. Loss can be reduced, and a small gate driving circuit 100 can be obtained.
  • the gate-source voltage VgsL has a negative voltage value.
  • the accumulated charge Ciss of the input capacitor 10 can be regenerated during the turn-on period of the semiconductor switch 9.
  • the gate-source voltage VgsL cannot be held at a negative voltage value during the fixed off duration T3 of the semiconductor switch 9. That is, the gate-source voltage VgsL finally becomes zero at the end of the OFF fixed duration T3.
  • the gate-source voltage VgsL can be reliably held at a negative voltage value during the off-fixed duration T3.
  • the negative voltage application period is increased from that in the first embodiment, and there is an advantage that the turn-on timing setting of the semiconductor switch of the high-voltage side arm (not shown) connected in series to the semiconductor switch 9 can be facilitated.
  • the predetermined period tc described in the period T4 is set so that the voltage applied to the first capacitor 21 becomes zero. Until this applied voltage reaches zero, a current can flow through the reactor 6, so that the accumulated charge Ciss of the input capacitor 10 connected in parallel to the first capacitor 21 can be efficiently regenerated into the reactor 6. It becomes possible.
  • the semiconductor switch 9 When the semiconductor switch 9 is fixed to OFF, the input capacitor 10 and the first capacitor 21 are connected in parallel when viewed from the gate terminal of the semiconductor switch 9. That is, the input capacity of the semiconductor switch 9 can be increased. Therefore, it goes without saying that the malfunction of the semiconductor switch 9 can be suppressed as described in the first embodiment.
  • the drive signal Q4 of the fourth switching element 4 and the drive signal Q5 of the fifth switching element 5 are set to different signals as shown in FIGS. In this way, the timings at which the fourth and fifth switching elements 4 and 5 are turned on can be shifted from each other, so that a function of reducing overcurrent failure is provided.
  • FIG. 20 shows a modification of the gate drive circuit shown in FIG. 8, and the same reference numerals are given to components corresponding to or corresponding to FIG.
  • the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the semiconductor switch 9.
  • the cathode terminal of the first Zener diode 31 is connected to the gate terminal of the semiconductor switch 9, and the cathode terminal of the second Zener diode 32 is connected to the source terminal of the semiconductor switch 9. Further, the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other.
  • a first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistor is connected between the second switching element 2 and the first node 11. (Roff) 42 is connected.
  • FIG. 20 the operational effect obtained by providing the second capacitor 22, the first and second Zener diodes 31, 32, and the first and second resistors 41, 42 is the same as that of the first embodiment. Since it is similar, detailed description is omitted here. 20 is the same as that of the configuration shown in FIG. 8, and thus detailed description thereof is omitted here.
  • FIG. FIG. 21 is a circuit diagram showing the configuration of the gate drive circuit according to the third embodiment of the present invention, and components corresponding to or corresponding to the configuration shown in FIG.
  • the gate drive circuit 100 having the configuration shown in FIG. 21 is connected to a pair of semiconductor switches 60 connected in series to the semiconductor switch 9 and the connection point thereof with respect to the circuit configuration of FIG. 1 described in the first embodiment.
  • An inductive load 70 is additionally provided.
  • the semiconductor switch serving as the low-voltage side arm is the first semiconductor switch 9 and the semiconductor switch serving as the high-voltage side arm paired therewith is the second semiconductor switch 60.
  • the voltage applied between the drain terminal and the source terminal of the second semiconductor switch 60 (hereinafter referred to as the second drain-source voltage) is VdsH
  • the voltage between the drain terminal and the source terminal of the first semiconductor switch 9 A voltage applied to (hereinafter referred to as a first drain-source voltage) is VdsL.
  • FIG. 22 is a timing chart showing the operation of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 in accordance with the on / off operation of the first and second semiconductor switches 9 and 60 to be driven and controlled. It is.
  • the first semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the first semiconductor switch 9 is turned on from the period T4 to the period T6. Within the period.
  • the six periods T1 to T6 are defined as follows.
  • Period T1 Excitation period of the reactor 6
  • Period T2 Generation period of self-turn-on of the first semiconductor switch 9
  • Period T3 Fixed off duration of the first semiconductor switch 9
  • period T4 Reactor 6 excitation period
  • period T5 Positive voltage application period to the gate of the first semiconductor switch 9
  • period T6 On-fixed duration of the first semiconductor switch 9
  • FIG. 23 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG. 24 to 26 show current paths in the operation periods T1 to T3.
  • FIGS. 23 will be described with reference to FIGS.
  • Period T1 Excitation period of the reactor 6 In this period T1, the first switching element 1 is turned off and the fourth switching element 4 is determined in advance from the state where the first semiconductor switch 9 is fixed on. It turns on only for the time. The predetermined time is set such that the first semiconductor switch 9 is turned on by turning on the second semiconductor switch 60.
  • the current flows from the input capacitor 10 to the first node 11, flows into the fourth switching element 4 via the reactor 6 and the second node 12, and returns to the input capacitor 10.
  • Form a pathway Due to this current path, a resonant operation occurs between the reactor 6 and the input capacitor 10, the gate-source voltage VgsL decreases from the power supply voltage Vdc, and the current ig flowing through the input capacitor 10 increases from zero to the negative electrode.
  • Period T2 Self-turn-on period of the first semiconductor switch 9
  • the fourth switching element 4 is turned off, and the second switching element 2 is turned off for a predetermined time.
  • the gate-source voltage VgsL is set to zero or less.
  • the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 becomes conductive.
  • the current flows into the DC power source 7 and returns to the input capacitor 10.
  • the gate-source voltage VgsL increases to the negative electrode when current flows from the negative electrode of the DC power supply 7 to the input capacitor 10.
  • the semiconductor switch 9 is set to self-turn on during this period T1
  • the value of the gate-source voltage VgsL is the same between the gate and source described in the first and second embodiments. It is close to zero compared to the value of the voltage VgsL.
  • the first semiconductor switch 9 After the first semiconductor switch 9 is switched from on to off and the paired second semiconductor switch 60 is switched from off to on, the first semiconductor switch 9 is self-turned on. This is because the gate-source voltage VgsL is increased by increasing the drain-source voltage VdsL. With this self-turn-on, a current idL flows from the drain terminal to the source terminal of the first semiconductor switch 9, so that the recovery surge voltage Vrs of the semiconductor switch 9 is indicated by the hatched portion with respect to the drain-source voltage VdsL in FIG. Is reduced.
  • Period T3 OFF fixed continuation period of the first semiconductor switch 9
  • the second switching element 2 is turned on.
  • the diode 8 becomes conductive.
  • the current flows from the input capacitor 10 to the first node 11 and returns to the input capacitor 10 via the second switching element 2 and the diode 8.
  • the gate-source voltage VgsL of the first semiconductor switch 9 is clamped to zero by the diode 8 and continues to be turned off.
  • Period T4 Excitation period of the reactor 6
  • the third switching element 3 is turned on.
  • the current flows from the positive electrode of the DC power supply 7 to the second node 12 via the third switching element 3.
  • the second node 12 flows into the first node 11 through the reactor 6.
  • the current flows from the first node 11 to the cathode of the diode 8 via the second switching element 2 and returns to the negative electrode of the DC power supply 7.
  • the reactor 6 is excited by this current path.
  • Period T5 Positive voltage application period to the gate of the first semiconductor switch 9 In this period T5, the second switching element 2 is turned off. In this case, since the current continuously flows through the reactor 6, the input capacitor 10 is charged. As a result, the gate-source voltage VgsL increases to the positive electrode.
  • Period T6 On-fixing continuation period of the first semiconductor switch 9 In this period T6, the first switching element 1 is turned on. Then, a path is formed in which the current returns from the positive electrode of the DC power supply 7 to the negative electrode of the DC power supply 7 via the first switching element 1 and the input capacitor 10. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
  • the turn-on time of the paired second semiconductor switch 60 is generally delayed, but the switching loss of the second semiconductor switch 60 increases.
  • the second semiconductor switch 60 is turned on by self-turning on the first semiconductor switch 9 when the second semiconductor switch 60 is turned on.
  • the recovery surge voltage Vrs can be reduced without increasing the switching loss. Therefore, the effect of simultaneously reducing the loss of the paired second semiconductor switch 60 while suppressing the occurrence of a failure due to the overvoltage of the first semiconductor switch 9 can be obtained.
  • FIG. 8 described in the second embodiment may be used. Needless to say.
  • FIG. 27 shows a gate drive circuit 100 showing a modified example of the configuration shown in FIG. 21.
  • Components corresponding to or corresponding to those in FIG. 21 are denoted by the same reference numerals.
  • FIG. 27 is different from the configuration of FIG. 21 in that the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the first semiconductor switch 9.
  • the cathode terminal of the first Zener diode 31 is connected to the gate terminal of the first semiconductor switch 9.
  • the cathode terminal of the second Zener diode 32 is connected to the source terminal of the first semiconductor switch 9.
  • the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other.
  • a first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistance is connected between the second switching element 2 and the first node 11.
  • a resistor (Roff) 42 is connected.
  • Embodiment 4 the turn-off loss of the semiconductor switch 9 is reduced compared to the first embodiment by adding a period during which the first switching element 1 is turned on to the period T1 in the first embodiment.
  • the contents will be specifically described below.
  • FIG. 28 is a timing chart showing the operations of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 accompanying the turn-off operation of the semiconductor switch 9 to be driven.
  • the turn-off of the semiconductor switch 9 to be driven and controlled will be described in the period from the period T1 to the period T4. Since the operation within the period when the semiconductor switch 9 is turned on is the same as that of the first embodiment, the detailed description is omitted.
  • the four periods from the period T1 to the period T4 are defined as follows.
  • Period T1 Initial excitation period of the reactor 6
  • Period T2 Excitation period of the reactor 6
  • Period T3 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage to the gate of the semiconductor switch 9
  • Application period (4) period T4 OFF fixed continuation period of the semiconductor switch 9
  • FIG. 29 is an operation waveform diagram showing changes in the current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG.
  • broken lines in FIG. 29 are current and voltage waveform diagrams of the respective parts based on the timing chart of the first embodiment (FIG. 2).
  • FIG. 30 shows a current path in an operation period T1 different from that in the first embodiment. Since the current path from the period T2 to the period T4 is the same as that in the first embodiment (FIGS. 4 to 6), detailed description is omitted here.
  • Period T1 Initial Excitation Period of Reactor 6
  • T1 the state where the first switching element 1 is on is continued.
  • the time for which the first switching element 1 is kept on is set to be shorter than the predetermined time ta for the fourth switching element 4.
  • the current flows from the DC power source 7 to the first node 11, flows into the fourth switching element 4 via the reactor 6 and the second node 12, and returns to the DC power source 7. To do.
  • the reactor current iL increases from zero to the negative electrode.
  • the reactor 6 is initially excited by the power supply voltage Vdc of the DC power supply 7.
  • Period T2 Excitation period of the reactor 6
  • the first switching element 1 is turned off, and the fourth switching element 4 is kept on for a predetermined time ta. Then, since reactor current iL continuously flows through reactor 6, the current flows as shown in FIG. At this time, since the reactor 6 is initially excited, the current value becomes larger than the reactor current iL (broken line) of the first embodiment as shown in FIG.
  • Period T3 Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9
  • the fourth switching element 4 is turned off and only for a predetermined time tb.
  • the second switching element 2 is turned off. Then, current flows as shown in FIG. At this time, since the reactor 6 is initially excited, the current value becomes larger than the reactor current iL (broken line) of the first embodiment as shown in FIG.
  • Period T4 Fixed off duration of semiconductor switch 9
  • the second switching element 2 is turned on.
  • current flows as shown in FIG. As a result, the gate-source voltage VgsL increases toward the positive electrode as shown in FIG. 29.
  • the gate-source voltage VgsL of the semiconductor switch 9 is zero by the diode 8. The semiconductor switch 9 continues to be turned off.
  • the current value of the reactor current iL is set to the first embodiment by providing a period during which the first switching element 1 and the fourth switching element 4 are simultaneously turned on. Can be larger. Therefore, the turn-off loss can be reduced as compared with the first embodiment, and the cooler of the semiconductor switch 9 can be downsized.
  • FIG. 8 described in the second embodiment can also be used. Needless to say, it is good.
  • the example in which the gate drive circuit of the first to fourth embodiments is applied to the first semiconductor switch 9 constituting the low voltage side arm has been described. It goes without saying that the same effect can be obtained even if the gate driving circuits of the first to fourth embodiments are applied to the second semiconductor switch 60 to be configured.
  • the present invention is not limited to the configurations of the first to fourth embodiments described above, and some of the configurations of the first to fourth embodiments may be changed without departing from the spirit of the present invention. Or the configuration thereof can be omitted, and the configurations of Embodiments 1 to 4 can be combined as appropriate.

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Abstract

A series circuit comprising first and second switching elements (1, 2), and a series circuit comprising third and fourth switching elements (3, 4) are connected in parallel to a direct current power supply (7), a reactor (6) is connected between a first node (11), i.e., a connecting point between the first and second switching elements (1, 2), and a second node (12), i.e., a connecting point between the third and fourth switching elements (3, 4), the first node (11) is connected to a gate terminal of a semiconductor switch (9), a diode (8) is connected between the second switching element (2) and the negative electrode terminal of the direct current power supply (7), and a switching control circuit (50) that controls on/off operations of the first to fourth switching elements (1-4) is provided.

Description

ゲート駆動回路Gate drive circuit
　この発明は、制御対象となる半導体スイッチをオン・オフ駆動するゲート駆動回路に関するものである。 The present invention relates to a gate drive circuit for driving on / off a semiconductor switch to be controlled.
　従来のゲート駆動回路では、直流電源の正極端子と第１のノードの間に、直列接続された第１のスイッチング素子と、第１のノードと直流電源の負極の間に、直列接続された第２のスイッチング素子と、直流電源の正極端子と第２のノードの間に、直列接続された第３のスイッチング素子と、第２のノードと直流電源の負極端子の間に、直列接続された第４のスイッチング素子と、第１のノードと第２のノードの間に接続されたリアクトルと、第１、第２、第３、第４のスイッチング素子のそれぞれオン・オフ動作を制御するスイッチング制御回路を備え、第１のノードを、駆動制御対象となる半導体スイッチのゲート端子に接続し、直流電源の負極を半導体スイッチのソース端子に接続することで、半導体スイッチの入力容量の蓄積電荷を直流電源側に電力回生させるようにして、ゲート駆動回路の損失を低減し、回路を小型化する方法がある（例えば下記の特許文献１参照）。 In the conventional gate drive circuit, the first switching element connected in series between the positive terminal of the DC power supply and the first node, and the first connected in series between the first node and the negative electrode of the DC power supply. The second switching element, the third switching element connected in series between the positive electrode terminal of the DC power supply and the second node, and the second switching element connected in series between the second node and the negative electrode terminal of the DC power supply. 4 switching elements, a reactor connected between the first node and the second node, and a switching control circuit for controlling on / off operations of the first, second, third, and fourth switching elements, respectively. The first node is connected to the gate terminal of the semiconductor switch to be driven and the negative electrode of the DC power supply is connected to the source terminal of the semiconductor switch, so that the accumulated charge of the input capacitance of the semiconductor switch So as to power regenerated to the DC power supply side, to reduce the loss of the gate driving circuit, there is a method to reduce the size of the circuit (for example, see Patent Document 1 below).
特開２０１６―１２３１９９号公報Japanese Unexamined Patent Publication No. 2016-123199
　しかしながら、特許文献１に示された単電源の電力回生型ゲート駆動技術を、例えば高電圧側アームと低電圧側アームの半導体スイッチで構成されるハーフブリッジまたはフルブリッジ回路からなるインバータに用いたとすると、高電圧側アームの半導体スイッチをターンオンしたときに、低電圧側アームの半導体スイッチのドレイン端子－ソース端子間電圧が上昇することで、低電圧側アームの半導体スイッチのゲート端子－ソース端子間電圧が持ち上がり、オフしている低電圧側アームの半導体スイッチがオンしてしまうといった誤動作を引き起こす不具合が生じる。 However, when the power regeneration type gate drive technology of a single power source disclosed in Patent Document 1 is used for an inverter composed of a half-bridge or full-bridge circuit composed of semiconductor switches of a high-voltage side arm and a low-voltage side arm, When the semiconductor switch of the high-voltage side arm is turned on, the voltage between the drain terminal and the source terminal of the semiconductor switch of the low-voltage side arm rises, whereby the voltage between the gate terminal and the source terminal of the semiconductor switch of the low-voltage side arm This causes a malfunction that causes the malfunction of the semiconductor switch of the low-voltage side arm that is lifted and turned off.
　この発明は、前記のような問題点を解決するためになされたものであり、従来のような単電源の電力回生型ゲート駆動回路においても、該当半導体スイッチのゲート端子－ソース端子間へ負電圧を印加することができ、半導体スイッチの誤動作を防止することができることを目的としている。 The present invention has been made to solve the above-described problems, and in a conventional single power supply power regeneration type gate drive circuit, a negative voltage is applied between the gate terminal and the source terminal of the corresponding semiconductor switch. The purpose is to prevent malfunction of the semiconductor switch.
　この発明に係るゲート駆動回路は、
直流電源に対して、第１のスイッチング素子と第２のスイッチング素子からなる直列回路、および第３のスイッチング素子と第４のスイッチング素子からなる直列回路を並列に接続し、
上記第１のスイッチング素子と上記第２のスイッチング素子との互いの接続点である第１のノードと、上記第３のスイッチング素子と上記第４のスイッチング素子との互いの接続点である第２のノードとの間にリアクトルを接続し、
上記第１のノードを駆動制御対象となる半導体スイッチのゲート端子に接続し、
上記第２のスイッチング素子と上記直流電源の負極端子の間にダイオードを接続し、
上記第１、第２、第３、第４のスイッチング素子のそれぞれのオン・オフ動作を制御するスイッチング制御回路を備えている。 The gate drive circuit according to the present invention is:
A DC circuit is connected in parallel with a series circuit composed of a first switching element and a second switching element, and a series circuit composed of a third switching element and a fourth switching element,
A first node that is a connection point between the first switching element and the second switching element, and a second node that is a connection point between the third switching element and the fourth switching element. Connect a reactor between the node and
Connecting the first node to a gate terminal of a semiconductor switch to be driven and controlled;
A diode is connected between the second switching element and the negative terminal of the DC power supply;
A switching control circuit for controlling the on / off operation of each of the first, second, third, and fourth switching elements is provided.
　この発明のゲート駆動回路によれば、駆動制御対象となる半導体スイッチがオフしているときに、上記半導体スイッチの入力容量の蓄積電荷をリアクトルにより電源側に電力回生しつつ、上記半導体スイッチのゲートソース間に負電圧を印加することが可能となる。したがって、従来のような単電源の電力回生型ゲート駆動回路においても、上記半導体スイッチの誤動作の発生を確実に防止することができる効果を奏する。 According to the gate drive circuit of the present invention, when the semiconductor switch to be driven is turned off, the accumulated charge of the input capacitance of the semiconductor switch is regenerated to the power source side by the reactor, and the gate of the semiconductor switch It becomes possible to apply a negative voltage between the sources. Therefore, even in a conventional single power source power regeneration type gate drive circuit, it is possible to reliably prevent malfunction of the semiconductor switch.
この発明の実施の形態１によるゲート駆動回路の構成を示す回路図である。1 is a circuit diagram showing a configuration of a gate drive circuit according to a first embodiment of the present invention. FIG. この発明の実施の形態１によるゲート駆動回路の第１～第４のスイッチング素子の動作を示すタイミングチャートである。6 is a timing chart showing the operation of the first to fourth switching elements of the gate drive circuit according to the first embodiment of the present invention. 図２に示す第１～第４のスイッチング素子の動作に伴う各部の電流、電圧の変化を示す動作波形図である。FIG. 3 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements shown in FIG. 図２に示す一つの動作期間における電流経路図である。FIG. 3 is a current path diagram in one operation period shown in FIG. 2. 図２に示す一つの動作期間における電流経路図である。FIG. 3 is a current path diagram in one operation period shown in FIG. 2. 図２に示す一つの動作期間における電流経路図である。FIG. 3 is a current path diagram in one operation period shown in FIG. 2. この発明の実施の形態１によるゲート駆動回路の変形例を示す回路図である。It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 1 of this invention. この発明の実施の形態２によるゲート駆動回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the gate drive circuit by Embodiment 2 of this invention. この発明の実施の形態２によるゲート駆動回路の第１～第５のスイッチング素子の動作を示すタイミングチャートである。6 is a timing chart showing operations of first to fifth switching elements of a gate drive circuit according to a second embodiment of the present invention. 図９に示す第１～第５の各スイッチング素子の動作に伴う各部の電流、電圧の変化を示す動作波形図である。FIG. 10 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fifth switching elements shown in FIG. 9; 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. 図９に示す一つの動作期間における電流経路図である。FIG. 10 is a current path diagram in one operation period shown in FIG. 9. この発明の実施の形態２によるゲート駆動回路の変形例を示す回路図である。It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 2 of this invention. この発明の実施の形態３によるゲート駆動回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the gate drive circuit by Embodiment 3 of this invention. この発明の実施の形態３によるゲート駆動回路の第１～第４のスイッチング素子の動作を示すタイミングチャートである。14 is a timing chart showing operations of first to fourth switching elements of a gate drive circuit according to Embodiment 3 of the present invention. 図２２に示す第１～第４のスイッチング素子の動作に伴う各部の電流、電圧の変化を示す動作波形図である。FIG. 23 is an operation waveform diagram showing changes in currents and voltages of the respective parts accompanying the operations of the first to fourth switching elements shown in FIG. 22; 図２２に示す一つの動作期間における電流経路図である。FIG. 23 is a current path diagram in one operation period shown in FIG. 22. 図２２に示す一つの動作期間における電流経路図である。FIG. 23 is a current path diagram in one operation period shown in FIG. 22. 図２２に示す一つの動作期間における電流経路図である。FIG. 23 is a current path diagram in one operation period shown in FIG. 22. この発明の実施の形態３によるゲート駆動回路の変形例を示す回路図である。It is a circuit diagram which shows the modification of the gate drive circuit by Embodiment 3 of this invention. この発明の実施の形態４によるゲート駆動回路の第１～第４のスイッチングの動作を示すタイミングチャートである。14 is a timing chart showing first to fourth switching operations of a gate drive circuit according to a fourth embodiment of the present invention. 図２８に示す第１～第４の各スイッチング素子の動作に伴う各部の電流、電圧の変化を示す動作波形図である。FIG. 29 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of each of the first to fourth switching elements shown in FIG. 図２８に示す一つの動作期間における電流経路図である。FIG. 29 is a current path diagram in one operation period shown in FIG. 28.
実施の形態１．
　図１は、この実施の形態１におけるゲート駆動回路の構成を示す回路図である。
　この実施の形態１のゲート駆動回路１００は、入力容量１０を備えた電圧駆動型の半導体スイッチ９を駆動制御対象として、１つの直流電源７で上記半導体スイッチ９をオン・オフ駆動するものである。 Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a gate drive circuit according to the first embodiment.
The gate drive circuit 100 according to the first embodiment uses a voltage-driven semiconductor switch 9 having an input capacitor 10 as a drive control target and drives the semiconductor switch 9 on and off with a single DC power supply 7. .
　ゲート駆動回路１００の具体的な構成としては、直流電源７に対して、第１のスイッチング素子１と第２のスイッチング素子２からなる直列回路、および第３のスイッチング素子３と第４のスイッチング素子４からなる直列回路、を共に並列に接続する。第１のスイッチング素子１と第２のスイッチング素子２との互いの接続点である第１のノード１１と、第３のスイッチング素子３と第４のスイッチング素子４との互いの接続点である第２のノード１２との間にリアクトル６を接続し、第１のノード１１を駆動制御対象となる半導体スイッチ９のゲート端子に接続する。また、第２のスイッチング素子２と直流電源７の負極端子の間にダイオード８を接続している。さらに、第１、第２、第３、および第４のスイッチング素子１、２、３、４のそれぞれのオン・オフ動作を制御するスイッチング制御回路５０を備えている。 As a specific configuration of the gate drive circuit 100, a series circuit including a first switching element 1 and a second switching element 2, and a third switching element 3 and a fourth switching element with respect to the DC power supply 7. 4 series circuits are connected together in parallel. The first node 11, which is a connection point between the first switching element 1 and the second switching element 2, and the first connection point between the third switching element 3 and the fourth switching element 4. The reactor 6 is connected between the two nodes 12 and the first node 11 is connected to the gate terminal of the semiconductor switch 9 to be driven and controlled. A diode 8 is connected between the second switching element 2 and the negative terminal of the DC power supply 7. Further, a switching control circuit 50 that controls the on / off operations of the first, second, third, and fourth switching elements 1, 2, 3, and 4 is provided.
　ここで、直流電源７の直流電圧（以下、電源電圧と称す）をＶｄｃ、リアクトル６に流れる電流（以下、リアクトル電流と称す）をｉＬ、半導体スイッチ９の入力容量１０に流れる電流をｉｇ、半導体スイッチ９の入力容量１０を介してゲート端子－ソース端子間に印加される電圧（以下、ゲートソース間電圧と称す）をＶｇｓＬ、半導体スイッチ９のドレイン端子－ソース端子間に印加される電圧（以下、ドレインソース間電圧と称す）をＶｄｓＬ、半導体スイッチ９のドレイン端子に流れる電流をｉｄＬとする。 Here, the DC voltage of the DC power supply 7 (hereinafter referred to as power supply voltage) is Vdc, the current flowing through the reactor 6 (hereinafter referred to as reactor current) is iL, the current flowing through the input capacitor 10 of the semiconductor switch 9 is ig, the semiconductor A voltage applied between the gate terminal and the source terminal via the input capacitor 10 of the switch 9 (hereinafter referred to as a gate-source voltage) is VgsL, and a voltage applied between the drain terminal and the source terminal of the semiconductor switch 9 (hereinafter referred to as “voltage”). VsL), and the current flowing through the drain terminal of the semiconductor switch 9 is idL.
　また、第１のスイッチング素子１の駆動信号をＱ１、第２のスイッチング素子２の駆動信号をＱ２、第３のスイッチング素子３の駆動信号をＱ３、第４のスイッチング素子４の駆動信号をＱ４とする。また、リアクトル６のインダクタンス値をＬ、入力容量１０の容量値をＣｉｓｓとする。また、リアクトル６と入力容量１０で決まる共振周期をＴとすれば、共振周期Ｔは次の（式１）で表すことができる。 The driving signal for the first switching element 1 is Q1, the driving signal for the second switching element 2 is Q2, the driving signal for the third switching element 3 is Q3, and the driving signal for the fourth switching element 4 is Q4. To do. Further, the inductance value of the reactor 6 is L, and the capacitance value of the input capacitor 10 is Ciss. If the resonance period determined by the reactor 6 and the input capacitor 10 is T, the resonance period T can be expressed by the following (formula 1).
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　なお、この実施の形態１（図１）の回路構成において、第１～第４のスイッチング素子１～４は、ここでは一例として寄生のダイオードを備えたＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）として記載しているが、ダイオードとＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）を並列に接続した構成でもよい。また、その他として、ダイオードを並列に接続したサイリスタやＧＴＯ（Ｇａｔｅ　Ｔｕｒｎ－Ｏｆｆ　ｔｈｙｒｉｓｔｏｒ）でもよい。以降、この実施の形態１では、第１～第４のスイッチング素子１～４はＭＯＳＦＥＴと見なし、また、寄生ダイオードおよびダイオード８の順方向電圧はゼロと見なして説明する。 In the circuit configuration of the first embodiment (FIG. 1), the first to fourth switching elements 1 to 4 are MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) each including a parasitic diode as an example here. However, a configuration in which a diode and an IGBT (Insulated Gate Bipolar Transistor) are connected in parallel may be used. In addition, a thyristor or a GTO (Gate Turn-Off thyristor) in which diodes are connected in parallel may be used. Hereinafter, in the first embodiment, the first to fourth switching elements 1 to 4 are regarded as MOSFETs, and the forward voltage of the parasitic diode and the diode 8 is regarded as zero.
　図２は、駆動制御対象となる半導体スイッチ９のオン・オフ動作に伴う、ゲート駆動回路１００の第１～第４のスイッチング素子１～４の動作を示すタイミングチャートである。なお、ここでは駆動制御対象となる半導体スイッチ９がターンオフするのを期間Ｔ１から期間Ｔ３までの期間内とし、半導体スイッチ９がターンオンするのを期間Ｔ４から期間Ｔ６までの期間内とする。以下、上記の期間Ｔ１～Ｔ６の６期間を次のように定義する。 FIG. 2 is a timing chart showing the operations of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 in accordance with the on / off operation of the semiconductor switch 9 to be driven. Here, the semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the semiconductor switch 9 is turned on within the period from the period T4 to the period T6. Hereinafter, the six periods T1 to T6 are defined as follows.
（１）期間Ｔ１：リアクトル６の励磁期間
（２）期間Ｔ２：入力容量１０の蓄積電荷Ｃｉｓｓの電力回生期間および半導体スイッチ９のゲートヘの負電圧印加期間
（３）期間Ｔ３：半導体スイッチ９のオフ固定継続期間
（４）期間Ｔ４：リアクトル６の励磁期間
（５）期間Ｔ５：半導体スイッチ９のゲートへの正電圧印加期間
（６）期間Ｔ６：半導体スイッチ９のオン固定継続期間 (1) Period T1: Excitation period of the reactor 6 (2) Period T2: Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9 (3) Period T3: Semiconductor switch 9 off Fixed duration (4) Period T4: Reactor 6 excitation period (5) Period T5: Positive voltage application period to the gate of the semiconductor switch 9 (6) Period T6: Semiconductor switch 9 on-fixed duration
　図３は、図２に基づく第１～第４のスイッチング素子１～４の動作に伴う各部の電流、電圧の変化を示す動作波形図である。また、図４～図６は上記の期間Ｔ１～期間Ｔ３での電流経路を示す。以下、図３～図６を用いて動作原理を説明する。 FIG. 3 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG. 4 to 6 show current paths in the above-described periods T1 to T3. Hereinafter, the principle of operation will be described with reference to FIGS.
（１）期間Ｔ１：リアクトル６の励磁期間
　この期間Ｔ１では、第１のスイッチング素子１がオン、第２、第３、第４のスイッチング素子２、３、４が共にオフしていて、半導体スイッチ９がオン固定されている状態から、第１のスイッチング素子１をオフすると共に、第４のスイッチング素子４を予め定めた時間ｔａだけオンする。そうすると、図４に示すように、電流は、入力容量１０からノード１１に流れ込み、リアクトル６およびノード１２を介して第４のスイッチング素子４に流れ込み、入力容量１０に帰還する。 (1) Period T1: Excitation period of the reactor 6 In this period T1, the first switching element 1 is on, the second, third, and fourth switching elements 2, 3, and 4 are all off, and the semiconductor switch From the state in which 9 is fixed to ON, the first switching element 1 is turned off and the fourth switching element 4 is turned on for a predetermined time ta. Then, as shown in FIG. 4, the current flows from the input capacitor 10 to the node 11, flows into the fourth switching element 4 through the reactor 6 and the node 12, and returns to the input capacitor 10.
　この電流経路によってリアクトル６と入力容量１０の間で共振動作となり、ゲートソース間電圧ＶｇｓＬは電源電圧Ｖｄｃから減少し、リアクトル電流ｉＬはゼロから負極に増加する。この時、リアクトル６は入力容量１０の蓄積電荷Ｃｉｓｓによって、励磁される。 </ RTI> This current path causes resonance between the reactor 6 and the input capacitor 10, the gate-source voltage VgsL decreases from the power supply voltage Vdc, and the reactor current iL increases from zero to the negative electrode. At this time, the reactor 6 is excited by the accumulated charge Ciss of the input capacitor 10.
（２）期間Ｔ２：入力容量１０の蓄積電荷Ｃｉｓｓの電力回生期間および半導体スイッチ９のゲートヘの負電圧印加期間
　この期間Ｔ２では、第４のスイッチング素子４をオフし、予め定めた時間ｔｂだけ第２のスイッチング素子２をオフする。そうすると、図５に示すように、リアクトル６によってリアクトル電流ｉＬが継続して流れるため、第３のスイッチング素子３の寄生ダイオードが導通し、直流電源７の正極に流れ込み、入力容量１０に帰還する。この時、リアクトル６の励磁エネルギの一部は直流電源７に電力回生し、励磁エネルギの残りは直流電源７の負極から入力容量１０へ流れ込むので、ゲートソース間電圧ＶｇｓＬは負極に向けて、リアクトル電流ｉＬは正極に向けてそれぞれ増加する。よって、半導体スイッチ９のゲートヘは負電圧が印加される。 (2) Period T2: Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9 In this period T2, the fourth switching element 4 is turned off, and the first time period tb is reached. 2 switching element 2 is turned off. Then, as shown in FIG. 5, the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 is conducted, flows into the positive electrode of the DC power supply 7, and returns to the input capacitor 10. At this time, a part of the excitation energy of the reactor 6 is regenerated to the DC power source 7 and the remainder of the excitation energy flows from the negative electrode of the DC power source 7 to the input capacitor 10, so that the gate-source voltage VgsL is directed toward the negative electrode. The current iL increases toward the positive electrode. Therefore, a negative voltage is applied to the gate of the semiconductor switch 9.
（３）期間Ｔ３：半導体スイッチ９のオフ固定継続期間
　この期間Ｔ３では、第２のスイッチング素子２をオンする。その際、図３に示すように、ゲートソース間電圧ＶｇｓＬが負電圧、リアクトル電流ｉＬがゼロであるため、第４のスイッチング素子４の寄生ダイオードが導通する。その結果、図６に示すように、電流は入力容量１０から第４のスイッチング素子４の寄生ダイオードを介してノード１２へ流れ込む。その後、ノード１２からリアクトル６を介してノード１１に流れ、入力容量１０に帰還する。 (3) Period T3: Fixed off duration of semiconductor switch 9 In this period T3, the second switching element 2 is turned on. At this time, as shown in FIG. 3, since the gate-source voltage VgsL is a negative voltage and the reactor current iL is zero, the parasitic diode of the fourth switching element 4 becomes conductive. As a result, as shown in FIG. 6, current flows from the input capacitor 10 to the node 12 via the parasitic diode of the fourth switching element 4. Thereafter, the current flows from the node 12 through the reactor 6 to the node 11 and returns to the input capacitor 10.
　電流がノード１１から入力容量１０へ流れ込むことで、ゲートソース間電圧ＶｇｓＬは正極に向けて増加されるが、その際、第２のスイッチング素子２がオンしているので、ダイオード８により半導体スイッチ９のゲートソース間電圧ＶｇｓＬはゼロにクランプされて半導体スイッチ９はオフを継続する。なお、ゲートソース間電圧ＶｇｓＬの負極から正極への変化は、リアクトル６によって抑制されることは言うまでもない。 When the current flows from the node 11 to the input capacitor 10, the gate-source voltage VgsL is increased toward the positive electrode. At this time, since the second switching element 2 is turned on, the diode 8 causes the semiconductor switch 9. The gate-source voltage VgsL is clamped to zero and the semiconductor switch 9 continues to be turned off. Needless to say, the change in the gate-source voltage VgsL from the negative electrode to the positive electrode is suppressed by the reactor 6.
（４）期間Ｔ４：リアクトル６の励磁期間
　この期間Ｔ４では、第３のスイッチング素子３をオンする。その結果、電流は直流電源７の正極から第３のスイッチング素子３を介してノード１２に流れ込む。その後、ノード１２からリアクトル６および第２のスイッチング素子２を介してダイオード８のカソードに流れ、直流電源７の負極に帰還する。この電流経路によりリアクトル６は励磁されるので、リアクトル電流ｉＬは正極に増加する。 (4) Period T4: Excitation period of the reactor 6 In this period T4, the third switching element 3 is turned on. As a result, current flows from the positive electrode of the DC power supply 7 to the node 12 via the third switching element 3. Thereafter, the current flows from the node 12 to the cathode of the diode 8 through the reactor 6 and the second switching element 2, and returns to the negative electrode of the DC power supply 7. Since the reactor 6 is excited by this current path, the reactor current iL increases to the positive electrode.
（５）期間Ｔ５：半導体スイッチ９のゲートへの正電圧印加期間
　この期間Ｔ５では、第２のスイッチング素子２をオフする。この場合、リアクトル６によって、リアクトル電流ｉＬは継続して流れ、入力容量１０を充電する。その結果、ゲートソース間電圧ＶｇｓＬは正極に向けて増加する。 (5) Period T5: Positive voltage application period to the gate of the semiconductor switch 9 In this period T5, the second switching element 2 is turned off. In this case, the reactor current iL continuously flows through the reactor 6 and charges the input capacitor 10. As a result, the gate-source voltage VgsL increases toward the positive electrode.
（６）期間Ｔ６：半導体スイッチ９のオン固定継続期間
　この期間Ｔ６では、第１のスイッチング素子１をオンする。そうすると、電流は直流電源７の正極から第１のスイッチング素子１および入力容量１０を介して、直流電源７の負極に帰還する経路を形成する。この電流経路によりゲートソース間電圧ＶｇｓＬは電源電圧Ｖｄｃにクランプされ、半導体スイッチ９はオンを継続する。 (6) Period T6: On-fixing continuation period of the semiconductor switch 9 In this period T6, the first switching element 1 is turned on. Then, the current forms a path for returning from the positive electrode of the DC power source 7 to the negative electrode of the DC power source 7 via the first switching element 1 and the input capacitor 10. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
　以上のように、ゲート駆動回路１００を動作させることで、半導体スイッチ９のターンオフ時は、入力容量１０の蓄積電荷Ｃｉｓｓの一部をリアクトル６により直流電源７側に電力回生し、入力容量１０の蓄積電荷Ｃｉｓｓの残りを半導体スイッチ９のゲート－ソース間に負電圧として印加することが可能となる。したがって、従来のような負電源を設けなくても半導体スイッチ９の誤動作の発生を確実に防止することができ、簡素で小型化可能なゲート駆動回路１００を得ることができる。 As described above, by operating the gate driving circuit 100, when the semiconductor switch 9 is turned off, a part of the accumulated charge Ciss of the input capacitor 10 is regenerated to the DC power source 7 side by the reactor 6, and the input capacitor 10 The remainder of the accumulated charge Ciss can be applied as a negative voltage between the gate and source of the semiconductor switch 9. Therefore, it is possible to reliably prevent the malfunction of the semiconductor switch 9 without providing a negative power supply as in the prior art, and to obtain the gate drive circuit 100 that is simple and can be miniaturized.
　ここで、前記の期間Ｔ１で説明した予め定めた時間ｔａについて説明する。
　この時間ｔａのゲートソース間電圧ＶｇｓＬおよびリアクトル電流ｉＬは、次の（式２）と（式３）で示すように三角関数で表すことができる。 Here, the predetermined time ta described in the period T1 will be described.
The gate-source voltage VgsL and the reactor current iL at this time ta can be expressed by a trigonometric function as shown in the following (Expression 2) and (Expression 3).
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
　上記の予め定めた時間ｔａを、リアクトル６と入力容量１０で決まる共振周期Ｔの４分の１より長く、かつリアクトル６と入力容量１０で決まる共振周期Ｔの２分の１より短く設定したと仮定する。そうすると、ゲートソース間電圧ＶｇｓＬとリアクトル電流ｉＬは負の値になり、期間Ｔ１の一部において、半導体スイッチ９のゲート端子－ソース端子間に電圧ＶｇｓＬとして負電圧を印加する期間を設けることができる。その結果、負電圧印加期間が増えるので、半導体スイッチ９に直列接続される図示しない高電圧側アームのターンオンのタイミング設定を容易化できるメリットがある。なお、リアクトル電流ｉＬは負の値なので、リアクトル６は励磁されており、期間Ｔ２で励磁エネルギが直流電源７へ電力回生されることは言うまでもない。 The predetermined time ta is set to be longer than a quarter of the resonance period T determined by the reactor 6 and the input capacity 10 and shorter than a half of the resonance period T determined by the reactor 6 and the input capacity 10. Assume. Then, the gate-source voltage VgsL and the reactor current iL have negative values, and a period during which a negative voltage is applied as the voltage VgsL between the gate terminal and the source terminal of the semiconductor switch 9 can be provided in a part of the period T1. . As a result, since the negative voltage application period is increased, there is an advantage that the turn-on timing setting of a high voltage side arm (not shown) connected in series to the semiconductor switch 9 can be facilitated. Since reactor current iL is a negative value, reactor 6 is excited and it goes without saying that the excitation energy is regenerated to DC power supply 7 in period T2.
　さらに、前記の期間Ｔ２で説明した第２のスイッチング素子２をオフする予め定めた時間ｔｂについて説明する。この時間ｔｂを、ゲートソース間電圧ＶｇｓＬがゼロ以下の時と仮定する。言い換えれば、ゲートソース間電圧ＶｇｓＬが負の値の時に第２のスイッチング素子２をオンする。これにより期間Ｔ２において、第４のスイッチング素子４の寄生ダイオードを介した電流によるゲートソース間電圧ＶｇｓＬの正極への増加を防止することができ、半導体スイッチ９の誤動作の抑制が可能となる。 Furthermore, a predetermined time tb for turning off the second switching element 2 described in the period T2 will be described. This time tb is assumed to be when the gate-source voltage VgsL is less than or equal to zero. In other words, when the gate-source voltage VgsL is a negative value, the second switching element 2 is turned on. Thereby, in the period T2, an increase in the gate-source voltage VgsL to the positive electrode due to the current through the parasitic diode of the fourth switching element 4 can be prevented, and malfunction of the semiconductor switch 9 can be suppressed.
　図７は図１に示したゲート駆動回路の変形例を示すもので、図１と対応もしくは相当する構成部分には同一の符号を付す。 FIG. 7 shows a modification of the gate drive circuit shown in FIG. 1, and the same reference numerals are given to components corresponding to or corresponding to FIG.
　図７に示す構成のゲート駆動回路１００において、図１の構成と異なる点は、半導体スイッチ９のゲート端子とソース端子の間に第２のコンデンサ２２が並列接続されている。また、半導体スイッチ９のゲート端子に第１のツェナーダイオード３１のカソード端子が接続されている。また、半導体スイッチ９のソース端子に第２のツェナーダイオード３２のカソード端子が接続されている。さらに、第１のツェナーダイオード３１のアノード端子と第２のツェナーダイオード３２のアノード端子とが互いに接続されている。また、第１のスイッチング素子１と第１のノード１１との間に第１の抵抗（Ｒｏｎ）４１が接続され、第２のスイッチング素子２と第１のノード１１の間に第２の抵抗４２（Ｒｏｆｆ）が接続されている。 7 differs from the configuration of FIG. 1 in that the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the semiconductor switch 9. The cathode terminal of the first Zener diode 31 is connected to the gate terminal of the semiconductor switch 9. The cathode terminal of the second Zener diode 32 is connected to the source terminal of the semiconductor switch 9. Further, the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other. A first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistor 42 is connected between the second switching element 2 and the first node 11. (Roff) is connected.
　このように、第２のコンデンサ２２を接続することで、半導体スイッチ９の入力容量を増加することができる。そのため、例えば半導体スイッチ９に直列接続される図示しない高電圧側アームをターンオンさせたときに、低電圧側アームとなる半導体スイッチ９のドレイン端子－ソース端子間の電圧ＶｄｓＬが上昇することで発生するゲートソース間電圧ＶｇｓＬの正極側への持ち上がりを抑制できる。したがって、半導体スイッチ９の誤動作の抑制が可能となる。 Thus, by connecting the second capacitor 22, the input capacitance of the semiconductor switch 9 can be increased. Therefore, for example, when a high-voltage side arm (not shown) connected in series to the semiconductor switch 9 is turned on, the voltage VdsL between the drain terminal and the source terminal of the semiconductor switch 9 serving as the low-voltage side arm increases. Lifting of the gate-source voltage VgsL to the positive electrode side can be suppressed. Therefore, malfunction of the semiconductor switch 9 can be suppressed.
　また、第２のツェナーダイオード３２は、期間Ｔ１～期間Ｔ３において半導体スイッチ９のゲート端子－ソース端子間に、負の過電圧を印加させない効果を提供する。また、第１のツェナーダイオード３１は、例えば、期間Ｔ４以降に半導体スイッチ９をオン固定させる際において、半導体スイッチ９のゲート端子－ソース端子間に、正の過電圧を印加させない効果を提供する。 Further, the second Zener diode 32 provides an effect of preventing a negative overvoltage from being applied between the gate terminal and the source terminal of the semiconductor switch 9 in the period T1 to the period T3. Further, the first Zener diode 31 provides an effect of preventing a positive overvoltage from being applied between the gate terminal and the source terminal of the semiconductor switch 9 when, for example, the semiconductor switch 9 is fixed on after the period T4.
　さらに、第１の抵抗４１は、例えば、期間Ｔ３から半導体スイッチ９をオン固定させる際の、ゲートソース間電圧ＶｇｓＬと電源電圧Ｖｄｃとの電位差に基づいた突入電流を防止する効果を提供する。また、第２の抵抗４２は、期間Ｔ３においてゲートソース間電圧ＶｇｓＬをクランプする際の、ゲートソース間電圧ＶｇｓＬとダイオード８の順方向電圧の電位差に基づいた突入電流を防止する効果を提供する。なお、第１の抵抗４１は別途追加して設けなくても、第１のスイッチング素子１の内部抵抗を利用してもよい。同様に、第２の抵抗４２は別途追加して設けなくても、第２のスイッチング素子２の内部抵抗を利用してもよい。
　図７に示したゲート駆動回路１００におけるその他の構成および作用効果は、図１に示した構成の場合と同様であるから、詳しい説明は省略する。 Further, the first resistor 41 provides an effect of preventing an inrush current based on a potential difference between the gate-source voltage VgsL and the power supply voltage Vdc when the semiconductor switch 9 is fixed on from the period T3, for example. The second resistor 42 provides an effect of preventing an inrush current based on a potential difference between the gate-source voltage VgsL and the forward voltage of the diode 8 when clamping the gate-source voltage VgsL in the period T3. The first resistor 41 may not be provided separately and the internal resistance of the first switching element 1 may be used. Similarly, the internal resistance of the second switching element 2 may be used without providing the second resistor 42 separately.
The other configuration and operational effects of the gate drive circuit 100 shown in FIG. 7 are the same as those of the configuration shown in FIG.
実施の形態２．
　上記実施の形態１では、半導体スイッチ９のターンオフ時は、入力容量１０の蓄積電荷Ｃｉｓｓの一部をリアクトル６により直流電源７側に電力回生し、入力容量１０の蓄積電荷Ｃｉｓｓの残りを半導体スイッチ９のゲート端子－ソース端子間に負電圧として印加するようにしている。 Embodiment 2. FIG.
In the first embodiment, when the semiconductor switch 9 is turned off, a part of the stored charge Ciss of the input capacitor 10 is regenerated to the DC power supply 7 side by the reactor 6 and the remaining stored charge Ciss of the input capacitor 10 is transferred to the semiconductor switch. 9 is applied as a negative voltage between the gate terminal and the source terminal.
　しかし、上記実施の形態１の場合には、ゲートソース間電圧ＶｇｓＬが負の値の際には、電流は第４のスイッチング素子４の寄生ダイオードを介して入力容量１０に流れ込み、ゲートソース間電圧ＶｇｓＬを正極に向けて充電する。この充電により、ゲート駆動回路１００の損失が発生する。 However, in the case of the first embodiment, when the gate-source voltage VgsL is a negative value, the current flows into the input capacitor 10 via the parasitic diode of the fourth switching element 4, and the gate-source voltage VgsL is charged toward the positive electrode. Due to this charging, loss of the gate driving circuit 100 occurs.
　これに対して、この実施の形態２では、半導体スイッチ９がターンオンする際にゲートソース間電圧ＶｇｓＬを負の電圧値に保持し、その蓄積電荷Ｃｉｓｓを直流電源７側に電力回生させるものである。以下、そのための構成と制御内容について具体的に説明する。 On the other hand, in the second embodiment, when the semiconductor switch 9 is turned on, the gate-source voltage VgsL is held at a negative voltage value, and the accumulated charge Ciss is regenerated to the DC power supply 7 side. . Hereinafter, the configuration and control contents for that purpose will be described in detail.
　図８は、この発明の実施の形態２におけるゲート駆動回路の構成を示す回路図であり、図１に示した構成と対応もしくは相当する構成部分には同一の符号を付す。 FIG. 8 is a circuit diagram showing a configuration of the gate drive circuit according to the second embodiment of the present invention, and components corresponding to or corresponding to the configuration shown in FIG. 1 are denoted by the same reference numerals.
　この実施の形態２のゲート駆動回路１００は、実施の形態１（図１）の回路構成に対して、第４のスイッチング素子４と直流電源７の負極端子の間に第５のスイッチング素子５が直列接続されている。また、ダイオード８のアノード端子およびカソード端子に第１のコンデンサ２１が並列接続されている。さらに、スイッチング制御回路５０は第５のスイッチング素子５を駆動させる駆動信号Ｑ５が追加して設けられている。 The gate drive circuit 100 according to the second embodiment is different from the circuit configuration according to the first embodiment (FIG. 1) in that the fifth switching element 5 is provided between the fourth switching element 4 and the negative terminal of the DC power source 7. They are connected in series. A first capacitor 21 is connected in parallel to the anode terminal and the cathode terminal of the diode 8. Further, the switching control circuit 50 is additionally provided with a drive signal Q5 for driving the fifth switching element 5.
　図９は、駆動制御対象となる半導体スイッチ９のオン・オフ動作に伴うゲート駆動回路１００の第１～第５のスイッチング素子１～５の動作を示すタイミングチャートである。なお、ここでは駆動制御対象となる半導体スイッチ９がターンオフするのを期間Ｔ１から期間Ｔ３までの期間内とし、半導体スイッチ９がターンオンするのを期間Ｔ４から期間Ｔ９までの期間内とする。以下、上記の期間Ｔ１～期間Ｔ９の９期間を次のように定義する。 FIG. 9 is a timing chart showing the operation of the first to fifth switching elements 1 to 5 of the gate drive circuit 100 in accordance with the on / off operation of the semiconductor switch 9 to be driven and controlled. Here, the semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the semiconductor switch 9 is turned on within the period from the period T4 to the period T9. Hereinafter, the nine periods T1 to T9 are defined as follows.
（１）期間Ｔ１：リアクトル６の励磁期間
（２）期間Ｔ２：入力容量１０の蓄積電荷Ｃｉｓｓの電力回生期間および半導体スイッチ９のゲートへの負電圧印加期間
（３）期間Ｔ３：半導体スイッチ９のオフ固定継続期間
（４）期間Ｔ４：入力容量１０と第１のコンデンサ２１による蓄積電荷の電力回生期間およびリアクトル６の励磁期間
（５）期間Ｔ５：入力容量１０への電荷注入期間
（６）期間Ｔ６：リアクトル６への還流期間
（７）期間Ｔ７：リアクトル６の励磁電流による直流電源７への電力回生期間
（８）期間Ｔ８：リアクトル６の励磁電流による直流電源７への電力回生継続期間
（９）期間Ｔ９：半導体スイッチ９のオン固定継続期間 (1) Period T1: Excitation period of the reactor 6 (2) Period T2: Power regeneration period of the accumulated charge Ciss of the input capacitance 10 and negative voltage application period to the gate of the semiconductor switch 9 (3) Period T3: Semiconductor switch 9 OFF fixed continuation period (4) period T4: power regeneration period of charge accumulated by the input capacitor 10 and the first capacitor 21 and excitation period (5) period of the reactor 6 T5: charge injection period (6) period to the input capacitor 10 T6: Period of recirculation to reactor 6 (7) Period T7: Power regeneration period to DC power supply 7 by exciting current of reactor 6 (8) Period T8: Power regeneration continuation period to DC power supply 7 by exciting current of reactor 6 ( 9) Period T9: On-fixed duration of semiconductor switch 9
　図１０は、図９に基づく第１～第５の各スイッチング素子１～５の動作に伴う各部の電流、電圧の変化を示す動作波形図である。また、図１１～図１９は上記の各動作期間Ｔ１～Ｔ９での電流経路を示す。以下、図１０～図１９を用いて動作原理を説明する。 FIG. 10 is an operation waveform diagram showing changes in the current and voltage of each part accompanying the operation of each of the first to fifth switching elements 1 to 5 based on FIG. FIGS. 11 to 19 show current paths in the operation periods T1 to T9. Hereinafter, the operation principle will be described with reference to FIGS.
（１）期間Ｔ１：リアクトル６の励磁期間
　この期間Ｔ１では、第１のスイッチング素子１がオン、第２、第３、第４、第５のスイッチング素子２、３、４、５が共にオフしていて、半導体スイッチ９がオン固定されている状態から、第１のスイッチング素子１をオフすると共に、第４、第５のスイッチング素子４、５を予め定めた時間ｔａだけオンする。そうすると、図１１に示すように、電流は、入力容量１０からノード１１に流れ込み、リアクトル６およびノード１２を介して第４、第５のスイッチング素子４、５に流れ込み、入力容量１０に帰還する。 (1) Period T1: Excitation period of the reactor 6 In this period T1, the first switching element 1 is turned on, and the second, third, fourth, and fifth switching elements 2, 3, 4, and 5 are all turned off. In addition, from the state where the semiconductor switch 9 is fixed on, the first switching element 1 is turned off, and the fourth and fifth switching elements 4 and 5 are turned on for a predetermined time ta. Then, as shown in FIG. 11, the current flows from the input capacitor 10 to the node 11, flows into the fourth and fifth switching elements 4 and 5 through the reactor 6 and the node 12, and returns to the input capacitor 10.
（２）期間Ｔ２：入力容量１０の蓄積電荷Ｃｉｓｓの電力回生期間および半導体スイッチ９のゲートへの負電圧印加期間
　この期間Ｔ２では、第４のスイッチング素子４をオフし、予め定めた時間だけ第２のスイッチング素子２をオフする。そうすると、図１２に示すように、リアクトル６によってリアクトル電流ｉＬは継続して流れるため、第３のスイッチング素子３の寄生ダイオードが導通し、直流電源７の正極に流れ込む。そして、電流の一方は第１のコンデンサ２１と第２のスイッチング素子２の寄生ダイオードとを介してリアクトル６に帰還し、電流の他方は入力容量１０を介してリアクトル６に帰還する。 (2) Period T2: Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9 In this period T2, the fourth switching element 4 is turned off, and the period of time is predetermined. 2 switching element 2 is turned off. Then, as shown in FIG. 12, the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 becomes conductive and flows into the positive electrode of the DC power supply 7. One of the currents is fed back to the reactor 6 through the first capacitor 21 and the parasitic diode of the second switching element 2, and the other of the currents is fed back to the reactor 6 through the input capacitor 10.
　このように、電流の他方は直流電源７の負極から入力容量１０へ流れ込むので、ゲートソース間電圧ＶｇｓＬは、負極に増加する。第１のコンデンサ２１の印加電圧は図示していないが、ゲートソース間電圧ＶｇｓＬと同様に負極に増加することは言うまでもない。その後、リアクトル電流ｉＬの値はゼロに近づいていき、ゲートソース間電圧ＶｇｓＬはある負電圧の値になる。 Thus, since the other of the current flows from the negative electrode of the DC power source 7 to the input capacitor 10, the gate-source voltage VgsL increases to the negative electrode. Although the voltage applied to the first capacitor 21 is not shown, it goes without saying that the voltage increases to the negative electrode similarly to the gate-source voltage VgsL. Thereafter, the value of the reactor current iL approaches zero, and the gate-source voltage VgsL becomes a certain negative voltage value.
（３）期間Ｔ３：半導体スイッチ９のオフ固定継続期間
　この期間Ｔ３では、第２のスイッチング素子２をオンする。このとき、ゲートソース間電圧ＶｇｓＬと第１のコンデンサ２１の印加電圧とは共に負電圧であるが、一般的に第１のコンデンサ２１の容量は、半導体スイッチ９の入力容量１０よりも大きいので、ゲートソース間電圧ＶｇｓＬと第１のコンデンサ２１の印加電圧とに電圧差が生じる。 (3) Period T3: Fixed off duration of semiconductor switch 9 In this period T3, the second switching element 2 is turned on. At this time, the gate-source voltage VgsL and the applied voltage of the first capacitor 21 are both negative voltages. However, since the capacitance of the first capacitor 21 is generally larger than the input capacitance 10 of the semiconductor switch 9, A voltage difference is generated between the gate-source voltage VgsL and the voltage applied to the first capacitor 21.
　この電圧差をなくすように、電流は図１３に示すように、第１のコンデンサ２１から第２のスイッチング素子２を介して入力容量１０に流れ込み、入力容量１０を充電する。なお、ここでは第１のコンデンサ２１により入力容量１０を充電する例を示したが、入力容量１０により第１のコンデンサ２１を充電してもよい。いずれにしても、ゲートソース間電圧ＶｇｓＬは負電圧の値のまま保持されるので、半導体スイッチ９はオフ状態に固定される。 In order to eliminate this voltage difference, the current flows from the first capacitor 21 to the input capacitor 10 via the second switching element 2 as shown in FIG. 13, and charges the input capacitor 10. Although an example in which the input capacitor 10 is charged by the first capacitor 21 is shown here, the first capacitor 21 may be charged by the input capacitor 10. In any case, since the gate-source voltage VgsL is maintained as a negative voltage value, the semiconductor switch 9 is fixed to the off state.
（４）期間Ｔ４：入力容量１０と第１のコンデンサ２１による蓄積電荷の電力回生期間およびリアクトル６の励磁期間
　この期間Ｔ４では、半導体スイッチ９がターンオンされた状態で、第２のスイッチング素子２および第３のスイッチング素子３を予め定めた時間ｔｃだけオンする。そうすると、図１４に示すように、電流は直流電源７の正極から第３のスイッチング素子３、および第２のノード１２を介してリアクトル６に流れ込む。そして、この電流の一方は第１のノード１１から第２のスイッチング素子２、第１のコンデンサ２１を介して直流電源７の負極に帰還する。また、上記電流の他方は第１のノード１１から入力容量１０を介して直流電源７の負極に帰還する。 (4) Period T4: Power regeneration period of stored charges by the input capacitor 10 and the first capacitor 21 and the excitation period of the reactor 6 In this period T4, the second switching element 2 and the semiconductor switch 9 are turned on. The third switching element 3 is turned on for a predetermined time tc. Then, as shown in FIG. 14, current flows from the positive electrode of the DC power supply 7 into the reactor 6 through the third switching element 3 and the second node 12. Then, one of the currents is fed back from the first node 11 to the negative electrode of the DC power supply 7 via the second switching element 2 and the first capacitor 21. The other current is fed back from the first node 11 to the negative electrode of the DC power supply 7 through the input capacitor 10.
　この電流経路により、入力容量１０と第１のコンデンサ２１は共に放電動作となり、ゲートソース間電圧ＶｇｓＬは負の電圧値からゼロに近づいていく。この放電によって、入力容量１０と第１のコンデンサ２１の蓄積電荷はリアクトル６に電力回生される。 By this current path, both the input capacitor 10 and the first capacitor 21 are discharged, and the gate-source voltage VgsL approaches zero from the negative voltage value. As a result of this discharge, the electric charges stored in the input capacitor 10 and the first capacitor 21 are regenerated in the reactor 6.
　その後、ゲートソース間電圧ＶｇｓＬがゼロになると、入力容量１０に流れ込む電流ｉｇもゼロになり、ダイオード８が導通する。その結果、電流経路は、図示していないが、直流電源７の正極から第３のスイッチング素子３、第２のノード１２を介してリアクトル６に流れ込み、第２のスイッチング素子２、ダイオード８を介して、直流電源７の負極に帰還する。この電流経路により、リアクトル６は励磁動作となり、リアクトル電流ｉＬは正極へ増加する。 Thereafter, when the gate-source voltage VgsL becomes zero, the current ig flowing into the input capacitor 10 also becomes zero, and the diode 8 becomes conductive. As a result, the current path is not shown, but flows from the positive electrode of the DC power supply 7 to the reactor 6 via the third switching element 3 and the second node 12, and passes through the second switching element 2 and the diode 8. To the negative electrode of the DC power source 7. By this current path, the reactor 6 is excited and the reactor current iL increases to the positive electrode.
（５）期間Ｔ５：入力容量１０への電荷注入期間
　この期間Ｔ５では、第２のスイッチング素子２をオフする。その場合、図１５に示すように、リアクトル６はリアクトル電流ｉＬを継続して流すために、電流はリアクトル６から第１のノード１１、入力容量１０、直流電源７の負極に向かって流れ、入力容量１０を充電する。 (5) Period T5: Charge injection period to the input capacitor 10 In this period T5, the second switching element 2 is turned off. In that case, as shown in FIG. 15, since the reactor 6 continuously flows the reactor current iL, the current flows from the reactor 6 toward the first node 11, the input capacitor 10, and the negative electrode of the DC power source 7, Charge the capacity 10.
　この電流経路により、入力容量１０は充電動作となり、ゲートソース間電圧ＶｇｓＬはゼロから電源電圧Ｖｄｃに近づいていく。その後、ゲートソース間電圧ＶｇｓＬが電源電圧Ｖｄｃに達すると、第１のスイッチング素子１の寄生ダイオードが導通する。その場合でもリアクトル６はリアクトル電流ｉＬを継続して流すため、電流経路は図示していないが、リアクトル６から第１のノード１１、第１のスイッチング素子１の寄生ダイオード、第３のスイッチング素子３、第２のノード１２に向かって流れる。すなわち、リアクトル６は還流動作をしている。 The input capacitor 10 is charged by this current path, and the gate-source voltage VgsL approaches the power supply voltage Vdc from zero. Thereafter, when the gate-source voltage VgsL reaches the power supply voltage Vdc, the parasitic diode of the first switching element 1 becomes conductive. Even in that case, since the reactor 6 continuously flows the reactor current iL, the current path is not shown, but the first node 11, the parasitic diode of the first switching element 1, the third switching element 3 from the reactor 6. , And flows toward the second node 12. That is, the reactor 6 is performing a reflux operation.
（６）期間Ｔ６：リアクトル６への還流期間
　この期間Ｔ６では、第１のスイッチング素子１をオンする。この場合もリアクトル６はリアクトル電流ｉＬを継続して流すため、図１６に示すように、電流はリアクトル６から第１のノード１１、第１のスイッチング素子１、第３のスイッチング素子３、第２のノード１２に向かって流れる。すなわち、リアクトル６は還流動作を継続しているので、リアクトル電流ｉＬの値は変化しない。 (6) Period T6: Return Period to Reactor 6 In this period T6, the first switching element 1 is turned on. Also in this case, since the reactor 6 continuously flows the reactor current iL, the current flows from the reactor 6 to the first node 11, the first switching element 1, the third switching element 3, and the second as shown in FIG. It flows toward the node 12. That is, since the reactor 6 continues the reflux operation, the value of the reactor current iL does not change.
（７）期間Ｔ７：リアクトル６の励磁電流による直流電源７への電力回生期間
　この期間Ｔ７では、第５のスイッチング素子５をオンし、第３のスイッチング素子３をオフにする。この場合もリアクトル６はリアクトル電流ｉＬを継続して流すため、図１７に示すように、電流はリアクトル６から第１のノード１１、第１のスイッチング素子１を介して、直流電源７の正極に流れ込み、さらに直流電源７の負極から第５のスイッチング素子５、および第４のスイッチング素子４の寄生ダイオードを介してリアクトル６に帰還する。
　この電流経路により、リアクトル６の励磁電力は直流電源７に電力回生されるので、リアクトル電流ｉＬは正極から次第にゼロへ近づいていく。 (7) Period T7: Power regeneration period to the DC power source 7 by the exciting current of the reactor 6 In this period T7, the fifth switching element 5 is turned on and the third switching element 3 is turned off. Also in this case, the reactor 6 continuously flows the reactor current iL, so that the current flows from the reactor 6 to the positive electrode of the DC power supply 7 via the first node 11 and the first switching element 1 as shown in FIG. Furthermore, it returns to the reactor 6 from the negative electrode of the DC power source 7 through the fifth switching element 5 and the parasitic diode of the fourth switching element 4.
Due to this current path, the exciting power of the reactor 6 is regenerated to the DC power source 7, so that the reactor current iL gradually approaches zero from the positive electrode.
（８）期間Ｔ８：リアクトル６の励磁電流による直流電源７への電力回生継続期間
　この期間Ｔ８では、第４のスイッチング素子４をオンする。この場合もリアクトル６はリアクトル電流ｉＬを継続して流すため、図１８に示すように、電流はリアクトル６から第１のノード１１、第１のスイッチング素子１を介して直流電源７の正極に流れ込み、さらに、直流電源７の負極から第５のスイッチング素子５、および第４のスイッチング素子４を介してリアクトル６に帰還する。
　この電流経路により、リアクトル６の励磁電力は直流電源７に電力回生されるので、リアクトル電流ｉＬは正極からゼロへ近づいていく。 (8) Period T8: Power regeneration continuation period to the DC power supply 7 by the exciting current of the reactor 6 In this period T8, the fourth switching element 4 is turned on. Also in this case, the reactor 6 continuously flows the reactor current iL, so that the current flows from the reactor 6 to the positive electrode of the DC power supply 7 via the first node 11 and the first switching element 1 as shown in FIG. Further, the feedback is made from the negative electrode of the DC power source 7 to the reactor 6 through the fifth switching element 5 and the fourth switching element 4.
Due to this current path, the exciting power of the reactor 6 is regenerated to the DC power source 7, so that the reactor current iL approaches zero from the positive electrode.
（９）期間Ｔ９：半導体スイッチ９のオン固定継続期間
　この期間Ｔ９では、第５のスイッチング素子５をオフにする。そうすると、図１９に示すように、直流電源７の正極から第１のスイッチング素子１、入力容量１０を介して、直流電源７の負極に帰還する電流経路を形成する。この電流経路により、ゲートソース間電圧ＶｇｓＬは電源電圧Ｖｄｃにクランプされ、半導体スイッチ９はオンを継続する。 (9) Period T9: On-fixing continuation period of semiconductor switch 9 In this period T9, the fifth switching element 5 is turned off. Then, as shown in FIG. 19, a current path that returns from the positive electrode of the DC power source 7 to the negative electrode of the DC power source 7 through the first switching element 1 and the input capacitor 10 is formed. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
　以上のように、ゲート駆動回路１００を動作させることで、半導体スイッチ９のオフ固定継続期間Ｔ３に、ゲートソース間電圧ＶｇｓＬを負の電圧値のまま保持することが可能となる。その後、半導体スイッチ９のターンオン期間（期間Ｔ４～期間Ｔ９）に、入力容量１０と第１のコンデンサ２１の蓄積電荷はリアクトル６に電力回生されるので、実施の形態１と比べてゲート駆動回路１００の損失の低減が可能となり、小型なゲート駆動回路１００を得ることができる。 As described above, by operating the gate driving circuit 100, the gate-source voltage VgsL can be held at a negative voltage value during the off-fixed duration T3 of the semiconductor switch 9. Thereafter, during the turn-on period of the semiconductor switch 9 (period T4 to period T9), the charge stored in the input capacitor 10 and the first capacitor 21 is regenerated in the reactor 6, so that the gate drive circuit 100 is compared with the first embodiment. Loss can be reduced, and a small gate driving circuit 100 can be obtained.
　ここで、実施の形態２で説明した半導体スイッチ９のターンオン期間を、実施の形態１の期間Ｔ３の途中になるように設定したと仮定すると、ゲートソース間電圧ＶｇｓＬが負の電圧値にあるので、入力容量１０の蓄積電荷Ｃｉｓｓを半導体スイッチ９のターンオン期間に電力回生することができる。 Here, assuming that the turn-on period of the semiconductor switch 9 described in the second embodiment is set to be in the middle of the period T3 in the first embodiment, the gate-source voltage VgsL has a negative voltage value. The accumulated charge Ciss of the input capacitor 10 can be regenerated during the turn-on period of the semiconductor switch 9.
　しかしながら、実施の形態１では、半導体スイッチ９のオフ固定継続期間Ｔ３にゲートソース間電圧ＶｇｓＬを負の電圧値に保持することができない。つまり、オフ固定継続期間Ｔ３の終りにはゲートソース間電圧ＶｇｓＬは最終的にゼロになる。これに対して、この実施の形態２では、オフ固定継続期間Ｔ３に、ゲートソース間電圧ＶｇｓＬを負の電圧値に確実に保持することができる。その結果、負電圧印加期間が実施の形態１より増えるので、半導体スイッチ９に直列接続される図示しない高電圧側アームの半導体スイッチのターンオンタイミング設定を容易化できるメリットがある。 However, in the first embodiment, the gate-source voltage VgsL cannot be held at a negative voltage value during the fixed off duration T3 of the semiconductor switch 9. That is, the gate-source voltage VgsL finally becomes zero at the end of the OFF fixed duration T3. On the other hand, in the second embodiment, the gate-source voltage VgsL can be reliably held at a negative voltage value during the off-fixed duration T3. As a result, the negative voltage application period is increased from that in the first embodiment, and there is an advantage that the turn-on timing setting of the semiconductor switch of the high-voltage side arm (not shown) connected in series to the semiconductor switch 9 can be facilitated.
　ここで、前記の期間Ｔ４で説明した予め定めた期間ｔｃを、第１のコンデンサ２１の印加電圧がゼロになるように設定したと仮定する。この印加電圧がゼロに達するまで、リアクトル６に電流を流すことができるので、第１のコンデンサ２１に並列接続されている入力容量１０の蓄積電荷Ｃｉｓｓを、効率良くリアクトル６へ電力回生することが可能になる。 Here, it is assumed that the predetermined period tc described in the period T4 is set so that the voltage applied to the first capacitor 21 becomes zero. Until this applied voltage reaches zero, a current can flow through the reactor 6, so that the accumulated charge Ciss of the input capacitor 10 connected in parallel to the first capacitor 21 can be efficiently regenerated into the reactor 6. It becomes possible.
　半導体スイッチ９のオフ固定時は、半導体スイッチ９のゲート端子から見て、入力容量１０と第１のコンデンサ２１は並列に接続される。すなわち、半導体スイッチ９の入力容量を増加することができる。そのため、実施の形態１で説明したように、半導体スイッチ９の誤動作の抑制が可能となることは言うまでもない。 When the semiconductor switch 9 is fixed to OFF, the input capacitor 10 and the first capacitor 21 are connected in parallel when viewed from the gate terminal of the semiconductor switch 9. That is, the input capacity of the semiconductor switch 9 can be increased. Therefore, it goes without saying that the malfunction of the semiconductor switch 9 can be suppressed as described in the first embodiment.
　また、第４のスイッチング素子４の駆動信号Ｑ４と第５のスイッチング素子５の駆動信号Ｑ５とは、図９、図１０に示したように互いに異なる信号に設定している。このようにすれば、第４、第５の各スイッチング素子４、５がオンするタイミングを互いにずらすことができるので、過電流故障を低減する機能を有する。 Also, the drive signal Q4 of the fourth switching element 4 and the drive signal Q5 of the fifth switching element 5 are set to different signals as shown in FIGS. In this way, the timings at which the fourth and fifth switching elements 4 and 5 are turned on can be shifted from each other, so that a function of reducing overcurrent failure is provided.
　図２０は図８に示したゲート駆動回路の変形例を示すもので、図８と対応もしくは相当する構成部分には同一の符号を付す。 FIG. 20 shows a modification of the gate drive circuit shown in FIG. 8, and the same reference numerals are given to components corresponding to or corresponding to FIG.
　図２０に示す構成のゲート駆動回路１００において、図８の構成と異なる点は、半導体スイッチ９のゲート端子およびソース端子の間に第２のコンデンサ２２が並列接続されている。また、半導体スイッチ９のゲート端子に第１のツェナーダイオード３１のカソード端子が接続され、半導体スイッチ９のソース端子に第２のツェナーダイオード３２のカソード端子が接続されている。さらに、第１のツェナーダイオード３１のアノード端子と第２のツェナーダイオード３２のアノード端子とが互いに接続されている。また、第１のスイッチング素子１と第１のノード１１との間に第１の抵抗（Ｒｏｎ）４１が接続され、第２のスイッチング素子２と第１のノード１１との間に第２の抵抗（Ｒｏｆｆ）４２が接続されている。 20 differs from the configuration of FIG. 8 in that the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the semiconductor switch 9. The cathode terminal of the first Zener diode 31 is connected to the gate terminal of the semiconductor switch 9, and the cathode terminal of the second Zener diode 32 is connected to the source terminal of the semiconductor switch 9. Further, the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other. A first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistor is connected between the second switching element 2 and the first node 11. (Roff) 42 is connected.
　なお、図２０において、第２のコンデンサ２２、第１、第２のツェナーダイオード３１、３２、および第１、第２の抵抗４１、４２をそれぞれ設けたことによる作用効果は、実施の形態１と同様であるので、ここでは詳しい説明を省略する。また、図２０に示したゲート駆動回路１００におけるその他の構成および作用効果は、図８に示した構成の場合と同様であるから、ここでは詳しい説明は省略する。 In FIG. 20, the operational effect obtained by providing the second capacitor 22, the first and second Zener diodes 31, 32, and the first and second resistors 41, 42 is the same as that of the first embodiment. Since it is similar, detailed description is omitted here. 20 is the same as that of the configuration shown in FIG. 8, and thus detailed description thereof is omitted here.
実施の形態３．
　図２１は、この発明の実施の形態３におけるゲート駆動回路の構成を示す回路図であり、図１に示した構成と対応もしくは相当する構成部分には同一の符号を付す。 Embodiment 3 FIG.
FIG. 21 is a circuit diagram showing the configuration of the gate drive circuit according to the third embodiment of the present invention, and components corresponding to or corresponding to the configuration shown in FIG.
　図２１に示す構成のゲート駆動回路１００は、実施の形態１で説明した図１の回路構成に対して、半導体スイッチ９に直列接続された対となる半導体スイッチ６０と、その接続点に結線される誘導性負荷７０とが追加して設けられている。 The gate drive circuit 100 having the configuration shown in FIG. 21 is connected to a pair of semiconductor switches 60 connected in series to the semiconductor switch 9 and the connection point thereof with respect to the circuit configuration of FIG. 1 described in the first embodiment. An inductive load 70 is additionally provided.
　この実施の形態３では、低電圧側アームとなる半導体スイッチを第１の半導体スイッチ９と、これと対になる高電圧側アームとなる半導体スイッチを第２の半導体スイッチ６０とした場合に、第２の半導体スイッチ６０がターンオンしたときに、第１の半導体スイッチ９をセルフターンオンさせることで、第２の半導体スイッチ６０のスイッチング損失を増加させることなく、リカバリサージ電圧を低減するものである。以下、その内容について具体的に説明する。 In the third embodiment, when the semiconductor switch serving as the low-voltage side arm is the first semiconductor switch 9 and the semiconductor switch serving as the high-voltage side arm paired therewith is the second semiconductor switch 60, By turning on the first semiconductor switch 9 when the second semiconductor switch 60 is turned on, the recovery surge voltage is reduced without increasing the switching loss of the second semiconductor switch 60. The contents will be specifically described below.
　ここでは、第２の半導体スイッチ６０のドレイン端子－ソース端子間に印加される電圧（以下、第２のドレインソース間電圧と称す）をＶｄｓＨ、第１の半導体スイッチ９のドレイン端子－ソース端子間に印加される電圧（以下、第１のドレインソース間電圧と称す）をＶｄｓＬとする。 Here, the voltage applied between the drain terminal and the source terminal of the second semiconductor switch 60 (hereinafter referred to as the second drain-source voltage) is VdsH, and the voltage between the drain terminal and the source terminal of the first semiconductor switch 9 A voltage applied to (hereinafter referred to as a first drain-source voltage) is VdsL.
　図２２は、駆動制御対象となる第１、第２の半導体スイッチ９、６０のオン・オフ動作に伴うゲート駆動回路１００の第１～第４の各スイッチング素子１～４の動作を示すタイミングチャートである。なお、ここでは、駆動制御対象となる第１の半導体スイッチ９がターンオフするのを期間Ｔ１から期間Ｔ３までの期間内とし、第１の半導体スイッチ９がターンオンするのを期間Ｔ４から期間Ｔ６までの期間内とする。以下、上記の各期間Ｔ１～Ｔ６の６期間を次のように定義する。 FIG. 22 is a timing chart showing the operation of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 in accordance with the on / off operation of the first and second semiconductor switches 9 and 60 to be driven and controlled. It is. Here, the first semiconductor switch 9 to be driven and controlled is turned off within the period from the period T1 to the period T3, and the first semiconductor switch 9 is turned on from the period T4 to the period T6. Within the period. Hereinafter, the six periods T1 to T6 are defined as follows.
（１）期間Ｔ１：リアクトル６の励磁期間
（２）期間Ｔ２：第１の半導体スイッチ９のセルフターンオンの発生期間
（３）期間Ｔ３：第１の半導体スイッチ９のオフ固定継続期間
（４）期間Ｔ４：リアクトル６の励磁期間
（５）期間Ｔ５：第１の半導体スイッチ９のゲートへの正電圧印加期間
（６）期間Ｔ６：第１の半導体スイッチ９のオン固定継続期間 (1) Period T1: Excitation period of the reactor 6 (2) Period T2: Generation period of self-turn-on of the first semiconductor switch 9 (3) Period T3: Fixed off duration of the first semiconductor switch 9 (4) period T4: Reactor 6 excitation period (5) period T5: Positive voltage application period to the gate of the first semiconductor switch 9 (6) period T6: On-fixed duration of the first semiconductor switch 9
　図２３は、図２２に基づく第１～第４のスイッチング素子１～４の動作に伴う各部の電流、電圧の変化を示す動作波形図である。また、図２４～図２６は上記の動作期間Ｔ１～Ｔ３での電流経路を示す。以下、図２３～図２６を用いて動作原理を説明する。 FIG. 23 is an operation waveform diagram showing changes in current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG. 24 to 26 show current paths in the operation periods T1 to T3. Hereinafter, the principle of operation will be described with reference to FIGS.
（１）期間Ｔ１：リアクトル６の励磁期間
　この期間Ｔ１では、第１の半導体スイッチ９がオン固定している状態から、第１のスイッチング素子１をオフし、第４のスイッチング素子４を予め定めた時間だけオンする。この予め定めた時間は、第２の半導体スイッチ６０がターンオンによって第１の半導体スイッチ９がセルフターンオンさせるように設定する。 (1) Period T1: Excitation period of the reactor 6 In this period T1, the first switching element 1 is turned off and the fourth switching element 4 is determined in advance from the state where the first semiconductor switch 9 is fixed on. It turns on only for the time. The predetermined time is set such that the first semiconductor switch 9 is turned on by turning on the second semiconductor switch 60.
　そうすると、図２４に示すように、電流は入力容量１０から第１のノード１１に流れ込み、リアクトル６、第２のノード１２を介して第４のスイッチング素子４に流れ込み、入力容量１０に帰還する電流経路を形成する。この電流経路により、リアクトル６と入力容量１０の間で共振動作となり、ゲートソース間電圧ＶｇｓＬは電源電圧Ｖｄｃから減少し、入力容量１０に流れる電流ｉｇはゼロから負極に増加する。 Then, as shown in FIG. 24, the current flows from the input capacitor 10 to the first node 11, flows into the fourth switching element 4 via the reactor 6 and the second node 12, and returns to the input capacitor 10. Form a pathway. Due to this current path, a resonant operation occurs between the reactor 6 and the input capacitor 10, the gate-source voltage VgsL decreases from the power supply voltage Vdc, and the current ig flowing through the input capacitor 10 increases from zero to the negative electrode.
（２）期間Ｔ２：第１の半導体スイッチ９のセルフターンオン期間
　この期間Ｔ２では、第４のスイッチング素子４をオフし、予め定めた時間だけ第２のスイッチング素子２をオフする。この予め定めた時間は、ゲートソース間電圧ＶｇｓＬがゼロ以下と設定する。そうすると、図２５に示すように、リアクトル６によってリアクトル電流ｉＬは継続して流れるため、第３のスイッチング素子３の寄生ダイオードが導通する。その結果、電流は直流電源７に流れ込み、入力容量１０に帰還する。ゲートソース間電圧ＶｇｓＬは、電流が直流電源７の負極から入力容量１０へ流れ込むことで、負極に増加する。しかし、前記の期間Ｔ１で、半導体スイッチ９がこの期間にセルフターンオンするように設定しているので、ゲートソース間電圧ＶｇｓＬの値は、実施の形態１および実施の形態２で説明したゲートソース間電圧ＶｇｓＬの値と比べてゼロに近い。 (2) Period T2: Self-turn-on period of the first semiconductor switch 9 In this period T2, the fourth switching element 4 is turned off, and the second switching element 2 is turned off for a predetermined time. During this predetermined time, the gate-source voltage VgsL is set to zero or less. Then, as shown in FIG. 25, the reactor current iL continuously flows through the reactor 6, so that the parasitic diode of the third switching element 3 becomes conductive. As a result, the current flows into the DC power source 7 and returns to the input capacitor 10. The gate-source voltage VgsL increases to the negative electrode when current flows from the negative electrode of the DC power supply 7 to the input capacitor 10. However, since the semiconductor switch 9 is set to self-turn on during this period T1, the value of the gate-source voltage VgsL is the same between the gate and source described in the first and second embodiments. It is close to zero compared to the value of the voltage VgsL.
　第１の半導体スイッチ９がオンからオフへ切り替わり、対となる第２の半導体スイッチ６０がオフからオンに切り替わった後に、第１の半導体スイッチ９はセルフターンオンする。これは、ドレインソース間電圧ＶｄｓＬが上昇することで、ゲートソース間電圧ＶｇｓＬが持ち上がったことに起因する。このセルフターンオンによって、第１の半導体スイッチ９のドレイン端子からソース端子へ電流ｉｄＬが流れることで、図２３のドレインソース間電圧ＶｄｓＬに関して斜線部で示したように、半導体スイッチ９のリカバリサージ電圧Ｖｒｓが低減する。 After the first semiconductor switch 9 is switched from on to off and the paired second semiconductor switch 60 is switched from off to on, the first semiconductor switch 9 is self-turned on. This is because the gate-source voltage VgsL is increased by increasing the drain-source voltage VdsL. With this self-turn-on, a current idL flows from the drain terminal to the source terminal of the first semiconductor switch 9, so that the recovery surge voltage Vrs of the semiconductor switch 9 is indicated by the hatched portion with respect to the drain-source voltage VdsL in FIG. Is reduced.
（３）期間Ｔ３：第１の半導体スイッチ９のオフ固定継続期間
　この期間Ｔ３では、第２のスイッチング素子２をオンする。その場合、ゲートソース間電圧ＶｇｓＬが正電圧であるため、ダイオード８が導通する。そうすると、図２６に示すように、電流は入力容量１０から第１のノード１１に流れ込み、第２のスイッチング素子２とダイオード８を介して、入力容量１０に帰還する。その際、第２のスイッチング素子２がオンしているので、ダイオード８により第１の半導体スイッチ９のゲートソース間電圧ＶｇｓＬはゼロにクランプされてオフを継続する。 (3) Period T3: OFF fixed continuation period of the first semiconductor switch 9 In this period T3, the second switching element 2 is turned on. In that case, since the gate-source voltage VgsL is a positive voltage, the diode 8 becomes conductive. Then, as shown in FIG. 26, the current flows from the input capacitor 10 to the first node 11 and returns to the input capacitor 10 via the second switching element 2 and the diode 8. At this time, since the second switching element 2 is turned on, the gate-source voltage VgsL of the first semiconductor switch 9 is clamped to zero by the diode 8 and continues to be turned off.
（４）期間Ｔ４：リアクトル６の励磁期間
　この期間Ｔ４では、第３のスイッチング素子３をオンする。その結果、電流は直流電源７の正極から第３のスイッチング素子３を介して第２のノード１２に流れ込む。続いて、第２のノード１２からリアクトル６を介して第１のノード１１に流れ込む。その後、第１のノード１１から第２のスイッチング素子２を介してダイオード８のカソードに流れ、直流電源７の負極に帰還する。この電流経路によりリアクトル６は励磁される。 (4) Period T4: Excitation period of the reactor 6 In this period T4, the third switching element 3 is turned on. As a result, the current flows from the positive electrode of the DC power supply 7 to the second node 12 via the third switching element 3. Subsequently, the second node 12 flows into the first node 11 through the reactor 6. Thereafter, the current flows from the first node 11 to the cathode of the diode 8 via the second switching element 2 and returns to the negative electrode of the DC power supply 7. The reactor 6 is excited by this current path.
（５）期間Ｔ５：第１の半導体スイッチ９のゲートへの正電圧印加期間
　この期間Ｔ５では、第２のスイッチング素子２をオフする。この場合、リアクトル６によって電流は継続して流れるので、入力容量１０が充電される。その結果、ゲートソース間電圧ＶｇｓＬは正極に増加する。 (5) Period T5: Positive voltage application period to the gate of the first semiconductor switch 9 In this period T5, the second switching element 2 is turned off. In this case, since the current continuously flows through the reactor 6, the input capacitor 10 is charged. As a result, the gate-source voltage VgsL increases to the positive electrode.
（６）期間Ｔ６：第１の半導体スイッチ９のオン固定継続期間
　この期間Ｔ６では、第１のスイッチング素子１をオンする。そうすると、電流は直流電源７の正極から第１のスイッチング素子１、および入力容量１０を介して直流電源７の負極に帰還する経路を形成する。この電流経路により、ゲートソース間電圧ＶｇｓＬは電源電圧Ｖｄｃにクランプされ、半導体スイッチ９はオンを継続する。 (6) Period T6: On-fixing continuation period of the first semiconductor switch 9 In this period T6, the first switching element 1 is turned on. Then, a path is formed in which the current returns from the positive electrode of the DC power supply 7 to the negative electrode of the DC power supply 7 via the first switching element 1 and the input capacitor 10. By this current path, the gate-source voltage VgsL is clamped to the power supply voltage Vdc, and the semiconductor switch 9 is kept on.
　リカバリサージ電圧Ｖｒｓを低減する手段としては、対となる第２の半導体スイッチ６０のターンオン時間を遅くすることが一般的であるが、第２の半導体スイッチ６０のスイッチング損失が増加する。これに対して、この実施の形態３では、上記の動作原理で説明したとおり、第２の半導体スイッチ６０のターンオン時に、第１の半導体スイッチ９をセルフターンオンさせることで、第２の半導体スイッチ６０のスイッチング損失を増加させることなく、リカバリサージ電圧Ｖｒｓの低減が可能になる。したがって、第１の半導体スイッチ９の過電圧による故障発生を抑制しつつ、対となる第２の半導体スイッチ６０の損失を同時に低減する効果が得られる。 As a means for reducing the recovery surge voltage Vrs, the turn-on time of the paired second semiconductor switch 60 is generally delayed, but the switching loss of the second semiconductor switch 60 increases. On the other hand, in the third embodiment, as described in the above operating principle, the second semiconductor switch 60 is turned on by self-turning on the first semiconductor switch 9 when the second semiconductor switch 60 is turned on. The recovery surge voltage Vrs can be reduced without increasing the switching loss. Therefore, the effect of simultaneously reducing the loss of the paired second semiconductor switch 60 while suppressing the occurrence of a failure due to the overvoltage of the first semiconductor switch 9 can be obtained.
　なお、ここでは、ゲート駆動回路１００の回路構成として、実施の形態１（図１）と同じ構成のものを用いた例について示したが、実施の形態２で説明した図８を用いてもよいことは言うまでもない。 Note that although an example in which the same configuration as that of the first embodiment (FIG. 1) is used as the circuit configuration of the gate drive circuit 100 is shown here, FIG. 8 described in the second embodiment may be used. Needless to say.
　図２７は、図２１に示した構成の変形例を示すゲート駆動回路１００であり、図２１と対応もしくは相当する構成部分には同一の符号を付す。 FIG. 27 shows a gate drive circuit 100 showing a modified example of the configuration shown in FIG. 21. Components corresponding to or corresponding to those in FIG. 21 are denoted by the same reference numerals.
　図２７に示す構成のゲート駆動回路１００において、図２１の構成と異なる点は、第１の半導体スイッチ９のゲート端子およびソース端子の間に第２のコンデンサ２２が並列接続されている。また、第１の半導体スイッチ９のゲート端子に第１のツェナーダイオード３１のカソード端子が接続されている。また、第１の半導体スイッチ９のソース端子に第２のツェナーダイオード３２のカソード端子が接続されている。さらに、第１のツェナーダイオード３１のアノード端子と第２のツェナーダイオード３２のアノード端子とが互いに接続されている。また、第１のスイッチング素子１と第１のノード１１との間に第１の抵抗（Ｒｏｎ）４１が接続され、また第２のスイッチング素子２と第１のノード１１との間に第２の抵抗（Ｒｏｆｆ）４２が接続されている。 27 is different from the configuration of FIG. 21 in that the second capacitor 22 is connected in parallel between the gate terminal and the source terminal of the first semiconductor switch 9. The cathode terminal of the first Zener diode 31 is connected to the gate terminal of the first semiconductor switch 9. The cathode terminal of the second Zener diode 32 is connected to the source terminal of the first semiconductor switch 9. Further, the anode terminal of the first Zener diode 31 and the anode terminal of the second Zener diode 32 are connected to each other. In addition, a first resistor (Ron) 41 is connected between the first switching element 1 and the first node 11, and a second resistance is connected between the second switching element 2 and the first node 11. A resistor (Roff) 42 is connected.
　なお、図２７の構成において、第２のコンデンサ２２、第１、第２のツェナーダイオード３１、３２、および第１、第２の抵抗４１、４２をそれぞれ設けたことによる作用効果は、実施の形態１と同様であるので、ここでは詳しい説明を省略する。また、図２７に示したゲート駆動回路１００におけるその他の構成および作用効果は、図２１に示した構成の場合と同様であるから、ここでは詳しい説明は省略する。 In the configuration of FIG. 27, the operational effects obtained by providing the second capacitor 22, the first and second Zener diodes 31, 32, and the first and second resistors 41, 42 are the same as those in the embodiment. Since it is the same as 1, the detailed description is omitted here. 27 is the same as that of the configuration shown in FIG. 21, and thus the detailed description thereof is omitted here.
実施の形態４．
　実施の形態４では、実施の形態１の期間Ｔ１に、第１のスイッチング素子１をオンする期間を追加することで、半導体スイッチ９のターンオフ損失を実施の形態１より低減させるものである。以下、その内容について具体的に説明する。 Embodiment 4 FIG.
In the fourth embodiment, the turn-off loss of the semiconductor switch 9 is reduced compared to the first embodiment by adding a period during which the first switching element 1 is turned on to the period T1 in the first embodiment. The contents will be specifically described below.
　この実施の形態４のゲート駆動回路１００は、実施の形態１（図１）の回路構成と同様であるから、詳しい説明は省略する。 Since the gate drive circuit 100 of the fourth embodiment is the same as the circuit configuration of the first embodiment (FIG. 1), detailed description is omitted.
　図２８は、駆動制御対象となる半導体スイッチ９のターンオフ動作に伴うゲート駆動回路１００の第１～第４のスイッチング素子１～４の動作を示すタイミングチャートである。ここでは駆動制御対象となる半導体スイッチ９がターンオフするのを期間Ｔ１から期間Ｔ４までの期間で説明する。半導体スイッチ９がターンオンする期間内の動作は実施の形態１と同様であるから、詳しい説明は省略する。以下、上記の期間Ｔ１から期間Ｔ４までの４期間を次のように定義する。 FIG. 28 is a timing chart showing the operations of the first to fourth switching elements 1 to 4 of the gate drive circuit 100 accompanying the turn-off operation of the semiconductor switch 9 to be driven. Here, the turn-off of the semiconductor switch 9 to be driven and controlled will be described in the period from the period T1 to the period T4. Since the operation within the period when the semiconductor switch 9 is turned on is the same as that of the first embodiment, the detailed description is omitted. Hereinafter, the four periods from the period T1 to the period T4 are defined as follows.
（１）期間Ｔ１：リアクトル６の初期励磁期間
（２）期間Ｔ２：リアクトル６の励磁期間
（３）期間Ｔ３：入力容量１０の蓄積電荷Ｃｉｓｓの電力回生期間および半導体スイッチ９のゲートへの負電圧印加期間
（４）期間Ｔ４：半導体スイッチ９のオフ固定継続期間 (1) Period T1: Initial excitation period of the reactor 6 (2) Period T2: Excitation period of the reactor 6 (3) Period T3: Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage to the gate of the semiconductor switch 9 Application period (4) period T4: OFF fixed continuation period of the semiconductor switch 9
　図２９の実線は、図２８に基づく第１～第４のスイッチング素子１～４の動作に伴う各部の電流、電圧の変化を示す動作波形図である。一方、図２９の破線は、実施の形態１（図２）のタイミングチャートに基づく各部の電流、電圧波形図である。さらに、実施の形態１と異なる動作期間Ｔ１の電流経路を図３０に示す。期間Ｔ２から期間Ｔ４の電流経路は実施の形態１（図４～図６）を同様であるから、ここでは詳しい説明は省略する。以下、図２９～図３０を用いて動作原理を説明する。 29 is an operation waveform diagram showing changes in the current and voltage of each part accompanying the operation of the first to fourth switching elements 1 to 4 based on FIG. On the other hand, broken lines in FIG. 29 are current and voltage waveform diagrams of the respective parts based on the timing chart of the first embodiment (FIG. 2). Further, FIG. 30 shows a current path in an operation period T1 different from that in the first embodiment. Since the current path from the period T2 to the period T4 is the same as that in the first embodiment (FIGS. 4 to 6), detailed description is omitted here. Hereinafter, the principle of operation will be described with reference to FIGS.
（１）期間Ｔ１：リアクトル６の初期励磁期間
　この期間Ｔ１では、実施の形態１（図２）と異なり、第１のスイッチング素子１がオンしている状態を継続する。第１のスイッチング素子１がオンを継続する時間は、第４のスイッチング素子４を予め定めた時間ｔａより短く設定する。このとき、図３０に示すように、電流は直流電源７から、第１のノード１１に流れ込み、リアクトル６、第２のノード１２を介して第４のスイッチング素子４に流れ込み、直流電源７に帰還する。 (1) Period T1: Initial Excitation Period of Reactor 6 In this period T1, unlike the first embodiment (FIG. 2), the state where the first switching element 1 is on is continued. The time for which the first switching element 1 is kept on is set to be shorter than the predetermined time ta for the fourth switching element 4. At this time, as shown in FIG. 30, the current flows from the DC power source 7 to the first node 11, flows into the fourth switching element 4 via the reactor 6 and the second node 12, and returns to the DC power source 7. To do.
　この電流経路によってリアクトル電流ｉＬはゼロから負極に増加する。この時、リアクトル６は直流電源７の電源電圧Ｖｄｃによって、初期励磁される。 】 By this current path, the reactor current iL increases from zero to the negative electrode. At this time, the reactor 6 is initially excited by the power supply voltage Vdc of the DC power supply 7.
（２）期間Ｔ２：リアクトル６の励磁期間
　この期間Ｔ２では、第１のスイッチング素子１をオフし、第４のスイッチング素子４は予め定めた時間ｔａだけオンを継続する。そうすると、リアクトル６によってリアクトル電流ｉＬが継続して流れるため、電流は図４に示すように流れる。この時、リアクトル６は初期励磁されているので、図２９に示すとおり実施の形態１のリアクトル電流ｉＬ（破線）より大きい電流値になる。 (2) Period T2: Excitation period of the reactor 6 In this period T2, the first switching element 1 is turned off, and the fourth switching element 4 is kept on for a predetermined time ta. Then, since reactor current iL continuously flows through reactor 6, the current flows as shown in FIG. At this time, since the reactor 6 is initially excited, the current value becomes larger than the reactor current iL (broken line) of the first embodiment as shown in FIG.
（３）期間Ｔ３：入力容量１０の蓄積電荷Ｃｉｓｓの電力回生期間および半導体スイッチ９のゲートへの負電圧印加期間
　この期間Ｔ３では、第４のスイッチング素子４をオフし、予め定めた時間ｔｂだけ第２のスイッチング素子２をオフする。そうすると、電流は図５に示すように流れる。この時、リアクトル６は初期励磁されているので、図２９に示すとおり実施の形態１のリアクトル電流ｉＬ（破線）より大きい電流値になる。 (3) Period T3: Power regeneration period of the accumulated charge Ciss of the input capacitor 10 and negative voltage application period to the gate of the semiconductor switch 9 In this period T3, the fourth switching element 4 is turned off and only for a predetermined time tb. The second switching element 2 is turned off. Then, current flows as shown in FIG. At this time, since the reactor 6 is initially excited, the current value becomes larger than the reactor current iL (broken line) of the first embodiment as shown in FIG.
（４）期間Ｔ４：半導体スイッチ９のオフ固定継続期間
　この期間Ｔ４では、第２のスイッチング素子２をオンする。このとき、電流は図６に示すように流れる。その結果、ゲートソース間電圧ＶｇｓＬは図２９に示すとおり正極に向けて増加されるが、第２のスイッチング素子２がオンしているので、ダイオード８により半導体スイッチ９のゲートソース間電圧ＶｇｓＬはゼロにクランプされて半導体スイッチ９はオフを継続する。 (4) Period T4: Fixed off duration of semiconductor switch 9 In this period T4, the second switching element 2 is turned on. At this time, current flows as shown in FIG. As a result, the gate-source voltage VgsL increases toward the positive electrode as shown in FIG. 29. However, since the second switching element 2 is on, the gate-source voltage VgsL of the semiconductor switch 9 is zero by the diode 8. The semiconductor switch 9 continues to be turned off.
　ドレイン電流ｉｄＬ、ドレインソース間電圧ＶｄｓＬの時間積で決まるターンオフ損失を低減するには、半導体スイッチ９の入力容量を放電させる電流、すなわちリアクトル電流ｉＬの電流値を大きくする必要がある。この実施の形態４では、上記の動作原理で説明したとおり、第１のスイッチング素子１と第４のスイッチング素子４を同時オンする期間を設けることで、リアクトル電流ｉＬの電流値を実施の形態１より大きくすることができる。したがって、実施の形態１と比べてターンオフ損失の低減が可能になり、半導体スイッチ９の冷却器を小型化することができる。 In order to reduce the turn-off loss determined by the time product of the drain current idL and the drain-source voltage VdsL, it is necessary to increase the current that discharges the input capacitance of the semiconductor switch 9, that is, the current value of the reactor current iL. In the fourth embodiment, as described in the above operation principle, the current value of the reactor current iL is set to the first embodiment by providing a period during which the first switching element 1 and the fourth switching element 4 are simultaneously turned on. Can be larger. Therefore, the turn-off loss can be reduced as compared with the first embodiment, and the cooler of the semiconductor switch 9 can be downsized.
　なお、ここでは、ゲート駆動回路１００の回路構成として、実施の形態１で説明した図１と同じ構成のものを用いた例について示したが、実施の形態２で説明した図８を用いてもよいことは言うまでもない。 Here, an example in which the circuit configuration of the gate drive circuit 100 is the same as that of FIG. 1 described in the first embodiment is shown, but FIG. 8 described in the second embodiment can also be used. Needless to say, it is good.
　上記の実施の形態１～４においては、低電圧側アームを構成する第１の半導体スイッチ９に上記実施の形態１～４のゲート駆動回路を適用した例を説明したが、高電圧側アームを構成する第２の半導体スイッチ６０に対して、上記実施の形態１～４のゲート駆動回路を適用しても同様の効果が得られることは言うまでもない。 In the first to fourth embodiments, the example in which the gate drive circuit of the first to fourth embodiments is applied to the first semiconductor switch 9 constituting the low voltage side arm has been described. It goes without saying that the same effect can be obtained even if the gate driving circuits of the first to fourth embodiments are applied to the second semiconductor switch 60 to be configured.
　また、この発明は、上記の実施の形態１～４の構成のみに限定されるものではなく、この発明の趣旨を逸脱しない範囲内において、各実施の形態１～４の構成の一部を変更したり、その構成を省略することができ、また、各実施の形態１～４の構成を適宜組み合わせることが可能である。 Further, the present invention is not limited to the configurations of the first to fourth embodiments described above, and some of the configurations of the first to fourth embodiments may be changed without departing from the spirit of the present invention. Or the configuration thereof can be omitted, and the configurations of Embodiments 1 to 4 can be combined as appropriate.
１　第１のスイッチング素子、２　第２のスイッチング素子、３　第３のスイッチング素子、４　第４のスイッチング素子、５　第５のスイッチング素子、６　リアクトル、７　直流電源、８　ダイオード、９　半導体スイッチ（第１の半導体スイッチ）、１１　第１のノード、１２　第２のノード、２１　第１のコンデンサ、２２　第２のコンデンサ、３１　第１のツェナーダイオード、３２　第２のツェナーダイオード、４１　第１の抵抗、４２　第２の抵抗、５０　スイッチング制御回路、６０　第２の半導体スイッチ、７０　誘導性負荷、１００　ゲート駆動回路。 1. 1st switching element, 2nd switching element, 3rd switching element, 4th switching element, 5th switching element, 6 reactor, 7 DC power supply, 8 diode, 9 semiconductor switch 1 semiconductor switch), 11 first node, 12 second node, 21 first capacitor, 22 second capacitor, 31 first Zener diode, 32 second Zener diode, 41 first resistor, 42 second resistor, 50 switching control circuit, 60 second semiconductor switch, 70 inductive load, 100 gate drive circuit.

Claims (14)

  1. 直流電源に対して、第１のスイッチング素子と第２のスイッチング素子からなる直列回路、および第３のスイッチング素子と第４のスイッチング素子からなる直列回路を並列に接続し、
    上記第１のスイッチング素子と上記第２のスイッチング素子との互いの接続点である第１のノードと、上記第３のスイッチング素子と上記第４のスイッチング素子との互いの接続点である第２のノードとの間にリアクトルを接続し、
    上記第１のノードを駆動制御対象となる半導体スイッチのゲート端子に接続し、
    上記第２のスイッチング素子と上記直流電源の負極端子の間にダイオードを接続し、
    上記第１、第２、第３、第４のスイッチング素子のそれぞれのオン・オフ動作を制御するスイッチング制御回路を備えるゲート駆動回路。     A DC circuit is connected in parallel with a series circuit composed of a first switching element and a second switching element, and a series circuit composed of a third switching element and a fourth switching element,
    A first node that is a connection point between the first switching element and the second switching element, and a second node that is a connection point between the third switching element and the fourth switching element. Connect a reactor between the node and
    Connecting the first node to a gate terminal of a semiconductor switch to be driven and controlled;
    A diode is connected between the second switching element and the negative terminal of the DC power supply;
    A gate drive circuit comprising a switching control circuit for controlling the on / off operation of each of the first, second, third, and fourth switching elements.
  2. 上記スイッチング制御回路は、上記半導体スイッチのオン固定時には、上記第１のスイッチング素子を継続的にオン固定とするとともに、上記第２、第３、第４のスイッチング素子は継続的にオフ固定とし、また、上記半導体スイッチのオフ固定時は、上記第２のスイッチング素子を継続的にオン固定とするとともに、上記第１、第３、第４のスイッチング素子は継続的にオフ固定とし、上記半導体スイッチのターンオフ時には、上記半導体スイッチがオン固定になっている状態から上記第４のスイッチング素子を予め定めた時間だけオンして、上記第１のノードから上記第２のノードへ電流を流してリアクトルを励磁した後、上記第４のスイッチング素子をオフしてリアクトルの励磁エネルギを電源側へ電力回生し、上記第４のスイッチング素子がオフになった状態から上記第２のスイッチング素子を予め定めた時間だけオフし、その後に上記第２のスイッチング素子をオン固定することで、上記半導体スイッチをオフ固定させる請求項１に記載のゲート駆動回路。 The switching control circuit continuously fixes the first switching element on when the semiconductor switch is fixed on, and continuously sets the second, third, and fourth switching elements off. Further, when the semiconductor switch is fixed to OFF, the second switching element is continuously fixed to ON, and the first, third, and fourth switching elements are continuously fixed to OFF. When the semiconductor switch is turned off, the fourth switching element is turned on for a predetermined time from the state in which the semiconductor switch is fixed, and a current is passed from the first node to the second node. After the excitation, the fourth switching element is turned off to regenerate the reactor excitation energy to the power source side, and the fourth switching element 2. The semiconductor switch according to claim 1, wherein the second switching element is turned off for a predetermined time from the state in which the element is turned off, and then the second switching element is turned on to fix the semiconductor switch off. Gate drive circuit.
  3. 上記スイッチング制御回路は、上記半導体スイッチがオン固定になっている状態から上記第４のスイッチング素子をオンする予め定めた時間として、上記リアクトルと上記半導体スイッチの入力容量とで決まる共振周期の４分の１より長く、かつ上記共振周期の２分の１より短くなるように設定するとともに、上記第４のスイッチング素子がオフになった状態から上記第２のスイッチング素子をオフする予め定めた時間として、上記半導体スイッチのゲート端子―ソース端子間電圧がゼロ以下の期間に設定する請求項２に記載のゲート駆動回路。 The switching control circuit has a resonance period of four minutes determined by the reactor and the input capacitance of the semiconductor switch as a predetermined time for turning on the fourth switching element from a state where the semiconductor switch is fixed on. Is set to be longer than 1 and shorter than half of the resonance period, and a predetermined time for turning off the second switching element from a state in which the fourth switching element is turned off. 3. The gate drive circuit according to claim 2, wherein a voltage between the gate terminal and the source terminal of the semiconductor switch is set to a period of zero or less.
  4. 上記第４のスイッチング素子と上記直流電源の負極端子の間に第５のスイッチング素子を直列接続するとともに、上記ダイオードに並列に第１のコンデンサを並列接続すると共に、
    上記スイッチング制御回路は、上記半導体スイッチのターンオン時において、上記半導体スイッチがオフ固定になっている状態から上記第２のスイッチング素子および上記第３のスイッチング素子を予め定めた時間だけオンして上記第２のノードから上記第１のノードへ電流を流して上記リアクトルを励磁した後、上記第２のスイッチング素子をオフして上記半導体スイッチの入力容量を充電し、次に上記第５のスイッチング素子をオンするとともに上記第３のスイッチング素子をオフして上記リアクトルの励磁電流を上記直流電源に電力回生し、その後に上記第１のスイッチング素子をオン固定することで上記半導体スイッチをオン固定させる請求項２または請求項３に記載のゲート駆動回路。     A fifth switching element is connected in series between the fourth switching element and the negative terminal of the DC power supply, and a first capacitor is connected in parallel to the diode.
    When the semiconductor switch is turned on, the switching control circuit turns on the second switching element and the third switching element for a predetermined time from a state in which the semiconductor switch is fixed to be off. After the current is passed from the second node to the first node to excite the reactor, the second switching element is turned off to charge the input capacitance of the semiconductor switch, and then the fifth switching element is turned on. The semiconductor switch is fixed on by turning on and turning off the third switching element to regenerate the exciting current of the reactor to the DC power supply, and then fixing the first switching element on. The gate drive circuit according to claim 2 or claim 3.
  5. 上記スイッチング制御回路は、上記半導体スイッチがオフ固定になっている状態から上記第２のスイッチング素子および上記第３のスイッチング素子をオンする予め定めた時間として、上記第１のコンデンサの印加電圧がゼロになるように設定する請求項４に記載のゲート駆動回路。 In the switching control circuit, the voltage applied to the first capacitor is zero as a predetermined time for turning on the second switching element and the third switching element from a state in which the semiconductor switch is fixed off. The gate drive circuit according to claim 4, wherein the gate drive circuit is set to be
  6. 上記スイッチング制御回路は、上記第４のスイッチング素子の駆動信号と上記第５のスイッチング素子の駆動信号とを互いに異なる信号に設定する請求項４または請求項５に記載のゲート駆動回路。 6. The gate drive circuit according to claim 4, wherein the switching control circuit sets the drive signal for the fourth switching element and the drive signal for the fifth switching element to different signals.
  7. 上記半導体スイッチのゲート端子－ソース端子間に対して、第２のコンデンサを並列接続している請求項１から請求項６のいずれか１項に記載のゲート駆動回路。 The gate drive circuit according to any one of claims 1 to 6, wherein a second capacitor is connected in parallel between the gate terminal and the source terminal of the semiconductor switch.
  8. 上記半導体スイッチのゲート端子に第１のツェナーダイオードのカソード端子を接続し、上記半導体スイッチのソース端子に第２のツェナーダイオードのカソード端子を接続し、上記第１のツェナーダイオードのアノード端子と上記第２のツェナーダイオードのアノード端子を接続し、かつ、上記第１のツェナーダイオードと上記第２のツェナーダイオードの各ツェナー電圧を互いに異なる値に設定している請求項１から請求項７のいずれか１項に記載のゲート駆動回路。 The cathode terminal of the first Zener diode is connected to the gate terminal of the semiconductor switch, the cathode terminal of the second Zener diode is connected to the source terminal of the semiconductor switch, and the anode terminal of the first Zener diode and the first terminal are connected. The anode terminal of two Zener diodes is connected, and the Zener voltages of the first Zener diode and the second Zener diode are set to different values. The gate drive circuit according to Item.
  9. 上記第１のスイッチング素子と上記第１のノードとの間に第１の抵抗を接続し、上記第２のスイッチング素子と上記第１のノードとの間に第２の抵抗を接続し、かつ、上記第１の抵抗と上記第２の抵抗の各抵抗値を互いに異なる値に設定している請求項１から請求項８のいずれか１項に記載のゲート駆動回路。 Connecting a first resistor between the first switching element and the first node, connecting a second resistor between the second switching element and the first node; and 9. The gate drive circuit according to claim 1, wherein resistance values of the first resistor and the second resistor are set to different values from each other.
  10. 上記半導体スイッチを第１の半導体スイッチとし、上記第１の半導体スイッチに対して第２の半導体スイッチを直列接続し、かつ上記第１の半導体スイッチと上記第２の半導体スイッチの接続点に誘導性負荷が結線される場合において、
    上記スイッチング制御回路は、上記第１の半導体スイッチがオン固定になっている状態から上記第４のスイッチング素子をオンする予め定めた時間として、上記第２の半導体スイッチのターンオンによって上記第１の半導体スイッチがセルフターンオンするように設定する一方、上記第４のスイッチング素子がオフになった状態から上記第２のスイッチング素子をオフする予め定めた時間として、上記第１の半導体スイッチのゲート端子－ソース端子間電圧がゼロ以下の期間に設定する請求項２、請求項４、請求項５、請求項６のいずれか１項に記載のゲート駆動回路。     The semiconductor switch is a first semiconductor switch, a second semiconductor switch is connected in series to the first semiconductor switch, and an inductive point is formed at a connection point between the first semiconductor switch and the second semiconductor switch. When the load is connected,
    The switching control circuit sets the first semiconductor by turning on the second semiconductor switch as a predetermined time for turning on the fourth switching element from a state in which the first semiconductor switch is fixed on. The gate terminal-source of the first semiconductor switch is set as a predetermined time for turning off the second switching element from the state in which the fourth switching element is turned off while setting the switch to be self-turned on. The gate drive circuit according to any one of claims 2, 4, 5, and 6, wherein a voltage between terminals is set to a period of zero or less.
  11. 上記第１の半導体スイッチのゲート端子－ソース端子間に対して、第２のコンデンサを並列接続している請求項１０に記載のゲート駆動回路。 The gate drive circuit according to claim 10, wherein a second capacitor is connected in parallel between the gate terminal and the source terminal of the first semiconductor switch.
  12. 上記第１の半導体スイッチのゲート端子に第１のツェナーダイオードのカソード端子を接続し、上記第１の半導体スイッチのソース端子に第２のツェナーダイオードのカソード端子を接続し、上記第１のツェナーダイオードのアノード端子と上記第２のツェナーダイオードのアノード端子を接続し、かつ、上記第１のツェナーダイオードと上記第２のツェナーダイオードの各ツェナー電圧を互いに異なる値に設定している請求項１０または請求項１１に記載のゲート駆動回路。 The gate terminal of the first semiconductor switch is connected to the cathode terminal of the first Zener diode, the source terminal of the first semiconductor switch is connected to the cathode terminal of the second Zener diode, and the first Zener diode is connected. The anode terminal of the second Zener diode is connected to the anode terminal of the second Zener diode, and the Zener voltages of the first Zener diode and the second Zener diode are set to different values. Item 12. The gate drive circuit according to Item 11.
  13. 上記第１のスイッチング素子と上記第１のノードとの間に第１の抵抗を接続し、上記第２のスイッチング素子と上記第１のノードとの間に第２の抵抗を接続し、かつ、上記第１の抵抗と上記第２の抵抗の各抵抗値を互いに異なる値に設定している請求項１０から請求項１２のいずれか１項に記載のゲート駆動回路。 Connecting a first resistor between the first switching element and the first node, connecting a second resistor between the second switching element and the first node; and The gate drive circuit according to any one of claims 10 to 12, wherein each resistance value of the first resistor and the second resistor is set to be different from each other.
  14. 上記スイッチング制御回路は、上記第１のスイッチング素子がオン固定になっている状態から、オンを継続する時間を追加し、追加する時間は、上記第４のスイッチング素子をオンする予め定めた時間より短く設定する請求項２から請求項６のいずれか１項に記載のゲート駆動回路。 The switching control circuit adds a time during which the first switching element is turned on from a state in which the first switching element is fixed to be on, and the time to be added is greater than a predetermined time for turning on the fourth switching element. The gate drive circuit according to claim 2, wherein the gate drive circuit is set short.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077462A (en) * 2009-10-02 2011-04-14 Hitachi Ltd Semiconductor drive circuit, and semiconductor device using the same
JP2015119625A (en) * 2013-11-15 2015-06-25 パナソニックＩｐマネジメント株式会社 Drive unit and electric power converter
JP2016040967A (en) * 2014-08-12 2016-03-24 ニチコン株式会社 Gate drive circuit
JP2016123199A (en) * 2014-12-25 2016-07-07 パナソニックＩｐマネジメント株式会社 Driving device and power conversion device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077462A (en) * 2009-10-02 2011-04-14 Hitachi Ltd Semiconductor drive circuit, and semiconductor device using the same
JP2015119625A (en) * 2013-11-15 2015-06-25 パナソニックＩｐマネジメント株式会社 Drive unit and electric power converter
JP2016040967A (en) * 2014-08-12 2016-03-24 ニチコン株式会社 Gate drive circuit
JP2016123199A (en) * 2014-12-25 2016-07-07 パナソニックＩｐマネジメント株式会社 Driving device and power conversion device

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