WO2018209732A1 - 一种像素驱动电路及阵列基板、显示面板 - Google Patents

一种像素驱动电路及阵列基板、显示面板 Download PDF

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Publication number
WO2018209732A1
WO2018209732A1 PCT/CN2017/086230 CN2017086230W WO2018209732A1 WO 2018209732 A1 WO2018209732 A1 WO 2018209732A1 CN 2017086230 W CN2017086230 W CN 2017086230W WO 2018209732 A1 WO2018209732 A1 WO 2018209732A1
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Prior art keywords
pixel electrode
pixel
switches
thin film
driving circuit
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PCT/CN2017/086230
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English (en)
French (fr)
Inventor
磨光阳
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深圳市华星光电技术有限公司
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Priority to US15/541,704 priority Critical patent/US20180330683A1/en
Publication of WO2018209732A1 publication Critical patent/WO2018209732A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display panel technologies, and in particular, to a pixel driving circuit, an array substrate, and a display panel.
  • the frame rate is the number of frames that drive the display screen per second. The larger the frame rate, the more pictures can be displayed per unit time, and the smoother the screen display.
  • the charging time of the switch to the pixel electrode is correspondingly reduced, which may result in insufficient charging of the pixel electrode, resulting in a decrease in the display quality of the display screen, which largely restricts the development of the liquid crystal display panel and application.
  • the inventor of the present application found in the long-term research and development that in the prior art, in order to solve the problem of insufficient charging of the pixel electrode when displaying high frame rate, two technical solutions are generally adopted: one is to reduce the RC by Delay to increase the charging speed, specifically by increasing the thickness of the metal copper layer and the width of the metal copper to reduce the impedance and capacitance to reduce the RC Delay, but this method will increase the cost, and will increase the size of the non-display area of the liquid crystal display panel or the thickness of the liquid crystal display panel; the other is to improve the charging ability of the pixel electrode in the high frame rate scanning period, which can be adopted by The switch of the high carrier mobility material charges the pixel electrode.
  • the application of the current high carrier mobility materials is more difficult in technology and cannot be widely used.
  • the technical problem to be solved by the present application is to provide a pixel driving circuit, an array substrate, and a display panel to speed up the charging process of the pixel electrodes, thereby improving the display quality of the display screen.
  • the pixel driving circuit includes a data line, a scan line, a first pixel electrode, at least two first switches, a second pixel electrode, and at least two second switches; respective input ends of the at least two first switches are connected
  • the data lines, the respective output ends of the at least two first switches are connected to the same one of the first pixel electrodes, and the respective control ends of the at least two first switches are connected to the scan line to speed up the a charging process of the first pixel electrode;
  • the respective control ends of the at least two second switches are connected to the scan line, the input end of the second switch is connected to the data line, and the output end is connected to the second a pixel electrode, an input end of the other second switch is connected to an output end of the second switch to lower a pixel voltage of the second pixel electrode; and the scan line provides a scan signal having a frequency greater than 120 Hz.
  • the array substrate includes a plurality of pixel driving circuits arranged in a matrix; the pixel driving circuit includes: a data line, a scan line, a first pixel electrode, and at least two first switches; and each of the at least two first switches The input ends are connected to the data lines, the respective output ends of the at least two first switches are connected to the same one of the first pixel electrodes, and the respective control ends of the at least two first switches are connected to the scan lines In order to speed up the charging process of the first pixel electrode; wherein the same column of pixel driving circuits share the same data line, the same row of pixel driving circuits share the same scanning line; or the same row of pixel driving circuits share the same In the data line, the same column of pixel driving circuits share the same scanning line.
  • the display panel includes a first substrate, a second substrate, and a liquid crystal layer; the first substrate and/or the second substrate is the array substrate; wherein the liquid crystal layer is located between the first substrate and the second substrate .
  • the pixel driving circuit of the embodiment of the present application includes a data line, a scan line, a first pixel electrode, and at least two first switches; respective inputs of at least two first switches
  • the data lines are connected to the terminals, and the control terminals are connected to the scan lines, and the respective output ends are connected to the same first pixel electrode.
  • the first pixel electrode is charged by the at least two first switches, so that the charging process of the first pixel electrode can be accelerated, and the display quality of the display screen can be improved.
  • FIG. 1 is a circuit diagram of an embodiment of a pixel driving circuit of the present application.
  • Figure 2 is a schematic structural view of the embodiment of Figure 1;
  • FIG. 3 is a schematic structural view of a TFT conductive channel in the embodiment of FIG. 2;
  • 4A is a schematic circuit diagram of another embodiment of a pixel driving circuit of the present application.
  • FIG. 4B is a schematic structural view of the embodiment of FIG. 4A;
  • FIG. 5 is a schematic structural view of an embodiment of an array substrate of the present application.
  • FIG. 6 is a schematic structural view of an embodiment of a display panel of the present application.
  • FIG. 1 is a schematic circuit diagram of an embodiment of a pixel driving circuit of the present application.
  • the embodiment includes a data line Data, a scan line Scan, a first pixel electrode 101, and at least two first switches T1, T2; respective input ends 102, 103 of at least two first switches T1, T2 are connected to the data line Data, The respective output ends 104, 105 of the at least two first switches T1, T2 are connected to the same first pixel electrode 101, and the respective control terminals 106, 107 of the at least two first switches T1, T2 are connected to the scan line Scan to speed up The charging process of the first pixel electrode 101.
  • the frame rate of the screen display is also getting larger and larger, the pixel scanning signal period is getting smaller and smaller, and the scanning signal of the pixel is continuously driven for less and less time.
  • the charging time of the pixel electrode is also shorter and shorter, which easily leads to insufficient charging of the pixel electrode, thereby causing the display quality of the display screen to be degraded or even not displayed properly.
  • the number of the first switches T1 and T2 connected to the first pixel electrode 101 is increased to speed up the charging process of the first pixel electrode 101.
  • the more the number of the first switches T1 and T2 the charging of the first pixel electrode 101.
  • the faster the process the better the problem of insufficient charging of the first pixel electrode 101 can be solved, thereby adapting to the trend of increasing frame rate of the picture display.
  • the respective input ends 102, 103 of the at least two first switches T1, T2 are connected to the data line Data, and the respective output ends 104, 105 of the at least two first switches T1, T2 are connected.
  • the same first pixel electrode 101, the respective control terminals 106, 107 of the at least two first switches T1, T2 are connected to the scan line Scan, and driven by the scan signal provided by the scan line Scan, so as to be connected to the first pixel electrode 101.
  • At least two of the first switches T1 and T2 charge the first pixel electrode 101, which can speed up the charging process of the first pixel electrode 101, thereby improving the display quality of the display screen.
  • the respective input ends of the at least two first switches T1 and T2 of the embodiment are connected to the same data line Data, and the respective control ends of the at least two first switches T1 and T2 are connected to the same scan line Scan, so that At least two first switches T1, T2 simultaneously charge the first pixel electrode 101 to maximize the charging process.
  • each of the first switches of the implementation is a TFT.
  • the control end of the first switch is the gate of the TFT, the input end is the source of the TFT, and the output end is the drain of the TFT.
  • the input end of the first switch is the drain of the TFT.
  • the output is the source of the TFT.
  • the first switch may also be another electronic component having a switching function, such as a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), etc.
  • CMOS complementary Metal Oxide Semiconductor
  • FIG. 2 is a schematic structural view of the embodiment of FIG. 1.
  • the gates 201, 202 of at least two TFTs are disposed in the same layer as the scan line Scan, and are all connected with the scan line Scan; the sources 203, 204 and the data lines of the at least two TFTs
  • the data is set in the same layer and is connected to the data line Data.
  • the drains 205 and 206 of the at least two TFTs are connected to the first pixel electrode 207, and the drains 205 and 206 of the at least two TFTs are connected to the first layer.
  • a pixel electrode 207 is disposed in the same layer or in a non-same layer.
  • the scan signal provided by the scan line Scan drives at least two TFTs to work
  • the data voltage provided by the data line Data passes through the at least two TFTs to simultaneously charge the first pixel electrode 207 to speed up The charging process of charging the first pixel electrode 207.
  • the TFT of the embodiment is an amorphous silicon TFT.
  • an amorphous indium gallium zinc material may be used instead of the amorphous silicon material.
  • FIG. 3 is a schematic structural diagram of a conductive channel of the TFT in the embodiment of FIG.
  • the charging speed of the first pixel electrode 101 by the amorphous silicon TFT largely depends on the mobility ⁇ of the carrier of the amorphous silicon TFT, and ⁇ is related to the width to length ratio W/L of the conductive channel.
  • W/L the larger W/L
  • the arrangement of the at least two first switches and the first pixel electrode in the above embodiment may increase the width W of the conductive channel for migrating carriers.
  • the conductive channel sizes of the first switches are the same, the sum of the mobility of the carriers of the conductive channels of the N first switches is N* ⁇ , and the charging speed of the N first switches to the first pixel electrode By speeding up N times, the charging process of the entire pixel electrode will be accelerated by N times.
  • FIG. 4A is a circuit diagram of another embodiment of the pixel driving circuit of the present application
  • 4B is a schematic structural view of the embodiment of FIG. 4A.
  • the embodiment further includes a second pixel electrode 401 and at least two second switches T3 and T4 on the basis of the above embodiment; the respective control ends 402 and 403 of the at least two second switches T3 and T4 are connected to the scan line Scan.
  • the input end 404 of the second switch T3 is connected to the data line Data
  • the output end 405 of the second switch T3 is connected to the second pixel electrode 401
  • the input end 406 of the second switch T4 is connected to the output end 405 of the second switch T3.
  • the pixel voltage of the two-pixel electrode 401 is a circuit diagram of another embodiment of the pixel driving circuit of the present application
  • 4B is a schematic structural view of the embodiment of FIG. 4A.
  • the embodiment further includes a second pixel electrode 401 and at least two second switches T3 and T4 on the basis of
  • the input 408 of the second switch T4 is coupled to a common electrode Com.
  • the first pixel electrode 407 and the second pixel electrode 401 having two different pixel voltages may be disposed in the same pixel.
  • the first pixel electrode 407 of the embodiment has been performed in the above embodiment. A detailed description is not repeated here.
  • the second switch T3 of the embodiment provides charging for the second pixel electrode 401 to provide a pixel voltage, and in order to realize different pixel voltages of the first pixel electrode 407 and the second pixel electrode 401, the second switch is used in this embodiment.
  • T4 pulls down the pixel voltage of the second pixel electrode 401.
  • the second switch T4 when the second switch T4 is turned on, a part of the output voltage of the output end 405 of the second switch T3, that is, the pixel voltage of the second pixel electrode 401 is divided by the second switch T4 to the output end of the second switch T4.
  • the connected common electrode Com reduces the pixel voltage of the second pixel electrode 401.
  • the first pixel electrode 407 and the second pixel electrode 401 collectively provide a pixel voltage for one pixel; and the first pixel electrode 407 is a main pixel electrode of the pixel.
  • a plurality of second pixel electrodes may be used, and each of the second pixel electrodes is disposed to have a different pixel voltage to further increase the viewing angle of the liquid crystal display panel; in yet another embodiment It is also possible to set a first switch for each of the second element electrodes to speed up the charging process.
  • the embodiment further includes a first storage capacitor C1 and a second storage capacitor C2.
  • the first storage capacitor C1 and the second storage capacitor C2 are respectively connected to the first pixel electrode 407 and the second pixel electrode 401, respectively
  • the charging charge of the first pixel electrode 407 and the second pixel electrode 401 is stored by the pixel driving circuit so that after the first switches T1, T2 and the second switch T3 are turned off, before being turned on again, the first pixel electrode 407 and The second pixel electrode 401 provides a pixel voltage to cause the pixel to operate normally.
  • At least two second switches T3 and T4 of the embodiment are TFTs, and the structure and working principle of the TFTs are not repeatedly described.
  • the layers of the present embodiment are similar to the embodiment of FIG. 2, and the description thereof will not be repeated.
  • the scan signal provided by the scan line Scan has a frequency greater than 120 Hz, that is, the frame rate is greater than 120 Hz.
  • a frame rate greater than 120 Hz is generally defined as a high frame rate, and an application of a high frame rate driven display helps to better meet the demand for picture fluency of a viewer.
  • FIG. 5 is a schematic structural diagram of an embodiment of an array substrate of the present application.
  • This embodiment includes a plurality of pixel driving circuits 501 arranged in a matrix; the specific structure and working principle of the pixel driving circuit have been described in detail in the above embodiments, and are not repeated here.
  • the same row of pixel driving circuits 501 share the same data line Data, and the same row of pixel driving circuits 501 share the same scanning line Scan.
  • the same row of pixel driving circuits 501 can share the same data line Data, and the same column of pixel driving circuits 501 can share the same scanning line Scan.
  • the pixel driving circuit 501 of the embodiment charges the first pixel electrode by using at least two first switches T1 and T2, which can speed up the charging process of the first pixel electrode, thereby improving the display quality of the display screen. .
  • FIG. 6 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • the embodiment includes a first substrate 601, a second substrate 602, and a liquid crystal layer 603; the first substrate 601 and/or the second substrate 602 are the array substrate of the above embodiment; wherein the liquid crystal layer 603 is located on the first substrate 601 and the second
  • the transmittance of the backlight is adjusted between the substrates 602 and under the control of the first substrate 601 and the second substrate 602.
  • the pixel driving circuit of the array substrate of the embodiment charges the first pixel electrode by using at least two first switches, which can speed up the charging process of the first pixel electrode, thereby improving the display quality of the display screen.

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Abstract

一种像素驱动电路（501）及阵列基板、显示面板。像素驱动电路（501）包括数据线（Data）、扫描线（Scan）、第一像素电极（101, 207, 407）和至少两个第一开关（T1, T2）；该至少两个第一开关（T1, T2）的各自输入端（102, 103）均连接数据线（Data），该至少两个第一开关（T1, T2）的各自输出端（104, 105）均连接同一个第一像素电极（101, 207, 407），该至少两个第一开关（T1, T2）的各自控制端（106, 107）均连接扫描线（Scan），以加快第一像素电极（101, 207, 407）的充电过程，从而改善因第一像素电极（101, 207, 407）充电不足引起的显示画面显示质量下降的问题。

Description

一种像素驱动电路及阵列基板、显示面板
【技术领域】
本申请涉及显示面板技术领域，特别是涉及一种像素驱动电路及阵列基板、显示面板。
【背景技术】
随着显示技术的发展，人们对液晶显示面板的高清和逼真的显示画面的需求越来越普遍，特别是3D显示技术的高逼真画面越来越受到影视观众的喜爱。在以开关，如薄膜晶体管（Thin Film Transistor，TFT）等驱动的液晶显示面板技术中，帧频是每秒驱动显示画面的帧数量，帧频越大代表单位时间内能显示越多的画面，画面显示也就越流畅。
但随着帧频的增大，开关对像素电极的充电时间会相应减少，会导致像素电极充电不足的问题，从而导致显示画面的显示质量降低，很大程度上制约着液晶显示面板的发展及应用。
本申请的发明人在长期的研发中发现，在目前现有技术中，为解决高帧频显示时，像素电极充电不足的问题，一般采用两种技术方案：一种是通过降低RC 延时，以提高充电速度，具体可以通过增大金属铜膜层厚度和金属铜线宽以降低阻抗和电容来降低RC 延时，但该方法会增加成本，且会增加液晶显示面板的非显示区的尺寸或液晶显示面板的厚度；另一种是在高帧频扫描周期内提高像素电极充电能力，可以通过采用具有高载流子迁移率材料的开关对像素电极进行充电。但目前的高载流子迁移率材料的应用在技术上的存在较多难点，尚不能普遍使用。
【发明内容】
本申请主要解决的技术问题是提供一种像素驱动电路及阵列基板、显示面板，以加快对像素电极的充电过程，从而提高显示画面的显示质量。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种像素驱动电路。所述像素驱动电路包括数据线、扫描线、第一像素电极、至少两个第一开关、第二像素电极及至少两个第二开关；所述至少两个第一开关的各自输入端均连接所述数据线，所述至少两个第一开关的各自输出端均连接同一个所述第一像素电极，所述至少两个第一开关的各自控制端均连接所述扫描线，以加快所述第一像素电极的充电过程；所述至少两个第二开关的各自控制端均连接所述扫描线，所述一第二开关的输入端连接所述数据线，输出端连接所述第二像素电极，所述另一第二开关的输入端连接所述一第二开关的输出端，以拉低所述第二像素电极的像素电压；所述扫描线提供的扫描信号的频率大于120Hz。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种阵列基板。所述阵列基板包括多个成矩阵排列的像素驱动电路；所述像素驱动电路包括：数据线、扫描线、第一像素电极及至少两个第一开关；所述至少两个第一开关的各自输入端均连接所述数据线，所述至少两个第一开关的各自输出端均连接同一个所述第一像素电极，所述至少两个第一开关的各自控制端均连接所述扫描线，以加快所述第一像素电极的充电过程；其中，同一列像素驱动电路共用同一条所述数据线，同一行像素驱动电路共用同一条所述扫描线；或同一行像素驱动电路共用同一条所述数据线，同一列像素驱动电路共用同一条所述扫描线。
为解决上述技术问题，本申请采用的又一个技术方案是：提供一种显示面板。所述显示面板包括第一基板、第二基板及液晶层；所述第一基板和/或第二基板为上述阵列基板；其中，液晶层位于所述第一基板及所述第二基板之间。
本申请实施例的有益效果是：区别于现有技术，本申请实施例像素驱动电路包括数据线、扫描线、第一像素电极和至少两个第一开关；至少两个第一开关的各自输入端均连接数据线，各自控制端均连接扫描线，各自输出端均连接同一个第一像素电极。申请实施例通过该至少两个第一开关给该第一像素电极充电，能够加快对该第一像素电极的充电过程，进而能够提高显示画面的显示质量。
【附图说明】
图1是本申请像素驱动电路一实施例的电路示意图；
图2是图1实施例的结构示意图；
图3是图2实施例中TFT导电沟道的结构示意图；
图4A是本申请像素驱动电路另一实施例的电路示意图；
图4B是图4A实施例的结构示意图；
图5是本申请阵列基板一实施例的结构示意图；
图6是本申请显示面板的一实施例的结构示意图。
【具体实施方式】
请参阅图1，图1是本申请像素驱动电路一实施例的电路示意图。本实施例包括数据线Data、扫描线Scan、第一像素电极101和至少两个第一开关T1、T2；至少两个第一开关T1、T2的各自输入端102、103均连接数据线Data，至少两个第一开关T1、T2的各自输出端104、105均连接同一个第一像素电极101，至少两个第一开关T1、T2的各自控制端106、107均连接扫描线Scan，以加快第一像素电极101的充电过程。
为满足用户对画面显示流畅性的越来越高的要求，画面显示的帧频也越来越大，像素扫描信号周期越来越小，像素得到的扫描信号持续驱动时间越来越小，相应的像素电极充电时间也越来越短，极易导致像素电极充电不足，从而导致显示画面的显示质量下降，甚至不能正常显示。
本实施例采用增加与第一像素电极101连接的第一开关T1、T2的数量来加快第一像素电极101的充电过程，第一开关T1、T2的数量越多，第一像素电极101的充电过程就越快，因此，能够解决第一像素电极101充电不足的问题，从而适应画面显示的帧频越来越大的趋势。
区别于现有技术，本实施例将至少两个第一开关T1、T2的各自输入端102、103均连接数据线Data，至少两个第一开关T1、T2的各自输出端104、105均连接同一个第一像素电极101，至少两个第一开关T1、T2的各自控制端106、107均连接扫描线Scan，在扫描线Scan提供的扫描信号驱动下，使得与第一像素电极101连接的至少两个第一开关T1、T2均给第一像素电极101充电，能够加快第一像素电极101的充电过程，从而能够提高显示画面的显示质量。
在一个应用场景中，本实施例的至少两个第一开关T1、T2的各自输入端连接同一数据线Data，至少两个第一开关T1、T2的各自控制端连接同一扫描线Scan，以使至少两个第一开关T1、T2同时给第一像素电极101充电，最大限度的加开充电过程。
可选地，本实施的各第一开关均为TFT。其中，第一开关的控制端为TFT的栅极，输入端为TFT的源极，输出端为TFT的漏极，当然，在另一实施例中，第一开关的输入端为TFT的漏极，输出端为TFT的源极。在又一实施例中，第一开关也可以是其它具有开关功能的电子元器件，如互补金属氧化物半导体（Complementary Metal Oxide Semiconductor，CMOS）等。
具体地，请参阅图2，图2是图1实施例的结构示意图。从图2中可以看出，至少两个TFT的栅极201、202与扫描线Scan同层设置，且均与连接扫描线Scan在一起；该至少两个TFT的源极203、204与数据线Data同层设置，且均与数据线Data连接在一起；该至少两个TFT的漏极205、206均与第一像素电极207连接，且该至少两个TFT的漏极205、206均与第一像素电极207同层或非同层设置，当扫描线Scan提供的扫描信号驱动至少两TFT工作时，数据线Data提供的数据电压经过该至少两TFT同时给第一像素电极207充电，以加快第一像素电极207充电的充电过程。
可选地，本实施例的TFT为非晶硅TFT。当然，在其它实施例中，可采用非晶氧化铟镓锌材料代替非晶硅材料。
请参阅图3，图3是图2实施例中TFT的导电沟道的结构示意图。非晶硅TFT对第一像素电极101的充电速度很大程度上取决于非晶硅TFT的载流子的迁移率μ，μ与其导电沟道的宽长比W/L有关， W/L越大，μ越大。从图3中可以看出，在上述实施例的至少两个第一开关与第一像素电极的设置方式可以增加用于迁移载流子的导电沟道的宽度W。若各第一开关的导电沟道尺寸一致，则N个第一开关的导电沟道的载流子的迁移率的和为N*μ，该N个第一开关给第一像素电极的充电速度加快N倍，整个像素电极的充电过程将加快N倍。
可选地，请参阅图4A，图4A是本申请像素驱动电路另一实施例的电路示意图; 图4B是图4A实施例的结构示意图。本实施例在上述实施例的基础上进一步包括第二像素电极401及至少两个第二开关T3、T4；至少两个第二开关T3、T4的各自控制端402、403均连接扫描线Scan，第二开关T3的输入端404连接数据线Data，第二开关T3的输出端405连接第二像素电极401，第二开关T4的输入端406连接第二开关T3的输出端405，以拉低第二像素电极401的像素电压。
在一个应用场景中，第二开关T4的输入端408连接一公共电极Com。
为增加液晶显示面板的视角，可以在同一个像素内设置具有两种不同像素电压的第一像素电极407及第二像素电极401，本实施例的第一像素电极407已经在上述实施例中进行了详细的叙述，这里不重复。本实施例的第二开关T3为第二像素电极401提供充电，以提供像素电压，而为实现第一像素电极407与第二像素电极401的具有不同的像素电压，本实施例利用第二开关T4来拉低第二像素电极401的像素电压。具体地，第二开关T4导通时，会有一部分第二开关T3输出端405的输出电压，即第二像素电极401的像素电压经第二开关T4分压到与第二开关T4的输出端连接的公共电极Com，从而使第二像素电极401的像素电压降低。
可选地，本实施例中，第一像素电极407及第二像素电极401共同为一像素提供像素电压；且第一像素电极407为该像素的主像素电极。
当然，在另一实施例中，可以采用利用多个第二像素电极，同时设置各第二像素电极具有不同的像素电压，以更进一步的增大液晶显示面板的视角；在又一实施例中，还可以给每个第二素电极设置第一开关以加快其充电过程。
可选地，本实施例进一步包括第一存储电容C1及第二存储电容C2；第一存储电容C1及第二存储电容C2分别与第一像素电极407及第二像素电极401连接，分别用于存储像素驱动电路对第一像素电极407及第二像素电极401的充电电荷，以使在第一开关T1、T2及第二开关T3截止后，再次导通前，分别给第一像素电极407及第二像素电极401提供像素电压，使像素正常工作。
可选地，本实施例的至少两个第二开关T3、T4为TFT，关于TFT的结构与工作原理这例不重复介绍。且本实施例的各层设置与图2实施例类似，这不不重复叙述。
可选地，本实施例中扫描线Scan提供的扫描信号的频率大于120Hz，即帧频大于120Hz。在液晶显示技术领域，通常将大于120Hz的帧频定义为高帧频，高帧频驱动显示的应用有助于更好满足影视观众对画面流畅性的需求。
请参阅图5，图5是本申请阵列基板一实施例的结构示意图。本实施例包括多个成矩阵排列的像素驱动电路501；像素驱动电路的具体结构及工作原理已经在上述实施例中进行了详细的叙述，这里不重复。
其中，同一列像素驱动电路501共用同一条数据线Data，同一行像素驱动电路501共用同一条扫描线Scan。当然，在其它实施例中，同一行像素驱动电路501可共用同一条数据线Data，同一列像素驱动电路501可共用同一条扫描线Scan。
区别于现有技术，本实施例的像素驱动电路501利用至少两个第一开关T1、T2给第一像素电极充电，能够加快该第一像素电极的充电过程，从而能够提高显示画面的显示质量。
请参阅图6，图6是本申请显示面板的一实施例的结构示意图。本实施例包括第一基板601、第二基板602及液晶层603；第一基板601和/或第二基板602为上述实施例的阵列基板；其中，液晶层603位于第一基板601及第二基板602之间，且在第一基板601及第二基板602的控制下调节背光的透过率。
阵列基板的结构及工作原理及流程已在上述实施例中进行了详细的叙述，这里也不重复。
区别于现有技术，本实施例的阵列基板的像素驱动电路利用至少两个第一开关给第一像素电极充电，能够加快该第一像素电极的充电过程，从而能够提高显示画面的显示质量。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种像素驱动电路，其中，包括：
    数据线、扫描线、第一像素电极、至少两个第一开关、第二像素电极及至少两个第二开关；
    所述至少两个第一开关的各自输入端均连接所述数据线，所述至少两个第一开关的各自输出端均连接同一个所述第一像素电极，所述至少两个第一开关的各自控制端均连接所述扫描线，以加快所述第一像素电极的充电过程；
    所述至少两个第二开关的各自控制端均连接所述扫描线，所述一第二开关的输入端连接所述数据线，输出端连接所述第二像素电极，所述另一第二开关的输入端连接所述一第二开关的输出端，以拉低所述第二像素电极的像素电压；
    所述扫描线提供的扫描信号的频率大于120Hz。
  2. 根据权利要求1所述的像素驱动电路，其中，
    所述第一像素电极及所述第二像素电极共同为所述像素提供像素电压；且所述第一像素电极为所述像素的主像素电极。
  3. 根据权利要求1所述的像素驱动电路，其中，
    进一步包括：第一存储电容及第二存储电容；
    所述第一存储电容及所述第二存储电容分别与所述第一像素电极及所述第二像素电极连接，分别用于存储所述像素驱动电路对所述第一像素电极及所述第二像素电极的充电电荷。
  4. 根据权利要求1所述的像素驱动电路，其中，
    所述第一及第二开关均为薄膜晶体管，所述控制端为所述薄膜晶体管的栅极，所述输入端为所述薄膜晶体管的漏极与源极中的一者，所述输出端为所述薄膜晶体管的漏极与源极中的另一者。
  5. 根据权利要求4所述的像素驱动电路，其中，
    所述薄膜晶体管为非晶硅薄膜晶体管。
  6. 根据权利要求4所述的像素驱动电路，其中，
    改变所述薄膜晶体管的导电沟道的宽长比，以加快所述第一、第二像素电极的充电过程。
  7. 一种阵列基板，其中，包括：
    多个成矩阵排列的像素驱动电路；所述像素驱动电路包括：数据线、扫描线、第一像素电极及至少两个第一开关；所述至少两个第一开关的各自输入端均连接所述数据线，所述至少两个第一开关的各自输出端均连接同一个所述第一像素电极，所述至少两个第一开关的各自控制端均连接所述扫描线，以加快所述第一像素电极的充电过程；
    其中，同一列像素驱动电路共用同一条所述数据线，同一行像素驱动电路共用同一条所述扫描线；或同一行像素驱动电路共用同一条所述数据线，同一列像素驱动电路共用同一条所述扫描线。
  8. 根据权利要求7所述的阵列基板，其中，
    所述像素驱动电路进一步包括第二像素电极及至少两个第二开关；所述至少两个第二开关的各自控制端均连接所述扫描线，所述一第二开关的输入端连接所述数据线，输出端连接所述第二像素电极，所述另一第二开关的输入端连接所述一第二开关的输出端，以拉低所述第二像素电极的像素电压。
  9. 根据权利要求8所述的阵列基板，其中，
    所述第一像素电极及所述第二像素电极共同为所述像素提供像素电压；且所述第一像素电极为所述像素的主像素电极。
  10. 根据权利要求8所述的阵列基板，其中，
    所述像素驱动电路进一步包括：第一存储电容及第二存储电容；
    所述第一存储电容及所述第二存储电容分别与所述第一像素电极及所述第二像素电极连接，分别用于存储所述像素驱动电路对所述第一像素电极及所述第二像素电极的充电电荷。
  11. 根据权利要求8所述的阵列基板，其中，
    所述第一及第二开关均为薄膜晶体管，所述控制端为所述薄膜晶体管的栅极，所述输入端为所述薄膜晶体管的漏极与源极中的一者，所述输出端为所述薄膜晶体管的漏极与源极中的另一者。
  12. 根据权利要求11所述的阵列基板，其中，
    所述薄膜晶体管为非晶硅薄膜晶体管。
  13. 根据权利要求11所述的阵列基板，其中，
    改变所述薄膜晶体管的导电沟道的宽长比，以加快所述第一、第二像素电极的充电过程。
  14. 根据权利要求7所述的阵列基板，其中，
    所述扫描线提供的扫描信号的频率大于120Hz。
  15. 一种显示面板，其中，包括：
    第一基板、第二基板及液晶层；所述第一基板和/或第二基板为权利要求7所述的阵列基板；
    其中，液晶层位于所述第一基板及所述第二基板之间。
  16. 根据权利要求15所述的显示面板，其中，
    所述阵列基板的所述像素驱动电路进一步包括第二像素电极及至少两个第二开关；所述至少两个第二开关的各自控制端均连接所述扫描线，所述一第二开关的输入端连接所述数据线，输出端连接所述第二像素电极，所述另一第二开关的输入端连接所述一第二开关的输出端，以拉低所述第二像素电极的像素电压。
  17. 根据权利要求16所述的阵列基板，其中，
    所述第一像素电极及所述第二像素电极共同为所述像素提供像素电压；且所述第一像素电极为所述像素的主像素电极。
  18. 根据权利要求16所述的阵列基板，其中，
    所述阵列基板的所述像素驱动电路进一步包括：第一存储电容及第二存储电容；
    所述第一存储电容及所述第二存储电容分别与所述第一像素电极及所述第二像素电极连接，分别用于存储所述像素驱动电路对所述第一像素电极及所述第二像素电极的充电电荷。
  19. 根据权利要求16所述的阵列基板，其中，
    所述第一及第二开关均为薄膜晶体管，所述控制端为所述薄膜晶体管的栅极，所述输入端为所述薄膜晶体管的漏极与源极中的一者，所述输出端为所述薄膜晶体管的漏极与源极中的另一者。
  20. 根据权利要求19所述的阵列基板，其中，
    所述薄膜晶体管为非晶硅薄膜晶体管。
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