WO2018205930A1 - 薄膜晶体管及制造方法、阵列基板、显示面板、显示装置 - Google Patents

薄膜晶体管及制造方法、阵列基板、显示面板、显示装置 Download PDF

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WO2018205930A1
WO2018205930A1 PCT/CN2018/086032 CN2018086032W WO2018205930A1 WO 2018205930 A1 WO2018205930 A1 WO 2018205930A1 CN 2018086032 W CN2018086032 W CN 2018086032W WO 2018205930 A1 WO2018205930 A1 WO 2018205930A1
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thin film
film transistor
metal
copper
drain
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PCT/CN2018/086032
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English (en)
French (fr)
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李海旭
曹占锋
姚琪
汪建国
孟凡娜
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京东方科技集团股份有限公司
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Priority to US16/333,102 priority Critical patent/US10811510B2/en
Publication of WO2018205930A1 publication Critical patent/WO2018205930A1/zh

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    • H—ELECTRICITY
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor and a manufacturing method thereof, an array substrate, a display panel, and a display device.
  • flat panel display devices such as liquid crystal displays (LCDs)
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • LCD TVs high-definition flat panel display devices
  • customers' requirements for display panels are also increasing, which is accompanied by an increase in response time, power consumption and resolution requirements of display panels.
  • Thin film transistors (TFTs) are key components in liquid crystal display devices and play an important role in the performance of display devices.
  • the metal layer material in the thin film transistor selects a material with a small electrical resistance and a high electrical conductivity to reduce power consumption, reduce voltage drop, and improve response speed.
  • the material of the drain source is generally selected from copper.
  • the copper has low resistivity and good resistance to electromigration, and can meet the requirements of large size, high resolution and high driving frequency of the display device.
  • a thin film transistor including: a drain and a source, the drain and/or the first metal thin film containing copper having a germanium element doped with a germanium element, and
  • the surface of the first metal thin film is a beryllium copper oxide formed by an annealing treatment.
  • the material of the first metal thin film is copper or a copper alloy.
  • the material of the first metal thin film is copper, and the mass fraction of the doping amount of the germanium element is less than 0.06% and more than 0.005%.
  • the mass fraction of the doping amount of the lanthanum element is 0.02%.
  • the thin film transistor further includes a gate, the gate is a second metal film containing copper doped with germanium, and the surface of the second metal film is The formed beryllium copper oxide is annealed.
  • the surface of the first metal thin film is an oxide of the complex Y 2 Cu 8 .
  • the surface of the second metal thin film is an oxide of the complex Y 2 Cu 8 .
  • a method of fabricating a thin film transistor including:
  • drain and/or the source is heavily doped with a lanthanum-containing first metal film comprising copper;
  • the first metal thin film is annealed to form a beryllium copper oxide on the surface of the first metal thin film.
  • the material of the first metal thin film is copper or a copper alloy.
  • the material of the first metal thin film is copper, and the mass fraction of the doping amount of the germanium element is less than 0.06% and more than 0.005%.
  • the mass fraction of the doping amount of the lanthanum element is 0.02%.
  • the method further includes: forming a gate, the gate being a second metal film containing copper doped with germanium;
  • the second metal thin film is annealed to form a beryllium copper oxide on the surface of the second metal thin film.
  • annealing the first metal film to form a beryllium copper oxide on the surface of the first metal film comprises: annealing the first metal film to make the first metal film The surface forms an oxide of the complex Y 2 Cu 8 .
  • annealing the second metal film to form a beryllium copper oxide on the surface of the second metal film comprises: annealing the second metal film to make the second metal film The surface forms an oxide of the complex Y 2 Cu 8 .
  • an array substrate comprising the thin film transistor of the first aspect.
  • a display panel comprising the array substrate of the third aspect.
  • a display device comprising the display panel of the fourth aspect.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to this embodiment.
  • FIG. 3 is a flow chart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 4 is a flow chart of another method of fabricating a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural view of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural view of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of another method of fabricating a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural view of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of a thin film transistor according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a thin film transistor and a manufacturing method thereof, an array substrate, a display panel, and a display device.
  • An embodiment of the present disclosure provides a thin film transistor including a drain A and a source B, and the drain A and/or the source B are a first metal thin film containing copper doped with germanium, and the first The surface of the metal thin film is a beryllium copper oxide formed by annealing.
  • the drain A and/or the source B of the thin film transistor in the embodiment of the present disclosure have good conductivity and oxidation resistance for the following reasons:
  • cerium element In terms of electrical conductivity, compared with copper, cerium element is more easily compounded with elements such as oxygen and sulfur to form a rare earth compound having a higher melting point, a higher thermal stability, a smaller specific gravity, and a smaller size. If the lanthanum element is added to copper or copper alloy, the lanthanum element will rob the oxygen and sulfur atoms combined with the copper element, and the smaller size compound will be formed, which will weaken the copper lattice distortion, reduce the electron scattering probability and reduce the resistance. Rate, thereby improving the conductivity of copper or copper alloys. The effect of the content of niobium on the conductivity of copper can be found in the table below.
  • the lanthanum element and the copper element can be combined to form a complex Y 2 Cu 8 .
  • the oxide film layer of the complex is dense, and an effective barrier layer can be formed on the surface of the copper or copper alloy to block oxygen and copper. Further oxidation.
  • the structure of the oxide formed by the reaction of the complex with oxygen has a superconductor structure, so that the oxide thin film layer can effectively protect the copper or copper alloy from being oxidized, and can not affect the overall electrical conductivity of the copper or copper alloy.
  • the conductivity of the drain and/or source can be improved by arranging the drain and/or source of the thin film transistor to be doped with a germanium element and annealed copper-containing first metal film.
  • the oxidation resistance, reducing the contact resistance between the drain and the source and the structure in contact with it, for example, the drain is set to be doped with an antimony element and the annealed copper-containing first metal film can reduce the drain
  • the contact resistance with the pixel electrode makes the performance of the thin film transistor more stable, for example, the response time of the thin film transistor can be shortened.
  • the material of the first metal thin film is copper or a copper alloy.
  • the material of the first metal film is copper.
  • the doping amount of the germanium element (that is, the amount added to the copper) has a mass fraction of less than 0.06%, and the germanium element The mass fraction of the doping amount is greater than 0.005%.
  • the mass fraction of the doping amount of the lanthanum element is 0.02%.
  • the drain and/or source with higher conductivity can be obtained using the above example values.
  • the annealing temperature of the first metal film containing copper doped with antimony is an annealing temperature of 150-250 degrees (for example, 150 degrees, 160 degrees, 170 degrees, 180 degrees, 190 degrees, 200 degrees). Degree, 210 degrees, 220 degrees, 230 degrees, 240 degrees, 250, etc.), the annealing atmosphere is air, and the annealing time is 0.5-1 hour (for example, 0.5 hour, 0.6 hour, 0.7 hour, 0.8 hour, 0.9 hour, 1 hour, etc.) ).
  • the thin film transistor in the embodiment of the present disclosure includes a thin film transistor of a bottom gate structure and a thin film transistor of a top gate structure.
  • the structure of the thin film transistor of the bottom gate structure includes: a substrate 1 and a gate 2 formed on the substrate 1 and formed on the gate.
  • a gate insulating layer 3 on the pole 2 an active layer 4 formed on the gate insulating layer 3, and a drain A and a source B formed on the active layer 4.
  • the structure of the film transistor of the top gate structure includes: a base substrate 1, an active layer 4 formed on the base substrate 1, and formed on The etch stop layer 5 on the active layer 4, and the etch stop layer 5 is provided with a via 501 (see FIG. 9), and a gate 2, a drain A, and a source formed on the etch stop layer 5. B, and the drain A and the source B are connected to the active layer 4 through the via 501.
  • a buffer layer is not provided on the drain A and/or the source B.
  • a buffer layer is provided on the drain A and the source B to prevent the drain A and the source B from being oxidized.
  • the buffer layer is typically a metal film.
  • the buffer layer is added, the following problems are caused: when the two metal layers (including the metal layer where the drain A and the source B are located and the buffer layer) are simultaneously etched, the buffer layer is etched slowly, and The tip structure (ie, the roof structure) is generated, which affects the overlapping of the upper film layers.
  • the drain A and/or the source B in the embodiment of the present disclosure is a first metal film containing copper doped with an antimony element and annealed, the surface of the drain A and/or the source B is made.
  • Forming a dense oxide layer C see FIGS. 1 and 2), such that the thin film transistor of the embodiment of the present disclosure does not need to provide a buffer layer on the drain A and/or the source B, not only the manufacturing process of the thin film transistor Simplification, and also avoiding the formation of a tip structure (ie, a roof structure) in a simultaneous etching of two layers of stacked metal layers (including the metal layer of the drain A and/or the source B, the buffer layer).
  • both the drain A and the source B in the thin film transistor shown in FIG. 1 and FIG. 2 are provided as a first metal thin film containing copper doped with germanium, and the drain A and the source are opposite. B is annealed.
  • the base substrate 1 in the thin film transistor of the bottom gate structure or the top gate structure may be a transparent substrate such as a glass substrate, a silicon substrate, a plastic substrate, or the like.
  • the gate electrode 2 in the thin film transistor of the bottom gate structure or the top gate structure may be a metal electrode such as Al (aluminum), Cu (copper), Mo (molybdenum), Cr (chromium), Ti ( Metal electrodes such as titanium; the gate 2 can also be designed by overlapping multiple layers of metal.
  • the gate electrode is provided as a second metal film containing copper doped with germanium, and the surface of the second metal film is a beryllium copper oxide formed by annealing.
  • the electrical conductivity of the gate can be improved, and the oxidation resistance can also be improved.
  • the gate insulating layer 3 in the thin film transistor of the bottom gate structure may be a silicon nitride or silicon oxynitride layer.
  • the etch barrier layer 5 in the thin film transistor of the top gate structure may be a material such as aluminum oxide, zirconium oxide or the like.
  • the active layer 4 in the thin film transistor of the bottom gate structure or the top gate structure may be made of amorphous silicon, polycrystalline silicon, oxide, or the like.
  • FIG. 3 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure. Referring to FIG. 3, the method includes:
  • Step 101 forming a drain A and a source B, wherein the drain A and/or the source B are a first metal thin film containing copper doped with germanium;
  • the material of the first metal thin film is copper or a copper alloy.
  • the material of the first metal film is copper.
  • the doping amount of the germanium element (that is, the amount added to the copper) has a mass fraction of less than 0.06%, and the germanium element The mass fraction of the doping amount is greater than 0.005%.
  • the mass fraction of the doping amount of the lanthanum element is 0.02%.
  • the drain and/or source with higher conductivity can be obtained using the above example values.
  • Step 102 Annealing the first metal film to form a beryllium copper oxide on the surface of the first metal film.
  • a dense oxide layer C of the complex Y 2 Cu 8 can be formed on the surface of the drain A and/or the source B.
  • the annealing temperature of the first metal film containing copper doped with antimony is an annealing temperature of 150-250 degrees (for example, 150 degrees, 160 degrees, 170 degrees, 180 degrees, 190 degrees, 200 degrees). Degree, 210 degrees, 220 degrees, 230 degrees, 240 degrees, 250, etc.), the annealing atmosphere is air, and the annealing time is 0.5-1 hour (for example, 0.5 hour, 0.6 hour, 0.7 hour, 0.8 hour, 0.9 hour, 1 hour, etc.) ).
  • the drain A and/or the source B containing a mass fraction of 0.06% yttrium are annealed (annealing temperature is 250 ° C, annealing atmosphere is air, annealing time is 0.5 h) ), a thin film transistor having an electrical conductivity of 58 Ms/m and improved oxidation resistance can be obtained.
  • the drain A and/or the source B containing the 0.02% by mass element are annealed (the annealing temperature is 250 ° C, the annealing atmosphere is air, and the annealing time is 0.5).
  • the annealing temperature is 250 ° C
  • the annealing atmosphere is air
  • the annealing time is 0.5.
  • the conductivity of the drain and/or source and the oxidation resistance can be improved by disposing the drain and/or the source of the thin film transistor as a first metal film containing copper which is doped with antimony and annealed.
  • the performance reduces the contact resistance between the drain and the source and the structure in contact with it, making the performance of the thin film transistor more stable, for example, shortening the response time of the thin film transistor.
  • FIG. 4 is a flow chart of another method for fabricating a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 4, the method may include:
  • Step 201 Providing a base substrate 1.
  • the base substrate 1 may be a transparent substrate substrate such as a glass substrate, a silicon substrate, a plastic substrate, or the like. Alternatively, the provided substrate substrate 1 may be cleaned in advance to ensure the cleaning of the substrate substrate 1.
  • Step 202 Forming the gate electrode 2 on the base substrate 1.
  • the gate electrode 2 can be formed on the base substrate 1 by a patterning process. For example, a metal layer is formed on the substrate substrate 1 by sputtering, and then the gate electrode 2 is obtained by an etching process.
  • the gate 2 may be a metal electrode, such as a metal electrode such as Al (aluminum), Cu (copper), Mo (molybdenum), Cr (chromium), or Ti (titanium); the gate 2 may also be designed by using a plurality of layers of metal overlap. .
  • the gate is provided as a second metal film containing copper doped with antimony element to improve the electrical conductivity and oxidation resistance of the gate.
  • the annealing treatment of the second metal thin film may be simultaneously annealed with the first metal thin film (see step 206), and the order of the above two annealing treatments is not limited herein.
  • Step 203 Forming a gate insulating layer 3 on the gate 2.
  • the gate insulating layer 3 is formed on the base substrate 1 on which the gate electrode 2 is formed, for example, a layer is deposited on the base substrate 1 on which the gate electrode 2 is formed.
  • the gate insulating layer 3 may be a silicon nitride or silicon oxynitride layer.
  • Step 204 Forming the active layer 4 on the gate insulating layer 3.
  • the active layer 4 can be formed by a single patterning process.
  • an active layer 4 is first formed on the gate insulating layer 3 by deposition, specifically by plasma-enhanced chemistry. Vapor deposition (PECVD), and then through an etching process, specifically using inductively coupled plasma (ICP) to form the active layer 4 shown in FIG.
  • PECVD plasma-enhanced chemistry.
  • ICP inductively coupled plasma
  • the active layer 4 can be made of amorphous silicon, polycrystalline silicon, oxide, or the like.
  • Step 205 forming a drain A and a source B on the active layer 4, wherein the drain A and/or the source B are a first metal thin film containing copper doped with germanium.
  • the drain electrode A and the source B may be formed by a patterning process on the substrate substrate 1 on which the active layer 4 is formed, specifically: magnetron sputtering may be first performed. The process then forms an etch process to form drain A and source B as shown in FIG.
  • the target used to deposit the drain A and/or the source B is a copper plate doped with antimony.
  • Step 206 Annealing the entire thin film transistor.
  • the entire thin film transistor is annealed to form a dense oxide layer C of the complex Y 2 Cu 8 on the surfaces of the drain A and the source B (see the figure). 1). In the same way, the same chemical change process occurs in the gate.
  • the dense oxide layer C of the complex Y 2 Cu 8 has a dense and superconducting property, which can effectively block the contact of oxygen with the surface of the first metal film to cause oxidation, affect the characteristics of the thin film transistor, and can not conduct overall conductivity of the thin film transistor. Sex has an impact.
  • the annealing temperature of the thin film transistor is 150-250 degrees (eg, 150 degrees, 160 degrees, 170 degrees). , 180 degrees, 190 degrees, 200 degrees, 210 degrees, 220 degrees, 230 degrees, 240 degrees, 250, etc.), the annealing atmosphere is air, and the annealing time is 0.5-1 hours (for example, 0.5 hours, 0.6 hours, 0.7 hours, 0.8) Hours, 0.9 hours, 1 hour, etc.).
  • the drain A and/or the source B in the embodiment of the present disclosure are an annealed first metal thin film doped with a germanium element, the surfaces of the drain A and/or the source B respectively form an oxide layer C ( Referring to FIG. 1), in this way, the thin film transistor of the embodiment of the present disclosure does not need to provide a buffer layer on the drain A and/or the source B, which not only simplifies the manufacturing process of the thin film transistor, but also avoids After the buffer layer is disposed on the drain A and/or the source B, the problem of uneven etching is caused, thereby avoiding superimposing the metal layer on both layers (including the metal layer and the buffer layer where the drain A and/or the source B are located).
  • the tip structure ie, the roof structure
  • Embodiments of the present disclosure can improve the conductivity and oxidation resistance of the drain and/or source by disposing the drain and/or source of the thin film transistor as the annealed first metal film doped with germanium.
  • the contact resistance between the drain-source and the structure in contact with it is reduced, so that the performance of the thin film transistor is more stable, for example, the response time of the thin film transistor can be shortened.
  • FIG. 7 is a flowchart of another method for fabricating a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 7, the method specifically includes:
  • Step 301 Providing the base substrate 1.
  • the base substrate 1 may be a transparent substrate substrate such as a glass substrate, a silicon substrate, a plastic substrate, or the like. Alternatively, the provided substrate substrate 1 may be cleaned in advance to ensure the cleaning of the substrate substrate 1.
  • Step 302 Forming the active layer 4 on the base substrate 1.
  • the active layer 4 may be formed on the base substrate 1 by one patterning process.
  • an active layer 4 is first formed on the base substrate 1 by deposition, specifically by plasma enhanced chemical vapor deposition, and then Through the etching process, an inductively coupled plasma can be specifically used to form the active layer 4 shown in FIG.
  • the active layer 4 can be made of amorphous silicon, polycrystalline silicon, oxide, or the like.
  • Step 303 forming an etch stop layer 5 on the active layer 4.
  • an etch stop layer 5 can be deposited on the base substrate 1 on which the active layer 4 is formed, and the resulting etch stop layer 5 is subjected to a patterning process to form Hole 501.
  • the etch barrier layer 5 may be a material such as alumina or zirconia.
  • Step 304 Forming a gate 2, a drain A and a source B on the etch barrier layer 5, wherein the drain A and the source B are a first metal thin film containing copper doped with germanium.
  • a gate pattern 2, a drain A, and a source B may be formed on the etch barrier layer 5 by a patterning process, for example, by a magnetron sputtering process and then by an etching process. 2, the gate 2, the drain A and the source B are shown, and the target used for depositing the drain A and/or the source B at this time is a copper plate doped with germanium.
  • the gate 2 may be a metal electrode, such as a metal electrode such as Al (aluminum), Cu (copper), Mo (molybdenum), Cr (chromium), or Ti (titanium); the gate 2 may also be designed by using a plurality of layers of metal overlap. .
  • the gate electrode may be provided as a second metal film containing copper doped with germanium to increase the electrical conductivity and oxidation resistance of the gate.
  • the second metal film needs to be annealed and simultaneously annealed with the first metal film (see steps). 305), the order of the above two annealing treatments is not limited herein.
  • Step 305 Annealing the entire thin film transistor.
  • the entire thin film transistor is annealed to form a complex on the surface of the drain A and/or the source B.
  • a dense oxide layer C of Y 2 Cu 8 (see Figure 2). In the same way, the same chemical change process occurs in the gate.
  • the annealing temperature of the thin film transistor is 150-250 degrees (eg, 150 degrees, 160 degrees, 170) Degree, 180 degrees, 190 degrees, 200 degrees, 210 degrees, 220 degrees, 230 degrees, 240 degrees, 250, etc.), the annealing atmosphere is air, and the annealing time is 0.5-1 hours (for example, 0.5 hours, 0.6 hours, 0.7 hours, 0.8 hours, 0.9 hours, 1 hour, etc.).
  • the drain A and/or the source B in the embodiment of the present disclosure are the first metal thin film doped with germanium and subjected to annealing, the surfaces of the drain A and/or the source B respectively form a dense oxide layer.
  • C see FIG. 2
  • the thin film transistor of the embodiment of the present disclosure does not need to provide a buffer layer on the drain A and/or the source B, which not only simplifies the manufacturing process of the thin film transistor but also avoids
  • the tip structure ie, the roof structure
  • the tip structure is formed in the simultaneous etching of the two layers of the stacked metal layer (including the metal layer where the drain A and/or the source B are located and the buffer layer).
  • the embodiment of the present disclosure can improve the conductivity and oxidation resistance of the drain and/or source by reducing the drain and/or source of the thin film transistor to the annealed first metal film doped with germanium.
  • the contact resistance between the source and the structure in contact with it makes the performance of the thin film transistor more stable, for example, shortening the response time of the thin film transistor.
  • An embodiment of the present disclosure further provides an array substrate including the thin film transistor illustrated in FIG.
  • the drain and/or source of the thin film transistor of the present disclosure is extremely doped with an annealed first metal thin film, which improves the conductivity and oxidation resistance of the drain and/or source, and reduces the drain and source thereof.
  • the contact resistance between the structures in contact with each other makes the performance of the thin film transistor more stable, for example, the response time of the thin film transistor can be shortened.
  • An embodiment of the present disclosure further provides a display panel including the above array substrate.
  • the display panel provided by the embodiment of the present disclosure may be any product having a display panel, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the drain and/or source of the thin film transistor of the embodiment of the present disclosure is extremely doped with an annealed first metal thin film, which can improve the conductivity and oxidation resistance of the drain and/or source, and reduce the leakage source.
  • the contact resistance between the poles in contact with the poles makes the performance of the thin film transistor more stable, for example, the response time of the thin film transistor can be shortened.
  • Embodiments of the present disclosure can obtain a low power, high response speed display panel by employing the array substrate described above in a display panel.
  • Embodiments of the present disclosure also provide a display device including the above display panel.
  • the display device provided by the embodiment of the present disclosure may be any product having a display device, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the drain and/or source of the thin film transistor of the embodiment of the present disclosure is extremely doped with an annealed first metal thin film, which can improve the conductivity and oxidation resistance of the drain and/or source, and reduce the leakage source.
  • the contact resistance between the structures in contact with the poles makes the performance of the thin film transistor more stable, for example, the response time of the thin film transistor can be shortened.
  • Embodiments of the present disclosure can obtain a display device of low power and high response speed by employing the display panel described above in a display device.

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Abstract

公开了一种薄膜晶体管及制造方法、阵列基板、显示面板、显示装置，属于显示技术领域。所述薄膜晶体管包括漏极和源极，所述漏极和/或所述源极为掺杂有钇元素的第一金属薄膜，且所述第一金属薄膜的表面为退火处理形成的钇铜络合氧化物。

Description

薄膜晶体管及制造方法、阵列基板、显示面板、显示装置
相关专利申请
本申请主张于2017年5月8日提交的中国专利申请No.201710318516.4的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，特别涉及一种薄膜晶体管及制造方法、阵列基板、显示面板、显示装置。
背景技术
在显示技术领域，平板显示装置，如液晶显示器(LCD)，因其具有轻、薄、低功耗、高亮度，以及高画质等优点，在平板显示领域占据重要的地位。尤其是大尺寸、高分辨率，以及高画质的平板显示装置，如液晶电视，在当前的平板显示装置市场已经占据了主导地位。目前，客户对显示面板的要求也不断提高，随之而来的是对显示面板响应时间、功耗及分辨率要求的提高。薄膜晶体管(TFT)是液晶显示装置中的关键器件，对显示装置的工作性能起到十分重要的作用。
目前，薄膜晶体管中的金属层材料会选择电阻尽量小、导电性强的材料，以便减少功耗、降低压降及提高响应速度。其中，漏源极的材料一般选用铜，铜具有较低的电阻率及良好的抗电迁移能力，可满足显示装置大尺寸、高分辨率及高驱动频率的要求。
但是，铜本身因其活泼性的原因，易与氧气及水分接触发生氧化，使得漏源极与像素电极之间的接触电阻增加，进而会影响薄膜晶体管的特性。
发明内容
第一方面，提供了一种薄膜晶体管，所述薄膜晶体管包括：漏极和源极，所述漏极和/或所述源极为掺杂有钇元素的含有铜的第一金属薄膜，且所述第一金属薄膜的表面为经过退火处理形成的钇铜氧化物。
具体地，所述第一金属薄膜的材料为铜或者铜合金。
具体地，所述第一金属薄膜的材料为铜，且所述钇元素的掺杂量 的质量分数为小于0.06％且大于0.005％。
具体地，所述钇元素的掺杂量的质量分数为0.02％。
在本公开实施例的一种实现方式中，所述薄膜晶体管还包括栅极，所述栅极为掺杂有钇元素的含有铜的第二金属薄膜，且所述第二金属薄膜的表面为经过退火处理形成的钇铜氧化物。
具体地，所述第一金属薄膜的表面为络合物Y 2Cu 8的氧化物。
具体地，所述第二金属薄膜的表面为络合物Y 2Cu 8的氧化物。
第二方面，提供了一种薄膜晶体管制造方法，包括：
形成漏极和源极，其中所述漏极和/或所述源极为掺杂有钇元素的含有铜的第一金属薄膜；以及
对所述第一金属薄膜进行退火处理，使所述第一金属薄膜的表面形成钇铜氧化物。
具体地，所述第一金属薄膜的材料为铜或者铜合金。
具体地，所述第一金属薄膜的材料为铜，且所述钇元素的掺杂量的质量分数为小于0.06％且大于0.005％。
具体地，所述钇元素的掺杂量的质量分数为0.02％。
在本公开实施例的一种实现方式中，所述方法还包括：形成栅极，所述栅极为掺杂有钇元素的含有铜的第二金属薄膜；
对所述第二金属薄膜进行退火处理，使所述第二金属薄膜的表面形成钇铜氧化物。
具体地，对所述第一金属薄膜进行退火处理，使所述第一金属薄膜的表面形成钇铜氧化物，包括：对所述第一金属薄膜进行退火处理，使所述第一金属薄膜的表面形成络合物Y 2Cu 8的氧化物。
具体地，对所述第二金属薄膜进行退火处理，使所述第二金属薄膜的表面形成钇铜氧化物，包括：对所述第二金属薄膜进行退火处理，使所述第二金属薄膜的表面形成络合物Y 2Cu 8的氧化物。
第三方面，提供一种阵列基板，所述阵列基板包括第一方面所述的薄膜晶体管。
第四方面，提供一种显示面板，所述显示面板包括第三方面所述的阵列基板。
第五方面，提供了一种显示装置，所述显示装置包括第四方面所述的显示面板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种薄膜晶体管的结构示意图；
图2是本实施例提供的另一种薄膜晶体管的结构示意图；
图3是本公开实施例提供的一种薄膜晶体管制作方法的流程图；
图4是本公开实施例提供的另一种薄膜晶体管制作方法的流程图；
图5是本公开实施例提供的薄膜晶体管制作过程中的结构示意图；
图6是本公开实施例提供的薄膜晶体管制作过程中的结构示意图；
图7是本公开实施例提供的另一种薄膜晶体管制作方法的流程图；
图8是本公开实施例提供的薄膜晶体管制作过程中的结构示意图；
图9是本公开实施例提供的薄膜晶体管制作过程中的结构示意图；以及
图10是本公开实施例提供的薄膜晶体管制作过程中的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
为了解决漏源极易氧化，而增加漏源极与像素电极之间的接触电阻的问题，本公开实施例提供了一种薄膜晶体管及制造方法、阵列基板、显示面板、显示装置。
本公开实施例提供了一种薄膜晶体管，该薄膜晶体管包括漏极A和源极B，漏极A和/或源极B为掺杂有钇元素的含有铜的第一金属薄膜，且第一金属薄膜的表面为经过退火处理形成的钇铜氧化物。
本公开实施例中的薄膜晶体管的漏极A和/或源极B具有良好的导电性与抗氧化性，其原因如下：
在导电性方面，与铜元素相比，钇元素更易与氧、硫等元素进行复合，形成熔点较高、热稳定性强、比重较小且尺寸较小的稀土化合物。若把钇元素添加到铜或铜合金中，钇元素会抢夺与铜元素结合的 氧、硫原子，而生成尺寸较小的化合物，使铜晶格畸变减弱，减少了电子散射几率，减少了电阻率，从而改善了铜或铜合金的导电性。钇元素的含量对铜的导电率的影响，可参见下表。
钇的添加量(wt％) 0 0.02 0.04 0.06 0.08 0.1
电导率(MSm -1) 57.9 59.9 59.2 58.9 38 36
从上表中可看出，在一定质量分数范围内，随着钇元素添加量的增加，纯铜的导电率也逐渐增加，故，向含有铜的第一金属薄膜中掺杂钇元素，可改善含有铜的第一金属薄膜的电导率。
在抗氧化性方面，钇元素与铜元素可结合产生络合物Y 2Cu 8，该络合物的氧化物薄膜层致密，可在铜或铜合金表面形成有效的阻挡层，阻挡氧与铜的进一步氧化。且，该络合物与氧反应生成的氧化物的结构具有超导体结构，故该氧化物薄膜层可有效保护铜或铜合金不被氧化，又能不影响铜或铜合金整体的导电性能。
值得说明的是，向铜或铜合金中加入钇元素后，需要对铜或铜合金进行退火处理，这样使得位于铜或铜合金内部的钇元素富集到铜或铜合金的表面，进而才能在铜或铜合金表面形成致密氧化物。
综上所述，通过将薄膜晶体管的漏极和/或源极设置为掺杂有钇元素，且经过退火处理的含有铜的第一金属薄膜，可提高漏极和/或源极的导电率以及抗氧化性能，减少漏源极与其相接触的结构之间的接触电阻，例如，将漏极设置为掺杂有钇元素、且经过退火处理的含有铜的第一金属薄膜，可以减少漏极与像素电极之间的接触电阻，使薄膜晶体管的性能更加稳定，例如可缩短薄膜晶体管的响应时间。
在本公开实施例中，第一金属薄膜的材料为铜或者铜合金。
例如，第一金属薄膜的材料为铜。
进一步地，本实施例为了使薄膜晶体管的漏极和/或源极的导电率得到提高，钇元素的掺杂量(即向铜中添加的量)的质量分数为小于0.06％，且钇元素的掺杂量的质量分数大于0.005％。
例如，钇元素的掺杂量的质量分数为0.02％。采用上述示例值可获得具有较高电导率的漏极和/或源极。
在本公开实施例中，对掺杂有钇元素的含有铜的第一金属薄膜的进行退火的退火温度为150-250度(例如150度、160度、170度、180度、190度、200度、210度、220度、230度、240度、250等)，退 火气氛是空气，退火时间为0.5-1小时(例如0.5小时、0.6小时、0.7小时、0.8小时、0.9小时、1小时等)。
本公开实施例中的薄膜晶体管包括底栅结构的薄膜晶体管和顶栅结构的薄膜晶体管。
图1显示了一种底栅结构的薄膜晶体管，如图1所示，该底栅结构的薄膜晶体管的结构包括：衬底基板1、形成在衬底基板1上的栅极2、形成在栅极2上的栅绝缘层3、形成在栅绝缘层3上的有源层4、以及形成在有源层4上的漏极A和源极B。
图2显示了一种顶栅结构的薄膜晶体管，如图2所示，该顶栅结构的膜晶体管的结构包括：衬底基板1、形成在衬底基板1上的有源层4、形成在有源层4上的刻蚀阻挡层5，且刻蚀阻挡层5设置有过孔501(可参见图9)、以及形成在刻蚀阻挡层5上的栅极2、漏极A和源极B，且，漏极A和源极B通过过孔501与有源层4连接。
在图1和图2提供的薄膜晶体管中，漏极A和/或源极B上没有设置缓冲层。而在已知技术中在漏极A和源极B上设置缓冲层，以起到防止漏极A和源极B被氧化的作用。缓冲层一般为金属薄膜。但是，增加缓冲层后，会带来以下问题：当两层金属层(包括漏极A和源极B所在的金属层以及缓冲层)同步刻蚀时，由于缓冲层刻蚀速度较慢，而产生tip结构(即屋顶结构)，影响上层膜层搭接。
可见，由于本公开实施例中的漏极A和/或源极B为掺杂有钇元素，并经过退火处理的含有铜的第一金属薄膜，使得漏极A和/或源极B的表面形成致密氧化层C(参见图1和图2)，这样的话，本公开实施例的薄膜晶体管中就不需在漏极A和/或源极B上设置缓冲层，不仅使薄膜晶体管的制造工艺简单化，而且也避免在两层叠加金属层(包括漏极A和/或源极B所在的金属层、缓冲层)同步刻蚀中形成tip结构(即屋顶结构)。
需要说明的是，图1和图2中所示的薄膜晶体管中的漏极A与源极B都设置为掺杂有钇元素的含有铜的第一金属薄膜，且对漏极A与源极B都进行了退火处理。在本公开实施例中，底栅结构或者顶栅结构的薄膜晶体管中的衬底基板1可以为透明衬底，例如玻璃衬底、硅衬底和塑料衬底等。
在本公开实施例中，底栅结构或者顶栅结构的薄膜晶体管中的栅 极2可以为金属电极，例如Al(铝)、Cu(铜)、Mo(钼)、Cr(铬)、Ti(钛)等金属电极；栅极2也可以采用多层金属重叠设计而成。
例如，栅极设置为掺杂有钇元素的含有铜的第二金属薄膜，且该第二金属薄膜的表面为经过退火处理形成的钇铜氧化物。这样的话，即可提高栅极的导电性能，也可以提高抗氧化性能。
在本公开实施例中，底栅结构的薄膜晶体管中的栅极绝缘层3可以为氮化硅或氮氧化硅层。
在本公开实施例中，顶栅结构的薄膜晶体管中的刻蚀阻挡层5可以为氧化铝、氧化锆等物质。
在本公开实施例中，底栅结构或者顶栅结构的薄膜晶体管中的有源层4可以使用非晶硅、多晶硅，氧化物等制成。
图3是本公开实施例提供的一种薄膜晶体管制作方法的流程图，参见图3，该方法包括：
步骤101：形成漏极A和源极B，其中漏极A和/或源极B为掺杂有钇元素的含有铜的第一金属薄膜；
在本公开实施例中，第一金属薄膜的材料为铜或者铜合金。
例如，第一金属薄膜的材料为铜。
进一步地，本实施例为了使薄膜晶体管的漏极和/或源极的导电率得到提高，钇元素的掺杂量(即向铜中添加的量)的质量分数为小于0.06％，且钇元素的掺杂量的质量分数大于0.005％。
例如，钇元素的掺杂量的质量分数为0.02％。采用上述示例值可获得具有较高电导率的漏极和/或源极。
步骤102：对第一金属薄膜进行退火处理，使所述第一金属薄膜的表面形成钇铜氧化物。
经过退火处理，可在漏极A和/或源极B的表面形成络合物Y 2Cu 8的致密氧化层C。
在本公开实施例中，对掺杂有钇元素的含有铜的第一金属薄膜的进行退火的退火温度为150-250度(例如150度、160度、170度、180度、190度、200度、210度、220度、230度、240度、250等)，退火气氛是空气，退火时间为0.5-1小时(例如0.5小时、0.6小时、0.7小时、0.8小时、0.9小时、1小时等)。
在本公开实施例的一种实现形式中，对含有质量分数为0.06％钇元 素的漏极A和/或源极B进行退火处理(退火温度为250℃、退火氛围为空气、退火时间0.5h)，可获得电导率达到58Ms/m、抗氧化性能提高的薄膜晶体管。
在本公开实施例的另外一种实现形式中，对含有质量分数为0.02％钇元素的漏极A和/或源极B进行退火处理(退火温度为250℃、退火氛围为空气、退火时间0.5h)，可获得电导率达到59Ms/m、抗氧化性能提高的薄膜晶体管。
可见，通过将薄膜晶体管的漏极和/或源极设置为掺杂有钇元素、且经过退火处理的含有铜的第一金属薄膜，可提高漏极和/或源极的导电率以及抗氧化性能，减少漏源极与其相接触的结构之间的接触电阻，使薄膜晶体管的性能更加稳定，例如可缩短薄膜晶体管的响应时间。
图4是本公开实施例提供的另一种薄膜晶体管制造方法的流程图，如图4所示，该方法可包括：
步骤201：提供衬底基板1。
衬底基板1可为透明衬底基板，例如玻璃衬底、硅衬底和塑料衬底等。可选的，可预先对提供的衬底基板1进行清理，保证该衬底基板1的清洁。
步骤202：在衬底基板1上形成栅极2。
如图5所示，可在衬底基板1上采用一次构图工艺制成栅极2，例如，在衬底基板1上通过溅射方式形成金属层，然后通过刻蚀工艺得到栅极2。
栅极2可以为金属电极，例如Al(铝)、Cu(铜)、Mo(钼)、Cr(铬)、Ti(钛)等金属电极；栅极2也可以采用多层金属重叠设计而成。
例如，栅极设置为掺杂有钇元素的含有铜的第二金属薄膜，以提高栅极的导电性能与抗氧化性能。为了使位于第二金属薄膜内的钇元素富集到第二金属薄膜的表面而形成致密氧化物，故需要对第二金属薄膜进行退火处理。对第二金属薄膜的退火处理可与第一金属薄膜同时进行退火处理(可参见步骤206)，在本文中并不限制上述两个退火处理的顺序。
步骤203：在栅极2上形成栅绝缘层3。
如图5所示，在栅极2制作完成后，在制作有栅极2的衬底基板1 上制作栅极绝缘层3，例如，在制作有栅极2的衬底基板1上沉积一层栅极绝缘层3。栅极绝缘层3可以为氮化硅或氮氧化硅层。
步骤204：在栅绝缘层3上形成有源层4。
在形成栅极绝缘层3后，可采用一次构图工艺制成有源层4，例如，首先通过沉积方式在栅极绝缘层3上形成一层有源层4，具体可先采用等离子体增强化学气相沉积法(PECVD)，然后通过刻蚀工艺，可具体采用电感耦合等离子体(ICP)，以形成图6所示的有源层4。有源层4可以使用非晶硅、多晶硅，氧化物等制成。
步骤205：在有源层4上形成漏极A和源极B，其中漏极A和/或源极B为掺杂有钇元素的含有铜的第一金属薄膜。
如图6所示，在形成有源层4后，可在制作有有源层4的衬底基板1通过一次构图工艺形成漏极A和源极B，具体为：可先通过磁控溅射工艺，然后采用刻蚀工艺形成如图6所示的漏极A和源极B。沉积漏极A和/或源极B所采用的靶材为掺杂有钇元素的铜板。
步骤206：对薄膜晶体管整体进行退火处理。
在有源层4上形成漏极A和源极B以后，对薄膜晶体管整体进行退火处理，在漏极A和源极B的表面形成络合物Y 2Cu 8的致密氧化层C(参见图1)。同理，栅极也发生同样的化学变化过程。
络合物Y 2Cu 8的致密氧化层C具有致密且超导的特性，既能有效阻挡氧气与第一金属薄膜的表面接触产生氧化而影响薄膜晶体管的特性，又能不对薄膜晶体管的整体导电性产生影响。
在本实施例中，对薄膜晶体管(即掺杂有钇元素的含有铜的第一金属薄膜和第二金属薄膜)进行退火的退火温度为150-250度(例如150度、160度、170度、180度、190度、200度、210度、220度、230度、240度、250等)，退火气氛是空气，退火时间为0.5-1小时(例如0.5小时、0.6小时、0.7小时、0.8小时、0.9小时、1小时等)。
由于本公开实施例中的漏极A和/或源极B为掺杂有钇元素的经过退火处理的第一金属薄膜，使得漏极A和/或源极B的表面分别形成氧化层C(参见图1)，这样的话，本公开实施例的薄膜晶体管中就不需在漏极A和/或源极B上设置缓冲层，这样不仅使薄膜晶体管的制造工艺简单化，而且也避免了在漏极A和/或源极B上设置缓冲层后，带来刻蚀不均匀的问题，从而避免在两层叠加金属层(包括漏极A和/或源 极B所在的金属层、缓冲层)同步刻蚀中形成tip结构(即屋顶结构)。
本公开实施例通过将薄膜晶体管的漏极和/或源极设置为掺杂有钇元素的经过退火处理的第一金属薄膜，可提高漏极和/或源极的导电率以及抗氧化性能，减少漏源极与其相接触的结构之间的接触电阻，使薄膜晶体管的性能更加稳定，例如可缩短薄膜晶体管的响应时间。
图7是本公开实施例提供的另一种薄膜晶体管制造方法的流程图，如图7所示，该方法具体包括：
步骤301：提供衬底基板1。
衬底基板1可以为透明衬底基板，例如玻璃衬底、硅衬底和塑料衬底等。可选的，可预先对提供的衬底基板1进行清理，保证该衬底基板1的清洁。
步骤302：在衬底基板1上形成有源层4。
可在衬底基板1上采用一次构图工艺制成有源层4，例如，首先通过沉积方式在衬底基板1上形成一层有源层4，具体可采用等离子体增强化学气相沉积法，然后通过刻蚀工艺，可具体采用电感耦合等离子体，以形成图8所示的有源层4。
有源层4可以使用非晶硅、多晶硅，氧化物等制成。
步骤303：在有源层4上形成刻蚀阻挡层5。
如图9所示，在形成有源层4后，可在制作有有源层4的衬底基板1沉积刻蚀阻挡层5，并对得到的刻蚀阻挡层5进行一次构图工艺从而形成过孔501。
刻蚀阻挡层5可以为氧化铝、氧化锆等物质。
步骤304：在刻蚀阻挡层5上形成栅极2、漏极A与源极B，其中漏极A与源极B为掺杂有钇元素的含有铜的第一金属薄膜。
如图10所示，可在刻蚀阻挡层5上采用一次构图工艺制成栅极2、漏极A与源极B，例如可先通过磁控溅射工艺，然后采用刻蚀工艺形成如图2所示的栅极2、漏极A与源极B，此时沉积漏极A和/或源极B所采用的靶材为掺杂有钇元素的铜板。
栅极2可以为金属电极，例如Al(铝)、Cu(铜)、Mo(钼)、Cr(铬)、Ti(钛)等金属电极；栅极2也可以采用多层金属重叠设计而成。
例如，栅极可设置为掺杂有钇元素的含有铜的第二金属薄膜，以 增加栅极的导电性能与抗氧化性能。为了使位于第二金属薄膜内的钇元素富集到第二金属薄膜的表面而形成致密氧化物，故需要对第二金属薄膜进行退火处理，可与第一金属薄膜同时进行退火处理(参见步骤305)，在本文中并不限制上述两个退火处理的顺序。
步骤305：对薄膜晶体管整体进行退火处理。
如图2所示，在刻蚀阻挡层5上形成栅极2、漏极A和源极B后，对薄膜晶体管整体进行退火处理，在漏极A和/或源极B的表面形成络合物Y 2Cu 8的致密氧化层C(参见图2)。同理，栅极也发生同样的化学变化过程。
在本公开实施例中，对薄膜晶体管(即掺杂有钇元素的含有铜的第一金属薄膜和第二金属薄膜)进行退火的退火温度为150-250度(例如150度、160度、170度、180度、190度、200度、210度、220度、230度、240度、250等)，退火气氛是空气，退火时间为0.5-1小时(例如0.5小时、0.6小时、0.7小时、0.8小时、0.9小时、1小时等)。
由于本公开实施例中的漏极A和/或源极B为掺杂有钇元素，并经过退火处理的第一金属薄膜，使得漏极A和/或源极B的表面分别形成致密氧化层C(参见图2)，这样的话，本公开实施例的薄膜晶体管中就不需在漏极A和/或源极B上设置缓冲层，这样不仅使薄膜晶体管的制造工艺简单化，而且也避免在两层叠加金属层(包括漏极A和/或源极B所在的金属层以及缓冲层)同时刻蚀中形成tip结构(即屋顶结构)。
本公开实施例通过将薄膜晶体管的漏极和/源极设置为掺杂有钇元素的经过退火处理的第一金属薄膜，可提高漏极和/源极的导电率以及抗氧化性能，减少漏源极与其相接触的结构之间的接触电阻，使薄膜晶体管的性能更加稳定，例如可缩短薄膜晶体管的响应时间。
本公开实施例还提供了一种阵列基板，该阵列基板包括图1所示出的薄膜晶体管。
本公开的薄膜晶体管的漏极和/或源极为掺杂有钇元素的经过退火处理的第一金属薄膜，可提高漏极和/或源极的导电率以及抗氧化性能，减少漏源极与其相接触的结构之间的接触电阻，使薄膜晶体管的性能更加稳定，例如可缩短薄膜晶体管的响应时间。
本公开实施例还提供了一种显示面板，该显示面板包括上述阵列基板。
在具体实施时，本公开实施例提供的显示面板可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示面板的产品。
本公开实施例的薄膜晶体管的漏极和/或源极为掺杂有钇元素的经过退火处理的第一金属薄膜，可提高漏极和/或源极的导电率以及抗氧化性能，减少漏源极与其相接触的结构极之间的接触电阻，使薄膜晶体管的性能更加稳定，例如可缩短薄膜晶体管的响应时间。
本公开实施例通过在显示面板中采用前文所述的阵列基板，可获得低功率、高响应速度的显示面板。
本公开实施例还提供了一种显示装置，该显示装置包括上述显示面板。
在具体实施时，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示装置的产品。
本公开实施例的薄膜晶体管的漏极和/或源极为掺杂有钇元素的经过退火处理的第一金属薄膜，可提高漏极和/或源极的导电率以及抗氧化性能，减少漏源极与其相接触的结构之间的接触电阻，使薄膜晶体管的性能更加稳定，例如可缩短薄膜晶体管的响应时间。
本公开实施例通过在显示装置中采用前文所述的显示面板，可获得低功率、高响应速度的显示装置。
上述所有可选技术方案，可以采用任意结合形成本公开的可选实施例，在此不再一一赘述。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种薄膜晶体管，其中所述薄膜晶体管包括漏极和源极，所述漏极和/或所述源极为掺杂有钇元素的含有铜的第一金属薄膜，且所述第一金属薄膜的表面为经过退火处理形成的钇铜氧化物。
  2. 根据权利要求1所述的薄膜晶体管，其中所述第一金属薄膜的材料为铜或者铜合金。
  3. 根据权利要求2所述的薄膜晶体管，其中所述第一金属薄膜的材料为铜，且所述钇元素的掺杂量的质量分数为小于0.06％且大于0.005％。
  4. 根据权利要求3所述的薄膜晶体管，其中所述钇元素的掺杂量的质量分数为0.02％。
  5. 根据权利要求1所述的薄膜晶体管，其中所述薄膜晶体管还包括栅极，所述栅极为掺杂有钇元素的含有铜的第二金属薄膜，且所述第二金属薄膜的表面为经过退火处理形成的钇铜氧化物。
  6. 根据权利要求1所述的薄膜晶体管，其中所述第一金属薄膜的表面为络合物Y 2Cu 8的氧化物。
  7. 根据权利要求5所述的薄膜晶体管，其中所述第二金属薄膜的表面为络合物Y 2Cu 8的氧化物。
  8. 一种薄膜晶体管制造方法，包括：
    形成漏极和源极，其中所述漏极和/或所述源极为掺杂有钇元素的含有铜的第一金属薄膜；以及
    对所述第一金属薄膜进行退火处理，使所述第一金属薄膜的表面形成钇铜氧化物。
  9. 根据权利要求8所述的方法，其中所述第一金属薄膜的材料为铜或者铜合金。
  10. 根据权利要求9所述的方法，其中所述第一金属薄膜的材料为铜，且所述钇元素的掺杂量的质量分数为小于0.06％且大于0.005％。
  11. 根据权利要求10所述的方法，其中所述钇元素的掺杂量的质量分数为0.02％。
  12. 根据权利要求8所述的方法，还包括：
    形成栅极，所述栅极为掺杂有钇元素的含有铜的第二金属薄膜； 以及
    对所述第二金属薄膜进行退火处理，使所述第二金属薄膜的表面形成钇铜氧化物。
  13. 根据权利要求8所述的方法，其中对所述第一金属薄膜进行退火处理，使所述第一金属薄膜的表面形成钇铜氧化物，包括：对所述第一金属薄膜进行退火处理，使所述第一金属薄膜的表面形成络合物Y 2Cu 8的氧化物。
  14. 根据权利要求12所述的方法，其中对所述第二金属薄膜进行退火处理，使所述第二金属薄膜的表面形成钇铜氧化物，包括：对所述第二金属薄膜进行退火处理，使所述第二金属薄膜的表面形成络合物Y 2Cu 8的氧化物。
  15. 一种阵列基板，包括权利要求1-7任一项所述的薄膜晶体管。
  16. 一种显示面板，包括权利要求15所述的阵列基板。
  17. 一种显示装置，包括权利要求16所述的显示面板。
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