WO2018205322A1 - 移位元暂存电路及其波形产生方法与其应用的显示面板 - Google Patents

移位元暂存电路及其波形产生方法与其应用的显示面板 Download PDF

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Publication number
WO2018205322A1
WO2018205322A1 PCT/CN2017/086645 CN2017086645W WO2018205322A1 WO 2018205322 A1 WO2018205322 A1 WO 2018205322A1 CN 2017086645 W CN2017086645 W CN 2017086645W WO 2018205322 A1 WO2018205322 A1 WO 2018205322A1
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Prior art keywords
switch
electrically coupled
pulse signal
shift register
node
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PCT/CN2017/086645
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English (en)
French (fr)
Inventor
陈猷仁
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US15/546,123 priority Critical patent/US10453412B2/en
Publication of WO2018205322A1 publication Critical patent/WO2018205322A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present application relates to a circuit structure in a display, and more particularly to a display device for a shifting element temporary storage circuit and a waveform generating method thereof and an application thereof.
  • planar liquid crystal display driving circuit is mainly composed of an external IC connected to the panel, but this method cannot reduce the cost of the product and can not make the panel thinner.
  • a liquid crystal display device usually has a gate driving circuit, a source driving circuit, and a pixel array.
  • the pixel array has a plurality of pixel circuits, each pixel circuit is turned on and off according to a scan signal provided by the gate driving circuit, and displays a data picture according to the data signal provided by the source driving circuit.
  • the gate driving circuit usually has a multi-stage shift register, and outputs the scanning signal to the pixel array by means of the first-stage shift register being transferred to the next-stage shift register.
  • the pixel circuit is sequentially turned on to enable the pixel circuit to receive the data signal.
  • the gate driving circuit is directly fabricated on the array substrate instead of the driving chip fabricated by the external connection IC.
  • This is called Gate On Array (GOA) technology.
  • Applications can be used directly around the panel, reducing production processes, reducing product costs and making the panel thinner.
  • the potential pull-down of the current Gate Array Drive (GOA) technology is controlled by two sets of signals, with a duty cycle of 50%. Under such conditions, the transistor responsible for the pull-down potential will be in a positive voltage state for a long time and cannot be fully rested, which will cause the reliability of these transistors to rapidly drop and generate a risk of leakage, thereby directly causing a drop in display quality or even a display device. damage. Therefore, how to improve the above-mentioned conventional gate array driving circuit substrate technology is lacking, and thus a gate array shift register with low fabrication cost and easy processing is proposed.
  • an object of the present invention is to provide a shifting element temporary storage circuit, a waveform generating method thereof and a display panel thereof, which solve the problem of leakage of a gate array driving circuit substrate and improve product reliability. And service life.
  • a shifting element temporary storage circuit includes a multi-stage shift register, each shift register includes: a first switch, a control end of the first switch is electrically coupled to a first node a first end of the first switch is electrically coupled to a frequency signal, a second end of the first switch is electrically coupled to an output pulse signal, and a second switch is coupled to the second switch
  • the control terminal is electrically coupled to the input pulse signal, a first end of the second switch is electrically coupled to the input pulse signal, and a second end of the second switch is electrically coupled to the first node a third switch, a control end of the third switch is electrically coupled to a second node, and a first end of the third switch is electrically coupled to the Outputting a pulse signal, a second end of the third switch is electrically coupled to a low preset potential; and a fourth switch, a control end of the fourth switch is electrically coupled to the second node,
  • a first switch a control end of the first switch is electrically coupled to a first node
  • Another object of the present application is a waveform generation method for a shift meta temporary storage circuit for a multi-stage shift register, wherein the shift register includes a first switch, a second switch, a third switch, and a a fourth switch, a compensation circuit, a sub-drain circuit and a sub-drain circuit controller, the first switch is configured to generate an output pulse signal of the shift register, and provide the next stage shift register,
  • the waveform generating method includes: turning on the first switch, and pulling up a potential of an output end of the shift register by a frequency signal; and reducing a control end of the fourth switch by adding a compensation circuit a potential difference at one end; and pulling the potential of the output terminal of the shift register via the second switch and the sub-pull-down circuit through the input pulse signal.
  • the method further includes a compensation circuit, including: a fifth switch, a control end of the fifth switch is electrically coupled to the output pulse signal, and a first switch The second end of the fifth switch is electrically coupled to the low preset potential.
  • a sub-pull-down circuit is further coupled to the first node, the output pulse signal, and the low preset potential in the shift register.
  • a sub-pull-down circuit controller is further coupled to the low preset potential of the shift register and the sub-pull-down circuit.
  • the compensation circuit is configured to reduce a potential difference between the control end and the first end of the fourth switch.
  • the waveform generating method the step of reducing a potential difference between a control terminal and a first terminal in the fourth switch by adding a compensation circuit includes: in the shift register Adding a fifth switch, a control end of the fifth switch is electrically coupled to an output pulse signal, a first end of the fifth switch is electrically coupled to the output pulse signal, and the fifth switch is A second end is electrically coupled to a low preset potential.
  • the waveform generating method further includes a sub-pull-down circuit electrically coupled to the first node in the shift register, the output pulse signal, and the low pre- Set the potential.
  • the waveform generating method further includes a sub-pull-down circuit controller electrically coupled to the low preset potential of the shift register and the sub-pull-down circuit.
  • the waveform generating method is configured to reduce a potential difference between a control end and a first end of the fourth switch.
  • a display panel of the present invention includes a first substrate, a plurality of pixels formed on the first substrate, and a shifting unit temporary storage circuit disposed on the first substrate.
  • the application solves the problem of leakage of the grid array driving circuit substrate and improves the reliability and service life of the product.
  • Figure 1a is a schematic diagram of an exemplary liquid crystal display.
  • FIG. 1b is a schematic diagram of a liquid crystal display according to an embodiment of the present application.
  • FIG. 1c is a schematic diagram of a boost point waveform in an exemplary gate drive circuit substrate.
  • 2a is a schematic diagram of an exemplary shifting element temporary storage circuit.
  • Figure 2b is a schematic diagram of waveforms due to leakage in an exemplary shifting element temporary storage circuit.
  • 2c is a schematic diagram of potential differences due to leakage in an exemplary shifting element temporary storage circuit.
  • 2d is a schematic diagram of a transistor in an exemplary shift cell temporary storage circuit.
  • FIG. 3a is a schematic diagram of a shifting unit temporary storage circuit according to an embodiment of the present application.
  • FIG. 3b is a schematic diagram of a compensation circuit in a shift element temporary storage circuit according to an embodiment of the present application.
  • Figure 4a is a schematic illustration of the distance between the first end and the second end internal passage of an exemplary active switch.
  • 4b is a schematic diagram of the distance between the first end and the second end internal passage in the active switch according to an embodiment of the present application.
  • 4c is a schematic diagram of the distance between the first end and the second end of the active switch in another embodiment of the present application.
  • FIG. 5 is a schematic diagram of a liquid crystal display panel according to another embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means that it is above or below the target component, and not It means that it must be on the top based on the direction of gravity.
  • the display panel of the present application may be, for example, a liquid crystal display panel, which may include a thin film transistor (TFT) substrate, a color filter (CF) substrate, and a liquid crystal layer formed between the two substrates.
  • TFT thin film transistor
  • CF color filter
  • the active array (TFT) and the color filter layer (CF) of the present application may be formed on the same substrate.
  • the liquid crystal panel of the present application may be a curved display panel.
  • FIG. 1a is a schematic diagram of an exemplary liquid crystal display.
  • a liquid crystal display 10 includes a color filter substrate 100, an active array substrate 110, and a driving chip 103 for driving the circuit.
  • FIG. 1b is a schematic diagram of a liquid crystal display according to an embodiment of the present application.
  • a liquid crystal display 11 having a gate array driving includes a color filter substrate 100, an active array substrate 110, and a gate array driver 105.
  • a gate driving circuit is formed on the array substrate 110.
  • FIG. 1c is a schematic diagram of a boost point waveform in an exemplary gate drive circuit substrate.
  • a waveform 120 of a lifting point in a gate driving circuit substrate wherein the waveform 120 has a high voltage level 125.
  • a shifting unit temporary storage circuit includes a multi-stage shift register.
  • Each shift register 200 includes a first switch T10, and a control terminal 101a of the first switch T10 is electrically coupled.
  • a first node P1(n) a first end 101b of the first switch T10 is electrically coupled to a frequency signal CK, and a second end 101c of the first switch T10 is electrically coupled to an output pulse signal.
  • a second switch T20, a control terminal 201a of the second switch T20 is electrically coupled to an input pulse signal ST, and a first end 201b of the second switch T20 is electrically coupled to the input pulse signal.
  • a second end 201c of the second switch T20 is electrically coupled to the first node P1(n); a third switch T30, a control end 301a of the third switch T30 is electrically coupled a second node P2(n), a first end 301b of the third switch T30 is electrically coupled to the output pulse signal Gn, and a second end 301c of the third switch T30 is electrically coupled to a low pre- a potential Vss; and a fourth switch T40, a control terminal 401a of the fourth switch T40 is electrically coupled to the second node P2(n), and a fourth switch T40 Terminal 401b is electrically coupled to the first node P1 (n), a second end 401c of the fourth switch T40 is electrically coupled to the predetermined low potential Vss.
  • a sub-pull circuit 220 is further coupled to the first node P1(n), the output pulse signal Gn, and the low preset potential in the shift register 200. Vss.
  • a sub-pull circuit controller 210 is further coupled to the low preset potential Vss of the shift register 200 and the sub-pull circuit 220.
  • FIG. 2b is a schematic diagram of waveforms generated by leakage in an exemplary shifting element temporary storage circuit
  • FIG. 2c is a schematic diagram of potential difference due to leakage in an exemplary shifting element temporary storage circuit
  • FIG. 2d is an exemplary Schematic diagram of the transistor in the shift meta temporary circuit. Referring to FIG. 2b, a waveform 250 generated by a leakage of a lift point in a gate drive circuit substrate, wherein the waveform 250 has a chamfered waveform 255.
  • control terminal 401a of the fourth switch T40 has a potential waveform 270 and a potential waveform 260 of the first end 401b.
  • the transistor 280 in the fourth switch T40 has a current flow direction as shown in FIG. 2d.
  • FIG. 3a is a schematic diagram of a shifting unit temporary storage circuit according to an embodiment of the present invention
  • FIG. 3b is a schematic diagram of a compensation circuit in a shifting element temporary storage circuit according to an embodiment of the present application
  • FIG. 4a is a first end of an exemplary active switch
  • FIG. 4b is a schematic diagram of the distance between the first end and the second end internal passage in the active switch according to an embodiment of the present invention
  • FIG. 4c is an active switch in another embodiment of the present application. Schematic diagram of the distance between the first end and the second internal end of the second end. Referring to FIG. 3a, FIG. 3b, FIG. 4a, FIG. 4b and FIG.
  • a shifting element temporary storage circuit includes a multi-stage shift register, and each shift register 300 includes: a first switch T10, a control terminal 101a of the first switch T10 is electrically coupled to a first node P1(n), and a first end 101b of the first switch T10 is electrically coupled to a frequency signal CK.
  • a second end 101c of the first switch T10 is electrically coupled to an output pulse signal Gn; a second switch T20, a control end 201a of the second switch T20 is electrically coupled to an input pulse signal ST, a first end 201b of the second switch T20 is electrically coupled to the input pulse signal ST, and a second end 201c of the second switch T20 is electrically coupled to the first node P1(n); a third switch T30, a control terminal 301a of the third switch T30 is electrically coupled to a second node P2(n), and a first end 301b of the third switch T30 is electrically coupled to the output pulse signal Gn a second terminal 301c of the third switch T30 is electrically coupled to a low preset potential Vss; and a fourth switch T40, a control terminal 401a of the fourth switch T40 is electrically Connected to the second node P2(n), a first end 401b of the fourth switch T40 is electrically coupled to the first node P
  • a compensation circuit 500 is further included, including: a fifth switch T50, a control terminal 501a of the fifth switch T50 is electrically coupled to the output pulse signal Gn, and the fifth switch T50 A first end 501b is electrically coupled to the output pulse signal Gn, and a second end 501c of the fifth switch T50 is electrically coupled to the low preset potential Vss.
  • a sub-pull circuit 220 is further coupled to the first node P1(n), the output pulse signal Gn, and the low preset potential in the shift register 300. Vss.
  • a sub-pull circuit controller 210 is further coupled to the low pre-control of the shift register 300.
  • a potential Vss and the sub-down pull circuit 220 are provided.
  • the compensation circuit 500 is configured to reduce a potential difference between the control terminal 401a and the first terminal 401b of the fourth switch T40 to avoid leakage.
  • a waveform generating method of a shifting unit temporary storage circuit is provided for a multi-stage shift register, wherein the shift register 300 includes a first switch T10. a second switch T20, a third switch T30, a fourth switch T40, a compensation circuit 500, a sub-pull circuit 220 and a sub-pull circuit controller 210, the first switch T10 is used to generate the shift An output pulse signal Gn of the bit register 300 is supplied to the next stage shift register.
  • the waveform generating method includes: turning on the first switch T10, and pulling up the shift register 300 by a frequency signal CK.
  • a potential of an output terminal a potential difference between the control terminal 401a and the first terminal 401b in the fourth switch T40 is reduced by adding a compensation circuit 500; and the second switch T20 is passed through the input pulse signal ST and The sub-pull-down circuit 220 pulls down the potential of the output terminal of the shift register 300.
  • the waveform generating method, the step of reducing a potential difference between the control terminal 401a and the first terminal 401b in the fourth switch T40 by adding a compensation circuit 500 includes: shifting A fifth switch T50 is added to the register 300.
  • a control terminal 501a of the fifth switch T50 is electrically coupled to an output pulse signal Gn.
  • a first end 501b of the fifth switch T50 is electrically coupled to the output pulse.
  • a second end 501c of the fifth switch T50 is electrically coupled to a low preset potential Vss.
  • the waveform generating method further includes a sub-pull circuit 220 electrically coupled to the first node P1(n), the output pulse signal Gn, and the shift register 300.
  • the low preset potential Vss is the low preset potential.
  • the waveform generating method further includes a sub-pull circuit controller 210 electrically coupled to the low preset potential Vss of the shift register 300 and the sub-pull circuit 220.
  • the waveform generating method is configured to reduce a potential difference between the control terminal 401a and the first terminal 401b in the fourth switch T40 to prevent leakage.
  • FIG. 5 is a schematic diagram of a liquid crystal display panel according to another embodiment of the present application.
  • a liquid crystal display panel 30 includes: a first substrate 301 (eg, an active array substrate); a second substrate 302 (eg, a color filter substrate), and The first substrate 301 is oppositely disposed; the liquid crystal layer 303 is disposed between the first substrate 301 and the second substrate 302; and further includes the shifting element temporary storage circuit 300, disposed at the first The substrate 301 is interposed between the second substrate 302 (for example, on the surface of the first substrate 301).
  • first polarizer 306 disposed on an outer surface of the first substrate 301; and a second polarizer 307 disposed on an outer surface of the second substrate 302, wherein the first polarizer 306
  • the polarization directions with the second polarizer 307 are parallel to each other.
  • the display panel may be an OLED display panel, a QLED display panel, or a plasma display panel and
  • the display panel includes: a first substrate; a plurality of pixels formed on the first substrate; and a shifting unit temporary storage circuit 300 disposed on the first substrate.
  • the application solves the problem of leakage of the grid array driving circuit substrate and improves the reliability and service life of the product.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种移位元暂存电路及其波形产生方法与其应用的显示面板，移位元暂存电路包括：多级移位寄存器(300)，其包括：第一开关(T10)，此第一开关(T10)的控制端(101a)电性耦接第一节点(P1(n))，此第一开关(T10)的第一端(101b)电性耦接频率讯号(CK)，此第一开关(T10)的第二端(101c)电性耦接输出脉冲讯号(Gn)；第二开关(T20)，此第二开关(T20)的控制端(201a)电性耦接输入脉冲讯号(ST)，此第二开关(T20)的第一端(201b)电性耦接此输入脉冲讯号(ST)，此第二开关(T20)的第二端(201c)电性耦接此第一节点(P1(n))；第三开关(T30)，此第三开关(T30)的控制端(301a)电性耦接第二节点(P2(n))，此第三开关(T30)的第一端(301b)电性耦接此输出脉冲讯号(Gn)，此第三开关(T30)的第二端(301c)电性耦接低预设电位(Vs)；以及第四开关(T40)，此第四开关(T40)的控制端(401a)电性耦接此第二节点(P2(n))，此第四开关(T40)的第一端(401b)电性耦接此第一节点(P1(n))，此第四开关(T40)的第二端(401c)电性耦接此低预设电位(Vss)；其中此第四开关(T40)的第一端(401b)与第二端(401c)的内部通道之间距离(L)加大，或此第四开关(T40)的第一端(401b)与第二端(401c)的内部通道之间距离(L)设计为双通道(L2、L3)。

Description

移位元暂存电路及其波形产生方法与其应用的显示面板 技术领域
本申请涉及一种显示器中的电路结构，特别是涉及一种移位元暂存电路及其波形产生方法与其应用的显示面板。
背景技术
近年来，随着科技的进步，平面液晶显示器逐渐普及化，其具有轻薄等优点。目前平面液晶显示器驱动电路主要是由面板外连接IC来组成，但是此方法无法将产品的成本降低、也无法使面板更薄型化。
且液晶显示设备中通常具有栅极驱动电路、源极驱动电路和画素阵列。画素阵列中具有多个画素电路，每一个画素电路依据栅极驱动电路提供的扫描讯号开启和关闭，并依据源极驱动电路提供的数据讯号，显示数据画面。以栅极驱动电路来说，栅极驱动电路通常具有多级移位寄存器，并藉由一级移位寄存器传递至下一级移位寄存器的方式，来输出扫描讯号到画素阵列中，以依序地开启画素电路，使画素电路接收数据讯号。
因此在驱动电路的制程中，便直接将栅极驱动电路制作在阵列基板上，来取代由外连接IC制作的驱动芯片，此种被称为栅极阵列驱动(Gate On Array，GOA)技术的应用可直接做在面板周围，减少制作程序、降低产品成本且使面板更薄型化。但是现行栅极阵列驱动(GOA)技术的电位下拉是由两组讯号轮流进行控制，工作周期为50％。在此种条件下，负责下拉电位的晶体管会长时间处于正压状态而无法得到充分休息，如此将使得这些晶体管的可靠度快速下降并产生漏电风险，进而直接造成显示质量的低落甚或显示设备的损坏。因此，如何改善上述惯用栅极阵列驱动电路基板技术的缺失，因而提出一种制作成本低且加工容易的栅极阵列移位寄存器。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种移位元暂存电路及其波形产生方法与其应用的显示面板，解决了栅极阵列驱动电路基板漏电的问题，并提高产品的信赖性和使用寿命。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种移位元暂存电路，包括多级移位寄存器，每一移位寄存器包括：一第一开关，所述第一开关的一控制端电性耦接一第一节点，所述第一开关的一第一端电性耦接一频率讯号，所述第一开关的一第二端电性耦接一输出脉冲讯号；一第二开关，所述第二开关的一控制端电性耦接一输入脉冲讯号，所述第二开关的一第一端电性耦接所述输入脉冲讯号，所述第二开关的一第二端电性耦接所述第一节点；一第三开关，所述第三开关的一控制端电性耦接一第二节点，所述第三开关的一第一端电性耦接所述 输出脉冲讯号，所述第三开关的一第二端电性耦接一低预设电位；以及一第四开关，所述第四开关的一控制端电性耦接所述第二节点，所述第四开关的一第一端电性耦接所述第一节点，所述第四开关的一第二端电性耦接所述低预设电位；其中所述第四开关的第一端与第二端的内部通道之间距离加大，或所述第四开关的第一端与第二端的内部通道之间距离设计为双通道。
本申请的另一目的一种移位元暂存电路的波形产生方法，用于多级移位寄存器，其中所述移位寄存器包括一第一开关、一第二开关、一第三开关、一第四开关、一补偿电路、一子下拉电路及一子下拉电路控制器，所述第一开关用以产生所述移位寄存器的一输出脉冲讯号，并提供至下一级移位寄存器，所述波形产生方法包括：导通所述第一开关，并通过一频率讯号上拉所述移位寄存器的一输出端的电位；通过增加一补偿电路来降低所述第四开关中的控制端与第一端的电位差；以及通过所述输入脉冲讯号经由所述第二开关及所述子下拉电路，以下拉所述移位寄存器的所述输出端的电位。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，更包括一补偿电路，包括：一第五开关，所述第五开关的一控制端电性耦接所述输出脉冲讯号，所述第五开关的一第一端电性耦接所述输出脉冲讯号，所述第五开关的一第二端电性耦接所述低预设电位。
在本申请的一实施例中，更包括一子下拉电路，电性耦接于所述移位寄存器中的所述第一节点、所述输出脉冲讯号及所述低预设电位。
在本申请的一实施例中，更包括一子下拉电路控制器，电性耦接于所述移位寄存器的所述低预设电位及所述子下拉电路。
在本申请的一实施例中，所述补偿电路用以降低所述第四开关中的控制端与第一端的电位差。
在本申请的一实施例中，所述波形产生方法，所述通过增加一补偿电路来降低所述第四开关中的控制端与第一端的电位差的步骤包括：在所述移位寄存器中增加第五开关，所述第五开关的一控制端电性耦接一输出脉冲讯号，所述第五开关的一第一端电性耦接所述输出脉冲讯号，所述第五开关的一第二端电性耦接一低预设电位。
在本申请的一实施例中，所述波形产生方法，更包括一子下拉电路，电性耦接于所述移位寄存器中的所述第一节点、所述输出脉冲讯号及所述低预设电位。
在本申请的一实施例中，所述波形产生方法，更包括一子下拉电路控制器，电性耦接于所述移位寄存器的所述低预设电位及所述子下拉电路。
在本申请的一实施例中，所述波形产生方法，所述补偿电路用以降低所述第四开关中的控制端与第一端的电位差。
本申请的再一目的一种显示面板，包括：第一基板；多个像素，形成于所述第一基板上；还包括所述的移位元暂存电路，设置于所述第一基板。
有益效果
本申请解决了栅极阵列驱动电路基板漏电的问题，并提高产品的信赖性和使用寿命。
附图说明
图1a是范例性的液晶显示器示意图。
图1b是本申请一实施例的液晶显示器示意图。
图1c是范例性的栅极驱动电路基板中的提升点波形示意图。
图2a是范例性的移位元暂存电路示意图。
图2b是范例性的移位元暂存电路中的因漏电所产生的波形示意图。
图2c是范例性的移位元暂存电路中的因漏电所产生的电位差示意图。
图2d是范例性的移位元暂存电路中的晶体管示意图。
图3a是本申请一实施例的移位元暂存电路示意图。
图3b是本申请一实施例的移位元暂存电路中的补偿电路示意图。
图4a是范例性的主动开关中第一端与第二端内部通道之间距离示意图。
图4b是本申请一实施例的主动开关中第一端与第二端内部通道之间距离示意图。
图4c是本申请另一实施例的主动开关中第一端与第二端内部双通道之间距离示意图。
图5是本申请另一实施例的液晶显示面板示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不 意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种移位元暂存电路及其波形产生方法与其应用的显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
本申请的显示面板可例如为液晶显示面板，其可包括主动阵列(thin film transistor，TFT)基板、彩色滤光层(color filter，CF)基板与形成于两基板之间的液晶层。在一实施例中，本申请的主动阵列(TFT)及彩色滤光层(CF)可形成于同一基板上。
在一实施例中，本申请的液晶面板可为曲面型显示面板。
图1a为范例性的液晶显示器示意图。请参照图1a，一种液晶显示器10，包括一彩色滤光片基板100、一主动阵列基板110及一驱动芯片103，用以驱动电路。
图1b为本申请一实施例的液晶显示器示意图。请参照图1b，在本申请一实施例中，一种具有栅极阵列驱动的液晶显示器11，包括一彩色滤光片基板100、一主动阵列基板110及一栅极阵列驱动105，用以将栅极驱动电路制作在阵列基板110上。
图1c为范例性的栅极驱动电路基板中的提升点波形示意图。请参照图1c，一种栅极驱动电路基板中的提升点的波形120，其中所述波形120具有一高电压准位125。
图2a为范例性的移位元暂存电路示意图。请参图2a，一种移位元暂存电路，包括多级移位寄存器，每一移位寄存器200包括：一第一开关T10，所述第一开关T10的一控制端101a电性耦接一第一节点P1(n)，所述第一开关T10的一第一端101b电性耦接一频率讯号CK，所述第一开关T10的一第二端101c电性耦接一输出脉冲讯号Gn；一第二开关T20，所述第二开关T20的一控制端201a电性耦接一输入脉冲讯号ST，所述第二开关T20的一第一端201b电性耦接所述输入脉冲讯号ST，所述第二开关T20的一第二端201c电性耦接所述第一节点P1(n)；一第三开关T30，所述第三开关T30的一控制端301a电性耦接一第二节点P2(n)，所述第三开关T30的一第一端301b电性耦接所述输出脉冲讯号Gn，所述第三开关T30的一第二端301c电性耦接一低预设电位Vss；以及一第四开关T40，所述第四开关T40的一控制端401a电性耦接所述第二节点P2(n)，所述第四开关T40的一第一端401b电性耦接所述第一节点P1(n)，所述第四开关T40的一第二端401c电性耦接所述低预设电位Vss。
在一实施例中，更包括一子下拉电路220，电性耦接于所述移位寄存器200中的所述第一节点P1(n)、所述输出脉冲讯号Gn及所述低预设电位Vss。
在一实施例中，更包括一子下拉电路控制器210，电性耦接于所述移位寄存器200的所述低预设电位Vss及所述子下拉电路220。
图2b为范例性的移位元暂存电路中的因漏电所产生的波形示意图、图2c为范例性的移位元暂存电路中的因漏电所产生的电位差示意图及图2d为范例性的移位元暂存电路中的晶体管示意图。请参照图2b，一种栅极驱动电路基板中的提升点因漏电所产生的波形250，其中所述波形250具有一削角波形255。
请参照图2a及图2c，在一实施例中，所述第四开关T40中的控制端401a电位波形270与第一端401b的电位波形260。
请参照图2a及图2d，在一实施例中，所述第四开关T40中的晶体管280电流流动方向，其如图2d所示。
图3a为本申请一实施例的移位元暂存电路示意图、图3b为本申请一实施例的移位元暂存电路中的补偿电路示意图、图4a为范例性的主动开关中第一端与第二端内部通道之间距离示意图、图4b为本申请一实施例的主动开关中第一端与第二端内部通道之间距离示意图、图4c为本申请另一实施例的主动开关中第一端与第二端内部双通道之间距离示意图。请参图3a、图3b、图4a、图4b及图4c，在本申请一实施例中，一种移位元暂存电路，包括多级移位寄存器，每一移位寄存器300包括：一第一开关T10，所述第一开关T10的一控制端101a电性耦接一第一节点P1(n)，所述第一开关T10的一第一端101b电性耦接一频率讯号CK，所述第一开关T10的一第二端101c电性耦接一输出脉冲讯号Gn；一第二开关T20，所述第二开关T20的一控制端201a电性耦接一输入脉冲讯号ST，所述第二开关T20的一第一端201b电性耦接所述输入脉冲讯号ST，所述第二开关T20的一第二端201c电性耦接所述第一节点P1(n)；一第三开关T30，所述第三开关T30的一控制端301a电性耦接一第二节点P2(n)，所述第三开关T30的一第一端301b电性耦接所述输出脉冲讯号Gn，所述第三开关T30的一第二端301c电性耦接一低预设电位Vss；以及一第四开关T40，所述第四开关T40的一控制端401a电性耦接所述第二节点P2(n)，所述第四开关T40的一第一端401b电性耦接所述第一节点P1(n)，所述第四开关T40的一第二端401c电性耦接所述低预设电位Vss；其中所述第四开关T40的第一端401b与第二端401c的内部通道之间距离L加大为L1，或所述第四开关T40的第一端401b与第二端401c的内部通道之间距离L设计为双通道L2、L3。
在一实施例中，更包括一补偿电路500，包括：一第五开关T50，所述第五开关T50的一控制端501a电性耦接所述输出脉冲讯号Gn，所述第五开关T50的一第一端501b电性耦接所述输出脉冲讯号Gn，所述第五开关T50的一第二端501c电性耦接所述低预设电位Vss。
在一实施例中，更包括一子下拉电路220，电性耦接于所述移位寄存器300中的所述第一节点P1(n)、所述输出脉冲讯号Gn及所述低预设电位Vss。
在一实施例中，更包括一子下拉电路控制器210，电性耦接于所述移位寄存器300的所述低预 设电位Vss及所述子下拉电路220。
在一实施例中，所述补偿电路500用以降低所述第四开关T40中的控制端401a与第一端401b的电位差，以避免产生漏电。
请参图3a及图3b，在本申请一实施例中，一种移位元暂存电路的波形产生方法，用于多级移位寄存器，其中所述移位寄存器300包括一第一开关T10、一第二开关T20、一第三开关T30、一第四开关T40、一补偿电路500、一子下拉电路220及一子下拉电路控制器210，所述第一开关T10用以产生所述移位寄存器300的一输出脉冲讯号Gn，并提供至下一级移位寄存器，所述波形产生方法包括：导通所述第一开关T10，并通过一频率讯号CK上拉所述移位寄存器300的一输出端的电位；通过增加一补偿电路500来降低所述第四开关T40中的控制端401a与第一端401b的电位差；以及通过所述输入脉冲讯号ST经由所述第二开关T20及所述子下拉电路220，以下拉所述移位寄存器300的所述输出端的电位。
在一实施例中，所述波形产生方法，所述通过增加一补偿电路500来降低所述第四开关T40中的控制端401a与第一端401b的电位差的步骤包括：在所述移位寄存器300中增加第五开关T50，所述第五开关T50的一控制端501a电性耦接一输出脉冲讯号Gn，所述第五开关T50的一第一端501b电性耦接所述输出脉冲讯号Gn，所述第五开关T50的一第二端501c电性耦接一低预设电位Vss。
在一实施例中，所述波形产生方法，更包括一子下拉电路220，电性耦接于所述移位寄存器300中的所述第一节点P1(n)、所述输出脉冲讯号Gn及所述低预设电位Vss。
在一实施例中，所述波形产生方法，更包括一子下拉电路控制器210，电性耦接于所述移位寄存器300的所述低预设电位Vss及所述子下拉电路220。
在一实施例中，所述波形产生方法，所述补偿电路500用以降低所述第四开关T40中的控制端401a与第一端401b的电位差以避免产生漏电。
图5为本申请另一实施例的液晶显示面板示意图。请参照图5及图3a，在本申请的一实施例中，一种液晶显示面板30包括：第一基板301(例如主动阵列基板)；第二基板302(例如彩色滤光片基板)，与所述第一基板301相对设置；液晶层303，设置于所述第一基板301与所述第二基板302之间；且还包括所述移位元暂存电路300，设置于所述第一基板301与所述第二基板302之间(例如位于所述第一基板301的表面)。且更包括第一偏光片306设置于所述第一基板301的一外表面上；以及第二偏光片307设置于所述第二基板302的一外表面上，其中所述第一偏光片306与所述第二偏光片307的偏振方向为互相平行。
在其他实施例中，显示面板可为OLED显示面板、QLED显示面板或等离子体显示面板及其 他显示面板，所述显示面板包括：第一基板；多个像素，形成于所述第一基板上；还包括所述的移位元暂存电路300，设置于所述第一基板。
本申请解决了栅极阵列驱动电路基板漏电的问题，并提高产品的信赖性和使用寿命。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的较佳实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以较佳实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (15)

  1. 一种移位元暂存电路，包括多级移位寄存器，每一移位寄存器包括：
    一第一开关，所述第一开关的一控制端电性耦接一第一节点，所述第一开关的一第一端电性耦接一频率讯号，所述第一开关的一第二端电性耦接一输出脉冲讯号；
    一第二开关，所述第二开关的一控制端电性耦接一输入脉冲讯号，所述第二开关的一第一端电性耦接所述输入脉冲讯号，所述第二开关的一第二端电性耦接所述第一节点；
    一第三开关，所述第三开关的一控制端电性耦接一第二节点，所述第三开关的一第一端电性耦接所述输出脉冲讯号，所述第三开关的一第二端电性耦接一低预设电位；以及
    一第四开关，所述第四开关的一控制端电性耦接所述第二节点，所述第四开关的一第一端电性耦接所述第一节点，所述第四开关的一第二端电性耦接所述低预设电位；其中所述第四开关的第一端与第二端的内部通道之间距离加大，或所述第四开关的第一端与第二端的内部通道之间距离设计为双通道。
  2. 如权利要求1所述的移位元暂存电路，更包括一补偿电路，包括：一第五开关，所述第五开关的一控制端电性耦接所述输出脉冲讯号，所述第五开关的一第一端电性耦接所述输出脉冲讯号，所述第五开关的一第二端电性耦接所述低预设电位。
  3. 如权利要求1所述的移位元暂存电路，更包括一子下拉电路，电性耦接于所述移位寄存器中的所述第一节点、所述输出脉冲讯号及所述低预设电位。
  4. 如权利要求3所述的移位元暂存电路，更包括一子下拉电路控制器，电性耦接于所述移位寄存器的所述低预设电位及所述子下拉电路。
  5. 如权利要求2所述的移位元暂存电路，其中，所述补偿电路用以降低所述第四开关中的控制端与第一端的电位差。
  6. 一种移位元暂存电路的波形产生方法，用于多级移位寄存器，其中，所述移位寄存器包括一第一开关、一第二开关、一第三开关、一第四开关、一补偿电路、一子下拉电路及一子下拉电路控制器，所述第一开关用以产生所述移位寄存器的一输出脉冲讯号，并提供至下一级移位寄存器，所述波形产生方法包括：
    导通所述第一开关，并通过一频率讯号上拉所述移位寄存器的一输出端的电位；
    通过增加一补偿电路来降低所述第四开关中的控制端与第一端的电位差；以及
    通过所述输入脉冲讯号经由所述第二开关及所述子下拉电路，以下拉所述移位寄存器的所述输出端的电位。
  7. 如权利要求6所述的移位元暂存电路的波形产生方法，其中，所述通过增加一补偿电路来降低 所述第四开关中的控制端与第一端的电位差的步骤包括：
    在所述移位寄存器中增加第五开关，所述第五开关的一控制端电性耦接一输出脉冲讯号，所述第五开关的一第一端电性耦接所述输出脉冲讯号，所述第五开关的一第二端电性耦接一低预设电位。
  8. 如权利要求7所述的移位元暂存电路的波形产生方法，更包括一子下拉电路，电性耦接于所述移位寄存器中的第一节点、所述输出脉冲讯号及所述低预设电位。
  9. 如权利要求8所述的移位元暂存电路的波形产生方法，更包括一子下拉电路控制器，电性耦接于所述移位寄存器的所述低预设电位及所述子下拉电路。
  10. 如权利要求6所述的移位元暂存电路的波形产生方法，其中，所述补偿电路用以降低所述第四开关中的控制端与第一端的电位差。
  11. 一种显示面板，包括：
    第一基板；
    多个像素，形成于所述第一基板上；
    移位元暂存电路，包括多级移位寄存器，每一移位寄存器包括：
    第一开关，所述第一开关的一控制端电性耦接一第一节点，所述第一开关的一第一端电性耦接一频率讯号，所述第一开关的一第二端电性耦接一输出脉冲讯号；
    第二开关，所述第二开关的一控制端电性耦接一输入脉冲讯号，所述第二开关的一第一端电性耦接所述输入脉冲讯号，所述第二开关的一第二端电性耦接所述第一节点；
    第三开关，所述第三开关的一控制端电性耦接一第二节点，所述第三开关的一第一端电性耦接所述输出脉冲讯号，所述第三开关的一第二端电性耦接一低预设电位；以及
    第四开关，所述第四开关的一控制端电性耦接所述第二节点，所述第四开关的一第一端电性耦接所述第一节点，所述第四开关的一第二端电性耦接所述低预设电位；
    其中，所述第四开关的第一端与第二端的内部通道之间距离加大，或所述第四开关的第一端与第二端的内部通道之间距离设计为双通道；
    其中，所述移位元暂存电路设置于所述第一基板。
  12. 如权利要求11所述的显示面板，更包括一补偿电路，包括：一第五开关，所述第五开关的一控制端电性耦接所述输出脉冲讯号，所述第五开关的一第一端电性耦接所述输出脉冲讯号，所述第五开关的一第二端电性耦接所述低预设电位。
  13. 如权利要求11所述的显示面板，更包括一子下拉电路，电性耦接于所述移位寄存器中的所述第一节点、所述输出脉冲讯号及所述低预设电位。
  14. 如权利要求13所述的显示面板，更包括一子下拉电路控制器，电性耦接于所述移位寄存器的所述低预设电位及所述子下拉电路。
  15. 如权利要求12所述的显示面板，其中，所述补偿电路用以降低所述第四开关中的控制端与第一端的电位差。
PCT/CN2017/086645 2017-05-12 2017-05-31 移位元暂存电路及其波形产生方法与其应用的显示面板 Ceased WO2018205322A1 (zh)

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