WO2018205311A1 - 像素单元及包含其的阵列基板 - Google Patents

像素单元及包含其的阵列基板 Download PDF

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WO2018205311A1
WO2018205311A1 PCT/CN2017/085838 CN2017085838W WO2018205311A1 WO 2018205311 A1 WO2018205311 A1 WO 2018205311A1 CN 2017085838 W CN2017085838 W CN 2017085838W WO 2018205311 A1 WO2018205311 A1 WO 2018205311A1
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electrode
region
area
edge
disposed
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English (en)
French (fr)
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安立扬
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/539,819 priority Critical patent/US10916612B2/en
Publication of WO2018205311A1 publication Critical patent/WO2018205311A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention belongs to the field of liquid crystal display technologies, and in particular, to a pixel unit and an array substrate including the same.
  • Water mark defects are a common problem of liquid crystal panels. Generally, uneven images such as raindrops, clusters, and fog defects are called water mark defects. There are many reasons for water marks, including uneven cell gaps, uneven metal etching, and differences in group accuracy between different regions. The difference in group accuracy between different regions causes the storage capacitance of pixel units in different regions to be inconsistent, resulting in water marks.
  • the storage capacitor of the pixel unit plays a crucial role in the process of displaying an image on the liquid crystal panel.
  • the storage capacitor can finitely reduce the feedthrough effect, maintain the voltage across the liquid crystal molecules, and make the pixel unit display more stable.
  • the design will ensure a large storage capacitor as much as possible to make the picture display more uniform and stable.
  • 1 is a schematic diagram of a conventional small-sized pixel design in the prior art.
  • the storage capacitor 10 includes a first electrode 11 located in a first metal layer and a second electrode 12 located in a second metal layer, and the second electrode 12 A second region 121 and a third region 122 connected to the drain electrode are included. At the same time, an insulating layer is provided between the first electrode 11 and the second electrode 12.
  • the area of the overlapping area of the second electrode 12 and the first electrode 11 determines the size of the storage capacitor.
  • the overlapping area of the second electrode 12 and the first electrode 11 is constituted by the overlapping area of the second region 121 and the third region 122 together with the first electrode 11.
  • the area of the second region 121 is smaller than the area of the first electrode 11 as viewed in the normal direction of the array substrate, that is, the circumferential edge 110 of the first electrode 11 is offset outward by at least 2.5 from the circumferential edge of the second region 121.
  • this setting mainly considers the characteristics of the 4 mask process and its influence on the group accuracy.
  • the difference in group precision of different regions causes the second electrode of the storage capacitor of the pixel unit of different regions to be offset with respect to the first electrode, but the offset does not exceed 2.5 micrometers.
  • Adoption The setup shown in Figure 1.
  • the overlapping area of the third region 122 and the first electrode 11 is negligible, that is, the area of the overlapping region of the second electrode 12 and the first electrode 11 is from the second region 121 and the first electrode.
  • the area of the overlapping area of 11 is composed.
  • FIGS. 2a, 2b, and 2c are schematic diagrams showing the positional relationship between the second electrode 12 and the first electrode 11 when the second electrode 12 is aligned, moved downward, and moved upward with respect to the position of the first electrode 11, and it can be seen that The second electrode moves downward or upward relative to the first electrode, and the area of the overlapping area of the second electrode 12 and the first electrode 11 remains unchanged, that is, the storage capacitance remains unchanged. In this way, water marks due to changes in storage capacitance are avoided.
  • FIGS. 3a, 3b, and 3c are schematic views of the second electrode 12' and the first electrode 11 in a normal position, in which case the area of the overlap region is S1; when the second electrode 12' is offset downward relative to the first electrode 11, The area of the overlapping area is S2. Obviously, S2 is smaller than S1, as shown in FIG. 3b.
  • the area of the overlapping area is S3.
  • S3 is larger than S1, as shown in Figure 3c.
  • the difference in the area of the overlap area causes a change in the storage capacitance. This amount of variation has less impact on products with larger pixel sizes, but has a greater impact on products with smaller pixel sizes.
  • the storage capacitance of a small-sized pixel is relatively small, but the line width of the drain electrode is substantially the same as the line width of the drain electrode of the large-sized pixel, so that the change in the capacitance value caused by the offset is expressed in the small-sized pixel. more obvious.
  • Differences in group accuracy between different regions result in differences in storage capacitance between different regions. This difference causes water marks when displayed in low gray levels, resulting in a decline in product quality. .
  • the present invention proposes a pixel unit, by providing a structure of a first electrode or a second electrode of a storage capacitor such that when the first electrode and the second electrode of the pixel unit of different regions are In the case of a difference in group precision, the storage capacitances of different pixel units are kept consistent, thereby avoiding water marks caused by differences in storage capacitance.
  • the storage capacitor of the pixel unit is disposed on an array substrate, the storage capacitor includes a first electrode disposed on the first metal layer and a second electrode disposed on the second metal layer, in the first An insulating layer is disposed between the electrode and the second electrode, wherein
  • the second electrode and the first electrode overlap each other to form a first overlapping area. If the offset of the second electrode relative to the first electrode is within a preset distance, the area of the first overlapping area Keep one To.
  • the area of the overlapping area of the second electrode and the first electrode determines the size of the storage capacitor. Therefore, when the area of the overlapping area remains the same, the size of the storage capacitor remains the same, thereby avoiding the difference in storage capacitance of different pixel units.
  • the water marks caused by the product improve the quality of the product.
  • the pixel unit as described above wherein the first electrode includes a first region, and the second electrode includes a second region and a third region, wherein when the second region When the centers of the first regions overlap each other, the circumferential edge of the first region is offset from the circumferential edge of the second region toward the outside of the second region by a first distance, the third region is set Extending at a first edge of the second region and toward a second side of the second region, the width of the third region in the first direction being a first width, the first direction and the The second direction is vertical, and the preset distance is equal to the first distance.
  • the first distance here can select the maximum pair accuracy error, so that in the grouping process, the second area is always inside the first area, avoiding the change of the area of the first overlapping area due to the second area.
  • the third region may protrude outside of the first region.
  • the overlapping area of the third region and the first region may change, thereby causing a difference in the area of the first overlapping region of the different pixel units, further This causes a difference in storage capacitance, resulting in water marks.
  • there is also an overlapping area between the fourth area and the first area when there is a difference in the precision of the pair of the first electrode and the second electrode of the different pixel units, the overlapping area of the fourth area and the first area also changes.
  • the change in the overlapping area of the fourth region and the first region can reduce the change in the overlapping area of the third region with the first region, especially when the fourth region is in the first direction
  • the width of the third region is equal to the width of the third region in the first direction
  • the change of the overlapping area of the fourth region and the first region is more able to compensate for the change of the overlapping area between the third region and the first region, thereby reducing the number of different pixel units.
  • the difference in area of an overlap region reduces the difference between the storage capacitors, and improves the water mark caused by the difference in the precision of the pair of the first electrode and the second electrode of the different pixel units.
  • the fourth area and the third area are located on the same center line in the second direction. Regardless of the shape of the outer circumference of the first area and the second area, the fourth area and the The change of the overlapping area of one region can make up for the change of the overlapping area of the third region and the first region to the greatest extent, and improve the water mark caused by the difference in the precision of the pair of the first electrode and the second electrode of the different pixel units.
  • the pixel unit as described above wherein the length of the fourth region in the second direction is equal to or greater than twice the first distance.
  • the change in the overlapping area of the fourth region and the first region can completely compensate for the overlap of the third region and the first region.
  • the area is changed such that the area of the first overlapping area of the different pixel units remains the same, so that the storage capacitance remains consistent, avoiding the resulting water marks.
  • the first electrode further includes a blank region disposed at a third edge of the first region and extending toward the inside of the first region in the second direction, the third An edge is parallel to the first edge and is disposed on an opposite side of the first edge.
  • the overlapping area of the second area and the first area is no longer equal to the area of the second area, but the area of the second area minus the overlapping area of the blank area and the second area.
  • the overlapping area of the blank area and the second area is set as a blank overlapping area
  • the overlapping area of the third area and the first area is set as the second overlapping area
  • the area of the first overlapping area is That is, the sum of the area of the second area and the area of the second overlap minus the area of the blank overlap.
  • the change of the blank overlap area can compensate for the change of the second overlap area, thereby weakening the different pixel units.
  • the difference in area of the first overlapping region improves the water mark caused by the difference in the precision of the pair of the first electrode and the second electrode of the different pixel units.
  • the pixel unit as described above, wherein the center line of the blank area in the second direction and the center line of the third area in the second direction coincide with each other. At this time, the blank area and the third area are located on the same center line in the second direction. Regardless of the outer peripheral shape of the first region and the second region, the change in the overlapping area of the blank region and the second region can compensate for the change in the overlapping area of the third region and the first region to the greatest extent, and the difference in the pixel unit is improved. A water mark caused by a difference in the accuracy of the pair of electrodes and the second electrode.
  • the pixel unit as described above wherein the length of the blank area in the second direction is equal to or greater than twice the first distance.
  • the change of the overlapping area of the blank area and the second area can completely compensate for the overlapping area of the third area and the first area. The change is such that the areas of the first overlapping regions of the different pixel units are kept consistent so that the storage capacitance remains consistent, avoiding the resulting water marks.
  • the array substrate proposed by the present invention includes the pixel unit as described above.
  • the area of the first overlapping area can be made uniform, thereby improving the water mark generated thereby, and improving the product. quality.
  • the storage capacitor of the pixel unit proposed by the present invention can compensate for the change of the overlapping area of the third area and the first area by setting the fourth area or the blank area, thereby reducing the area difference of the first overlapping area of the different pixel units.
  • the difference in storage capacitance is reduced, and the water mark caused by the difference in the pair precision between the first electrode and the second electrode of different pixel units is improved, and the product quality is improved. It also improves the product quality of the array substrate containing this storage capacitor.
  • FIG. 1 is a schematic diagram of a conventional small-sized pixel unit in the prior art
  • 2a, 2b, and 2c are respectively for a product having a larger pixel size, when the connection between the second electrode and the drain electrode is neglected, and when the second electrode is aligned, moved down, or moved up relative to the position of the first electrode, A schematic diagram of a change in the overlapping area of the second electrode and the first electrode;
  • 3a, 3b, and 3c are respectively for a product having a small pixel size, and when the connection between the second electrode and the drain electrode cannot be ignored, when the second electrode is aligned, moved up, and moved up relative to the first electrode position, respectively a schematic diagram of a change in an overlapping area of the second electrode and the first electrode;
  • 4a, 4b, and 4c are schematic diagrams showing changes in overlapping regions of the second electrode and the first electrode when the second electrode is aligned, moved down, and moved up relative to the first electrode in the first embodiment of the present invention. ;
  • FIG. 6, and FIG. 7 are respectively schematic diagrams showing changes in overlapping regions of the second electrode and the first electrode when the second electrode is aligned, moved up, and moved up relative to the first electrode in the second embodiment of the present invention. .
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 4 is a schematic structural diagram of a storage capacitor of a pixel unit in the embodiment.
  • the storage capacitor of the pixel unit includes a first electrode 21 disposed on the first metal layer and a second electrode 22 disposed on the second metal layer, and an insulating layer is disposed between the first electrode 21 and the second electrode 22.
  • 4a is a schematic structural view of the storage capacitor when viewed along the normal direction of the array substrate.
  • the first electrode 21 includes a first region 211
  • the second electrode 22 includes a second region 221, a third region 222, and a fourth region 223.
  • the first electrode 21 and the second electrode 22 of different pixel units may have a difference in group precision.
  • FIG. 4a is a schematic view showing the structure when the second electrode 22 and the first electrode 21 are aligned, and the alignment accuracy of the second electrode 22 and the first electrode 21 at this time is in accordance with the ideal group precision.
  • the second region 221 and the center of the first region 211 coincide with each other, and the circumferential edge of the first region 211 is spaced apart from the circumferential edge of the second region 221 by a first distance D1, in a specific implementation process,
  • the first distance D1 is preferably the maximum error to the group accuracy, and at this time, the first distance D1 is also a preset distance of the design allowable deviation.
  • the direction in which the first edge 2211 of the second region 221 is located is the first direction 100
  • the direction perpendicular to the first direction 100 is the second direction 200.
  • the third region 222 is disposed on the first edge 2211 of the second region 221 and extends in the second direction 200 toward the outside of the second region 221 to the drain electrode also disposed on the second metal layer ( Not shown in the figure). Obviously, the third area 222 protrudes from the first area 211.
  • the width of the third region 222 in the first direction 100 is set to be the first width W1.
  • the second edge 2212 of the second region 221 is disposed in parallel with the first edge 2211.
  • the fourth region 223 is disposed at the second edge 2212 and extends toward the outside of the second region 221 in the second direction 200.
  • the width W2 of the fourth region 223 in the first direction 100 is equal to the first width W1.
  • the area of the first overlapping region formed by the first electrode 21 and the second electrode 22 includes the second overlapping area S12 formed by the second region 221 and the first region 211, and the third region 222 and the first region 211.
  • the third overlapping area S13 and the fourth overlapping area S14 formed by the fourth area 223 and the first area 211, that is, the area of the first overlapping area is equal to the sum of the second overlapping area S12, the third overlapping area S13 and the fourth overlapping area S14. +S13+S14.
  • the group precision may vary in different regions, so that the relative positions of the second electrode and the first electrode in different regions are different, so that for small-sized panels, due to leakage
  • the presence of a pole causes a difference in the area of the first overlapping area of different pixel units.
  • by adding the fourth region 223 to the second electrode it can be ensured that the area of the first overlapping region can be effectively maintained when the difference is within the preset distance range, which will be described below.
  • the specific case of the first overlap region when the group precision changes along the second direction 200.
  • the second electrode 22 is downwardly displaced in the second direction 200 with respect to the first electrode 21, and at this time, the area of the first overlapping region is S12 + S13' + S14'. Since the offset is smaller than the preset first distance D1, the second region 221 is always inside the first region 211, so the second overlap area S12 remains unchanged. However, the third overlap area S13' is reduced with respect to the third overlap area S13 in FIG. 4a, and the fourth overlap area S14' is increased with respect to the fourth overlap area S14 in FIG. 4a, so the change of the fourth overlap area can The effect of the change in the third overlap area on the area of the first overlap area is reduced.
  • the change of the fourth overlap area can minimize the influence of the change of the third overlap area on the area of the first overlap area, thereby making the area and the map of the first overlap area in FIG. 4b
  • the area of the first overlap region in 4a is kept uniform, which improves the difference in storage capacitance caused by the difference in group precision, and also improves the resulting water mark.
  • the second electrode 22 is offset upward relative to the first electrode 21 in the second direction 200.
  • the area of the first overlap region is S12+S13"+S14". Since the offset is also smaller than the preset first distance D1, the second overlap area S12 remains unchanged. 4b, the third overlap area S13" is increased with respect to the third overlap area S13 in FIG. 4a, and the fourth overlap area S14" is decreased with respect to the fourth overlap area S14 in FIG. 4a, so the fourth The change in the overlap area can reduce the influence of the change in the third overlap area on the area of the first overlap area.
  • the change of the fourth overlap area can minimize the influence of the change of the third overlap area on the area of the first overlap area, thereby making the area and the map of the first overlap area in FIG. 4c
  • the area of the first overlap region in 4a is kept uniform, thereby improving the difference in storage capacitance caused by the difference in group precision, and improving the resulting water mark.
  • the length D2 of the fourth region 223 in the second direction 200 is equal to or greater than twice the first distance D1.
  • the amount of change in the second direction of the fourth overlap area S14 is always equal to The amount of change of the third overlap area S13 in the second direction 200, Thereby, the area of the first overlapping area can be made constant. Thereby, the difference in storage capacitance due to the difference in group precision is avoided, and the resulting water mark is avoided.
  • the area of the first overlapping region can not only remain unchanged, but also is not affected by the first region 211 and the second region 221.
  • the effect of the shape of the peripheral edge is not only remain unchanged, but also is not affected by the first region 211 and the second region 221.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 5 is a schematic structural diagram of a storage capacitor of a pixel unit in the embodiment.
  • the storage capacitor of the pixel unit also includes a first electrode 31 disposed on the first metal layer and a second electrode 32 disposed on the second metal layer, and at the same time, the first electrode 31 and the second electrode 32. An insulating layer is provided between them.
  • FIG. 5 is a schematic structural view of the storage capacitor when viewed along the normal direction of the array substrate.
  • the first electrode 31 includes a first region 311 and a blank region 312, and no metal is disposed at the blank region 312.
  • the second electrode 32 includes a second region 321 and a third region 322.
  • the first electrode 31 and the second electrode 32 of different pixel units may have a difference in group accuracy.
  • FIG. 5 is a schematic view showing the structure when the second electrode 32 and the first electrode 31 are aligned, and the alignment accuracy of the second electrode 32 and the first electrode 31 at this time is in an ideal condition.
  • the centers of the second region 321 and the first region 311 coincide with each other, and the circumferential edge of the first region 311 is offset from the outer edge of the second region 321 by a first distance toward the outer side of the second region 321 .
  • D1' in a specific implementation process, the first distance D1' is preferably the maximum error of the group precision, and at this time, the first distance D1 is also a preset distance of the design allowable deviation.
  • the direction in which the first edge 3211 of the second region 321 is located is the first direction 100'
  • the direction perpendicular to the first direction 100' is the second direction 200'.
  • the third region 322 is disposed on the first edge 3211 of the second region 321 and extends in the second direction 200' toward the outside of the second region 321 to the drain electrode also disposed on the second metal layer (Fig. Not shown). Obviously, the third area 322 protrudes from the first area 311. Also, here, the width of the third region 322 in the first direction 100' is set to be the first width W1'.
  • the third edge 3111 of the first region 311 is disposed in parallel with the first edge 3211 and is located on the opposite side of the first edge 3211.
  • the blank area 312 is disposed at the third edge 3111 and extends toward the inside of the first area 311 in the second direction 200'.
  • the width W2' of the blank area 312 in the first direction 100' is equal to the first width W1'.
  • the area of the first overlapping area formed by the first electrode 31 and the second electrode 32 is the second area 321
  • the second electrode 32 is downwardly displaced in the second direction 200' with respect to the first electrode 31, and at this time, the area of the first overlapping region is S22' + S23' - S25'. Since the offset is smaller than the preset first distance D1', the second area 321 is always inside the first area 311, so the second overlapping area S22 remains unchanged. However, the third overlap area S23' is reduced with respect to the third overlap area S23 in FIG. 5, while the blank overlap area S25' is also reduced with respect to the blank overlap area S25 in FIG. 5, so that S22'+S23' can be made. The change of -S25' is minimized, reducing the effect of the difference in group accuracy on the area of the first overlap region.
  • the influence on the area of the first overlapping area on the difference in group precision can be minimized, so that the area of the first overlapping area in FIG. 6 overlaps with the first in FIG.
  • the area of the area remains the same, which improves the difference in storage capacitance caused by the difference in group accuracy and improves the resulting water marks.
  • the second electrode 32 is offset upward in the second direction 200' with respect to the first electrode 31.
  • the area of the first overlap region is S22"+S23"-S25".
  • the second overlapping area S22 remains unchanged from the preset first distance D1'.
  • the third overlapping area S23" is increased relative to the third overlapping area S23 in FIG. 5, and blank.
  • the overlap area S25" is also increased with respect to the blank overlap area S25 in FIG. 5, so that the change of S22"+S23"-S25" can be minimized, and the difference in group precision is caused to the area of the first overlap area. Impact.
  • the influence on the area of the first overlapping area on the difference in group precision can be minimized, so that the area of the first overlapping area in FIG. 7 overlaps with the first in FIG.
  • the area of the area remains the same, which improves the difference in storage capacitance caused by the difference in group accuracy and improves the resulting water marks.
  • the length D2' of the blank area 312 in the second direction 200' is equal to or greater than twice the first distance D1'.
  • the amount of change in the blank overlap area in the second direction is always equal to The amount of change in the third overlapping area in the second direction, therefore, enables the area of the first overlapping area to remain unchanged. Thereby avoiding storage capacitors due to differences in group accuracy The difference avoids the resulting water marks.
  • the area of the first overlap area can not only remain unchanged, but also is not affected by the first area 311 and The influence of the shape of the outer peripheral edge of the second region 321 .
  • the present invention also provides an array substrate, which includes the storage capacitors of the pixel unit proposed in Embodiment 1 or Embodiment 2, thereby avoiding the difference in alignment accuracy between the first electrode and the second electrode of different pixel units.
  • the resulting difference in storage capacitance avoids the resulting water marks, ensures uniform display of the panel, and improves the quality of the product.

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Abstract

一种像素单元，存储电容设置在阵列基板上，存储电容包括设置在第一金属层的第一电极（21）和设置在第二金属层的第二电极（22），在第一电极（21）和第二电极（22）之间设置有绝缘层，第二电极（22）和第一电极（21）相互重叠形成第一重叠区域，若第二电极（22）相对于第一电极（21）的偏移在预设距离范围内，第一重叠区域的面积保持一致，避免了由于对组精度差异引起的存储电容差异，从而避免了由此产生的水痕。还提供一种包括像素单元的阵列基板。

Description

像素单元及包含其的阵列基板
相关申请的交叉引用
本申请要求享有于2017年05月09日提交的名称为“像素单元及包含其的阵列基板”的中国专利申请CN201710319935.X的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于液晶显示技术领域，具体涉及一种像素单元及包含其的阵列基板。
背景技术
水痕缺陷是液晶面板较常见的一类问题，通常将不均匀的画面，如雨点状、团状、雾状的缺陷称为水痕缺陷。产生水痕的原因有多种，包括液晶盒间隙不均、金属蚀刻不均匀、不同区域的对组精度差异等。不同区域的对组精度差异会造成不同区域的像素单元的存储电容不一致，从而产生水痕。
在液晶面板显示图像的过程中，像素单元的存储电容起到至关重要的作用。存储电容能够有限减小馈通效应(feedthrough)，保持液晶分子两端的电压，使像素单元显示画面更加稳定。在充电率允许的情况下，设计中会尽可能保证较大的存储电容，以使画面显示更均匀、稳定。图1为现有技术中一种常见的小尺寸像素(pixel)设计示意图，存储电容10包括位于第一金属层的第一电极11和位于第二金属层的第二电极12，第二电极12包括第二区域121和连接至漏电极的第三区域122。同时，在第一电极11和第二电极12之间设置有绝缘层。其中，第二电极12与第一电极11的重叠区域的面积决定了存储电容的大小。在图1中，第二电极12与第一电极11的重叠区域由第二区域121和第三区域122共同与第一电极11的重叠区域构成。常规设计中，沿阵列基板法线方向观测，第二区域121的面积小于第一电极11的面积，即第一电极11的周向边缘110较第二区域121的周向边缘向外偏离至少2.5微米，这种设置主要考虑了4掩膜制程的特点及对组精度的影响。
在阵列基板制程中，不同区域的对组精度差异，导致不同区域像素单元的存储电容的第二电极相对于第一电极发生偏移，但偏移量不超过2.5微米。采用如 图1所示的设置。对于像素尺寸较大的产品来说，第三区域122与第一电极11的重叠区域可以忽略不计，即第二电极12与第一电极11的重叠区域的面积由第二区域121与第一电极11的重叠区域的面积构成。这样，即使第二电极相对于第一电极发生了偏移，第二电极12与第一电极11的重叠区域的面积也不会改变，从而存储电容也不会改变。图2a、2b、2c分别为第二电极12相对于第一电极11位置对正、下移、上移时，第二电极12与第一电极11的位置关系示意图，从中可以看出，无论是第二电极相对于第一电极下移还是上移，第二电极12与第一电极11的重叠区域的面积均保持不变，即存储电容保持不变。这样，也就避免了由于存储电容改变而产生的水痕。
但是，对于像素尺寸较小的产品来说，第三区域122’与第一电极11的重叠区域不能够忽略不计。这样，当第二电极12’相对于第一电极11发生相对偏移时，第二电极12’与第一电极11的重叠区域的面积会发生改变，如图3a、图3b、图3c所示。图3a为第二电极12’与第一电极11处于正常位置时示意图，此时，二者重叠区域的面积为S1；当第二电极12’相对于第一电极11向下偏移时，二者重叠区域的面积为S2，显然，S2小于S1，如图3b所示；当第二电极12’相对于第一电极11向上偏移时，二者重叠区域的面积为S3，显然，S3大于S1，如图3c所示。重叠区域面积的差异导致了存储电容的改变。这种变化量对像素尺寸较大的产品影响较小，但对像素尺寸较小的产品影响很大。这是因为，小尺寸的像素的存储电容相对较小，但漏电极的线宽与大尺寸像素的漏电极线宽基本一致，所以，偏移导致的电容值的变化在小尺寸像素中表现的更加明显。不同区域的对组精度的差异，导致不同区域的存储电容产生差异。这种差异在低灰阶显示时会引发水痕，造成产品品质下降。。
发明内容
针对现有技术中存在的问题，本发明提出了一种像素单元，通过设置存储电容的第一电极或第二电极的结构，使得当不同区域的像素单元的第一电极和第二电极之间的对组精度存在差异情况下，不同像素单元的存储电容保持一致，从而避免了由于存储电容差异而产生的水痕。
一种像素单元，所述像素单元的存储电容设置在阵列基板上，所述存储电容包括设置在第一金属层的第一电极和设置在第二金属层的第二电极，在所述第一电极和所述第二电极之间设置有绝缘层，其中，
所述第二电极和所述第一电极相互重叠形成第一重叠区域，若所述第二电极相对于所述第一电极的偏移在预设距离范围内，所述第一重叠区域的面积保持一 致。
第二电极和第一电极的相互重叠区域的面积决定了存储电容的大小，因此，当重叠区域的面积保持一致时，存储电容的大小保持一致，从而避免了由于不同像素单元的存储电容的差异引起的水痕，提升了产品品质。
作为对本发明的进一步改进，如上所述的像素单元，其中，所述第一电极包括第一区域，所述第二电极包括第二区域和第三区域，其中，当所述第二区域与所述第一区域的中心相互重合时，所述第一区域的周向边缘相对于所述第二区域的周向边缘朝向所述第二区域的外侧偏移第一距离，所述第三区域设置在所述第二区域的第一边缘并沿第二方向朝向所述第二区域的外侧延伸，所述第三区域在第一方向上的宽度为第一宽度，所述第一方向与所述第二方向垂直，所述预设距离与所述第一距离相等。
这里的第一距离可以选取最大对组精度误差，从而，在对组过程中，第二区域始终处于第一区域的内部，避免了由于第二区域引起的第一重叠区域面积的改变。
作为对本发明的进一步改进，如上所述的像素单元，其中，所述第二电极还包括第四区域，所述第四区域设置在所述第二区域的第二边缘并沿所述第二方向朝向所述第二区域的外部延伸，所述第四区域在所述第一方向上的宽度等于所述第一宽度，所述第二边缘与所述第一边缘相对平行设置。
由于第三区域沿第二方向朝向第二区域的外侧延伸，所以第三区域会突出第一区域的外部。当不同像素单元的第一电极与第二电极的对组精度存在差异时，第三区域与第一区域的重叠面积会发生改变，从而导致不同像素单元的第一重叠区域的面积产生差异，进一步导致存储电容产生差异，导致水痕。同理，第四区域与第一区域也存在重叠面积，当不同像素单元的第一电极与第二电极的对组精度存在差异时，第四区域与第一区域的重叠面积也会发生改变。当第四区域设置在第三区域的相对侧时，第四区域与第一区域的重叠面积的改变能够减弱第三区域与第一区域重叠面积的改变，尤其当第四区域在第一方向上的宽度等于第三区域在第一方向上的宽度时，第四区域与第一区域的重叠面积的改变更加能够弥补第三区域与第一区域重叠面积的改变，从而减小不同像素单元的第一重叠区域的面积差异，减小存储电容之间的差异，改善由于不同像素单元的第一电极与第二电极的对组精度存在差异引起的水痕。
作为对第四区域的设置位置的进一步改进，如上所述的像素单元，其中，所述第四区域与所述第三区域相对设置。此时，第四区域与第三区域在第二方向上位于同一条中心线上。无论第一区域和第二区域的外周形状如何，第四区域与第 一区域的重叠面积的改变都能最大程度地弥补第三区域与第一区域的重叠面积的改变，改善由于不同像素单元的第一电极与第二电极的对组精度存在差异引起的水痕。
作为对第四区域的进一步改进，如上所述的像素单元，其中，所述第四区域在所述第二方向上的长度等于或大于所述第一距离的2倍。这样的第四区域，在不同像素单元的第一电极与第二电极的对组精度存在差异时，第四区域与第一区域的重叠面积的改变能够完全弥补第三区域与第一区域的重叠面积的改变，从而使得不同像素单元的第一重叠区域的面积保持一致，使得存储电容保持一致，避免了由此产生的水痕。
如上所述的像素单元，其中，所述第一电极还包括设置在所述第一区域的第三边缘并沿所述第二方向朝向所述第一区域内部延伸的空白区域，所述第三边缘与所述第一边缘相互平行且设置在所述第一边缘的相对侧。
由于空白区域不设置有金属，所以第二区域与第一区域的重叠面积不再等于第二区域的面积，而是为第二区域的面积减去空白区域与第二区域的重叠面积。为了方便说明该技术方案，在这里设定空白区域与第二区域的重叠面积为空白重叠面积，设定第三区域与第一区域的重叠面积为第二重叠面积，那么第一重叠区域的面积即为第二区域面积与第二重叠面积之和减去空白重叠面积。当空白区域设置在于第一边缘相对的第三边缘时，即空白重叠面积设置在第二重叠面积的相对侧，那么空白重叠面积的改变就能够弥补第二重叠面积的改变，从而减弱不同像素单元的第一重叠区域的面积差异，改善由于不同像素单元的第一电极与第二电极的对组精度存在差异引起的水痕。
作为对空白区域的设置位置的进一步改进，如上所述的像素单元，其中，所述空白区域的沿第二方向的中心线与所述第三区域的沿第二方向的中心线相互重合。此时，空白区域与第三区域在第二方向上位于同一条中心线上。无论第一区域和第二区域的外周形状如何，空白区域与第二区域的重叠面积的改变都能最大程度地弥补第三区域与第一区域的重叠面积的改变，改善由于不同像素单元的第一电极与第二电极的对组精度存在差异引起的水痕。
作为对空白区域的进一步改进，如上所述的像素单元，其中，所述空白区域在所述第二方向上的长度等于或大于所述第一距离的2倍。这样的空白区域，在不同像素单元的第一电极与第二电极的对组精度存在差异时，空白区域与第二区域的重叠面积的改变能够完全弥补第三区域与第一区域的重叠面积的改变，从而使得不同像素单元的第一重叠区域的面积保持一致，使得存储电容保持一致，避免了由此产生的水痕。
如上所述的像素单元，其中，所述第一方向为所述第一边缘所在的方向，所述第二方向为所述第二电极相对于所述第一电极的偏移方向。
本发明提出的阵列基板，包括如上所述的像素单元。这样的阵列基板，在不同像素单元的第一电极与第二电极的对组精度存在差异时，能够使得第一重叠区域的面积保持一致，从而改善了由此产生的水痕，提高了产品的品质。
总之，本发明提出的像素单元的存储电容，通过设置第四区域或空白区域，能够弥补第三区域与第一区域重叠面积的改变，从而减小不同像素单元的第一重叠区域的面积差异，减小存储电容的差异，改善了由于不同像素单元的第一电极与第二电极的对组精度存在差异引起的水痕，提高了产品品质。同时也提高了包含此存储电容的阵列基板的产品品质。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1为现有技术中一种常见的小尺寸像素单元的设计示意图；
图2a、图2b和图2c分别为对于像素尺寸较大的产品，忽略第二电极与漏电极之间连线时，第二电极相对于第一电极位置对正、下移、上移时，第二电极与第一电极的重叠区域变化示意图；
图3a、图3b和图3c分别为对于像素尺寸较小的产品，不能忽略第二电极与漏电极之间连线时，第二电极相对于第一电极位置对正、下移、上移时，第二电极与第一电极的重叠区域变化示意图；
图4a、图4b和图4c分别为本发明第一个实施例中，第二电极相对于第一电极位置对正、下移和上移时，第二电极与第一电极的重叠区域变化示意图；
图5、图6和图7分别为本发明第二个实施例中，第二电极相对于第一电极位置对正、下移和上移时，第二电极与第一电极的重叠区域变化示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
结合附图和本发明具体实施方式的描述，能够更加清楚地了解本发明的细节。但是，在此描述的本发明的具体实施方式，仅用于解释本发明的目的，而不能以任何方式理解成是对本发明的限制。在本发明的教导下，技术人员可以构想基于本发明的任意可能的变形，这些都应被视为属于本发明的范围，下面将结合 附图对本发明作进一步说明。
以下将结合附图对本发明的内容作出详细的说明，下文中的“上”“下”“左”“右”均为相对于图示方向，不应理解为对本发明的限制。
实施例一：
如图4a所示，为本实施例中的像素单元的存储电容的结构示意图。该像素单元的存储电容包括设置在第一金属层的第一电极21和设置在第二金属层的第二电极22，同时，在第一电极21与第二电极22之间设置有绝缘层。图4a为沿阵列基板的法线方向观测时，该存储电容的结构示意图。从图4a中可以看出，第一电极21包括第一区域211，第二电极22包括第二区域221、第三区域222和第四区域223。在阵列基板的制程中，不同像素单元的第一电极21与第二电极22会存在对组精度差异。图4a为第二电极22与第一电极21位置对正时的结构示意图，此时的第二电极22与第一电极21的对组精度符合理想情况的对组精度。在理想情况下，第二区域221与第一区域211的中心相互重合，且第一区域211的周向边缘与第二区域221的周向边缘相距第一距离D1，在具体的实施过程中，第一距离D1优选地为对组精度的最大误差，此时，第一距离D1也是设计时允许偏差的预设距离。
在这里设定第二区域221的第一边缘2211所在的方向为第一方向100，与第一方向100垂直的方向为第二方向200。
如图4a所示，第三区域222设置在第二区域221的第一边缘2211并沿第二方向200朝向所述第二区域221的外侧延伸连接至同样设置在第二金属层的漏电极(图中未示出)。显然，第三区域222突出第一区域211。在这里，设定第三区域222沿第一方向100的宽度为第一宽度W1。
第二区域221的第二边缘2212与第一边缘2211相对平行设置。第四区域223设置在第二边缘2212并沿第二方向200朝向第二区域221的外部延伸。优选地，第四区域223在第一方向100上的宽度W2等于第一宽度W1。
此时，第一电极21与第二电极22形成的第一重叠区域的面积包括第二区域221与第一区域211形成的第二重叠面积S12、第三区域222与第一区域211形成的第三重叠面积S13和第四区域223与第一区域211形成的第四重叠面积S14，即第一重叠区域的面积等于第二重叠面积S12、第三重叠面积S13与第四重叠面积S14之和S12+S13+S14。
根据背景技术，在阵列基板制程中，对组精度会在不同区域范围内存在差异，使得第二电极与第一电极在不同区域内的相对位置出现差异，从而对于小尺寸面板而言，由于漏电极的存在，会导致不同像素单元的第一重叠区域的面积产生差异。而在本发明的本实施例中，通过在第二电极中增设了第四区域223，可以确保当差异在预设距离范围内时，能有效保持第一重叠区域面积的不变，以下将说明对组精度沿第二方向200变化时，第一重叠区域的具体情况。
如图4b所示，第二电极22相对于第一电极21沿第二方向200向下偏移，此时，第一重叠区域的面积为S12+S13’+S14’。由于偏移量小于预设的第一距离D1，第二区域221始终处于第一区域211的内部，所以第二重叠面积S12保持不变。然而，第三重叠面积S13’相对于图4a中的第三重叠面积S13减小，第四重叠面积S14’相对于图4a中的第四重叠面积S14增大，因此第四重叠面积的改变能够减小第三重叠面积的改变对第一重叠区域的面积造成的影响。尤其当W2等于W1时，第四重叠面积的改变能够最大程度地减小第三重叠面积的改变对第一重叠区域的面积造成的影响，从而使得图4b中的第一重叠区域的面积与图4a中的第一重叠区域的面积保持一致，这样就改善了对组精度差异引起的存储电容差异，也就改善了由此产生的水痕。
如图4c所示，第二电极22相对于第一电极21沿第二方向200向上偏移，此时，第一重叠区域的面积为S12+S13”+S14”。由于偏移量同样小于预设的第一距离D1，第二重叠面积S12仍旧保持不变。与图4b不同的是，第三重叠面积S13”相对于图4a中的第三重叠面积S13增大，第四重叠面积S14”相对于图4a中的第四重叠面积S14减小，因此第四重叠面积的改变能够减小第三重叠面积的改变对第一重叠区域的面积造成的影响。尤其当W2等于W1时，第四重叠面积的改变能够最大程度地减小第三重叠面积的改变对第一重叠区域的面积造成的影响，从而使得图4c中的第一重叠区域的面积与图4a中的第一重叠区域的面积保持一致，从而改善了对组精度差异引起的存储电容差异，改善了由此产生的水痕。
优选地，如图4a所示，第四区域223在第二方向200上的长度D2等于或大于第一距离D1的2倍。这样，无论第二电极22相对于第一电极21沿第二方向200向下还是向上偏移，只要偏移量保持在D1以内，那么第四重叠面积S14在第二方向上的改变量始终等于第三重叠面积S13在第二方向200上的改变量，因 此，能够使得第一重叠区域的面积保持不变。从而避免了由于对组精度差异引起的存储电容差异，避免了由此产生的水痕。
尤其当第四区域223与第三区域222相对设置时，只要偏移量小于预设距离第一重叠区域的面积不仅能够保持不变，而且也不会受到第一区域211和第二区域221的外周边缘形状的影响。
实施例二：
如图5所示，为本实施例中的像素单元的存储电容的结构示意图。与实施例一相同，该像素单元的存储电容也包括设置在第一金属层的第一电极31和设置在第二金属层的第二电极32，同时，在第一电极31与第二电极32之间设置有绝缘层。图5为沿阵列基板的法线方向观测时，该存储电容的结构示意图。从图5中可以看出，第一电极31包括第一区域311和空白区域312，且空白区域312处不设置金属。第二电极32包括第二区域321和第三区域322。在阵列基板的制程中，不同像素单元的第一电极31与第二电极32会存在对组精度差异。图5为第二电极32与第一电极31位置对正时的结构示意图，此时的第二电极32与第一电极31的对组精度符合理想情况。在理想情况下，第二区域321与第一区域311的中心相互重合，且第一区域311的周向边缘相对于第二区域321的周向边缘朝向第二区域321的外侧偏移第一距离D1’，在具体的实施过程中，第一距离D1’优选地为对组精度的最大误差，此时，第一距离D1也是设计时允许偏差的预设距离。
在这里设定第二区域321的第一边缘3211所在的方向为第一方向100’，与第一方向100’垂直的方向为第二方向200’。
如图5所示，第三区域322设置在第二区域321的第一边缘3211并沿第二方向200’朝向第二区域321的外侧延伸连接至同样设置在第二金属层的漏电极(图中未示出)。显然，第三区域322突出第一区域311。同样，在这里，设定第三区域322沿第一方向100’的宽度为第一宽度W1’。
第一区域311的第三边缘3111与第一边缘3211平行设置，且位于第一边缘3211的相对侧。空白区域312设置在第三边缘3111并沿第二方向200’朝向第一区域311的内部延伸。优选地，空白区域312在第一方向100’上的宽度W2’等于第一宽度W1’。
此时，第一电极31与第二电极32形成的第一重叠区域的面积为第二区域321 与第一区域311形成的第二重叠面积S22与第三区域322与第一区域311形成的第三重叠面积S23之和，同时再减去空白区域312与第二区域321形成的空白重叠面积S25，即第一重叠区域的面积等于S22+S23-S25。
与实施例一相同，在本实施例中，也只需说明对组精度沿第二方向200’变化时，第一重叠区域面积的变化情况。
如图6所示，第二电极32相对于第一电极31沿第二方向200’向下偏移，此时，第一重叠区域的面积为S22’+S23’-S25’。由于偏移量小于预设的第一距离D1’，第二区域321始终处于第一区域311的内部，所以第二重叠面积S22保持不变。然而，第三重叠面积S23’相对于图5中的第三重叠面积S23减小，同时空白重叠面积S25’相对于图5中的空白重叠面积S25也减小，从而能够将S22’+S23’-S25’的改变降到最小，减小了对组精度差异对第一重叠区域的面积造成的影响。尤其当W2’等于W1’时，能够最大程度地减小对组精度差异对第一重叠区域的面积造成的影响，从而使得图6中的第一重叠区域的面积与图5中的第一重叠区域的面积保持一致，这样就改善了对组精度差异引起的存储电容差异，也就改善了由此产生的水痕。
如图7所示，第二电极32相对于第一电极31沿第二方向200’向上偏移，此时，第一重叠区域的面积为S22”+S23”-S25”。由于偏移量同样小于预设的第一距离D1’，第二重叠面积S22仍旧保持不变。与图6不同的是，第三重叠面积S23”相对于图5中的第三重叠面积S23增大，同时，空白重叠面积S25”相对于图5中的空白重叠面积S25也增大，从而能够将S22”+S23”-S25”的改变降到最小，减小了对组精度差异对第一重叠区域的面积造成的影响。尤其当W2’等于W1’时，能够最大程度地减小对组精度差异对第一重叠区域的面积造成的影响，从而使得图7中的第一重叠区域的面积与图5中的第一重叠区域的面积保持一致，这样就改善了对组精度差异引起的存储电容差异，也就改善了由此产生的水痕。
优选地，如图5所示，空白区域312在第二方向200’上的长度D2’等于或大于第一距离D1’的2倍。这样，无论第二电极32相对于第一电极31沿第二方向200’向下还是向上偏移，只要偏移量保持在D1’以内，空白重叠面积在第二方向上的改变量始终等于第三重叠面积在第二方向上的改变量，因此，能够使得第一重叠区域的面积保持不变。从而避免了由于对组精度差异引起的存储电容 差异，避免了由此产生的水痕。
尤其当空白区域的沿第二方向的中心线与第三区域的沿第二方向的中心线相互重合时，第一重叠区域的面积不仅能够保持不变，而且也不会受到第一区域311和第二区域321的外周边缘形状的影响。
本发明还提出了一种阵列基板，该阵列基板包括实施例一或实施例二中提出的像素单元的存储电容，从而避免了由于不同像素单元的第一电极与第二电极的对组精度差异引起的存储电容差异，避免了由此产生的水痕，保证了面板显示的均匀，提高了产品的品质。
最后说明的是，以上实施例仅用于说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换。尤其是，只要不存在结构上的冲突，各实施例中的特征均可相互结合起来，所形成的组合式特征仍属于本发明的范围内。只要不脱离本发明技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (17)

  1. 一种像素单元，所述像素单元的存储电容设置在阵列基板上，所述存储电容包括设置在第一金属层的第一电极和设置在第二金属层的第二电极，在所述第一电极和所述第二电极之间设置有绝缘层，其中，
    所述第二电极和所述第一电极相互重叠形成第一重叠区域，若所述第二电极相对于所述第一电极的偏移在预设距离范围内，所述第一重叠区域的面积保持一致。
  2. 根据权利要求1所述的像素单元，其中，所述第一电极包括第一区域，所述第二电极包括第二区域和第三区域，其中，
    当所述第二区域与所述第一区域的中心相互重合时，所述第一区域的周向边缘相对于所述第二区域的周向边缘朝向所述第二区域的外侧偏移第一距离，
    所述第三区域设置在所述第二区域的第一边缘并沿第二方向朝向所述第二区域的外侧延伸，所述第三区域在第一方向上的宽度为第一宽度，
    所述第一方向与所述第二方向垂直，所述预设距离与所述第一距离相等。
  3. 根据权利要求2所述的像素单元，其中，所述第二电极还包括第四区域，所述第四区域设置在所述第二区域的第二边缘并沿所述第二方向朝向所述第二区域的外部延伸，所述第四区域在所述第一方向上的宽度等于所述第一宽度，所述第二边缘与所述第一边缘相对平行设置。
  4. 根据权利要求3所述的像素单元，其中，所述第四区域与所述第三区域相对设置。
  5. 根据权利要求3所述的像素单元，其中，所述第四区域在所述第二方向上的长度等于或大于所述第一距离的2倍。
  6. 根据权利要求2所述的像素单元，其中，所述第一电极还包括设置在所述第一区域的第三边缘并沿所述第二方向朝向所述第一区域内部延伸的空白区域，所述第三边缘与所述第一边缘相互平行且设置在所述第一边缘的相对侧。
  7. 根据权利要求6所述的像素单元，其中，所述空白区域的沿第二方向的中心线与所述第三区域的沿第二方向的中心线相互重合。
  8. 根据权利要求6所述的像素单元，其中，所述空白区域在所述第二方向上的长度等于或大于所述第一距离的2倍。
  9. 根据权利要求2所述的像素单元，其中，所述第一方向为所述第一边缘所在的方向，所述第二方向为所述第二电极相对于所述第一电极的偏移方向。
  10. 一种阵列基板，其中，所述阵列基板包括像素单元，所述像素单元的存储电容设置在阵列基板上，所述存储电容包括设置在第一金属层的第一电极和设置在第二金属层的第二电极，在所述第一电极和所述第二电极之间设置有绝缘层，其中，
    所述第二电极和所述第一电极相互重叠形成第一重叠区域，若所述第二电极相对于所述第一电极的偏移在预设距离范围内，所述第一重叠区域的面积保持一致。
  11. 根据权利要求10所述的阵列基板，其中，所述第一电极包括第一区域，所述第二电极包括第二区域和第三区域，其中，
    当所述第二区域与所述第一区域的中心相互重合时，所述第一区域的周向边缘相对于所述第二区域的周向边缘朝向所述第二区域的外侧偏移第一距离，
    所述第三区域设置在所述第二区域的第一边缘并沿第二方向朝向所述第二区域的外侧延伸，所述第三区域在第一方向上的宽度为第一宽度，
    所述第一方向与所述第二方向垂直，所述预设距离与所述第一距离相等。
  12. 根据权利要求11所述的阵列基板，其中，所述第二电极还包括第四区域，所述第四区域设置在所述第二区域的第二边缘并沿所述第二方向朝向所述第二区域的外部延伸，所述第四区域在所述第一方向上的宽度等于所述第一宽度，所述第二边缘与所述第一边缘相对平行设置。
  13. 根据权利要求12所述的阵列基板，其中，所述第四区域与所述第三区域相对设置。
  14. 根据权利要求11所述的阵列基板，其中，所述第一电极还包括设置在所述第一区域的第三边缘并沿所述第二方向朝向所述第一区域内部延伸的空白区域，所述第三边缘与所述第一边缘相互平行且设置在所述第一边缘的相对侧。
  15. 根据权利要求14所述的阵列基板，其中，所述空白区域的沿第二方向的中心线与所述第三区域的沿第二方向的中心线相互重合。
  16. 根据权利要求14所述的阵列基板，其中，所述空白区域在所述第二方向上的长度等于或大于所述第一距离的2倍。
  17. 根据权利要求11所述的阵列基板，其中，所述第一方向为所述第一边缘 所在的方向，所述第二方向为所述第二电极相对于所述第一电极的偏移方向。
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CN102544110A (zh) * 2012-03-19 2012-07-04 深圳市华星光电技术有限公司 具有寄生电容补正结构的薄膜晶体管及用该薄膜晶体管的液晶显示器

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