WO2018202040A1 - 嵌入式基板及其制造方法 - Google Patents

嵌入式基板及其制造方法 Download PDF

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Publication number
WO2018202040A1
WO2018202040A1 PCT/CN2018/085337 CN2018085337W WO2018202040A1 WO 2018202040 A1 WO2018202040 A1 WO 2018202040A1 CN 2018085337 W CN2018085337 W CN 2018085337W WO 2018202040 A1 WO2018202040 A1 WO 2018202040A1
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Prior art keywords
substrate
chip
embedded
layer
metal
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PCT/CN2018/085337
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English (en)
French (fr)
Inventor
鲍宽明
王军鹤
侯召政
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18794023.4A priority Critical patent/EP3608956A4/en
Publication of WO2018202040A1 publication Critical patent/WO2018202040A1/zh
Priority to US16/673,389 priority patent/US20200066644A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit

Definitions

  • the present application relates to the field of electronic materials and components, and in particular, to an embedded substrate and a method of fabricating the same.
  • ECP Embedded component packaging
  • FIG. 1 is a schematic structural view of a substrate (hereinafter referred to as an embedded substrate) based on an embedded component package.
  • the chip 102 required for the embedded substrate is embedded in the substrate 101, and each pin 1020 is disposed on the chip 102.
  • a plurality of drill holes 104 are opened on the substrate 101 by a drilling process, and the conductor material (such as copper) is filled in the drill holes 104 by a process such as electroplating, so that the respective pins of the component 102 pass through the conductor material in the drill hole 104.
  • the substrate 101 is taken out to be interconnected with other chips.
  • the laser of the drilling hole 104 may damage the chip; in actual processing, the performance of the drilling device limits the minimum drilling aperture, and during the drilling process The deviation of the borehole that can be caused by the control deviation. Due to these limitations, pins with dense pins, such as integrated chips, are also densely placed on the pins. To avoid chip damage, the holes cannot be too large or drilled. For existing drilling processes, A problem.
  • the embodiment of the present application provides an embedded substrate and a manufacturing method thereof to solve the problem that the drilling aperture cannot exceed the size of the chip pad in the existing embedded component packaging process.
  • an embodiment of the present application provides an embedded substrate, including: a substrate and a chip embedded in the substrate; a metal bump is disposed at a pin of the chip, and the pin and the One end of the metal boss forms an electrical connection, wherein a height direction of the metal boss is perpendicular to a plane of the chip, and a height value of the metal bump is 100 micrometers or more; on a first surface of the substrate Providing a conductor layer that meets the pin connection requirements, wherein the first surface is a surface on the substrate that is parallel to the chip and closest to the metal bump; the metal bump on the substrate a hole is formed between the other end of the stage and the conductor layer, and the hole is filled with a conductor material to pass a pin having a connection requirement on the chip through the metal boss and the conductor material. And connecting the conductor layer, wherein the borehole cross section exceeds a range of a cross section of the other end of the metal boss.
  • the drill hole can be kept at a certain distance from the chip, so that even if the hole is beyond the metal
  • the top surface of the boss has a substrate material having the same thickness as the metal bump, and the chip can be protected from damage. Therefore, the embedded substrate provided in the embodiment of the present application does not need to be based on the pad or the actual processing.
  • the size of the metal boss limits the aperture size of the borehole.
  • the application of the embodiment of the present application can expand the chip selection range, that is, the embedded package can be performed on any chip, and it is not necessary to consider whether the minimum aperture achieved by the drilling device is smaller than the pad size of the chip.
  • the application of the embodiment of the present application can also expand the selection range of the embedded substrate factory, and the minimum aperture achieved by the drilling equipment of each embedded substrate factory is no longer the main selection limiting factor, and can be based only on The selection of factors such as quotation will help reduce the cost of chip packaging.
  • the hole diameter of the hole in the embodiment of the present application is not limited by the pad size of the chip or the size of the metal boss, the hole diameter of the hole can be enlarged as much as possible in the actual packaging process to improve the flow and heat dissipation capability of the embedded substrate. .
  • the substrate includes: an intermediate substrate layer for embedding the chip and the metal bump, and a first surface substrate layer pressed onto one surface of the intermediate substrate layer;
  • the outer surface of the surface substrate layer is provided as the first surface, and the conductor layer is disposed, and the hole is formed in a region corresponding to each metal boss on the first surface substrate layer.
  • the substrate further includes: a second surface layer of the substrate laminated to the other surface of the intermediate substrate layer.
  • the intermediate substrate layer, the first surface substrate layer and the second surface substrate layer are all formed by resin processing; and the conductor layer comprises a metal plating layer.
  • the embedded substrate further includes a resistive element embedded in the substrate; a hole is formed between the terminal of the resistive element and the conductor layer, and the hole is filled with a conductor a material; a terminal of the tolerant element is connected to the conductor layer by a conductor material in a corresponding bore.
  • the embedded substrate provided by the implementation method has a simple structure, and the required process and materials are also easy to implement and obtain, and the manufacturing cost is not increased, and the conventional embedded component package is solved by setting a metal bump on the chip pin.
  • the problem that the hole diameter of the process is limited by the size of the pad on the chip makes the drilling operation easier to perform and does not damage the chip, which expands the selection range of the chip in the substrate factory, and also expands the chip supplier to the embedded substrate factory.
  • the selection range is beneficial to save the cost of chip packaging.
  • the aperture of the drilling hole is not limited in the embodiment of the present application, the aperture can be increased as much as possible to facilitate the flow and heat dissipation of the embedded substrate.
  • the embodiment of the present application further provides a method for manufacturing an embedded substrate, comprising: respectively providing a metal bump at each pin of the chip required for the embedded substrate, and placing the pin Forming an electrical connection with one end of the metal stud, wherein a height direction of the metal stud is perpendicular to a plane of the chip, and a height value of the metal stud is 100 micrometers or more; according to the embedded substrate Determining a relative position of each of the electronic components required for the embedded substrate, wherein the electronic component includes the chip to be embedded; filling a substrate material between respective electronic components determined at a relative position to form a substrate, so that The electronic component and the metal bump are embedded in the substrate; a conductor layer is disposed on the first surface of the substrate according to the connection requirement of the respective electronic components; the first surface is on the substrate and the a surface of the chip parallel and closest to the metal boss; a hole is formed between the other end of the metal boss and the conductor layer on the substrate, and the hole is filled in the
  • the borehole cross section extends beyond the cross section of the other end of the metal boss. Since the metal boss has a certain height, even if the cross section of the hole exceeds the cross section of the other end of the metal boss, a substrate material of a considerable thickness is protected from damage. Therefore, the embodiment of the present application is applied.
  • the mutual limitation of the chip pad size and the minimum hole diameter of the prior art can be eliminated; the relevant technician can appropriately set the hole diameter of the hole according to factors such as the drilling density and the heat dissipation of the chip.
  • filling the substrate material between the respective electronic components determined by the relative positions to form the substrate comprises: filling the substrate material between the respective electronic components determined at the relative positions, forming an intermediate substrate layer, and the chip and the metal bump Buried in the intermediate substrate layer; pressing the substrate material on the one surface of the intermediate substrate layer to form a first surface substrate layer; first in the substrate according to connection requirements of the respective electronic components Providing the conductor layer on the surface includes: providing a conductor layer on an outer surface of the first surface substrate layer according to a connection requirement of the respective electronic components.
  • a hole is formed between the other end of the metal boss and the conductor layer on the substrate, including: according to an actual embedded depth of the chip in the substrate and each metal boss The height value determines a corresponding drilling depth of each of the metal bosses; and a hole is formed in each of the regions corresponding to each of the metal bosses on the first surface substrate layer according to the drilling depth.
  • filling the substrate material between the respective electronic components determined by the relative positions to form the substrate further comprises: pressing the substrate material on the other surface of the intermediate substrate layer to form a second surface layer substrate layer.
  • the electronic component further includes a resistance resistive component; the method further includes: corresponding to the wiring of the capacitive resistive component on the substrate according to an actual embedded depth of the resistive resistive component in the substrate A bore is formed in the end region and the bore is filled with a conductor material such that the terminals of the resistive element are connected to the conductor layer through conductor material in the respective bore.
  • the application of the embodiment of the present application can expand the chip selection range, that is, the embedded package can be performed on any chip, and it is not necessary to consider whether the minimum aperture achieved by the drilling device is smaller than the pad size of the chip.
  • the application of the embodiment of the present application can also expand the selection range of the embedded substrate factory, and the minimum aperture achieved by the drilling equipment of each embedded substrate factory is no longer the main selection limiting factor, and can be based only on The selection of factors such as quotation will help reduce the cost of chip packaging.
  • the hole diameter of the hole in the embodiment of the present application is not limited by the pad size of the chip or the size of the metal boss, the hole diameter of the hole can be enlarged as much as possible in the actual packaging process to improve the flow and heat dissipation capability of the embedded substrate. .
  • 1 is a schematic structural view of a conventional embedded substrate
  • FIG. 2 is a schematic structural diagram of an embedded substrate according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another embedded substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a method for manufacturing an embedded substrate according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a process flow of a method for manufacturing an embedded substrate according to an embodiment of the present application.
  • the embedded substrate includes a substrate 21 and a chip 22 embedded in the substrate 21.
  • each of the pins 220 of the chip 22 is provided with a metal bump 23, and the pin 220 is electrically connected with one end of the corresponding metal boss 23; the height direction of the metal boss 23 is perpendicular to the plane of the chip 22, and the metal bump
  • the height direction of the stage 23 is parallel to the thickness (H) direction of the substrate 21, and the height value h1 of the metal boss 23 can be determined according to the embedded depth h0 of the chip 22 in the substrate 21, that is, the deeper the chip is embedded (the larger the h0), The height value h1 of the desired metal boss is also larger.
  • the height value h1 of each metal boss 23 is greater than 100 micrometers.
  • the first surface of the substrate 21 is provided with a conductor layer 25 conforming to the connection requirements of the respective pins 220, wherein the first surface is a surface on the substrate 21 which is parallel to the chip 22 and closest to the metal land 23.
  • Drill holes 24 are formed in the substrate 21 between the other end of each of the metal bosses 23 and the conductor layer 25, and each of the bore holes 24 is filled with a conductor material.
  • the cross section of the bore 24 may exceed the range of the cross section of the other end of the metal boss 23, thereby ensuring that the cross section of the metal boss 23 is small.
  • the contact area between the other end of the metal boss 23 and the conductor material is not less than the cross-sectional area of the metal boss 23, thereby ensuring an effective connection between the metal boss and the conductor material.
  • one end of the metal boss 23 is connected to the corresponding pin 220, and the other end is connected to the conductor material in the corresponding bore 24, and at the same time, the conductor material and the conductor in the bore 24 are on the surface of the substrate.
  • the layers are connected such that the pins having connection requirements in a single chip or between the plurality of chips in the embedded substrate embedded substrate are connected by metal bumps and conductor materials.
  • the interconnection between the five pins is implemented as shown in Figure 2.
  • the chip packaged by the above structure may be a chip provided with a pad, that is, a metal bump may be disposed on each pad, and then the chip is embedded (including drilling, filling a conductor material, providing a conductor layer, etc.).
  • a metal bump is placed directly on each pin of the chip, and then embedded in the package.
  • the metal boss has a certain height (greater than 100 micrometers), so that the deepest part of the hole can be kept at a certain distance from the chip, so that even if the hole is beyond the metal boss
  • the top surface range for example, the metal boss is a cylindrical boss with a diameter of 110um, the hole diameter of the hole is 150umm
  • the substrate material having the same thickness as the metal boss in the excess area can protect the chip from damage, so
  • the embedded substrate provided by the application embodiment does not need to limit the aperture size of the drill hole according to the size of the pad or the metal boss during the actual processing.
  • the application of the embodiment of the present application can expand the chip selection range, that is, the embedded package can be performed on any chip, and it is not necessary to consider whether the minimum aperture achieved by the drilling device is smaller than the pad size of the chip.
  • the application of the embodiment of the present application can also expand the selection range of the embedded substrate factory, and the minimum aperture achieved by the drilling equipment of each embedded substrate factory is no longer the main selection limiting factor, and can be based only on The selection of factors such as quotation will help reduce the cost of chip packaging.
  • the chip size of the chip A provided by a chip provider is 110um
  • the minimum hole diameter that the substrate factory C can reach is 110um
  • the price is 0.074 US dollars
  • the minimum drilling hole diameter that the substrate factory D can reach is 150um.
  • the quotation is 0.068 US dollars.
  • only the substrate manufacturer C with higher quotation can be selected to perform embedded packaging on the chip A; if the embodiment of the present application is applied, the pad size of the chip A or the added
  • the size of the metal bumps and the minimum aperture of each substrate factory can be selected for the embedded package of the chip A with the lower price of the substrate manufacturer D.
  • the packaging cost per chip can be saved by 0.006 US dollars.
  • the hole diameter of the hole in the embodiment of the present application is not limited by the pad size of the chip or the size of the metal boss, the hole diameter of the hole can be enlarged as much as possible in the actual packaging process to improve the flow and heat dissipation capability of the embedded substrate. .
  • FIG. 3 is a schematic structural diagram of another embedded substrate according to an embodiment of the present application. With respect to the structure shown in FIG. 2, FIG. 3 shows a specific structure of the substrate 21, that is, the intermediate substrate layer 211 and the first surface substrate layer 212 which is pressed against one surface of the intermediate substrate layer 211.
  • the intermediate substrate layer 211 is used for embedding the chip and the metal bump 23 thereof.
  • the end surface of the other end of the metal bump 23 is on the same plane as the surface of the intermediate substrate layer 211 on which the first surface substrate layer 212 is pressed. That is, the end face of the metal boss 23 is just exposed on the surface of the intermediate substrate layer 211.
  • the intermediate substrate layer 211 may be formed by filling between chips.
  • the outer surface of the first surface substrate layer 212 serves as a first surface (front surface) of the embedded substrate, and is provided with a conductor layer 25, and an end surface and a conductor at the other end of each metal bump 23 on the first surface substrate layer 212 A bore 24 is provided in the area between the layers 25. Since the end surface of the metal bump 23 is exposed on the first surface of the intermediate substrate layer 211, as long as the drilling depth is not less than the thickness of the first surface substrate layer 212, the filled conductor material is ensured inside the substrate and the metal convex. Station connection.
  • the end surface of the metal bump 23 is not exposed on the surface of the intermediate substrate layer 211, but is buried in the intermediate substrate layer 211, it can be ensured by increasing the drilling depth during drilling.
  • the metal boss is connected to the conductor material.
  • the substrate 21 in the embedded substrate may further include: a second surface substrate layer 213 that is pressed against the other surface of the intermediate substrate layer 211.
  • the outer surface of the second surface substrate layer 213 serves as the second surface (back surface) of the embedded substrate, and a conductor layer (generally used as a ground end) may be provided. Additionally, the drilled holes may pass through the entire substrate 21, communicating with the first and second surfaces of the embedded substrate, such as the bore 241 in FIG.
  • the electronic component embedded in the embedded substrate may include a capacitive resistive component 222 (ie, a capacitor, a resistor, etc.) in addition to the chip 221 having various functions. ).
  • the capacitive resistive element 222 is directly connected to the conductor material within the borehole within the substrate 21.
  • the embedding depth is the same, that is, the surface of the terminal of the resistive element 222 is ensured to be coplanar with the surface of the intermediate substrate layer which is laminated with the first surface substrate layer, that is, coplanar with the end surface of the metal stud, as shown in FIG.
  • the height h1 of the metal bump can be determined according to the maximum thickness h2 of the resistive element to be embedded in the embedded substrate: the larger the thickness h2 of the resistive element, the larger the thickness of the substrate required for the embedded package, and the metal bump
  • the height h1 of the stage can be set to a larger value to protect the chip from damage to a greater extent.
  • the basic material used for the intermediate substrate layer, the first surface substrate layer and the second surface substrate layer may specifically be a resin;
  • the conductor layer on the surface of the substrate may be a metal plating layer, such as a copper plating layer. That is, the metal wire layer which is processed by the electroplating process and meets the requirements of each pin connection of the embedded substrate, the conductor material in the drill hole may also be copper, which may be filled by a plating process, so that the electronic components in the embedded substrate (including The chip and the capacitive resistance element are connected to form a circuit having a specific function.
  • the embedded substrate provided by the embodiment of the present application has a simple structure, and the required processes and materials are also easy to implement and obtain, and the manufacturing cost is not increased, especially by providing metal bumps on the chip pins.
  • the platform solves the problem that the drilling aperture is limited by the size of the pad on the chip in the traditional embedded component packaging process, which makes the drilling operation easier to execute without damaging the chip, and expands the selection range of the chip factory to the chip, and also expands the scope.
  • the choice of the chip supplier to the embedded substrate factory is conducive to saving the cost of chip packaging.
  • the aperture of the drilling hole is not limited in the embodiment of the present application, the aperture can be increased as much as possible to facilitate the flow and heat dissipation of the embedded substrate.
  • FIG. 4 is a flowchart of the method for manufacturing the embedded substrate
  • FIG. 5 is a schematic diagram of a process flow corresponding to the method.
  • the method of manufacturing the embedded substrate includes the following steps:
  • Step S1 respectively providing a metal bump at each pin of the chip required for the embedded substrate, and electrically connecting the pin to one end of the metal boss;
  • the height direction of the metal bump 23 is perpendicular to the plane of the chip 221 .
  • the height of the metal boss 23 is greater than 100 micrometers.
  • Step S2 determining a relative position of each electronic component required for the embedded substrate according to a preset structure of the embedded substrate
  • the electronic component includes at least the chip 221 .
  • the electronic component may further include a capacitive resistive component 222.
  • Step S3 filling a substrate material between the respective electronic components determined at the relative positions to form a substrate
  • the electronic components are placed on the processing table according to the preset structure of the embedded substrate, and the relative positions are fixed, and then the basic materials are filled between the electronic components to form the substrate, and at the same time, the electronic components and the metal bumps are realized.
  • the stage is embedded in the substrate.
  • Step S4 providing a conductor layer on the first surface of the substrate according to the connection requirements of the respective electronic components
  • the first surface is a surface on the substrate that is parallel to the chip and closest to the metal bump. For details, refer to FIGS. 2 to 4.
  • step S5 a hole is formed between the other end of the metal boss and the conductor layer on the substrate, and a conductor material is filled in the hole.
  • the conductor material in the bore is connected to the end surface of the metal boss inside the substrate, and is connected to the conductor layer on the first surface of the substrate, so that each pin passes through the metal boss and the conductor.
  • the material is connected to the conductor layer to achieve the connection between the different pins where the connection requirements exist.
  • the four pins of the chip are led to the first surface of the embedded substrate through the metal bump and the conductor material in the drilled hole, and the terminals of the two resistive elements also pass through the conductor material in the drilled hole. Leading to the first surface of the embedded substrate and achieving its connection to other pins through the conductor layer 25 on the first surface of the embedded substrate.
  • the depth of the end surface of the metal boss in the substrate in order to keep the depths of the respective drilling holes uniform and to facilitate uniform control during the drilling operation, it is necessary to ensure the depth of the end surface of the metal boss in the substrate, and the wiring of the resistance-resisting component.
  • the surface on which the end is located has the same depth of embedding in the substrate, that is, the surface on which the terminal of the resistive element 222 is located is coplanar with the top surface of the intermediate substrate layer and the metal land.
  • the embodiment of the present application can determine the height of the metal bump based on the maximum thickness of the resistive component to be embedded in the embedded substrate: the greater the thickness of the resistive component, the greater the thickness of the substrate required for the embedded package Large, metal boss heights can be set to larger values to protect the chip from damage to a greater extent.
  • the borehole cross section exceeds a range of a cross section of the other end of the metal boss. Since the metal boss has a certain height, even if the cross section of the hole exceeds the cross section of the other end of the metal boss, a substrate material of a considerable thickness is protected from damage. Therefore, the embodiment of the present application is applied.
  • the mutual limitation of the chip pad size and the minimum hole diameter of the prior art can be eliminated; the relevant technician can appropriately set the hole diameter of the hole according to factors such as the drilling density and the heat dissipation of the chip.
  • the plurality of bores 24, as shown in Figure 5, have a larger diameter than the top surface of the metal boss.
  • the cross-sectional area of the other end of the metal boss is small, the cross-section of the drill hole in the embodiment exceeds the cross-section of the other end of the metal boss, and the metal boss can be ensured.
  • the contact area between the other end and the conductor material is not less than the cross-sectional area of the other end of the metal boss, thereby ensuring an effective connection between the metal boss and the conductor material.
  • the embedded substrate provided by the embodiment of the present application does not need to limit the aperture size of the drill hole according to the size of the pad or the metal bump during the actual processing.
  • the application of the embodiment of the present application can expand the chip selection range, that is, the embedded package can be performed on any chip, and it is not necessary to consider whether the minimum aperture achieved by the drilling device is smaller than the pad size of the chip.
  • the application of the embodiment of the present application can also expand the selection range of the embedded substrate factory, and the minimum aperture achieved by the drilling equipment of each embedded substrate factory is no longer the main selection limiting factor, and can be based only on The selection of factors such as quotation will help reduce the cost of chip packaging.
  • the hole diameter of the hole in the embodiment of the present application is not limited by the pad size of the chip or the size of the metal boss, the hole diameter of the hole can be enlarged as much as possible in the actual packaging process to improve the flow and heat dissipation capability of the embedded substrate. .
  • the substrate material is filled between the respective electronic components determined by the relative position as described in the above step S3 to form a substrate, and specifically includes the following steps:
  • Step S31 filling the substrate material between the respective electronic components determined by the relative position, forming the intermediate substrate layer 211;
  • the resistive element, the chip, and the metal bump are embedded in the intermediate substrate layer 211 by filling the substrate material.
  • Step S32 pressing the substrate material on the first surface of the intermediate substrate layer 211 to form the first surface layer substrate layer 212.
  • step S32 may further include: pressing the substrate material on the second surface of the intermediate substrate layer 211 to form the second surface substrate layer 213.
  • step S32, step S4 may be performed on the first surface substrate layer 212, and the conductor layer described in step S5 may also be disposed on the outer surface of the first surface substrate layer 212; As shown in FIG. 5, in some possible embodiments, the surface of the second surface substrate layer 213 may also be provided with a conductor layer, and the conductor layer of the outer surface of the first surface substrate layer is connected by drilling through the entire substrate.
  • the top surface of the metal bump and the surface of the terminal of the resistance resisting element may be controlled, and the intermediate substrate layer 211 is The first surfaces are coplanar, so that the drilling depth of each of the drill holes can be kept consistent in step S4, which is the thickness of the first surface substrate layer 212, which is convenient for uniform control during drilling operation.
  • each drilling depth may not be completely the same.
  • each of the actual embedded depth of the chip in the substrate and the height value of each metal boss is determined.
  • Corresponding drilling depths of the metal bosses are respectively drilled in the regions corresponding to the terminals of each of the metal bosses and/or the capacitive resistive elements on the first surface substrate layer according to the determined drilling depth.
  • the substrate material used in the embodiments of the present application may be a resin, and the metal bumps may be formed by using copper.
  • the conductor material and the conductor layer may also be made of metal copper and processed by an electroplating process.
  • the materials used in the manufacturing process of the embedded substrate provided by the embodiments of the present application are easy to obtain, and the process technology used is simple and easy to implement, especially eliminating the mutual limitation of the chip pad size and the minimum hole diameter of the prior art.
  • the borehole diameter of the borehole is maximized, on the one hand, the performance requirements of the drilling equipment are reduced, and on the other hand, the flow-through and heat dissipation capability of the embedded substrate after molding can be improved.

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Abstract

本申请实施例公开了一种嵌入式基板及其制造方法，该嵌入式基板包括基板和埋嵌于所述基板内的芯片；该芯片的各个引脚处设有高度值大于100微米的金属凸台，该基板上对应于金属凸台的区域设有钻孔，钻孔内填充导体材料，该基板的第一表面设有符合各引脚连接需求的导体层，存在连接需求的各个引脚之间通过金属凸台、导体材料及导体层实现连接。本实施例中通过金属凸台使钻孔与芯片保持一定距离，即使钻孔超出金属凸台的范围，超出区域的基板材料也可以保护芯片不受损坏，故不需要限制钻孔的孔径大小，扩大了基板厂对芯片的选型范围和芯片提供方对埋嵌基板厂的选择范围，有利于节约成本。同时，钻孔孔径可以尽量增大，利于嵌入式基板的通流和散热。

Description

嵌入式基板及其制造方法
本申请要求于2017年5月5日提交中国专利局、申请号为201710313770.5、发明名称为“嵌入式基板及其制造方法”的中国专利申请的中国专利申请的优先权，这些中国专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子材料与元器件技术领域，尤其涉及一种嵌入式基板及其制造方法。
背景技术
嵌入式元件封装(embedded component packaging,ECP)，是一种将电容、电阻和芯片等电子元件埋嵌入基板内部的封装形态。它可以缩短元件之间的链接路径，降低传输损失，提升产品集成度，减少模块外形尺寸，同时能提升产品的可靠性和电热性能，是实现便携式电子设备多功能化和高性能化的一种重要手段。
现有生产工艺中，嵌入式元件封装一般是通过钻孔及电镀工艺实现的。如图1所示的现有一种基于嵌入式元件封装的基板(以下称嵌入式基板)结构示意图，该嵌入式基板所需的芯片102嵌入基板101内部，芯片102上设置有各个引脚1020，并通过钻孔工艺在基板101上开设多个钻孔104，，再通过电镀等工艺在钻孔104中填充导体材料(如铜)，使得元件102的各个引脚通过钻孔104中的导体材料引出基板101外，以便与其他芯片互连。
可见，依照上述现有嵌入式元件封装工艺，钻孔104钻孔时的激光会对芯片有损伤；而实际加工过程中，钻孔设备的性能限制了其最小钻孔孔径，且钻孔过程中控制偏差可能导致的钻孔偏移。由于这些限制因素，引脚交密集的芯片，如集成芯片，其上设置的引脚也会很密集，为避免芯片损伤，钻孔不能太大或者钻偏，对现有钻孔工艺来说是一个难题。
发明内容
本申请实施例提供了一种嵌入式基板及其制造方法，以解决现有嵌入式元件封装工艺中钻孔孔径不能超过芯片焊盘尺寸的问题。
第一方面，本申请实施例提供了一种嵌入式基板，包括：基板和埋嵌于所述基板内的芯片；所述芯片的引脚处设置有金属凸台，且所述引脚与所述金属凸台的一端形成电连接，其中，所述金属凸台的高度方向垂直于所述芯片所在平面，且所述金属凸台的高度值为100微米以上；所述基板的第一表面上设置有配合所述引脚连接需求的导体层，其中，所述第一表面为所述基板上与所述芯片平行且与所述金属凸台距离最近的表面；所述基板上所述金属凸台的另一端与与所述导体层之间开设有钻孔，所述钻孔内填充有导体材料，以将所述芯片上存在连接需求的引脚通过所述金属凸台及所述导体材料，和所述导体层实现连接，其中，所述钻孔横截面超出所述金属凸台所述另一端的横截面的范围。
采用本实现方式，在保证基板内嵌入的电子元件引脚正常连接的前提下，由于金属凸台存在一定高度(100微米以上)，可以使得钻孔与芯片保持一定距离，从而即使钻孔超出金属凸台的顶面范围，超出区域也有厚度与金属凸台高度相同的基板材料，可以保护芯片 不受损坏，因此本申请实施例提供的嵌入式基板在实际加工过程中，不需要根据焊盘或金属凸台的尺寸限制钻孔的孔径大小。对于埋嵌基板厂而言，应用本申请实施例可以扩大芯片选型范围，即可以对任意芯片进行嵌入式封装，不需要考虑自己的钻孔设备所达到的最小孔径是否小于芯片的焊盘尺寸；对于芯片提供方而言，应用本申请实施例也可以扩大对埋嵌基板厂的选择范围，各个埋嵌基板厂的钻孔设备所达到的最小孔径不再是主要选择限制因素，可以仅根据报价等因素进行选择，有利于降低芯片封装成本。
另外，由于本申请实施例中钻孔孔径不受芯片的焊盘尺寸或金属凸台尺寸限制，故在实际封装过程中可以尽量扩大钻孔的孔径，以提高嵌入式基板的通流和散热能力。
可选的，所述基板包括：用于埋嵌所述芯片及所述金属凸台的中间基板层，及压合于所述中间基板层的一个表面的第一表层基板层；所述第一表层基板层的外表面作为所述第一表面，设置有所述导体层，所述第一表层基板层上对应于每个金属凸台的区域开设有所述钻孔。
可选的，所述基板还包括：压合于所述中间基板层的另一个表面的第二表层基板层。
可选的，所述中间基板层、第一表层基板层和第二表层基板层均由树脂加工形成；所述导体层包括金属镀层。
可选的，所述嵌入式基板还包括埋嵌于所基板内的容阻元件；所述容阻元件的接线端与所述导体层之间开设有钻孔，所述钻孔内填充有导体材料；所述容阻元件的接线端通过相应钻孔内的导体材料与所述导体层连接。
本实现方式提供的嵌入式基板，结构简单，所需工艺及材料也较易实现、获得，不会增加制造成本，特别是通过在芯片引脚上设置金属凸台，解决了传统嵌入式元件封装工艺中钻孔孔径受芯片上焊盘尺寸限制的问题，使得钻孔操作更易执行且不会损坏芯片，扩大了基板厂对芯片的选型范围，也扩大了芯片提供方对埋嵌基板厂的选择范围，有利于节约芯片封装成本。同时，由于本申请实施例对钻孔的孔径无限制，故可以尽量增大孔径，利于嵌入式基板的通流和散热。
第二方面，本申请实施例还提供了一种嵌入式基板的制造方法，包括：在所述嵌入式基板所需的芯片的每个引脚处分别设置金属凸台，且将所述引脚与金属凸台的一端形成电连接，其中，所述金属凸台的高度方向垂直于所述芯片所在平面，且所述金属凸台的高度值为100微米以上；根据所述嵌入式基板的预设结构确定所述嵌入式基板所需的各个电子元件的相对位置，其中，所述电子元件包括所述待嵌入芯片；在相对位置确定的各个电子元件之间填充基板材料，形成基板，以使所述电子元件及金属凸台埋嵌于所述基板内；根据所述各个电子元件的连接需求在所述基板的第一表面设置导体层；所述第一表面为所述基板上与所述芯片平行且与所述金属凸台距离最近的表面；在所述基板上所述金属凸台的另一端与所述导体层之间开设钻孔，并在所述钻孔内填充导体材料，以将所述芯片上存在连接需求的引脚通过所述金属凸台及所述导体材料，和所述导体层实现连接，其中，所述钻孔横截面超出所述金属凸台所述另一端的横截面的范围。
采用本实现方式，所述钻孔横截面超出所述金属凸台所述另一端的横截面的范围。由于金属凸台存在一定高度，即使钻孔横截面超出金属凸台的所述另一端的横截面的范围，也会有相当厚度的基板材料保护芯片不被损坏，因此，应用本申请实施例，可以消除现有技术中芯片焊盘尺寸与钻孔最小孔径的相互限制；相关技术人员可以根据钻孔密集度和芯 片散热等因素，合理设置钻孔的孔径。
可选的，在相对位置确定的各个电子元件之间填充基板材料，形成基板，包括：在相对位置确定的各个电子元件之间填充基板材料，形成中间基板层，使所述芯片及金属凸台埋嵌于所述中间基板层内；在所述中间基板层的所述一个表面上压合基板材料，形成第一表层基板层；根据所述各个电子元件的连接需求在所述基板的第一表面设置导体层，包括：根据所述各个电子元件的连接需求在所述第一表层基板层的外表面设置导体层。
可选的，在所述基板上所述金属凸台的另一端与所述导体层之间开设钻孔，包括：根据所述芯片在所述基板内的实际嵌入深度及每个金属凸台的高度值确定每个金属凸台对应的钻孔深度；根据所述钻孔深度在所述第一表层基板层上对应于每个金属凸台的区域分别开设钻孔。
可选的，在相对位置确定的各个电子元件之间填充基板材料，形成基板，还包括：在所述中间基板层的另一表面压合基板材料，形成第二表层基板层。
可选的，所述电子元件还包括容阻元件；所述方法还包括：根据所述容阻元件在所述基板内的实际嵌入深度，在所述基板上对应于所述容阻元件的接线端的区域开设钻孔，并在所述钻孔内填充有导体材料，以使所述容阻元件的接线端通过相应钻孔内的导体材料与所述导体层连接。
本申请实施例提供的嵌入式基板的制造方法中，不需要根据焊盘或金属凸台的尺寸限制钻孔的孔径大小。对于埋嵌基板厂而言，应用本申请实施例可以扩大芯片选型范围，即可以对任意芯片进行嵌入式封装，不需要考虑自己的钻孔设备所达到的最小孔径是否小于芯片的焊盘尺寸；对于芯片提供方而言，应用本申请实施例也可以扩大对埋嵌基板厂的选择范围，各个埋嵌基板厂的钻孔设备所达到的最小孔径不再是主要选择限制因素，可以仅根据报价等因素进行选择，有利于降低芯片封装成本。另外，由于本申请实施例中钻孔孔径不受芯片的焊盘尺寸或金属凸台尺寸限制，故在实际封装过程中可以尽量扩大钻孔的孔径，以提高嵌入式基板的通流和散热能力。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有一种嵌入式基板的结构示意图；
图2为本申请实施例提供的一种嵌入式基板的结构示意图；
图3为本申请实施例提供的另一种嵌入式基板的结构示意图；
图4为本申请实施例提供的一种嵌入式基板的制造方法的流程图；
图5为本申请实施例提供的一种嵌入式基板的制造方法的工艺流程示意图。
具体实施方式
图2为本申请实施例提供的一种嵌入式基板的结构示意图，更具体的是沿该嵌入式基板的厚度方向的截面图。参照图2，该嵌入式基板包括：基板21和埋嵌于所述基板21内的芯片22。
其中，芯片22的各个引脚220处均设置有金属凸台23，引脚220与相应金属凸台23 的一端形成电连接；金属凸台23的高度方向垂直于芯片22所在平面，且金属凸台23的高度方向平行于基板21的厚度(H)方向，金属凸台23的高度值h1可以根据芯片22在基板21内的嵌入深度h0来确定，即芯片嵌入越深(h0越大)，所需金属凸台的高度值h1也越大。可选的，本实施例中，各个金属凸台23的高度值h1大于100微米。
基板21的第一表面设置有符合各个引脚220连接需求的导体层25，其中，所述第一表面为基板21上与芯片22平行且与金属凸台23距离最近的表面。基板21上在每个金属凸台23的另一端与导体层25之间均开设有钻孔24，每个钻孔24内填充有导体材料。其中，由于金属凸台23的横截面面积较小，故本实施例中，所述钻孔24的横截面可以超出所述金属凸台23的所述另一端的横截面的范围，从而可以保证金属凸台23的另一端与导体材料之间的接触面积不小于金属凸台23的横截面面积，从而保证金属凸台和导体材料之间的有效连接。
通过上述结构，在基板内部，金属凸台23的一端与相应的引脚220连接，另一端与相应钻孔24内的导体材料连接，同时，在基板表面，钻孔24内的导体材料与导体层连接，使得该嵌入式基板嵌入式基板内的单个芯片内或多个芯片之间上存在连接需求的引脚通过金属凸台及导体材料实现连接。如图2中实现了5个引脚之间的互连。
上述结构所封装的芯片可以为已设置有焊盘的芯片，即可以在各个焊盘上设置金属凸台，然后再对该芯片进行嵌入式封装(包括钻孔、填充导体材料、设置导体层等)；对于未设置焊盘的芯片，直接在芯片的各个引脚上设置金属凸台，然后进行嵌入式封装。
可见，本申请实施例在保证引脚正常连接的前提下，由于金属凸台存在一定高度(大于100微米)，可以使得钻孔最深处与芯片保持一定距离，从而即使钻孔超出金属凸台的顶面范围(例如，金属凸台为直径为110um的圆柱型凸台，钻孔的孔径为150umm)，超出区域也有厚度与金属凸台高度相同的基板材料，可以保护芯片不受损坏，因此本申请实施例提供的嵌入式基板在实际加工过程中，不需要根据焊盘或金属凸台的尺寸限制钻孔的孔径大小。对于埋嵌基板厂而言，应用本申请实施例可以扩大芯片选型范围，即可以对任意芯片进行嵌入式封装，不需要考虑自己的钻孔设备所达到的最小孔径是否小于芯片的焊盘尺寸；对于芯片提供方而言，应用本申请实施例也可以扩大对埋嵌基板厂的选择范围，各个埋嵌基板厂的钻孔设备所达到的最小孔径不再是主要选择限制因素，可以仅根据报价等因素进行选择，有利于降低芯片封装成本。
例如，某芯片提供方提供的芯片A的焊盘尺寸为110um，基板厂C所能达到的最小钻孔孔径为110um，报价为0.074美元，基板厂D所能达到的最小钻孔孔径为150um，报价为0.068美元，若依照现有技术，只能选择报价更高的基板厂C对芯片A进行嵌入式封装；而若应用本申请实施例，则不需考虑芯片A的焊盘尺寸或增设的金属凸台的尺寸与各个基板厂的最小孔径，可以选择报价更低的基板厂D对芯片A进行嵌入式封装，相对于选择基板厂C，每个芯片的封装成本可节省0.006美元。
另外，由于本申请实施例中钻孔孔径不受芯片的焊盘尺寸或金属凸台尺寸限制，故在实际封装过程中可以尽量扩大钻孔的孔径，以提高嵌入式基板的通流和散热能力。
图3为本申请实施例提供的另一种嵌入式基板的结构示意图。相对于图2所示结构，图3示出了基板21的一种具体结构，即包括：中间基板层211和压合于中间基板层211的一个表面的第一表层基板层212。
其中，中间基板层211用于埋嵌芯片及其金属凸台23，金属凸台23的另一端的端面与所述中间基板层211上压合有第一表层基板层212的表面在同一平面上，也即金属凸台23的端面恰好裸露于中间基板层211的表面上。中间基板层211可以在芯片之间填充形成。
第一表层基板层212的外表面作为上述嵌入式基板的第一表面(正面)，设置有导体层25，且第一表层基板层212上在每个金属凸台23的另一端的端面与导体层25之间的区域开设有钻孔24。由于金属凸台23的所述端面裸露于中间基板层211的第一表面上，故只要钻孔深度不小于第一表层基板层212的厚度，即可保证填充的导体材料在基板内部与金属凸台连接。实际加工过程中，即使金属凸台23的所述端面没有裸露在中间基板层211的表面上，而是也埋入中间基板层211内，也可以在钻孔时通过增加钻孔深度，来保证金属凸台与导体材料连接。
在本申请一个可行的实施例中，上述嵌入式基板中的基板21还可以包括：压合于中间基板层211的另一个表面的第二表层基板层213。
根据实际应用需求，第二表层基板层213的外表面作为嵌入式基板的第二表面(背面)，也可以设置导体层(一般作为接地端)。另外，钻孔可以穿过整个基板21，连通嵌入式基板的第一表面和第二表面，如图3中的钻孔241。
仍参照图3，在本申请一个可行的实施例中，上述嵌入式基板内埋嵌的电子元件除了具有各种功能的芯片221外，还可以包括容阻元件222(即电容、电阻等电子元件)。容阻元件222在基板21内部直接与钻孔内的导体材料连接。
本申请实施例中，为保持各个钻孔深度一致，便于钻孔操作时统一控制，需保证金属凸台的顶面在基板内的嵌入深度，与容阻元件的接线端所在表面在基板内的嵌入深度相同，即保证容阻元件222的接线端所在表面与中间基板层中压合有第一表层基板层的表面共面，也即与金属凸台的端面共面，如图3所示。有鉴于此，可以根据嵌入式基板内要嵌入的容阻元件的最大厚度h2确定金属凸台的高度h1：容阻元件厚度h2越大，埋嵌封装所需的基板厚度也越大，金属凸台的高度h1可以设置为越大的值，以更大程度上保护芯片不受损坏。
在本申请一个可行的实施例中，上述中间基板层、第一表层基板层和第二表层基板层所采用的基本材料具体可以为树脂；基板表面的导体层可以为金属镀层，如铜镀层，即通过电镀工艺加工得到的符合嵌入式基板的各个引脚连接需求的金属导线层，钻孔内的导体材料也可以为铜，具体可以通过电镀工艺填充，使得嵌入式基板内各个电子元件(包括芯片和容阻元件)连接形成具有特定功能的电路。
从以上实施例可以看出，本申请实施例提供的嵌入式基板，结构简单，所需工艺及材料也较易实现、获得，不会增加制造成本，特别是通过在芯片引脚上设置金属凸台，解决了传统嵌入式元件封装工艺中钻孔孔径受芯片上焊盘尺寸限制的问题，使得钻孔操作更易执行且不会损坏芯片，扩大了基板厂对芯片的选型范围，也扩大了芯片提供方对埋嵌基板厂的选择范围，有利于节约芯片封装成本。同时，由于本申请实施例对钻孔的孔径无限制，故可以尽量增大孔径，利于嵌入式基板的通流和散热。
基于上述结构，本申请实施例还提供了一种嵌入式基板的制造方法，图4为该嵌入式基板制造方法的流程图，图5为该方法对应的工艺流程示意图。
参照图4和图5，该嵌入式基板的制造方法包括以下步骤：
步骤S1，在所述嵌入式基板所需的芯片的每个引脚处分别设置金属凸台，且将所述引脚与金属凸台的一端形成电连接；
如图5所示的所述嵌入式基板所需的芯片221和金属凸台23，金属凸台23的高度方向垂直于芯片221所在平面。本实施例中，所述金属凸台23的高度值大于100微米。
步骤S2，根据所述嵌入式基板的预设结构确定所述嵌入式基板所需的各个电子元件的相对位置；
其中，如图5所示，所述电子元件至少包括所述芯片221。在本申请一些可行的实施例中，所述电子元件还可以包括容阻元件222。
步骤S3，在相对位置确定的各个电子元件之间填充基板材料，形成基板；
将各个电子元件按照该嵌入式基板的预设结构放置于加工台上，并保持其相对位置固定，然后在这些电子元件之间填充基本材料，即可形成基板，同时实现各个电子元件及金属凸台埋嵌于该基板内。
步骤S4，根据所述各个电子元件的连接需求在所述基板的第一表面设置导体层；
其中，所述第一表面为所述基板上与所述芯片平行且与所述金属凸台距离最近的表面，具体可参照图2～4。
步骤S5，在所述基板上所述金属凸台的另一端与所述导体层之间开设钻孔，并在所述钻孔内填充导体材料。
本实施例中，钻孔内的导体材料，在基板内部，与金属凸台的端面连接，在基板的第一表面上，与导体层连接，从而使各个引脚通过所述金属凸台及导体材料，实现与导体层的连接，进而实现存在连接需求的不同引脚之间的连接。如图5所示，芯片的四个引脚均通过金属凸台和钻孔内的导体材料引至嵌入式基板的第一表面，两个容阻元件的接线端也通过钻孔内的导体材料引至嵌入式基板的第一表面，并在嵌入式基板的第一表面上通过导体层25实现其与其他引脚的连接。
本申请一个可行的实施例中，为保持各个钻孔深度一致，便于钻孔操作时统一控制，需保证金属凸台的所述另一端的端面在基板内的嵌入深度，与容阻元件的接线端所在表面在基板内的嵌入深度相同，即保证容阻元件222的接线端所在表面与中间基板层的与金属凸台的顶面共面。可选的，本申请实施例可以以嵌入式基板中要嵌入的容阻元件的最大厚度为基准，确定金属凸台的高度：容阻元件厚度越大，埋嵌封装所需的基板厚度也越大，金属凸台的高度可以设置为越大的值，以更大程度上保护芯片不受损坏。
本实施例中，所述钻孔横截面超出所述金属凸台所述另一端的横截面的范围。由于金属凸台存在一定高度，即使钻孔横截面超出金属凸台的所述另一端的横截面的范围，也会有相当厚度的基板材料保护芯片不被损坏，因此，应用本申请实施例，可以消除现有技术中芯片焊盘尺寸与钻孔最小孔径的相互限制；相关技术人员可以根据钻孔密集度和芯片散热等因素，合理设置钻孔的孔径。如图5所示的多个钻孔24，其孔径均大于金属凸台的顶面直径。另外，由于金属凸台所述另一端的横截面面积较小，故本实施例中所述钻孔的横截面超出所述金属凸台所述另一端的横截面的范围，可以保证金属凸台所述另一端与导体材料之间的接触面积不小于该金属凸台所述另一端的横截面面积，进而保证金属凸台和导体材料之间的有效连接。
可见，本申请实施例提供的嵌入式基板在实际加工过程中，不需要根据焊盘或金属凸 台的尺寸限制钻孔的孔径大小。对于埋嵌基板厂而言，应用本申请实施例可以扩大芯片选型范围，即可以对任意芯片进行嵌入式封装，不需要考虑自己的钻孔设备所达到的最小孔径是否小于芯片的焊盘尺寸；对于芯片提供方而言，应用本申请实施例也可以扩大对埋嵌基板厂的选择范围，各个埋嵌基板厂的钻孔设备所达到的最小孔径不再是主要选择限制因素，可以仅根据报价等因素进行选择，有利于降低芯片封装成本。
另外，由于本申请实施例中钻孔孔径不受芯片的焊盘尺寸或金属凸台尺寸限制，故在实际封装过程中可以尽量扩大钻孔的孔径，以提高嵌入式基板的通流和散热能力。
参照图5，在本申请一个可行的实施例中，上述步骤S3所述的在相对位置确定的各个电子元件之间填充基板材料，形成基板，具体可以包括以下步骤：
步骤S31、在相对位置确定的各个电子元件之间填充基板材料，形成中间基板层211；
通过填充基板材料，使所述容阻元件、芯片及金属凸台均被埋嵌于所述中间基板层211内。
步骤S32、在所述中间基板层211的第一表面压合基板材料，形成第一表层基板层212。
在一个可行的实施例中，步骤S32还可以包括：在所述中间基板层211的第二表面压合基板材料，形成第二表层基板层213。
基于步骤S32，步骤S4所述的钻孔工艺，具体可以在第一表层基板层212上执行，同时，步骤S5所述的导体层也可以设置在第一表层基板层212的外表面；如图5所示，在一些可行的实施例中，第二表层基板层213的表面也可以设置导体层，并通过穿过整个基板的钻孔实现与第一表层基板层外表面的导体层连接。
在一个可行的实施例中，上述步骤S31中填充基板材料形成中间基板层211时，可以控制所述金属凸台的顶面和容阻元件的接线端所在表面，均与所述中间基板层211的第一表面共面，从而在步骤S4中，各个钻孔的钻孔深度可以保持一致，均为第一表层基板层212的厚度，便于钻孔操作时统一控制。
在其他可行的实施例中，各个钻孔深度也可以不完全相同，在执行步骤S4时，先根据所述芯片在所述基板内的实际嵌入深度及每个金属凸台的高度值确定每个金属凸台对应的钻孔深度，再根据所确定的钻孔深度在所述第一表层基板层上对应于每个金属凸台和/或容阻元件的接线端的区域分别开设钻孔。
本申请实施例所采用的基板材料可以为树脂，金属凸台具体可以采用铜加工而成，导体材料及导体层也可以采用金属铜，并通过电镀工艺加工。
可见，本申请实施例提供的嵌入式基板制造过程所采用的材料易获得，所使用的工艺技术简单易执行，尤其消除现有技术中芯片焊盘尺寸与钻孔最小孔径的相互限制，可以在钻孔密集度允许范围内，尽量扩大钻孔的孔径，一方面降低对钻孔设备的性能要求，另一方面可以提高成型后的嵌入式基板通流和散热能力。
本说明书中各个实施例之间相同相似的部分互相参见即可。以上所述的本发明实施方式并不构成对本发明保护范围的限定。

Claims (11)

  1. 一种嵌入式基板，其特征在于，包括：基板和埋嵌于所述基板内的芯片；
    所述芯片的引脚处设置有金属凸台，且所述引脚与所述金属凸台的一端形成电连接，其中，所述金属凸台的高度方向垂直于所述芯片所在平面，且所述金属凸台的高度值为100微米以上；
    所述基板的第一表面上设置有配合所述引脚连接需求的导体层，其中，所述第一表面为所述基板上与所述芯片平行且与所述金属凸台距离最近的表面；
    所述基板上所述金属凸台的另一端与与所述导体层之间开设有钻孔，所述钻孔内填充有导体材料，以将所述芯片上存在连接需求的引脚通过所述金属凸台及所述导体材料，和所述导体层实现连接，其中，所述钻孔横截面超出所述金属凸台所述另一端的横截面的范围。
  2. 根据权利要求1所述的嵌入式基板，其特征在于，所述基板包括：用于埋嵌所述芯片及所述金属凸台的中间基板层，及压合于所述中间基板层的一个表面的第一表层基板层；
    所述第一表层基板层的外表面作为所述第一表面，设置有所述导体层，所述第一表层基板层上对应于每个金属凸台的区域开设有所述钻孔。
  3. 根据权利要求2所述的嵌入式基板，其特征在于，所述基板还包括：压合于所述中间基板层的另一个表面的第二表层基板层。
  4. 根据权利要求3所述的嵌入式基板，其特征在于，所述中间基板层、第一表层基板层和第二表层基板层均由树脂加工形成；
    所述导体层包括金属镀层。
  5. 根据权利要求1至4中任一项所述的嵌入式基板，其特征在于，还包括埋嵌于所基板内的容阻元件；
    所述容阻元件的接线端与所述导体层之间开设有钻孔，所述钻孔内填充有导体材料；所述容阻元件的接线端通过相应钻孔内的导体材料与所述导体层连接。
  6. 根据权利要求5所述的嵌入式基板，其特征在于，所述引脚与所述金属凸台之间设置有焊盘，所述焊盘用于焊接所述引脚及所述金属凸台。
  7. 一种嵌入式基板的制造方法，其特征在于，包括：
    在所述嵌入式基板所需的芯片的每个引脚处分别设置金属凸台，且将所述引脚与金属凸台的一端形成电连接，其中，所述金属凸台的高度方向垂直于所述芯片所在平面，且所述金属凸台的高度值为100微米以上；
    根据所述嵌入式基板的预设结构确定所述嵌入式基板所需的各个电子元件的相对位置，其中，所述电子元件包括所述待嵌入芯片；
    在相对位置确定的各个电子元件之间填充基板材料，形成基板，以使所述电子元件及金属凸台埋嵌于所述基板内；
    根据所述各个电子元件的连接需求在所述基板的第一表面设置导体层；所述第一表面为所述基板上与所述芯片平行且与所述金属凸台距离最近的表面；
    在所述基板上所述金属凸台的另一端与所述导体层之间开设钻孔，并在所述钻孔内填充导体材料，以将所述芯片上存在连接需求的引脚通过所述金属凸台及所述导体 材料，和所述导体层实现连接，其中，所述钻孔横截面超出所述金属凸台所述另一端的横截面的范围。
  8. 根据权利要求7所述的方法，其特征在于，在相对位置确定的各个电子元件之间填充基板材料，形成基板，包括：
    在相对位置确定的各个电子元件之间填充基板材料，形成中间基板层，使所述芯片及金属凸台埋嵌于所述中间基板层内；
    在所述中间基板层的所述一个表面上压合基板材料，形成第一表层基板层；
    根据所述各个电子元件的连接需求在所述基板的第一表面设置导体层，包括：
    根据所述各个电子元件的连接需求在所述第一表层基板层的外表面设置导体层。
  9. 根据权利要求8所述的方法，其特征在于，在所述基板上所述金属凸台的另一端与所述导体层之间开设钻孔，包括：
    根据所述芯片在所述基板内的实际嵌入深度及每个金属凸台的高度值确定每个金属凸台对应的钻孔深度；
    根据所述钻孔深度在所述第一表层基板层上对应于每个金属凸台的区域分别开设钻孔。
  10. 根据权利要求9所述的方法，其特征在于，在相对位置确定的各个电子元件之间填充基板材料，形成基板，还包括：
    在所述中间基板层的另一表面压合基板材料，形成第二表层基板层。
  11. 根据权利要求8至10任一项所述的方法，其特征在于，所述电子元件还包括容阻元件；
    所述方法还包括：
    根据所述容阻元件在所述基板内的实际嵌入深度，在所述基板上对应于所述容阻元件的接线端的区域开设钻孔，并在所述钻孔内填充有导体材料，以使所述容阻元件的接线端通过相应钻孔内的导体材料与所述导体层连接。
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