WO2018196317A1 - 移位寄存单元、移位寄存电路、驱动方法及显示装置 - Google Patents

移位寄存单元、移位寄存电路、驱动方法及显示装置 Download PDF

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Publication number
WO2018196317A1
WO2018196317A1 PCT/CN2017/109260 CN2017109260W WO2018196317A1 WO 2018196317 A1 WO2018196317 A1 WO 2018196317A1 CN 2017109260 W CN2017109260 W CN 2017109260W WO 2018196317 A1 WO2018196317 A1 WO 2018196317A1
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WIPO (PCT)
Prior art keywords
node
transistor
shift register
level
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/109260
Other languages
English (en)
French (fr)
Inventor
王珍
孙建
黄飞
詹小舟
乔赟
张寒
秦文文
丛乐乐
王争奎
刘蕊
陈鹏骏
王立冬
赵爽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/071,964 priority Critical patent/US11011132B2/en
Publication of WO2018196317A1 publication Critical patent/WO2018196317A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register circuit, a driving method, and a display device.
  • the gate drive circuit is integrated on the array substrate of the display panel by using an integrated gate drive circuit (Gate Driver on Array, GOA) technology.
  • GOA Gate Driver on Array
  • Such a gate switching circuit integrated on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register unit circuit, and each shift register unit in the gate switch circuit is referred to as a GOA circuit or a shift register unit.
  • Embodiments of the present disclosure provide a shift register unit, a shift register circuit, a driving method, and a display device.
  • a shift register unit comprising: an input circuit connecting a first level terminal, an input signal terminal, and a first node; a reset circuit, the reset circuit connecting the second a level end, a reset signal end, and the first node; a control circuit, the control circuit is connected to the first clock signal end, the output signal end, the third level end, the first node and the second node; and an output circuit The output circuit is connected to the second clock signal terminal, the first node, the second node, the third level terminal, and the output signal terminal; a node reset circuit, and the node resets the power Connecting a scan signal end, the output signal end, the second node, and the third level end;
  • the node reset circuit in the pre-reset phase, is configured to transmit the voltage of the third level terminal to the second node and the scan signal at the output signal under the control of the scan signal of the scan signal end a reset circuit configured to transmit a voltage of the second level terminal to the first node under control of a reset signal of a reset signal terminal;
  • the input circuit is configured to be under the control of an input signal of the input signal terminal Transmitting the voltage of the first level terminal to the first node;
  • the control circuit is configured to set the first of the first clock signal ends under the control of the voltage of the first node, the voltage of the output signal terminal, and the first clock signal of the first clock signal end. Transmitting a clock signal to the second node and transmitting the voltage of the third level terminal to the first node under control of a voltage of the second node; the output circuit configured to control voltage at the second node The voltage of the third level terminal is transmitted to the signal output terminal.
  • the input circuit includes: a first transistor, a first electrode of the first transistor is connected to the first level terminal, and a second electrode of the first transistor is connected to the first node, the first transistor The gate is connected to the signal input.
  • the reset circuit includes: a second transistor, a first electrode of the second transistor is connected to the second level terminal, and a second electrode of the second transistor is connected to the first node, the second transistor The gate is connected to the reset signal terminal.
  • the control circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; a first pole of the third transistor is connected to the first clock signal end, and the third a second pole of the transistor is connected to the second node, a gate of the third transistor is connected to the first clock signal end; a first pole of the fourth transistor is connected to the first node, the fourth transistor a second pole connected to the third level terminal, a gate of the fourth transistor is connected to the second node; a first pole of the fifth transistor is connected to the first node, and a fifth transistor is a diode is connected to the third level terminal, a gate of the fifth transistor is connected to the first node; a first pole of the sixth transistor is connected to the second node, and a second pole of the sixth transistor Connecting the third level end, the gate of the sixth transistor is connected to the output signal end; the first pole of the first capacitor is connected to the second node, and the second pole of the first capacitor is connected The third level terminal
  • the output circuit includes: a seventh transistor, an eighth transistor, and a second capacitor; a first pole of the seventh transistor is connected to the output signal end, and a second pole of the seventh transistor is connected to the third a level terminal, a gate of the seventh transistor is connected to the second node; a first of the eighth transistor a pole connected to the second clock signal end, a second pole of the eighth transistor is connected to the signal output end, a gate of the eighth transistor is connected to the first node; and a first pole of the second capacitor The first node is connected, and the second pole of the second capacitor is connected to the signal output end.
  • the node reset circuit includes: a tenth transistor of the ninth transistor; a first pole of the ninth transistor is connected to the signal output end, and a second pole of the ninth transistor is connected to the scan signal end; a gate of the ninth transistor is connected to the scan signal end; a first pole of the tenth transistor is connected to the second node, and a second pole of the tenth transistor is connected to the third level end, A gate of the ten transistor is connected to the scan signal terminal.
  • each of the transistors of the shift register unit is an N-type transistor, the first level is a high level, and the second level is a low level.
  • each of the transistors of the shift register unit is a P-type transistor, the first level is a low level, and the second level is a high level.
  • a driving method of a shift register unit comprising: an input circuit, a reset circuit, a control circuit, an output circuit, and the input circuit, the reset circuit, a first node to which the control circuit and the output circuit are connected, a second node connected to the control circuit and the output circuit, and an output signal terminal connected to the control circuit and the output circuit; a node configured to cause the output circuit to output a pull-up signal at the output signal end by controlling the control circuit under control of an input circuit; the second node is configured to cause the output circuit to be under control of the control circuit The output signal terminal outputs a pull-down signal, and the reset circuit is configured to reset the first node and the output signal end; the driving method includes:
  • the second node is at a first level
  • the control circuit transmits a second level signal to the first node and the output signal end under the control of the voltage of the second node
  • the shift register unit operates normally.
  • the shift register unit further includes: a node reset circuit that connects the second node and the output signal end;
  • the method further includes
  • the first node and the second node are both at a second level under the control of the node reset circuit.
  • the second node is at a first level
  • the control circuit transmits the second level signal to the first node and the output signal end under the control of the voltage of the second node, including:
  • the control circuit transmits a first level to the second node under the control of the voltage of the first node and the voltage of the output signal terminal, and transmits the second level to the first node and under the control of the voltage of the second node The signal output.
  • the first node and the second node are both at a second level under the control of the node reset circuit: the node reset circuit transmits the first level to The output signal terminal transmits a second level to the second node; the reset circuit and the input circuit transmit a second level to the first node.
  • the normal working phase includes:
  • the input circuit transmits the first level to the first node;
  • the control circuit transmits the second level to the second node under control of the voltage of the first node;
  • the second level of the reset circuit is transmitted to the first node; the control circuit transmits the first level to the second node under control of the voltage of the first node and the voltage of the output signal terminal and The second level is transmitted to the first node under control of the voltage of the second node; the output circuit transmits the second level to the signal output under control of the voltage of the second node.
  • a shift register circuit comprising m cascaded shift register units according to claim 1 or 2;
  • the input signal end of the first stage shift register unit is connected to the start signal end, and the output signal end of the first stage shift register unit is connected to the signal input end of the second stage shift register unit, the first stage The reset signal end of the shift register unit is connected to the signal output end of the second stage shift register unit;
  • the input signal end of the m-th stage shift register unit is connected to the output signal end of the m-1th stage shift register unit, and the output signal end of the m-th stage shift register unit is connected to the reset signal of the m-1th stage shift register unit. end;
  • the input signal end of the nth stage shift register unit is connected to the signal output end of the n-1th stage shift register unit, and the signal output end of the nth stage shift register unit is connected to the signal input of the n+1th stage shift register unit.
  • the reset signal end of the nth stage shift register unit is connected to the signal output end of the n+1th shift register unit;
  • n are integers greater than 1 and m is greater than n.
  • a driving method of a shift register circuit configured to be driven
  • the shift register circuit of the fourth aspect comprising:
  • the first clock signal terminal inputs the first clock signal
  • the second clock signal terminal inputs the second clock signal
  • the shift register unit operates normally.
  • a display device comprising: a shift register circuit according to the present disclosure.
  • the functions corresponding to the pre-reset phase and the reset phase can be implemented by the node reset circuit, the reset circuit, and the input circuit when the display is powered on, and then the voltages of the first node, the second node, and the signal output end are further The reset is performed, so that the operation signal outputted by the shift register unit before normal operation can be avoided, thereby improving the display panel display abnormality caused by unstable register output at the time of power-on.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 4 is a flow chart showing the steps of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 6 is a flow chart showing the steps of a driving method of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of signal timing states of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a shift register circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a flow chart showing the steps of a driving method of a shift register circuit according to an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors (English name: Thin Film Transistor, TFT for short) or field effect transistors or metal-oxide-semiconductor transistors (English name: Metal-Oxide-semiconductor, referred to as: MOS tube) Other devices with the same characteristics.
  • the transistors employed in the embodiments of the present disclosure are primarily switching transistors in accordance with their role in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain can be interchanged. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, the source is referred to as a first pole, and the drain is referred to as a second pole.
  • the middle end of the transistor is the gate
  • the signal input end is the source
  • the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure includes a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is on a gate. Turns on when it is very high, and turns off when the gate is low.
  • Embodiments of the present disclosure provide a shift register unit.
  • the shift register unit includes an input circuit 11, a reset circuit 12, a control circuit 13, an output circuit 14, and a node reset circuit 15.
  • the input circuit 11 is connected to the first level terminal V1, the input signal terminal Input, and the first node a.
  • the reset circuit 12 is connected to the second level terminal V2, the reset signal terminal Reset, and the first node a.
  • the control circuit 13 is connected to the first clock signal terminal CLK1, the output signal terminal Output, the third level terminal V3, the first node a, and the second node b.
  • the output circuit 14 is connected to the second clock signal terminal CLK2, the first node a, and the output signal terminal Output, the third level terminal V3, and the second node b.
  • the node reset circuit 15 is connected to the scan signal terminal EN, the output signal terminal Output, the second node b, and the third level terminal V3.
  • the node reset circuit 15 is configured to transmit the voltage of the third level terminal V3 to the second node b under the control of the scan signal of the scan signal terminal EN and output the scan signal at the output signal terminal Output .
  • the reset circuit 12 is configured to transmit the voltage of the second level terminal V2 to the first node a under the control of the reset signal of the reset signal terminal Re set.
  • the input circuit 11 is configured to transmit the voltage of the first level terminal V1 to the first node a under the control of the input signal of the input signal terminal Input.
  • the control circuit 13 is configured to set the first clock signal of the first clock signal terminal CLK1 under the control of the voltage of the first node a, the voltage of the output signal terminal Output, and the first clock signal of the first clock signal terminal CLK1.
  • the voltage of the third level terminal V3 is transmitted to the first node a under transmission to the second node b and under the control of the voltage of the second node b.
  • the output circuit 14 is configured to transmit the voltage of the third level terminal V3 to the signal output terminal Output under the control of the voltage of the second node b.
  • the embodiment of the present disclosure further details the function of each function circuit of the shift register unit in the output gate drive signal stage.
  • the shift register unit outputting the gate drive signal phase may include: a first time period, a second time period, and a third time period.
  • the input unit 11 is configured to transmit the voltage of the first level terminal V1 to the first node a under the control of the input signal of the input signal terminal Input.
  • the control unit 13 is configured to transmit the voltage of the third level terminal V3 to the second node b under the control of the voltage of the first node a.
  • the output unit 14 is configured to output the voltage of the second clock signal terminal CLK2 at the signal output terminal Output as a gate drive signal under the control of the voltage of the first node a.
  • the reset unit 13 is configured to transmit the voltage of the second level terminal V2 to the first node a under the control of the reset signal of the reset signal terminal Reset.
  • the control unit 13 is configured to transmit the first clock signal of the first clock signal terminal CLK1 to the first control signal under the control of the voltage of the first node a, the voltage of the output signal terminal Output, and the first clock signal output by the first clock signal terminal CLK1.
  • the voltage of the third level terminal V3 is transmitted to the first node a under the control of the voltage of the second node b and the voltage of the second node b.
  • the output unit 14 is configured to transmit the voltage of the third level terminal V3 to the signal output terminal Output under the control of the voltage of the second node b.
  • the functions of the pre-reset phase and the reset phase can be realized by the node reset circuit, the reset circuit, and the input circuit when the display is turned on, and thus the first node, the second node, and the signal output end.
  • the voltage is reset. Therefore, the technical solution according to the embodiment of the present disclosure can avoid the work signal output by the shift register unit before the normal operation, thereby improving the display panel display abnormality caused by the instability of the register output at the time of booting.
  • the input circuit 11 includes a first transistor T1.
  • the first electrode of the first transistor T1 is connected to the first level terminal V1, the second electrode of the first transistor T1 is connected to the first node a; the gate of the first transistor T1 is connected to the signal input terminal Input.
  • the reset circuit 12 includes a second transistor T2.
  • the first transistor of the second transistor T2 is connected to the second level terminal V2
  • the second electrode of the second transistor T2 is connected to the first node a
  • the gate of the second transistor T2 is connected to the reset signal terminal Reset.
  • the control circuit 13 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1.
  • the first transistor of the third transistor T3 is connected to the first clock signal terminal CLK1
  • the second electrode of the third transistor T3 is connected to the second node b
  • the gate of the third transistor T3 is connected to the first clock signal terminal CLK1.
  • the first pole of the fourth transistor T4 is connected to the first node a
  • the second pole of the fourth transistor T4 is connected to the third level terminal V3, and the gate of the fourth transistor T4 is connected to the second node b.
  • the first electrode of the fifth transistor T5 is connected to the first node a, the second electrode of the fifth transistor T5 is connected to the third level terminal V3, and the gate of the fifth transistor T5 is connected to the first node a.
  • the first pole of the sixth transistor T6 is connected to the second node b, the second pole of the sixth transistor T6 is connected to the third level terminal V3, and the gate of the sixth transistor T6 is connected to the output signal terminal Output.
  • the first pole of the first capacitor C1 is connected to the second node b, and the second pole of the first capacitor C1 is connected to the third level terminal V3.
  • the output circuit 14 includes a seventh transistor T7, an eighth transistor T8, and a second capacitor C2.
  • the first pole of the seventh transistor T7 is connected to the output signal terminal Output
  • the second pole of the seventh transistor T7 is connected to the third level terminal V3, and the gate of the seventh transistor T7 is connected to the second node b.
  • the first electrode of the eighth transistor T8 is connected to the second clock signal terminal CLK2, the second electrode of the eighth transistor T8 is connected to the signal output terminal Output, and the gate of the eighth transistor T8 is connected to the first node a.
  • the first pole of the second capacitor C2 is connected to the first node a, and the second pole of the second capacitor C2 is connected to the signal output terminal Output.
  • the node reset circuit 15 includes a tenth transistor T10 of the ninth transistor T9.
  • the first pole of the ninth transistor T9 is connected to the signal output terminal Output, and the second pole of the ninth transistor T9 is connected to the scan signal terminal EN, The gate of the ninth transistor T9 is connected to the scanning signal terminal EN.
  • the first pole of the tenth transistor T10 is connected to the second node b, the second pole of the tenth transistor T10 is connected to the third level terminal V3, and the gate of the tenth transistor T10 is connected to the scan signal terminal EN.
  • Embodiments of the present disclosure provide a driving method of a shift register unit.
  • the shift register unit includes an input circuit 31, a reset circuit 32, a control circuit 33, and an output circuit 34, wherein the input circuit 31, the reset circuit 32, the control circuit 33, and the output circuit 34 are connected to the first node PU, The control circuit 33 and the output circuit 34 are connected to the second node PD, and the control circuit 33 and the output circuit 34 are connected to the output signal terminal Output.
  • the control circuit 33 is controlled by the first node PU to cause the output circuit 34 to output a pull-up signal at the output signal terminal Output.
  • the second node PD causes the output circuit 34 to output a pull-down signal at the output signal terminal Output, and the reset circuit 32 is configured to reset the first node PU and the output signal terminal Output.
  • the pull-up signal and the pull-down signal are used to control an on/off state of a transistor connected through an output signal terminal of the shift register unit. For example, when the output signal terminal of the shift register unit outputs a pull-up signal, the transistor connected to the output signal terminal of the shift register unit through the gate line is in an on state, and the output signal terminal of the shift register unit outputs a pull-down signal. At the time, the transistor connected to the output signal terminal of the shift register unit through the gate line is in an off state.
  • the pull-up signal is at a high level, and the pull-down signal is at a low level; when passing through the gate line and the shift register unit
  • the pull-up signal is low level and the pull-down signal is high level.
  • the driving method of the above shift register unit may include the following steps.
  • the second node is at the first level, and the control circuit transmits the second level to the first node and the output signal terminal under the control of the voltage of the second node.
  • the above step S41 may include: the control circuit 43 transmits the first level to the second node PD under the control of the voltage of the first node PU and the voltage of the output signal terminal Output, and under the control of the voltage of the second node PD The second level is transmitted to the first node PU and the signal output Output.
  • step S42 may include the following stages.
  • the input circuit 31 transmits the first level to the first node PU; the control circuit 33 transmits the second level to the second node PD under the control of the voltage of the first node PU.
  • the output circuit 34 transmits the first level to the output signal terminal Output under the control of the voltage of the first node PU.
  • reset circuit 32 transmits the second level to the first node PU.
  • the control circuit 33 transmits the first level to the second node PD under the control of the voltage of the first node PU and the voltage of the output signal terminal Output, and transmits the second level to the second level under the control of the voltage of the second node PD.
  • the output circuit 34 transmits the second level to the signal output terminal Output under the control of the voltage of the second node PD.
  • each transistor in the shift register unit is an N-type transistor
  • the first level in the above embodiment is a high level
  • the second level is a low level.
  • the signal of the shift register unit needs to be adjusted to a phase opposite signal during the driving process of the shift register unit, that is, when each transistor in the shift register unit is a P-type transistor,
  • the first level in the above embodiment is a low level
  • the second level is a high level.
  • the first node and the second node may be first reset at the time of power-on, and the shift register unit outputs a non-operation signal. Therefore, the driving method of the shift register unit according to the embodiment of the present disclosure can avoid the operation signal outputted by the shift register unit before the normal operation, thereby improving the display panel display abnormality caused by the instability of the register output at the time of booting.
  • the shift register unit shown in FIG. 4 further includes a node reset circuit 35 that connects the second node PD and the output signal terminal Output.
  • the driving method may further include the following steps before the reset phase.
  • the first node PU and the second node PD are both at the second level under the control of the node reset circuit 35.
  • the first node and the second node are both at the second level under the control of the node reset circuit.
  • the step may include the node reset circuit 35 transmitting the first level to the output signal terminal Output and transmitting the second level to the second node PD; the reset circuit 12 and the input circuit 11 transmitting the second level to the first node PU .
  • Figure 7 shows the voltage signal of the first level terminal V1, the voltage signal V2 of the second level terminal, the scanning signal of the scanning signal terminal EN, and the input signal terminal.
  • Input signal of Input first clock signal of first clock signal terminal CLK1, second clock signal of second clock signal terminal CLK2, output signal of output signal terminal Output, voltage of first node a, and voltage of second node b Timing status.
  • the second level terminal V2 and the third level terminal V3 provide a stable low level.
  • the second level terminal V2 and the third level terminal V3 may be grounded. As shown in FIG. 7, it may include: phase 1 (pre-reset phase); phase 2 (reset phase); phase 3 (normal working phase), wherein the third phase 3 further includes: a first normal working sub-time period t31, The normal working sub-period t32 and the third normal working sub-period t33.
  • the scanning signal terminal EN is input to the high level, and thus the ninth transistor T9 and the tenth transistor T10 are turned on. Since the signal output terminal Output is connected to the scan signal terminal EN through the ninth transistor T9, the signal output terminal Output outputs a high level of the scan signal terminal EN.
  • the second node b is connected to the third level terminal V3 through the tenth transistor T10, so the third level terminal V3 resets the voltage of the second node b to a low level.
  • the reset signal terminal Reset inputs a high level
  • the input signal terminal Input inputs a high level
  • the first transistor T1 and the second transistor T2 are turned on, and the first node a is connected to the first level terminal through the first transistor T1, and passes through the first
  • the second transistor T2 is connected to the second level terminal V2, and the first level terminal V1 and the second level terminal V2 are both at a low level in this stage, thereby resetting the voltage of the first node a to a low level.
  • the operation principle of the first-stage shift register unit and the m-th stage shift register unit is slightly different, and the difference is that, in the phase 1, the input signal terminal Input of the first-stage shift register unit is input to a low level.
  • the reset signal terminal Reset of the m-th stage shift register unit inputs a low level.
  • the voltage of the first node a can be reset to even if the reset signal terminal Reset or the input signal terminal Input is input low level. Low level, so the voltage of the first stage shift register unit and the first node a of the mth stage shift register unit can also be reset to a low level in this stage.
  • phase 2 the first clock signal terminal CLK1 starts to output the first clock signal
  • the second clock signal terminal CLK2 starts to output the second clock signal.
  • the duty ratios of the first clock signal and the second clock signal are both 50%, and the first clock signal and the second clock signal are opposite in phase.
  • the third transistor T3 When the first clock signal of the first clock signal terminal CLK1 is at a high level, and the second clock signal of the second clock signal terminal CLK2 is at a low level, the third transistor T3 is turned on, and the second node b is connected through the third transistor T3.
  • the first clock signal terminal CLK1, the first clock signal terminal CLK1 pulls the voltage of the second node b Is high.
  • the second node b is at a high level, so the fourth transistor T4 is turned on, the first node a is connected to the third level terminal V3 through the fourth transistor T4, and the third level terminal V3 pulls the voltage of the first node a to a low level. .
  • the seventh transistor T7 is turned on, the signal output terminal Output is connected to the third level terminal V3 through the seventh transistor T7, and the third level terminal V3 pulls the voltage of the signal output terminal Output to a low level. Further, when the control circuit includes the first capacitor C1, the first capacitor C1 is charged.
  • the eighth transistor T8 is turned off, and the second clock signal outputted by the second clock signal terminal CLK2 cannot enter the GOA circuit through the eighth transistor T8. Therefore, when the second clock signal of the second clock signal terminal CLK2 is at a high level, the output signal is output. The terminal output remains low.
  • control circuit includes the first capacitor C1
  • the phase 2 can pull the voltage of the first node to a low level and the voltage of the second node to a high level, the output of the signal output terminal can be ensured to be a stable low level. Therefore, the GOA provided by the embodiment of the present disclosure is provided.
  • the driving method of the circuit and the GOA circuit can improve the display panel display abnormality caused by the unstable output of the GOA circuit at the time of power-on.
  • the number of periods in which the clock signal is included in the phase 2 can be set to any number according to actual requirements. In the embodiment of the present disclosure, the number of periods including the clock signal in the phase 2 is not limited.
  • the signal input terminal Input outputs a high level
  • the first level terminal V1 outputs a high level
  • the first transistor T1 is turned on
  • the first node a passes the first
  • the transistor T1 is connected to the first level terminal
  • the first level terminal V1 pulls the first node a to a high level.
  • the second capacitor C2 is charged. Because the first node a is at a high level, the fifth transistor T5 and the eighth transistor T8 are turned on, the second node b is connected to the third level terminal V3 through the fifth transistor T5, and the third level terminal V3 pulls the second node to Low level.
  • the first clock signal of the first clock signal terminal CLK1 is at a high level
  • the second clock signal of the second clock signal terminal CLK2 is at a low level, so that the output signal terminal outputs a low level.
  • the signal input terminal Input outputs a low level
  • the first transistor T1 is turned off
  • the first clock signal of the first clock signal terminal CLK1 is a low level
  • the fourth The transistor T4 is turned off, and the second capacitor C2 has no discharge path, so the second capacitor C2 is protected.
  • Holding the first node a is high.
  • the second clock signal of the second clock signal terminal CLK2 is at a high level. Therefore, the voltage of the second pole of the second capacitor C2 rises. Due to the bootstrap effect of the capacitor, the first pole of the second capacitor C2 (ie, the first node) The voltage is further increased, and the eighth transistor T8 is turned on more fully.
  • the signal output terminal Output is connected to the second clock signal terminal through the eighth transistor T8, and outputs a high level of the second clock signal terminal CLK2.
  • the reset signal terminal Re set inputs a high level, so that the second transistor T2 is turned on, and the first node a is connected to the second level terminal V2 through the second transistor T2.
  • the first node a is pulled low.
  • the third transistor T3 is turned on, the second node b is connected to the first clock signal terminal CLK1 through the third transistor T3, and the first clock signal terminal CLK1 is connected to the second node.
  • the voltage of b is pulled high.
  • the fourth transistor T4 and the seventh transistor T7 are turned on, and the first node a is connected to the third level terminal V3 through the fourth transistor T4, and the voltage of the first node a is further pulled down, and the output is The signal terminal Output is connected to the third level terminal V3 through the seventh transistor T7, and the output signal terminal outputs a low level.
  • the high level can be input from the first normal working sub-period t31 to the input signal terminal Input of the shift register unit of the present stage as a complete duty cycle of the shift register unit of the present stage. Therefore, in one duty cycle of the shift register unit of the present stage after the third normal operation sub-time period t33, a plurality of stages may be included, which is determined by the number of rows scanned by the shift register circuit. However, before the input signal terminal Input of the GOA circuit of the present stage is input to the high level again after the third normal working sub-time period t33, the output signal terminal Output of the shift register unit of the present stage is kept at a low level (output non-operation signal).
  • all the transistors in the shift register unit in the above embodiment may also be P-type transistors that are turned on at a low level. If all the transistors are P-type transistors, it is only necessary to readjust the timing state of each input signal of the shift register unit.
  • an N-type transistor and a P-type transistor can also be used at the same time.
  • the driving principle of the shift register unit shown in FIG. 6 should be configured as the shift register unit shown in FIG. 2 as an example to explain the working principle thereof, but the present disclosure It is not limited to this.
  • a further embodiment of the present disclosure provides a shift register circuit, which is shown in FIG.
  • the path includes m cascaded shift register units provided by the above embodiments.
  • the input signal end of the first stage shift register unit is connected to the start signal end, and the output signal end of the first stage shift register unit is connected to the signal input end of the second stage shift register unit, and the first stage shift register unit
  • the reset signal end is connected to the signal output end of the second stage shift register unit;
  • the input signal end of the mth stage shift register unit is connected to the output signal end of the m-1th stage shift register unit, and the mth stage shift register unit
  • the output signal end is connected to the reset signal end of the m-1th stage shift register unit;
  • the input signal end of the nth stage shift register unit is connected to the signal output end of the n-1th stage shift register unit, the nth stage shift
  • the signal output end of the register unit is connected to the signal input end of the n+1th shift register unit, and the reset signal end of
  • the input signal terminal of the first-stage shift register unit is connected to the start signal terminal STV, and the output signal terminal of the first-stage shift register unit is connected to the input signal terminal of the second-stage shift register unit and The gate line G1, the reset signal end of the first stage shift register unit is connected to the output signal end of the second stage shift register unit; the input signal end of the nth stage shift register unit is connected to the signal of the n-1 stage shift register unit The output end of the nth stage shift register unit is connected to the signal input end of the n+1th shift register unit, and the reset signal end of the nth stage shift register unit is connected to the n+1th stage shift register unit.
  • the output signal end of the m-th stage shift register unit (the last stage shift register unit) is connected to the output signal end of the m-1th stage shift register unit, and the output signal of the m-th stage shift register unit The terminal is connected to the input signal terminal of the m-1th stage shift register unit and the gate line Gm.
  • each of the shift register units includes a first clock signal terminal CLK1 and a second clock signal terminal CLK2.
  • a clock signal is provided to two clock signal terminals connected to each shift register unit by clock signals clock1 and clock2 of two systems, wherein CLK1 of the 2n-1th shift register unit is input to clock1, The CLK2 of the 2n-1 shift register unit is input to clock2, the CLK1 of the 2nth shift register unit is input to clock2, and the CLK2 of the 2nth shift register unit is input to clock1.
  • the timing state of the system clock refers to the first clock signal of the first clock signal terminal CLK1 and the second clock signal of the second clock signal terminal CLK2 in FIG. Among them, clock1 and clock2 have opposite phases, and clock1 and clock2 are clock signals with a duty ratio of 50%.
  • One embodiment of the present disclosure provides a driving method of a shift register circuit configured to drive the shift register circuit shown in FIG. 8.
  • the method may Includes the following steps.
  • the scan signal of the first-stage shift register unit of the shift register circuit is input. Enter the first level at the input.
  • the node reset unit of the shift register unit of the first stage transfers the first level to the shift register of the first stage.
  • the output signal end of the unit, the output signal end of the first stage shift register unit transmits the first level to the signal input end of the second stage shift register unit, and continues to transfer the low level, thereby shifting
  • the output signal terminals of all the shift register units in the register circuit output the first level.
  • the first clock signal terminal inputs the first clock signal
  • the second clock signal terminal inputs the second clock signal
  • An embodiment of the present disclosure provides a display device including the shift register circuit provided in the above embodiment.
  • the display device may be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., any product or component having a display function.

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Abstract

一种移位寄存单元、移位寄存电路、驱动方法及显示装置，涉及显示技术领域，配置为改善开机时移位寄存单元输出不稳定导致的显示面板显示异常的问题；该方法包括：在显示阶段，第二节点（b）为第一电平，控制电路（13）在第二节点（b）的电压的控制下，将第二电平信号传输至第一节点（a）和输出信号端；在正常工作阶段，移位寄存单元正常工作。

Description

移位寄存单元、移位寄存电路、驱动方法及显示装置
本申请要求于2017年4月27日提交的、申请号为201710289777.8的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存单元、移位寄存电路、驱动方法及显示装置。
背景技术
近些年来在显示领域，利用集成栅极驱动电路(英文全称：Gate Driver on Array，简称：GOA)技术将栅极驱动电路集成在显示面板的阵列基板上。这种利用GOA技术集成在阵列基板上的栅极开关电路也称为GOA电路或移位寄存单元电路，该栅极开关电路中的每个移位寄存单元称为GOA电路或移位寄存单元。
传统移位寄存单元电路在开机时所有输出信号均为低电平，因此移位寄存单元内的薄膜晶体管(英文全称：Thin Film Transistor，简称：TFT)的均处于不工作状态，导致无法确定移位寄存单元中的上拉节点和下拉节点的状态，若此时直接使移位寄存单元的各个输出信号端按照驱动时序输入驱动信号，则会导致移位寄存单元输出不稳定，进而导致显示面板显示异常。
发明内容
本公开实施例提供了一种移位寄存单元、移位寄存电路、驱动方法及显示装置。
根据本公开的第一方面，提供了一种移位寄存单元，包括：输入电路，所述输入电路连接第一电平端、输入信号端以及第一节点；复位电路，所述复位电路连接第二电平端、复位信号端以及所述第一节点；控制电路，所述控制电路连接第一时钟信号端、输出信号端、第三电平端、所述第一节点以及第二节点；输出电路，所述输出电路连接第二时钟信号端、所述第一节点、所述第二节点、所述第三电平端以及所述输出信号端；节点复位电路，所述节点复位电 路连接扫描信号端、所述输出信号端、所述第二节点以及所述第三电平端；
其中，在预复位阶段，所述节点复位电路配置为在所述扫描信号端的扫描信号的控制下将所述第三电平端的电压传输至第二节点以及将所述扫描信号在所述输出信号端输出；所述复位电路配置为在复位信号端的复位信号的控制下将所述第二电平端的电压传输至所述第一节点；输入电路配置为在所述输入信号端的输入信号的控制下将所述第一电平端的电压传输至所述第一节点；
在复位阶段，所述控制电路配置为在所述第一节点的电压、所述输出信号端的电压以及所述第一时钟信号端的第一时钟信号的控制下将所述第一时钟信号端的第一时钟信号传输至第二节点以及在所述第二节点的电压的控制下将所述第三电平端的电压传输至第一节点；所述输出电路配置为在所述第二节点的电压的控制下将所述第三电平端的电压传输至所述信号输出端。
例如，所述输入电路包括：第一晶体管，所述第一晶体管的第一极连接所述第一电平端，所述第一晶体管的第二极连接所述第一节点，所述第一晶体管的栅极连接所述信号输入端。
例如，所述复位电路包括：第二晶体管，所述第二晶体管的第一极连接所述第二电平端，所述第二晶体管的第二极连接所述第一节点，所述第二晶体管的栅极连接所述复位信号端。
例如，所述控制电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第一电容；所述第三晶体管的第一极连接所述第一时钟信号端，所述第三晶体管的第二极连接所述第二节点，所述第三晶体管的栅极连接所述第一时钟信号端；所述第四晶体管的第一极连接所述第一节点，所述第四晶体管的第二极连接所述第三电平端，所述第四晶体管的栅极连接所述第二节点；所述第五晶体管的第一极连接所述第一节点，所述第五晶体管的第二极连接所述第三电平端，所述第五晶体管的栅极连接所述第一节点；所述第六晶体管的第一极连接所述第二节点，所述第六晶体管的第二极连接所述第三电平端，所述第六晶体管的栅极连接所述输出信号端；所述第一电容的第一极连接所述第二节点，所述第一电容的第二极连接所述第三电平端。
例如，所述输出电路包括：第七晶体管、第八晶体管和第二电容；所述第七晶体管的第一极连接所述输出信号端，所述第七晶体管的第二极连接所述第三电平端，所述第七晶体管的栅极连接所述第二节点；所述第八晶体管的第一 极连接所述第二时钟信号端，所述第八晶体管的第二极连接所述信号输出端，所述第八晶体管的栅极连接所述第一节点；所述第二电容的第一极连接所述第一节点，所述第二电容的第二极连接所述信号输出端。
例如，所述节点复位电路包括：第九晶体管的第十晶体管；所述第九晶体管的第一极连接所述信号输出端，所述第九晶体管的第二极连接所述扫描信号端，所述第九晶体管的栅极连接所述扫描信号端；所述第十晶体管的第一极连接所述第二节点，所述第十晶体管的第二极连接所述第三电平端，所述第十晶体管的栅极连接所述扫描信号端。
例如，所述移位寄存单元的各个晶体管均为N型晶体管，所述第一电平为高电平，所述第二电平为低电平。
例如，所述移位寄存单元的各个晶体管均为P型晶体管，所述第一电平为低电平，所述第二电平为高电平。
根据本公开的第二方面，提供一种移位寄存单元的驱动方法，所述移位寄存单元包括：输入电路、复位电路、控制电路、输出电路、与所述输入电路、所述复位电路、所述控制电路以及所述输出电路均连接的第一节点、与所述控制电路和所述输出电路连接的第二节点、以及与所述控制电路和所述输出电路连接的输出信号端；第一节点配置为在输入电路的控制下通过控制所述控制电路使所述输出电路在所述输出信号端输出上拉信号；第二节点配置为在控制电路的控制下使所述输出电路在所述输出信号端输出下拉信号，所述复位电路配置为对第一节点和输出信号端进行复位；所述驱动方法包括：
在复位阶段，所述第二节点为第一电平，所述控制电路在所述第二节点的电压的控制下，将第二电平信号传输至第一节点和所述输出信号端；
在正常工作阶段，所述移位寄存单元正常工作。
例如，所述移位寄存单元还包括：连接所述第二节点和所述输出信号端的节点复位电路；
在所述复位阶段之前，所述方法还包括，
在预复位阶段，在所述节点复位电路的控制下使所述第一节点和所述第二节点均为第二电平。
例如，所述第二节点为第一电平，所述控制电路在所述第二节点的电压的控制下，将第二电平信号传输至第一节点和所述输出信号端，包括：
所述控制电路在第一节点的电压和输出信号端的电压控制下将第一电平传输至第二节点以及在所述第二节点的电压的控制下将第二电平传输至第一节点和所述信号输出端。
例如，所述在预复位阶段，在所述节点复位电路的控制下使所述第一节点和所述第二节点均为第二电平包括：所述节点复位电路将第一电平传输至所述输出信号端以及将第二电平传输至所述第二节点；所述复位电路和所述输入电路将第二电平传输至所述第一节点。
例如，所述正常工作阶段包括：
第一正常工作子时段，其中输入电路将第一电平传输至所述第一节点；控制电路在第一节点的电压的控制下将第二电平传输至第二节点；
第二正常工作子时段，其中输出电路在第一节点的电压的控制下将第一电平传输至输出信号端；
第三正常工作子时段，其中复位电路第二电平传输至第一节点；控制电路在第一节点的电压以及输出信号端的电压的控制下将第一电平传输至第二节点以及在所述第二节点的电压的控制下将第二电平传输至第一节点；输出电路在所述第二节点的电压的控制下将第二电平传输至所述信号输出端。
根据本公开的第三方面，提供一种移位寄存电路，包括m个级联的权利要求1或2所述的移位寄存单元；
其中，第1级移位寄存单元的输入信号端连接起始信号端，所述第1级移位寄存单元的输出信号端连接第2级移位寄存单元的信号输入端，所述第1级移位寄存单元的复位信号端连接第2级移位寄存单元的信号输出端；
第m级移位寄存单元的输入信号端连接第m-1级移位寄存单元的输出信号端，第m级移位寄存单元的输出信号端连接第m-1级移位寄存单元的复位信号端；
第n级移位寄存单元的输入信号端连接第n-1级移位寄存单元的信号输出端，第n级移位寄存单元的信号输出端连接第n+1级移位寄存单元的信号输入端，第n级移位寄存单元的复位信号端连接第n+1级移位寄存单元的信号输出端；
m、n为大于1的整数且m大于n。
根据本公开的第四方面，提供一种移位寄存电路的驱动方法，配置为驱动 第四方面所述的移位寄存电路，所述方法包括：
在预复位阶段，向所述移位寄存电路的第1级移位寄存单元的扫描信号输入端输入第一电平；
在复位阶段，第一时钟信号端输入第一时钟信号、第二时钟信号端输入第二时钟信号；
在正常工作阶段，所述移位寄存单元正常工作。
根据本公开的第五方面，提供一种显示装置，包括：根据本公开所述的移位寄存电路。
根据本公开实施例的技术方案，可以在显示器开机时通过节点复位电路、复位电路以及输入电路实现在预复位阶段以及复位阶段对应的功能，进而对第一节点、第二节点以及信号输出端的电压进行复位，因此能够避免移位寄存单元在正常工作之前输出的工作信号，进而改善开机时寄存器输出不稳定导致的显示面板显示异常的问题。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对本公开实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一个实施例的移位寄存单元的示意性结构图；
图2为根据本公开实施例的移位寄存单元电路；
图3为根据本公开另一实施例的移位寄存单元的示意性结构图；
图4为根据本公开一个实施例的移位寄存单元的驱动方法的步骤流程图；
图5为根据本公开另一实施例的移位寄存单元的示意性结构图；
图6为根据本公开另一实施例的移位寄存单元的驱动方法的步骤流程图；
图7为根据本公开实施例的移位寄存单元的信号时序状态示意图；
图8为根据本公开实施例的移位寄存电路的示意性结构图；以及
图9为根据本公开实施例的移位寄存电路的驱动方法的步骤流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管(英文名称：Thin Film Transistor，简称：TFT)或场效应管或金属-氧化物-半导体晶体管(英文名称：Metal-Oxide-semiconductor，简称：MOS管)其他特性相同的器件。根据在电路中的作用，本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中源极称为第一极，漏极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本公开实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。
还需要说明的是，为了便于清楚描述本公开实施例的技术方案，在本公开的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不是在对数量和执行次序进行限定。
本公开实施例提供了一种移位寄存单元。参照图1所示，该移位寄存单元包括：输入电路11、复位电路12、控制电路13、输出电路14以及节点复位电路15。
以下参照图1所示对移位寄存单元中各个功能电路的连接关系进行详细说明。
输入电路11连接第一电平端V1、输入信号端Input以及第一节点a。
复位电路12连接第二电平端V2、复位信号端Reset以及第一节点a。
控制电路13连接第一时钟信号端CLK1、输出信号端Output、第三电平端V3、第一节点a以及第二节点b。
输出电路14连接第二时钟信号端CLK2、第一节点a以及输出信号端Output、第三电平端V3、第二节点b。
节点复位电路15连接扫描信号端EN、输出信号端Output、第二节点b以及第三电平端V3。
进一步的，以下对上述各功能电路在移位寄存单元中所起的作用进行详细说明。
在预复位阶段，节点复位电路15配置为在扫描信号端EN的扫描信号的控制下将第三电平端V3的电压传输至第二节点b以及将所述扫描信号在所述输出信号端Output输出。复位电路12配置为在复位信号端Re set的复位信号的控制下将第二电平端V2的电压传输至第一节点a。输入电路11配置为在输入信号端Input的输入信号的控制下将第一电平端V1的电压传输至第一节点a。
在复位阶段，控制电路13配置为在第一节点a的电压、输出信号端Output的电压以及第一时钟信号端CLK1的第一时钟信号的控制下将第一时钟信号端CLK1的第一时钟信号传输至第二节点b以及在第二节点b的电压的控制下将第三电平端V3的电压传输至第一节点a。输出电路14配置为在第二节点b的电压的控制下将第三电平端V3的电压传输至信号输出端Output。
在复位阶段之后，根据本公开实施例的移位寄存单输出栅极驱动信号，本公开实施例进一步对移位寄存单元在输出栅极驱动信号阶段各功能电路的作用进行详细说明。例如，移位寄存单元输出栅极驱动信号阶段可以包括：第一时段、第二时段以及第三时段。
在第一时段，输入单元11配置为在输入信号端Input的输入信号的控制下将第一电平端V1的电压传输至第一节点a。控制单元13配置为在第一节点a的电压的控制下将第三电平端V3的电压传输至第二节点b。
在第二时段，输出单元14配置为在第一节点a的电压的控制下将第二时钟信号端CLK2的电压在信号输出端Output输出作为栅极驱动信号。
第三时段，复位单元13配置为在复位信号端Reset的复位信号的控制下将第二电平端V2的电压传输至第一节点a。控制单元13配置为在第一节点a的电压、输出信号端Output的电压以及第一时钟信号端CLK1输出的第一时钟信号的控制下将第一时钟信号端CLK1的第一时钟信号传输至第二节点b以及在第二节点b的电压的控制下将第三电平端V3的电压传输至第一节点a。输出单元14配置为在第二节点b的电压的控制下将第三电平端V3的电压传输至信号输出端Output。
根据本公开实施例的移位寄存单元，可以在显示器开机时通过节点复位电路、复位电路以及输入电路实现在预复位阶段以及复位阶段的功能，进而对第一节点、第二节点以及信号输出端的电压进行复位。因此根据本公开实施例的技术方案可以避免移位寄存单元在正常工作之前输出的工作信号，进而改善开机时寄存器输出不稳定导致的显示面板显示异常的问题。
进一步的，本公开实施例还提供了一种移位寄存单元的示例电路。参照图2所示，输入电路11包括第一晶体管T1。第一晶体管T1的第一极连接第一电平端V1，第一晶体管T1的第二极连接第一节点a；第一晶体管T1的栅极连接信号输入端Input。
复位电路12包括第二晶体管T2。第二晶体管T2的第一极连接第二电平端V2，第二晶体管T2的第二极连接第一节点a，第二晶体管T2的栅极连接复位信号端Reset。
控制电路13包括第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第一电容C1。第三晶体管T3的第一极连接第一时钟信号端CLK1，第三晶体管T3的第二极连接第二节点b，第三晶体管T3的栅极连接第一时钟信号端CLK1。第四晶体管T4的第一极连接第一节点a，第四晶体管T4的第二极连接第三电平端V3，第四晶体管T4的栅极连接第二节点b。第五晶体管T5的第一极连接第一节点a，第五晶体管T5的第二极连接第三电平端V3，第五晶体管T5的栅极连接第一节点a。第六晶体管T6的第一极连接第二节点b，第六晶体管T6的第二极连接第三电平端V3，第六晶体管T6的栅极连接输出信号端Output。第一电容C1的第一极连接第二节点b，第一电容C1的第二极连接第三电平端V3。
输出电路14包括第七晶体管T7、第八晶体管T8和第二电容C2。第七晶体管T7的第一极连接输出信号端Output，第七晶体管T7的第二极连接第三电平端V3，第七晶体管T7的栅极连接第二节点b。第八晶体管T8的第一极连接第二时钟信号端CLK2，第八晶体管T8的第二极连接信号输出端Output，第八晶体管T8的栅极连接第一节点a。第二电容C2的第一极连接第一节点a，第二电容C2的第二极连接信号输出端Output。
节点复位电路15包括第九晶体管T9的第十晶体管T10。第九晶体管T9的第一极连接信号输出端Output，第九晶体管T9的第二极连接扫描信号端EN， 第九晶体管T9的栅极连接扫描信号端EN。第十晶体管T10的第一极连接第二节点b，第十晶体管T10的第二极连接第三电平端V3，第十晶体管T10的栅极连接扫描信号端EN。
本公开实施例提供一种移位寄存单元的驱动方法。参照图3所示，移位寄存单元包括：输入电路31、复位电路32、控制电路33、输出电路34，其中输入电路31、复位电路32、控制电路33以及输出电路34连接第一节点PU，控制电路33和输出电路34连接第二节点PD，以及控制电路33和输出电路34连接输出信号端Output。
在输入电路31的控制下，由第一节点PU控制控制电路33使输出电路34在输出信号端Output输出上拉信号。在控制电路33的控制下，第二节点PD使输出电路34在输出信号端Output输出下拉信号，复位电路32配置为对第一节点PU和输出信号端Output进行复位。
上拉信号以及下拉信号用于控制通过与该移位寄存单元的输出信号端连接的晶体管的导通/截止状态。例如，当移位寄存单元的输出信号端输出上拉信号时，通过栅线与该移位寄存单元的输出信号端连接的晶体管处于导通状态，当移位寄存单元的输出信号端输出下拉信号时，通过栅线与该移位寄存单元的输出信号端连接的晶体管处于截止状态。例如，当通过栅线与该移位寄存单元的输出信号端连接的晶体管为N型晶体管时，上拉信号为高电平、下拉信号为低电平；当通过栅线与该移位寄存单元的输出信号端连接的晶体管为P型晶体管时，上拉信号为低电平、下拉信号为高电平。
参照图4所示，上述移位寄存单元的驱动方法可以包括以下步骤。
在复位阶段S41，第二节点为第一电平，控制电路在第二节点的电压的控制下，将第二电平传输至第一节点和输出信号端。
例如，上述步骤S41可以包括：控制电路43在第一节点PU的电压以及输出信号端Output的电压控制下将第一电平传输至第二节点PD以及在第二节点PD的电压的控制下将第二电平传输至第一节点PU和信号输出端Output。
在正常工作阶段S42，移位寄存单元正常工作。
例如，上述步骤S42的可以包括以下阶段。
在第一阶段，输入电路31将第一电平传输至第一节点PU；控制电路33在第一节点PU的电压的控制下将第二电平传输至第二节点PD。
在第二阶段，输出电路34在第一节点PU的电压的控制下将第一电平传输至输出信号端Output。
在第三阶段，复位电路32将第二电平传输至第一节点PU。控制电路33在第一节点PU的电压以及输出信号端Output的电压的控制下将第一电平传输至第二节点PD以及在第二节点PD的电压的控制下将第二电平传输至第一节点PU。输出电路34在第二节点PD的电压的控制下将第二电平传输至信号输出端Output。
需要说明的是，在上述实施例中，若移位寄存单元中各个晶体管均为N型晶体管，则上述实施例中的第一电平为高电平，第二电平为低电平。若在移位寄存单元中各个晶体管均为P型晶体管，则移位寄存单元的驱动过程中需要将信号调节为相位相反为信号，即在移位寄存单元中各个晶体管均为P型晶体管时，上述实施例中的第一电平为低电平，第二电平为高电平。
根据本公开实施例提供的移位寄存单元的驱动方法，可以在开机时首先对第一节点和第二节点进行复位，使移位寄存单元输出非工作信号。因此根据本公开实施例的移位寄存单元的驱动方法可以避免移位寄存单元在正常工作之前输出的工作信号，进而改善开机时寄存器输出不稳定导致的显示面板显示异常的问题。
进一步的，参照图5所示，图4所示的移位寄存单元还包括：连接第二节点PD和输出信号端Output的节点复位电路35。
参照图6所示，在复位阶段之前，所述驱动方法还可以包括以下步骤。
在预复位阶段S61，在节点复位电路35的控制下使第一节点PU和第二节点PD均为第二电平。
例如，上述在预复位阶段，在节点复位电路的控制下使第一节点和第二节点均为第二电平。该步骤可以包括节点复位电路35将第一电平传输至输出信号端Output以及将第二电平传输至第二节点PD；复位电路12和输入电路11将第二电平传输至第一节点PU。
以下参照图7所示的时序状态示意图，对根据本公开实施例的移位寄存单元的工作原理进行说明。其中，以图2所示的移位寄存单元中所有晶体管均为栅极高电平导通的N型晶体管为例进行说明。图7示出了第一电平端V1的电压信号、第二电平端的电压信号V2、扫描信号端EN的扫描信号、输入信号端 Input的输入信号、第一时钟信号端CLK1的第一时钟信号、第二时钟信号端CLK2的第二时钟信号、输出信号端Output的输出信号、第一节点a的电压以及第二节点b的电压的时序状态。其中，第二电平端V2、第三电平端V3提供稳定的低电平。示例性的，第二电平端V2、第三电平端V3可以接地。如图7所示，可以包括：阶段1(预复位阶段)；阶段2(复位阶段)；阶段3(正常工作阶段)，其中，第三阶段3进一步包括：第一正常工作子时段t31、第二正常工作子时段t32以及第三正常工作子时段t33。
在阶段1(预复位阶段)中，扫描信号端EN输入高电平，因此第九晶体管T9和第十晶体管T10导通。由于信号输出端Output通过第九晶体管T9连接扫描信号端EN，信号输出端Output输出扫描信号端EN的高电平。第二节点b通过第十晶体管T10连接第三电平端V3，因此第三电平端V3将第二节点b的电压复位为低电平。此外，复位信号端Reset输入高电平，输入信号端Input输入高电平，因此第一晶体管T1和第二晶体管T2导通，第一节点a通过第一晶体管T1连接第一电平端、通过第二晶体管T2连接第二电平端V2，且此阶段中第一电平端V1和第二电平端V2均为低电平，由此将第一节点a的电压复位为低电平。还需要说明的是，当m个移位寄存单元级联形成移位寄存电路时，上述移位寄存单元的工作原理与移位寄存电路中的第2至m-1级移位寄存单元对应。第1级移位寄存单元和第m级移位寄存单元的工作原理略有不同，其不同之处在于，在阶段1中，第1级移位寄存单元的输入信号端Input输入低电平，第m级移位寄存单元的复位信号端Reset输入低电平。但是，由于此阶段中第一电平端V1和第二电平端V2均为低电平，所以即使复位信号端Reset或输入信号端Input输入低电平，依然可以将第一节点a的电压复位为低电平，所以此阶段中也可以将第1级移位寄存单元和第m级移位寄存单元的第一节点a的电压复位为低电平。
在阶段2(复位阶段)中，第一时钟信号端CLK1开始输出第一时钟信号，第二时钟信号端CLK2开始输出第二时钟信号。第一时钟信号、第二时钟信号的占空比均为50％，第一时钟信号和第二时钟信号相位相反。
当第一时钟信号端CLK1的第一时钟信号为高电平，第二时钟信号端CLK2的第二时钟信号为低电平时，第三晶体管T3导通，第二节点b通过第三晶体管T3连接第一时钟信号端CLK1，第一时钟信号端CLK1将第二节点b的电压拉 为高电平。第二节点b为高电平，因此第四晶体管T4导通，第一节点a通过第四晶体管T4连接第三电平端V3，第三电平端V3将第一节点a的电压拉为低电平。第七晶体管T7导通，信号输出端Output通过第七晶体管T7连接第三电平端V3，第三电平端V3将信号输出端Output的电压拉为低电平。此外，当控制电路包括第一电容C1时，对第一电容C1充电。
当第二时钟信号端CLK2的第二时钟信号为高电平，第一时钟信号端CLK1的第一时钟信号为低电平时，第二节点b保持高电平，第一节点a保持低电平，第八晶体管T8截止，第二时钟信号端CLK2输出的第二时钟信号无法通过第八晶体管T8进入GOA电路中，因此当第二时钟信号端CLK2的第二时钟信号为高电平时，输出信号端Output仍保持低电平。此外，当控制电路包括第一电容C1时，由于在第一时钟信号端CLK1的第一时钟信号为高电平时，第一电容C1充电，且在第二时钟信号端CLK2的第二时钟信号为高电平时，第一电容C1没有放电路径，因此可以更好的使第二节点b保持高电平。
由于阶段2可以将第一节点的电压拉为低电平、将第二节点的电压拉为高电平，这样可保证信号输出端Output输出稳定的低电平，因此本公开实施例提供的GOA电路、GOA电路的驱动方法可以改善开机时GOA电路输出不稳定导致的显示面板显示异常的问题。
此外，阶段2中包含时钟信号的周期的数量可以根据实际需求设定为任意数量，本公开实施例中对阶段2中包含时钟信号的周期的数量不做限定。
在阶段3(正常工作阶段)的第一正常工作子时段t31，信号输入端Input输出高电平、第一电平端V1输出高电平，第一晶体管T1导通，第一节点a通过第一晶体管T1连接第一电平端，第一电平端V1将第一节点a拉为高电平。同时对第二电容C2进行充电。因为第一节点a为高电平，因此第五晶体管T5以及第八晶体管T8导通，第二节点b通过第五晶体管T5连接第三电平端V3，第三电平端V3将第二节点拉为低电平。此阶段第一时钟信号端CLK1的第一时钟信号为高电平、第二时钟信号端CLK2的第二时钟信号为低电平，因此输出信号端输出低电平。
在阶段3(正常工作阶段)的第二正常工作子时段t32，信号输入端Input输出低电平，第一晶体管T1截止，第一时钟信号端CLK1的第一时钟信号为低电平，第四晶体管T4截止，第二电容C2没有放电路径，因此第二电容C2保 持第一节点a为高电平。第二时钟信号端CLK2的第二时钟信号为高电平，因此，第二电容C2第二极的电压升高，由于电容的自举效应，第二电容C2第一极(即第一节点)的电压进一步升高，第八晶体管T8被导通的更加充分。信号输出端Output通过第八晶体管T8连接第二时钟信号端，并输出第二时钟信号端CLK2的高电平。
在阶段3(正常工作阶段)的第三正常工作子时段t33，复位信号端Re set输入高电平，因此第二晶体管T2导通，第一节点a通过第二晶体管T2连接第二电平端V2，第一节点a被拉为低电平。第一时钟信号端CLK1的第一时钟信号为高电平时，第三晶体管T3导通，第二节点b通过第三晶体管T3连接第一时钟信号端CLK1，第一时钟信号端CLK1将第二节点b的电压拉为高电平。由于第二节点b为高电平，因此第四晶体管T4和第七晶体管T7导通，第一节点a通过第四晶体管T4连接第三电平端V3，第一节点a的电压进一步拉低，输出信号端Output通过第七晶体管T7连接第三电平端V3，输出信号端输出低电平。
可以从第一正常工作子时段t31开始到本级移位寄存单元的输入信号端Input再次输入高电平作为本级移位寄存单元的一个完整工作周期。因此在上述第三正常工作子时段t33之后本级移位寄存单元的一个工作周期中还可以包括若干阶段，这是由移位寄存电路扫描的行数所决定的。但在第三正常工作子时段t33之后本级GOA电路的输入信号端Input再次输入的高电平之前，本级移位寄存单元的输出信号端Output保持低电平(输出非工作信号)。
进一步的，上述实施例中的移位寄存单元中所有晶体管还可以均为低电平导通的P型晶体管。若所有晶体管均为P型晶体管，则只需要重新调整移位寄存单元各个输入信号的时序状态即可。
再进一步的，上述移位寄存单元中也可以同时采用N型晶体管和P型晶体管，此时需保证移位寄存单元中通过同一个时序信号或电压控制的晶体管需要采用相同的类型。由于不同类型的晶体管的有源层掺杂材料不相同，因此移位寄存单元中采用统一类型的晶体管更有利于简化移位寄存单元的制程工艺。
此外，还需要说明的是，上述实施例中以将图6所示的移位寄存单元的驱动方法应配置为图2所示移位寄存单元为例对对其工作原理进行说明，但本公开并不限定于此。
本公开再一实施例提供一种移位寄存电路，参照图8所示，该移位寄存电 路包括m个级联的上述实施例提供的移位寄存单元。其中，第1级移位寄存单元的输入信号端连接起始信号端，第1级移位寄存单元的输出信号端连接第2级移位寄存单元的信号输入端，第1级移位寄存单元的复位信号端连接第2级移位寄存单元的信号输出端；第m级移位寄存单元的输入信号端连接第m-1级移位寄存单元的输出信号端，第m级移位寄存单元的输出信号端连接第m-1级移位寄存单元的复位信号端；第n级移位寄存单元的输入信号端连接第n-1级移位寄存单元的信号输出端，第n级移位寄存单元的信号输出端连接第n+1级移位寄存单元的信号输入端，第n级移位寄存单元的复位信号端连接第n+1级移位寄存单元的信号输出端；m、n为大于1的整数且m大于n。
例如，参照图8所示，第1级移位寄存单元的输入信号端连接起始信号端STV，第1级移位寄存单元的输出信号端连接第二级移位寄存单元的输入信号端以及栅线G1，第1级移位寄存单元的复位信号端连接第2级移位寄存单元的输出信号端；第n级移位寄存单元的输入信号端连接n-1级移位寄存单元的信号输出端，第n级移位寄存单元的输出信号端连接第n+1级移位寄存单元的信号输入端，第n级移位寄存单元的复位信号端连接第n+1级移位寄存单元的输出信号端，第m级移位寄存单元(最后一级移位寄存单元)的输入信号端连接第m-1级移位寄存单元的输出信号端，第m级移位寄存单元的输出信号端连接第m-1级移位寄存单元的输入信号端以及栅线Gm。
此外，每一个移位寄存单元包括一个第一时钟信号端CLK1和一个第二时钟信号端CLK2。参照图8所示，通过两个系统的时钟信号clock1、clock2向每个移位寄存单元连接的两个时钟信号端提供时钟信号，其中第2n-1级移位寄存单元的CLK1输入clock1，第2n-1级移位寄存单元的CLK2输入clock2，第2n级移位寄存单元的CLK1输入clock2，第2n级移位寄存单元的CLK2输入clock1。
系统时钟的时序状态参照图7中第一时钟信号端CLK1的第一时钟信号和第二时钟信号端CLK2的第二时钟信号。其中，clock1与clock2的相位相反，clock1与clock2均为占空比为50％的时钟信号。
本公开的一个实施例提供了一种移位寄存电路的驱动方法，该移位寄存电路的驱动方法配置为驱动图8所示的移位寄存电路，例如，参照图9所示，该方法可以包括以下步骤。
在预复位阶段S91，向移位寄存电路的第1级移位寄存单元的扫描信号输 入端输入第一电平。
向移位寄存电路的第1级移位寄存单元的扫描信号输入端输入第一电平，则第1级移位寄存单元的节点复位单元会将第一电平传输至第1级移位寄存单元的输出信号端，第1级移位寄存单元的输出信号端再将第一电平传输至第2级移位寄存单元的信号输入端，并继续对低电平进行传递，进而使移位寄存电路中所有移位寄存单元的输出信号端均输出第一电平。
此外，移位寄存电路中每一个移位寄存单元的其他控制过程以及原理可以参照上述任一提供的移位寄存单元的驱动方法，本公开再此不再赘述。
在复位阶段S92，第一时钟信号端输入第一时钟信号、第二时钟信号端输入第二时钟信号。
在正常工作阶段S93，移位寄存单元正常工作。
移位寄存电路中每一个移位寄存单元的其他控制过程以及原理可以参照上述任一提供的移位寄存单元的驱动方法，本公开再此不再赘述。
本公开一实施例提供了一种显示装置，包括上述实施例中提供的移位寄存电路。
另外，显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存单元，包括：输入电路、复位电路、控制电路、输出电路以及节点复位电路；
    所述输入电路连接第一电平端、输入信号端以及第一节点；所述复位电路连接第二电平端、复位信号端以及所述第一节点；所述控制电路连接第一时钟信号端、输出信号端、第三电平端、所述第一节点以及第二节点；所述输出电路连接第二时钟信号端、所述第一节点、所述第二节点、所述第三电平端以及所述输出信号端；所述节点复位电路连接扫描信号端、所述输出信号端、所述第二节点以及所述第三电平端；
    其中，在预复位阶段，所述节点复位电路配置为在所述扫描信号端的扫描信号的控制下将所述第三电平端的电压传输至第二节点以及将所述扫描信号在所述输出信号端输出；所述复位电路配置为在复位信号端的复位信号的控制下将所述第二电平端的电压传输至所述第一节点；输入电路配置为在所述输入信号端的输入信号的控制下将所述第一电平端的电压传输至所述第一节点；
    在复位阶段，所述控制电路配置为在所述第一节点的电压、所述输出信号端的电压以及所述第一时钟信号端的第一时钟信号的控制下将所述第一时钟信号端的第一时钟信号传输至第二节点以及在所述第二节点的电压的控制下将所述第三电平端的电压传输至第一节点；所述输出电路配置为在所述第二节点的电压的控制下将所述第三电平端的电压传输至所述信号输出端。
  2. 根据权利要求1所述的移位寄存单元，其中，所述输入电路包括：第一晶体管；所述第一晶体管的第一极连接所述第一电平端，所述第一晶体管的第二极连接所述第一节点；所述第一晶体管的栅极连接所述信号输入端。
  3. 根据权利要求1或2所述的移位寄存单元，其中，所述复位电路包括：第二晶体管；所述第二晶体管的第一极连接所述第二电平端，所述第二晶体管的第二极连接所述第一节点，所述第二晶体管的栅极连接所述复位信号端。
  4. 根据权利要求1至3之一所述的移位寄存单元，其中，所述控制电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第一电容；所述 第三晶体管的第一极连接所述第一时钟信号端，所述第三晶体管的第二极连接所述第二节点，所述第三晶体管的栅极连接所述第一时钟信号端；所述第四晶体管的第一极连接所述第一节点，所述第四晶体管的第二极连接所述第三电平端，所述第四晶体管的栅极连接所述第二节点；所述第五晶体管的第一极连接所述第一节点，所述第五晶体管的第二极连接所述第三电平端，所述第五晶体管的栅极连接所述第一节点；所述第六晶体管的第一极连接所述第二节点，所述第六晶体管的第二极连接所述第三电平端，所述第六晶体管的栅极连接所述输出信号端；所述第一电容的第一极连接所述第二节点，所述第一电容的第二极连接所述第三电平端。
  5. 根据权利要求1至4之一所述的移位寄存单元，其中，所述输出电路包括：第七晶体管、第八晶体管和第二电容；所述第七晶体管的第一极连接所述输出信号端，所述第七晶体管的第二极连接所述第三电平端，所述第七晶体管的栅极连接所述第二节点；所述第八晶体管的第一极连接所述第二时钟信号端，所述第八晶体管的第二极连接所述信号输出端，所述第八晶体管的栅极连接所述第一节点；所述第二电容的第一极连接所述第一节点，所述第二电容的第二极连接所述信号输出端。
  6. 根据权利要求1所述的移位寄存单元，其中，所述节点复位电路包括：第九晶体管的第十晶体管；所述第九晶体管的第一极连接所述信号输出端，所述第九晶体管的第二极连接所述扫描信号端，所述第九晶体管的栅极连接所述扫描信号端；所述第十晶体管的第一极连接所述第二节点，所述第十晶体管的第二极连接所述第三电平端，所述第十晶体管的栅极连接所述扫描信号端。
  7. 根据权利要求2所述的移位寄存单元，其中，所述节点复位电路包括：第九晶体管的第十晶体管；所述第九晶体管的第一极连接所述信号输出端，所述第九晶体管的第二极连接所述扫描信号端，所述第九晶体管的栅极连接所述扫描信号端；所述第十晶体管的第一极连接所述第二节点，所述第十晶体管的第二极连接所述第三电平端，所述第十晶体管的栅极连接所述扫描信号端。
  8. 根据权利要求3所述的移位寄存单元，其中，所述节点复位电路包括：第九晶体管的第十晶体管；所述第九晶体管的第一极连接所述信号输出端，所述第九晶体管的第二极连接所述扫描信号端，所述第九晶体管的栅极连接所述 扫描信号端；所述第十晶体管的第一极连接所述第二节点，所述第十晶体管的第二极连接所述第三电平端，所述第十晶体管的栅极连接所述扫描信号端。
  9. 根据权利要求4所述的移位寄存单元，其中，所述节点复位电路包括：第九晶体管的第十晶体管；所述第九晶体管的第一极连接所述信号输出端，所述第九晶体管的第二极连接所述扫描信号端，所述第九晶体管的栅极连接所述扫描信号端；所述第十晶体管的第一极连接所述第二节点，所述第十晶体管的第二极连接所述第三电平端，所述第十晶体管的栅极连接所述扫描信号端。
  10. 根据权利要求5所述的移位寄存单元，其中，所述节点复位电路包括：第九晶体管的第十晶体管；所述第九晶体管的第一极连接所述信号输出端，所述第九晶体管的第二极连接所述扫描信号端，所述第九晶体管的栅极连接所述扫描信号端；所述第十晶体管的第一极连接所述第二节点，所述第十晶体管的第二极连接所述第三电平端，所述第十晶体管的栅极连接所述扫描信号端。
  11. 根据权利要求2至10之一所述的移位寄存单元，其中，
    所述移位寄存单元的各个晶体管均为N型晶体管，所述第一电平为高电平，所述第二电平为低电平。
  12. 根据权利要求2至10之一所述的移位寄存单元，其中，所述移位寄存单元的各个晶体管均为P型晶体管，所述第一电平为低电平，所述第二电平为高电平。
  13. 一种移位寄存单元的驱动方法，其中，所述移位寄存单元包括：输入电路、复位电路、控制电路、输出电路、与所述输入电路、所述复位电路、所述控制电路以及所述输出电路均连接的第一节点、与所述控制电路和所述输出电路连接的第二节点、以及与所述控制电路和所述输出电路连接的输出信号端；第一节点配置为在输入电路的控制下通过控制所述控制电路使所述输出电路在所述输出信号端输出上拉信号；第二节点配置为在控制电路的控制下使所述输出电路在所述输出信号端输出下拉信号，所述复位电路配置为对第一节点和输出信号端进行复位；所述驱动方法包括：
    在复位阶段，所述第二节点为第一电平，所述控制电路在所述第二节点的电压的控制下，将第二电平信号传输至第一节点和所述输出信号端；
    在正常工作阶段，所述移位寄存单元正常工作。
  14. 根据权利要求13所述的方法，其中，所述移位寄存单元还包括：连接所述第二节点和所述输出信号端的节点复位电路；
    在所述复位阶段之前，所述方法还包括，
    在预复位阶段，在所述节点复位电路的控制下使所述第一节点和所述第二节点均为第二电平。
  15. 根据权利要求14所述的方法，其中，所述第二节点为第一电平，所述控制电路在所述第二节点的电压的控制下，将第二电平信号传输至第一节点和所述输出信号端，包括：
    所述控制电路在第一节点的电压和输出信号端的电压控制下将第一电平传输至第二节点以及在所述第二节点的电压的控制下将第二电平传输至第一节点和所述信号输出端。
  16. 根据权利要求14所述的方法，其中，所述在预复位阶段，在所述节点复位电路的控制下使所述第一节点和所述第二节点均为第二电平，包括：
    所述节点复位电路将第一电平传输至所述输出信号端以及将第二电平传输至所述第二节点；所述复位电路和所述输入电路将第二电平传输至所述第一节点。
  17. 根据权利要求13所述的方法，其中，所述正常工作阶段包括：
    第一正常工作子时段，其中输入电路将第一电平传输至所述第一节点；控制电路在第一节点的电压的控制下将第二电平传输至第二节点；
    第二正常工作子时段，其中输出电路在第一节点的电压的控制下将第一电平传输至输出信号端；
    第三正常工作子时段，其中复位电路将第二电平传输至第一节点；控制电路在第一节点的电压以及输出信号端的电压的控制下将第一电平传输至第二节点以及在所述第二节点的电压的控制下将第二电平传输至第一节点；输出电路在所述第二节点的电压的控制下将第二电平传输至所述信号输出端。
  18. 一种移位寄存电路，其中，包括m个级联的权利要求1至12之一所 述的移位寄存单元；
    其中，第1级移位寄存单元的输入信号端连接起始信号端，所述第1级移位寄存单元的输出信号端连接第2级移位寄存单元的信号输入端，所述第1级移位寄存单元的复位信号端连接第2级移位寄存单元的信号输出端；
    第m级移位寄存单元的输入信号端连接第m-1级移位寄存单元的输出信号端，第m级移位寄存单元的输出信号端连接第m-1级移位寄存单元的复位信号端；
    第n级移位寄存单元的输入信号端连接第n-1级移位寄存单元的信号输出端，第n级移位寄存单元的信号输出端连接第n+1级移位寄存单元的信号输入端，第n级移位寄存单元的复位信号端连接第n+1级移位寄存单元的信号输出端；
    m、n为大于1的整数且m大于n。
  19. 一种移位寄存电路的驱动方法，其中，配置为驱动权利要求18所述的移位寄存电路，所述方法包括：
    在预复位阶段，向所述移位寄存电路的第1级移位寄存单元的扫描信号输入端输入第一电平；
    在复位阶段，第一时钟信号端输入第一时钟信号、第二时钟信号端输入第二时钟信号；
    在正常工作阶段，所述移位寄存单元正常工作。
  20. 一种显示装置，包括：权利要求18所述的移位寄存电路。
PCT/CN2017/109260 2017-04-27 2017-11-03 移位寄存单元、移位寄存电路、驱动方法及显示装置 Ceased WO2018196317A1 (zh)

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