WO2018188299A1 - 阵列基板及其制造方法、显示面板和显示装置 - Google Patents

阵列基板及其制造方法、显示面板和显示装置 Download PDF

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WO2018188299A1
WO2018188299A1 PCT/CN2017/106860 CN2017106860W WO2018188299A1 WO 2018188299 A1 WO2018188299 A1 WO 2018188299A1 CN 2017106860 W CN2017106860 W CN 2017106860W WO 2018188299 A1 WO2018188299 A1 WO 2018188299A1
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Prior art keywords
ground line
array substrate
auxiliary ground
layer
metal layer
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English (en)
French (fr)
Inventor
谷晓芳
马小叶
王锡平
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/066,660 priority Critical patent/US11164895B2/en
Publication of WO2018188299A1 publication Critical patent/WO2018188299A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the array substrate, a display panel, and a display device.
  • the narrow border as a design trend has almost all the display fields.
  • the narrow bezel product has a larger screen display area, which allows the user to obtain a better visual effect, and the appearance of the product is more beautiful and stylish.
  • the narrow frame can achieve a better splicing effect.
  • a gate metal layer may be generally disposed in a peripheral region of the substrate to form a ground line to prevent occurrence of ESD.
  • the design of the narrow bezel causes the width of the peripheral region of the substrate to be small, which results in a small width of the grounding wire and a large electrical resistance, which cannot remove static electricity in a timely and effective manner, which may affect various components inside the display device. Performance.
  • An object of the present disclosure is to provide an array substrate, a method of manufacturing an array substrate, a display panel, and a display device, thereby at least partially obviating one or more problems due to limitations and disadvantages of the related art.
  • an array substrate including a display area and a peripheral area surrounding the display area, the array substrate comprising:
  • a gate metal layer disposed on the substrate and the gate metal layer includes a ground line at the peripheral region;
  • a gate insulating layer covering at least the gate metal layer
  • a conductive layer structure disposed above the gate insulating layer and the conductive layer structure includes an auxiliary ground line at the peripheral region; wherein the auxiliary ground line is connected to the ground line.
  • the conductive layer structure includes a source/drain metal layer and the auxiliary ground line includes a first auxiliary ground line at the source/drain metal layer.
  • the first auxiliary ground line is located directly above the ground line.
  • the array substrate further includes:
  • the conductive layer structure includes a transparent electrode layer and the auxiliary ground line includes a second auxiliary ground line at the transparent electrode layer.
  • a width of the second auxiliary ground line is greater than a width of the ground line.
  • the conductive layer structure includes a transparent electrode layer and the auxiliary ground line includes a second auxiliary ground line at the transparent electrode layer.
  • a width of the second auxiliary ground line is greater than a width of the ground line.
  • the array substrate further includes:
  • An electrostatic ring electrically connected to at least one of the ground line, the first auxiliary ground line, and the second auxiliary ground line.
  • a display panel including the array substrate according to any one of the above aspects is provided.
  • a display device comprising the display panel of any of the above.
  • an array substrate manufacturing method is provided, the array substrate includes a display area and a peripheral area surrounding the display area, and the array substrate manufacturing method includes:
  • the conductive layer structure including an auxiliary ground line at the peripheral region; wherein the auxiliary ground line is connected to the ground line.
  • the conductive layer structure includes a drain-source metal layer and the auxiliary ground line includes a first auxiliary ground line at the drain-source metal layer.
  • the conductive layer structure includes a transparent electrode layer and the auxiliary ground line includes a second auxiliary ground line at the transparent electrode layer.
  • the conductive layer structure including the auxiliary ground line is disposed above the gate insulating layer, the auxiliary ground line is disposed and the ground of the gate metal layer is combined.
  • the wire can constitute a structure of at least two layers of grounding wires, which reduces the resistance of the grounding wire for guiding static electricity, and helps prevent ESD.
  • Figure 1 is a schematic elevational view of an array substrate for preventing ESD
  • Figure 2 is a cross-sectional view schematically showing a portion of the array substrate of Figure 1 along a broken line AA';
  • FIG. 3 is a cross-sectional view schematically showing a first embodiment of a portion of an array substrate corresponding to a position of a broken line AA' according to an exemplary embodiment of the present disclosure
  • FIG. 4 schematically illustrates a cross-sectional view of a second embodiment of a portion of an array substrate corresponding to a broken line AA' position, according to an exemplary embodiment of the present disclosure
  • FIG. 5 is a cross-sectional view schematically showing a third embodiment of a portion of the array substrate corresponding to the position of the broken line AA' according to an exemplary embodiment of the present disclosure
  • FIG. 6 schematically illustrates a flow chart of a method of fabricating an array substrate according to an exemplary embodiment of the present disclosure.
  • the array substrate may include a display area 90 and a peripheral area surrounding the display area 90.
  • the peripheral area may include a substrate 10, a ground line 20 disposed on the substrate 10, a common electrode line 30, and a GOA (Gate Driver on Array) unit 40.
  • the peripheral area may further include silver.
  • the silver paste region 50 can be used to establish an electrical connection with the conductive film of the color filter substrate. The generated static electricity can be removed by the grounding wire 20 disposed in the peripheral area to prevent the influence of static electricity on various components on the array substrate.
  • FIG. 2 is a cross-sectional view showing a portion of the array substrate of FIG. 1 along a broken line AA'.
  • a ground line 20, a common electrode line 30, a cover ground line 20, and a common electrode line may be disposed on the substrate 10.
  • the width of the peripheral region surrounding the display region is generally small, which results in a small width of the grounding wire, a large resistance, and cannot conduct static electricity in a timely and effective manner, which may cause abnormal display. problem.
  • the array substrate can include:
  • a gate metal layer disposed on the substrate and the gate metal layer includes a ground line located in the peripheral region;
  • a gate insulating layer covering at least the gate metal layer
  • the conductive layer structure is disposed above the gate insulating layer and the conductive layer structure includes an auxiliary ground line located in the peripheral region.
  • a structure of at least two layers of ground lines may be formed, which reduces resistance of a ground line for guiding static electricity, and helps Prevent ESD.
  • the conductive layer structure may be an SD metal layer (ie, a source/drain metal layer), and the auxiliary ground line may be located at SD.
  • a first auxiliary ground line in the metal layer may be an SD metal layer (ie, a source/drain metal layer), and the auxiliary ground line may be located at SD.
  • the substrate 10 may be a glass substrate, however, the substrate 10 may also be a quartz substrate or a transparent plastic substrate for flexible display.
  • the present disclosure has been described by taking a glass substrate as an example, it is also within the scope of the present invention to use a substrate of another material.
  • a gate metal layer (not shown) may be disposed on the substrate 10, and the gate metal layer may include a ground line 20 at a peripheral region, and the ground line 20 may be made of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum.
  • Single layer grounding wire formed of (Al), aluminum-niobium alloy (AlNd), titanium (Ti) or copper (Cu).
  • the grounding wire 20 may also be made of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum ( Al), aluminum-niobium alloy (AlNd), titanium (Ti) or copper (Cu)
  • the ground line 20 may be a single layer ground line formed of Mo, Al or an alloy containing Mo or Al, or the ground line 20 may be formed of a plurality of materials of Mo, Al, an alloy containing Mo or Al. Composite laminate.
  • a common electrode line 30 may be disposed on the substrate 10, and the common electrode line 30 may be disposed in parallel with the ground line 20, and the material of the common electrode line 30 may be the same as the material of the 2 ground line 20, and details are not described herein again. .
  • a gate insulating layer 60 may also be disposed on the substrate 10, and the gate insulating layer 60 may cover at least the gate metal layer.
  • the gate insulating layer 60 may be a single insulating layer composed of a material of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), or the like, and the gate insulating layer 60 may also be composed of A composite laminate of at least two materials of silicon oxide (SiOx), silicon nitride (SiNx), and hafnium oxide (HfOx).
  • the gate insulating layer 60 may be a single insulating layer formed of SiOx.
  • a conductive layer structure may be disposed on the gate insulating layer 60, and the conductive layer structure may include an auxiliary ground line at a peripheral region.
  • the conductive layer structure may be an SD metal layer, and the auxiliary ground line may be the first auxiliary ground line 100 at the SD metal layer.
  • the material of the SD metal layer may be the same as the material of the grounding wire 20 described above, and details are not described herein again. However, the material of the SD metal layer may also be different from the material of the ground line 20.
  • the first auxiliary ground line 100 may be located directly above the ground line 20.
  • the first auxiliary ground line 100 may be disposed at any other position on the gate insulating layer 60, and the width of the first auxiliary ground line 100 is not limited to the relative width shown in FIG. 3, first The width of the auxiliary ground line 100 can be much wider than the width of the ground line 20.
  • first auxiliary ground line 100 and one end of the ground line 20 may be connected to a silver paste region (for example, the silver paste region 50 shown in FIG. 1). Therefore, the first auxiliary ground line 100 is combined with the ground line 20, and the ground line 20 is connected in parallel with another ground line. As a whole, the wider the width of the first auxiliary ground line 100, the smaller the resistance. Helps prevent ESD.
  • the array substrate of the first embodiment of the present disclosure may further include a passivation layer 70 covering at least the SD metal layer.
  • the material of the passivation layer 70 may be the same as that of the gate insulating layer 60.
  • the material of the passivation layer 70 may be an oxide of aluminum (AlOx), or the passivation layer 70 may be an organic material such as an acrylic material or a resin.
  • the configuration is not particularly limited in the exemplary embodiment.
  • the resistance of the ground line for guiding static electricity is lowered, contributing to prevention of ESD.
  • the conductive layer structure may be a transparent electrode layer, which may be, for example, ITO (Indium Tin Oxide). Layer).
  • the auxiliary ground line may be a second auxiliary ground line located in the transparent electrode layer.
  • the substrate 10, the ground line 20, the common electrode line 30, and the gate insulating layer 60 in FIG. 4 may be insulated from the substrate 10, the ground line 20, the common electrode line 30, and the gate shown in FIG. 3 in the first embodiment of the present disclosure.
  • Layer 60 is the same, I will not repeat them here.
  • a passivation layer 70 may be disposed on the gate insulating layer 60.
  • the material of the passivation layer 70 may be the same as that of the passivation layer 70 shown in FIG. 3 in the first embodiment, and details are not described herein again.
  • a conductive layer structure may be disposed on the passivation layer 70, and the conductive layer structure may include an auxiliary ground line located in the peripheral region.
  • the conductive layer structure may be a transparent electrode layer.
  • the transparent electrode layer may be, for example, an ITO layer
  • the auxiliary ground line may be a second auxiliary ground line 200 located in the transparent electrode layer.
  • the width of the second auxiliary ground line 200 may be greater than the width of the ground line 20.
  • the second auxiliary ground line 200 may cover the entire area corresponding to the broken line AA'.
  • the width of the second auxiliary ground line 200 is not limited thereto.
  • one end of the second auxiliary ground line 200 and one end of the ground line 20 may be connected to a silver paste region (for example, the silver paste region 50 shown in FIG. 1). Therefore, the second auxiliary ground line 200 is combined with the ground line 20, which is equivalent to connecting the ground line 20 with another ground line. As a whole, the width of the second auxiliary ground line 200 is wider, and the resistance is smaller. Helps prevent ESD.
  • the array substrate may further include an electrostatic ring (not shown) that may be electrically connected to at least one of the ground line 20 and the second auxiliary ground line 200.
  • the resistance of the ground line for guiding static electricity is reduced, which helps prevent ESD, and at the same time, the ESD prevention is further enhanced by configuring the electrostatic ring. ability.
  • the conductive layer structure may include an SD metal layer and a transparent electrode layer.
  • the auxiliary ground line may include a first auxiliary ground line respectively located at the SD metal layer and a second auxiliary ground line located at the transparent electrode layer.
  • the substrate 10, the ground line 20, the common electrode line 30, the gate insulating layer 60, the first auxiliary ground line 100, and the passivation layer 70 in FIG. 5 may be the substrate 10 shown in FIG. 3 in the first embodiment of the present disclosure,
  • the ground line 20, the common electrode line 30, the gate insulating layer 60, the first auxiliary ground line 100, and the passivation layer 70 are the same, and are not described herein again.
  • a transparent electrode layer may be disposed on the passivation layer 70, and the transparent electrode layer may include a second auxiliary ground line 200 at a peripheral region. Similar to the second embodiment of the present disclosure shown in FIG. 4, the width of the second auxiliary ground line 200 may be greater than the width of the ground line 20.
  • one end of the ground line 20, one end of the first auxiliary ground line 100, and one end of the second auxiliary ground line 200 may be connected to a silver paste region (for example, the silver paste region 50 shown in FIG. 1). Therefore, the grounding line 20, the first auxiliary grounding line 100 and the second auxiliary grounding line 200 are combined, and the grounding line 20, the first auxiliary grounding line 100 and the second auxiliary grounding line 200 constitute a three-electrode guiding static electricity.
  • the layer structure as a whole of the structure, greatly reduces the conduction resistance and can prevent ESD more effectively.
  • the array substrate may further include an electrostatic ring (not shown), The electrostatic ring may be electrically connected to at least one of the ground line 20, the first auxiliary ground line 100, and the second auxiliary ground line 200.
  • the resistance of the ground line for guiding static electricity is greatly reduced, which helps prevent ESD, and at the same time, by configuring static electricity
  • the ring further enhances the preventive capacity of ESD.
  • the exemplary embodiment further provides a method for manufacturing an array substrate.
  • the method for manufacturing the array substrate may include:
  • the conductive layer structure includes a drain-source metal layer and the auxiliary ground line includes a first auxiliary ground line at the drain-source metal layer.
  • the conductive layer structure includes a transparent electrode layer and the auxiliary ground line includes a second auxiliary ground line located in the transparent electrode layer.
  • a gate metal layer may be formed on a substrate by sputtering deposition, and a ground line may be formed by a patterning process.
  • a gate insulating layer covering at least the gate metal layer may be formed by PECVD (Plasma Enhanced Chemical Vapor Deposition).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a conductive layer structure may be formed over the gate insulating layer by sputter deposition, and an auxiliary ground line may be formed by a patterning process.
  • the method of forming the gate metal layer may further include thermal evaporation
  • the method of forming the conductive layer structure may further include PECVD. and many more.
  • a display panel is further provided in the exemplary embodiment, and the display panel includes the array substrate described above.
  • the present exemplary embodiment further provides a display device, which may include the display panel described above.
  • the display device may specifically be a product or a component having any display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • the array substrate, the display panel, and the display device provided by the present disclosure can prevent ESD more effectively.

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Abstract

一种阵列基板及其制造方法、显示面板和显示装置，该阵列基板包括：栅极金属层，设于基板（10）上且所述栅极金属层包括位于周边区域的接地线（20）；栅极绝缘层（60），至少覆盖所述栅极金属层；以及导电层结构，设于所述栅极绝缘层（60）上方且所述导电层结构包括位于所述周边区域的辅助接地线（100，200）；其中，所述辅助接地线（100，200）与所述接地线（20）连接，该阵列基板能够更加有效地预防ESD。

Description

阵列基板及其制造方法、显示面板和显示装置
交叉引用
本申请要求于2017年4月14日提交的申请号为201710244489.0、名称为“阵列基板及其制造方法、显示面板和显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板、该阵列基板的制造方法、显示面板和显示装置。
背景技术
随着信息社会的发展，人们对显示装置的要求越来越高，这促使对显示技术的研究不断深入。与此同时，显示装置的外观越来越受到重视。其中，窄边框作为一种设计潮流已几乎遍及整个显示领域。对于相同尺寸的面板，窄边框产品的屏幕显示面积更大，能够让用户获得更好的视觉效果，并且产品的外观更加美观、时尚。此外，在显示装置需要双屏拼接时，窄边框可以实现更好的拼接效果。
在显示装置的测试以及使用过程中，静电可能会造成诸多不良影响(如，显示画面不稳定、显示面板失效等)，因此，预防ESD(Electrostatic Discharge，静电放电)的设计十分重要。对于液晶显示装置而言，通常可以在基板的周边区域布置栅极金属层来形成接地线，以预防ESD的发生。然而，窄边框的设计通过会造成基板的周边区域的宽度较小，这就导致接地线的宽度较小而电阻较大，不能及时且有效地将静电移除，进而可能影响显示装置内部各部件的性能。
鉴于此，需要一种新的阵列基板、阵列基板的制造方法、显示面板和显示装置。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种阵列基板、阵列基板的制造方法、显示面板和显示装置，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
根据本公开的一个方面，提供一种阵列基板，包括显示区域和环绕所述显示区域的周边区域，所述阵列基板包括：
栅极金属层，设于基板上且所述栅极金属层包括位于所述周边区域的接地线；
栅极绝缘层，至少覆盖所述栅极金属层；以及
导电层结构，设于所述栅极绝缘层上方且所述导电层结构包括位于所述周边区域的辅助接地线；其中，所述辅助接地线与所述接地线连接。
在本公开的一种示例性实施例中，所述导电层结构包括源漏金属层且所述辅助接地线包括位于所述源漏金属层的第一辅助接地线。
在本公开的一种示例性实施例中，所述第一辅助接地线位于所述接地线的正上方。
在本公开的一种示例性实施例中，所述阵列基板还包括：
钝化层，至少覆盖所述源漏金属层。
在本公开的一种示例性实施例中，所述导电层结构包括透明电极层且所述辅助接地线包括位于所述透明电极层的第二辅助接地线。
在本公开的一种示例性实施例中，所述第二辅助接地线的宽度大于所述接地线的宽度。
在本公开的一种示例性实施例中，所述导电层结构包括透明电极层且所述辅助接地线包括位于所述透明电极层的第二辅助接地线。
在本公开的一种示例性实施例中，所述第二辅助接地线的宽度大于所述接地线的宽度。
在本公开的一种示例性实施例中，所述阵列基板还包括：
静电环，所述静电环与所述接地线、所述第一辅助接地线以及所述第二辅助接地线中的至少之一电连接。
根据本公开的一个方面，提供一种显示面板，所述显示面板包括上述任意一项所述的阵列基板。
根据本公开的一个方面，提供一种显示装置，所述显示装置包括上述任意一项所述的显示面板。
根据本公开的一个方面，提供一种阵列基板制造方法，所述阵列基板包括显示区域和环绕所述显示区域的周边区域，所述阵列基板制造方法包括：
在基板上形成栅极金属层，所述栅极金属层包括位于所述周边区域的接地线；
形成至少覆盖所述栅极金属层的栅极绝缘层；以及
在所述栅极绝缘层上方形成导电层结构，所述导电层结构包括位于所述周边区域的辅助接地线；其中，所述辅助接地线与所述接地线连接。
在本公开的一种示例性实施例中，所述导电层结构包括漏源金属层且所述辅助接地线包括位于所述漏源金属层的第一辅助接地线。
在本公开的一种示例性实施例中，所述导电层结构包括透明电极层且所述辅助接地线包括位于所述透明电极层的第二辅助接地线。
在本公开的一些实施例所提供的技术方案中，由于在栅极绝缘层上方配置了包括辅助接地线的导电层结构，因此，通过配置辅助接地线并结合栅极金属层的接地 线，可以构成至少两层接地线的结构，降低了用于引导静电的接地线的电阻，有助于预防ESD。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示意性示出了一种预防ESD的阵列基板的正视图；
图2示意性示出了图1中阵列基板沿虚线AA’的部分的截面图；
图3示意性示出了根据本公开的示例性实施方式的阵列基板的与虚线AA’位置对应的部分的第一实施例的截面图；
图4示意性示出了根据本公开的示例性实施方式的阵列基板的与虚线AA’位置对应的部分的第二实施例的截面图；
图5示意性示出了根据本公开的示例性实施方式的阵列基板的与虚线AA’位置对应的部分的第三实施例的截面图；以及
图6示意性示出了根据本公开的示例性实施方式的阵列基板的制造方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。另外，本公开中所使用的术语“上方”意指某结构“直接”形成于其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
附图中所示的流程图仅是示例性说明，不是必须包括所有的步骤。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。
图1示意性示出了一种预防ESD的阵列基板的正视图。参考图1，阵列基板可以包括显示区域90以及环绕该显示区域90的周边区域。进一步的，该周边区域可以包括基板10以及设于基板10上的接地线20、公共电极线30和GOA(Gate Driver on Array，阵列基板行驱动)单元40，此外，该周边区域还可以包括银胶区域50等其他结构，银胶区域50可以用于与彩膜基板的导电膜建立电连接。其中，通过在周边区域内设置的接地线20，可以将产生的静电移除，以防止静电对阵列基板上各部件的影响。
图2示意性示出了图1中阵列基板沿虚线AA’的部分的截面图，参考图2，在基板10上可以设置有接地线20、公共电极线30、覆盖接地线20和公共电极线30的栅极绝缘层60以及覆盖栅极绝缘层60的钝化层。
然而，对于窄边框设计的显示装置，环绕显示区域的周边区域的宽度通常较小，这就导致接地线的宽度较小，电阻较大，不能及时且有效地传导静电，有可能导致显示异常的问题。
鉴于此，本公开的示例性实施方式提供了一种新的阵列基板。该阵列基板可以包括：
栅极金属层，设于基板上且栅极金属层包括位于周边区域的接地线；
栅极绝缘层，至少覆盖该栅极金属层；以及
导电层结构，设于该栅极绝缘层上方且该导电层结构包括位于周边区域的辅助接地线。
在本公开的示例性实施方式中，通过配置辅助接地线并结合栅极金属层的接地线，可以构成至少两层接地线的结构，降低了用于引导静电的接地线的电阻，有助于预防ESD。
下面将参考图3对本公开的第一实施例进行说明，在本公开的第一实施例中，导电层结构可以是SD金属层(即，源漏金属层)，并且辅助接地线可以是位于SD金属层中的第一辅助接地线。
参考图3，基板10可以是玻璃基板，然而，基板10也可以是石英基板或者用于柔性显示的透明塑料基板。虽然本公开以玻璃基板为例进行说明，但使用其他材质的基板也应当属于本发明的保护范围。
在基板10上可以设置有栅极金属层(未示出)，栅极金属层可以包括位于周边区域的接地线20，接地线20可以是由钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)或铜(Cu)形成的单层接地线，另外，接地线20也可以是由钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)或铜(Cu) 中的多种材料形成的复合叠层。优选地，接地线20可以是由Mo、Al或者包含Mo或Al的合金形成的单层接地线，或者接地线20可以是由Mo、Al、包含Mo或Al的合金中的多种材料形成的复合叠层。
类似地，在基板10上还可以设置有公共电极线30，公共电极线30可以与接地线20平行设置，并且公共电极线30的材料可以与2接地线20的材料相同，在此不再赘述。
在基板10上还可以设置有栅极绝缘层60，栅极绝缘层60可以至少覆盖栅极金属层。栅极绝缘层60可以由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)等材质组成的单层绝缘层，另外，栅极绝缘层60也可以是由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)中的至少两种材料组成的复合叠层。优选地，栅极绝缘层60可以是由SiOx形成的单层绝缘层。
在栅极绝缘层60上可以设置有导电层结构，并且该导电层结构可以包括位于周边区域的辅助接地线。在本实施例中，导电层结构可以是SD金属层，并且辅助接地线可以是位于SD金属层的第一辅助接地线100。SD金属层的材料可以与上述接地线20的材料相同，在此不再赘述。然而，SD金属层的材料也可以与接地线20的材料不同。
此外，在本实例中，第一辅助接地线100可以位于接地线20的正上方。然而，在周边区域内，第一辅助接地线100可以设置在栅极绝缘层60上的任意其他位置，并且第一辅助接地线100的宽度也不限于图3中所示的相对宽度，第一辅助接地线100的宽度可以远宽于接地线20的宽度。
另外，可以将第一辅助接地线100的一端和接地线20的一端与银胶区域(例如图1中所示的银胶区域50)连接。由此，将第一辅助接地线100与接地线20相结合，相当于为接地线20并联了另一接地线，就整体而言，第一辅助接地线100的宽度越宽，电阻越小，有助于预防ESD。
本公开第一实施例的阵列基板还可以包括至少覆盖SD金属层的钝化层70。钝化层70的材料可以与栅极绝缘层60的材料相同，然而，钝化层70的材料可以是铝的氧化物(AlOx)，或者钝化层70可以由亚克力系材料或树脂等有机材料构成，本示例性实施方式中对此不做特殊限定。
在本公开的第一实施例中，通过配置第一辅助接地线100，降低了用于引导静电的接地线的电阻，有助于预防ESD。
下面将参考图4对本公开的第二实施例进行说明，在本公开的第二实施例中，导电层结构可以是透明电极层，该透明电极层可以例如是ITO(Indium Tin Oxide，铟锡氧化物)层。另外，辅助接地线可以是位于透明电极层中的第二辅助接地线。
图4中基板10、接地线20、公共电极线30和栅极绝缘层60可以与本公开的第一实施例中图3所示的基板10、接地线20、公共电极线30和栅极绝缘层60相同， 在此不再赘述。
参考图4，在栅极绝缘层60上可以设置有钝化层70，钝化层70的材料可以与第一实施例中图3所示的钝化层70相同，在此不再赘述。
在本公开的第二实施例中，在钝化层70上可以设置有导电层结构，并且该导电层结构可以包括位于周边区域的辅助接地线。在本实施例中，导电层结构可以是透明电极层，具体的，透明电极层可以例如是ITO层，并且辅助接地线可以是位于透明电极层中的第二辅助接地线200。
第二辅助接地线200的宽度可以大于接地线20的宽度，例如，在图4中，第二辅助接地线200可以覆盖虚线AA’对应的整个区域。然而，第二辅助接地线200的宽度不限于此。
另外，可以将第二辅助接地线200的一端和接地线20的一端与银胶区域(例如图1中所示的银胶区域50)连接。由此，将第二辅助接地线200与接地线20相结合，相当于为接地线20并联了另一接地线，就整体而言，第二辅助接地线200的宽度越宽，电阻越小，有助于预防ESD。
此外，在本公开的第二实施例中，阵列基板还可以包括静电环(未示出)，所述静电环可以与接地线20、第二辅助接地线200中的至少之一电连接。
在本公开的第二实施例中，通过配置第二辅助接地线200，降低了用于引导静电的接地线的电阻，有助于预防ESD，同时，通过配置静电环，进一步增强了ESD的预防能力。
下面将参考图5对本公开的第三实施例进行说明，在本公开的第三实施例中，导电层结构可以包括SD金属层和透明电极层。另外，辅助接地线可以包括分别位于SD金属层的第一辅助接地线和位于透明电极层的第二辅助接地线。
图5中基板10、接地线20、公共电极线30、栅极绝缘层60、第一辅助接地线100和钝化层70可以与本公开的第一实施例中图3所示的基板10、接地线20、公共电极线30、栅极绝缘层60、第一辅助接地线100和钝化层70相同，在此不再赘述。
参考图5，在钝化层70上可以设置有透明电极层，该透明电极层可以包括位于周边区域的第二辅助接地线200。与图4所示的本公开的第二实施例类似，第二辅助接地线200的宽度可以大于接地线20的宽度。
此外，可以将接地线20的一端、第一辅助接地线100的一端和第二辅助接地线200的一端与银胶区域(例如图1中所示的银胶区域50)连接。由此，将接地线20、第一辅助接地线100与第二辅助接地线200相结合，相当于接地线20、第一辅助接地线100和第二辅助接地线200构成了一引导静电的三层结构，就该结构整体而言，大大减小了传导电阻，能够更加有效地预防ESD。
此外，在本公开的第三实施例中，阵列基板还可以包括静电环(未示出)，所述 静电环可以与接地线20、第一辅助接地线100、第二辅助接地线200中的至少之一电连接。
在本公开的第三实施例中，通过配置第一辅助接地线100和第二辅助接地线200，大大降低了用于引导静电的接地线的电阻，有助于预防ESD，同时，通过配置静电环，进一步增强了ESD的预防能力。
进一步的，示例性实施方式还提供了一种阵列基板的制造方法，具体的，参考图6，阵列基板的制造方法可以包括：
S10.在基板上形成栅极金属层，所述栅极金属层包括位于所述周边区域的接地线；
S20.形成至少覆盖所述栅极金属层的栅极绝缘层；以及
S30.在所述栅极绝缘层上方形成导电层结构，所述导电层结构包括位于所述周边区域的辅助接地线。
根据本公开的示例性实施例，所述导电层结构包括漏源金属层且所述辅助接地线包括位于所述漏源金属层的第一辅助接地线。
根据本公开的示例性实施例，所述导电层结构包括透明电极层且所述辅助接地线包括位于所述透明电极层中的第二辅助接地线。
具体的，在本公开的示例性实施方式中，可以采用溅射沉积的方式在基板上形成栅极金属层，并可以通过构图工艺形成接地线。另外，可以采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)的方式形成至少覆盖栅极金属层的栅极绝缘层。此外，可以采用溅射沉积的方式在栅极绝缘层上方形成导电层结构，并可以通过构图工艺形成辅助接地线。然而，本领域技术人员容易联想到还可以采用其他工艺过程来对本公开的阵列基板进行制造，例如，形成栅极金属层的方法还可以包括热蒸发，形成导电层结构的方法还可以包括PECVD，等等。
应当注意，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
进一步的，本示例实施方式中还提供了一种显示面板，该显示面板包括上面描述的阵列基板。
进一步的，本示例性实施方式还提供了一种显示装置，该显示装置可以包括上面描述的显示面板。该显示装置具体可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等具有任何显示功能的产品或者部件。
本公开所提供的阵列基板、显示面板和显示装置可以更加有效地预防ESD。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其 它实施方式。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (14)

  1. 一种阵列基板，包括显示区域和环绕所述显示区域的周边区域，其中，所述阵列基板包括：
    基板；
    栅极金属层，设于所述基板上且所述栅极金属层包括位于所述周边区域的接地线；
    栅极绝缘层，至少覆盖所述栅极金属层；以及
    导电层结构，设于所述栅极绝缘层上方且所述导电层结构包括位于所述周边区域的辅助接地线；其中，所述辅助接地线与所述接地线连接。
  2. 根据权利要求1所述的阵列基板，其中，所述导电层结构包括源漏金属层且所述辅助接地线包括位于所述源漏金属层中的第一辅助接地线。(该从属权利要求对应图3所示的实施例)
  3. 根据权利要求2所述的阵列基板，其中，所述第一辅助接地线位于所述接地线的上方。
  4. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    钝化层，至少覆盖所述源漏金属层。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括设置在所述栅绝缘层上的钝化层，所述导电结构位于所述钝化层上，所述导电层结构包括透明电极层且所述辅助接地线包括位于所述透明电极层中的第二辅助接地线。(该从属权利要求对应图4所示的实施例)
  6. 根据权利要求5所述的阵列基板，其中，所述第二辅助接地线的宽度大于所述接地线的宽度。
  7. 根据权利要求4所述的阵列基板，其中，所述导电层结构还包括位于所述钝化层上的透明电极层且所述辅助接地线包括位于所述透明电极层中的第二辅助接地线(该从属权利要求对应图5所示的实施例)。
  8. 根据权利要求7所述的阵列基板，其中，所述第二辅助接地线的宽度大于所述接地线的宽度。
  9. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括：
    静电环，所述静电环与所述接地线、所述第一辅助接地线以及所述第二辅助接地线中的至少之一电连接。
  10. 一种显示面板，其中，所述显示面板包括权利要求1至9中任一项所述的阵列基板。
  11. 一种显示装置，其中，所述显示装置包括权利要求10所述的显示面板。
  12. 一种阵列基板制造方法，所述阵列基板包括显示区域和环绕所述显示区域的周边区域，其中，所述阵列基板制造方法包括：
    在基板上形成栅极金属层，所述栅极金属层包括位于所述周边区域中的接地线；
    形成至少覆盖所述栅极金属层的栅极绝缘层；以及
    在所述栅极绝缘层上方形成导电层结构，所述导电层结构包括位于所述周边区域中的辅助接地线；其中，所述辅助接地线与所述接地线连接。
  13. 根据权利要求12所述的阵列基板制造方法，其中，所述导电层结构包括漏源金属层且所述辅助接地线包括位于所述漏源金属层中的第一辅助接地线。
  14. 根据权利要求12或13所述的阵列基板制造方法，其中，所述导电层结构包括透明电极层且所述辅助接地线包括位于所述透明电极层中的第二辅助接地线。
PCT/CN2017/106860 2017-04-14 2017-10-19 阵列基板及其制造方法、显示面板和显示装置 Ceased WO2018188299A1 (zh)

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