WO2018188083A1 - 内存刷新技术及计算机系统 - Google Patents

内存刷新技术及计算机系统 Download PDF

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Publication number
WO2018188083A1
WO2018188083A1 PCT/CN2017/080637 CN2017080637W WO2018188083A1 WO 2018188083 A1 WO2018188083 A1 WO 2018188083A1 CN 2017080637 W CN2017080637 W CN 2017080637W WO 2018188083 A1 WO2018188083 A1 WO 2018188083A1
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Prior art keywords
rank
memory
refresh
access request
threshold
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PCT/CN2017/080637
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English (en)
French (fr)
Inventor
胡杏
梁传增
肖世海
王侃文
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2017/080637 priority Critical patent/WO2018188083A1/zh
Priority to SG11201908904T priority patent/SG11201908904TA/en
Priority to EP17905627.0A priority patent/EP3605541A4/en
Priority to CN201780089583.1A priority patent/CN110520929B/zh
Priority to JP2019553059A priority patent/JP6780897B2/ja
Publication of WO2018188083A1 publication Critical patent/WO2018188083A1/zh
Priority to US16/600,034 priority patent/US11074958B2/en
Priority to US17/370,755 priority patent/US11705180B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a memory refresh technology and a computer system.
  • the traditional system main memory usually consists of a dynamic random access memory (DRAM).
  • the DRAM has a simple structure and a fast reading speed.
  • the most basic memory cell of a DRAM is a DRAM cell, and each DRAM cell includes a transistor and a capacitor.
  • the DRAM cell uses the amount of capacitance stored to represent 0 and 1. In this way, a DRAM cell can store one bit. Due to the leakage of the capacitor, if the charge in the capacitor is insufficient, the stored data will be wrong. Therefore, in practical applications, the capacitor needs to be periodically charged to keep the information stored in the capacitor from being lost. This action of charging the internal capacitance of the DRAM is called refreshing.
  • the DRAM cells in the DRAM are arranged in a matrix. This matrix is called a DRAM bank, and any bit in the DRAM bank can be located by the corresponding row and column decoder.
  • Multiple DRAM banks can form a DRAM chip, multiple DRAM chips can form a DRAM rank, and multiple DRAM ranks can be integrated into one Dual In-Line-Memory-Modules (DIMM).
  • the refresh of the DRAM cell is performed by the sense amplifier (Sense Amp).
  • the rows in one or more banks can be refreshed according to a refresh command. In practical applications, refreshing is generally performed in units of rank. Specifically, in the retention time, the rows of all the banks in the rank need to be refreshed at least once, wherein the retention time refers to the time that the data in the DRAM cell can keep the data from being lost without the refresh operation. .
  • a method of selecting a refresh mode based on historical execution information is provided in the prior art. The method performs a refresh test every M time windows. In the test process, the refresh test is performed in 1X mode and 4X mode in successive N time windows respectively, the bus utilization in the two mode refreshes is compared, and the bus utilization is selected. The high refresh mode is used as the refresh mode for the next M time windows.
  • a memory refreshing technology and computer system provided in the present application can reduce system refreshing loss and improve the performance of the computer system during the refreshing process.
  • the present application provides a memory refresh method.
  • the memory refresh method is applied to a computer system including a memory controller and a dynamic random access memory DRAM, the DRAM including a plurality of ranks.
  • the memory controller receives a memory access request.
  • the memory controller refreshes the first rank of the plurality of ranks according to a time interval of T/N.
  • T is used to indicate a standard average refresh interval
  • N is an integer greater than 1.
  • the refresh mode in order to improve the system performance in the memory refresh process, the refresh mode may be dynamically adjusted according to the distribution of the target rank in the memory access request and the proportion of the read request or the write request in the memory access request. Therefore, by adjusting the refresh frequency to compensate for the performance overhead caused by the tFAW limitation of the system, the utilization of the system bus is improved, and the performance of the system during the refresh process can be improved.
  • the memory refresh method provided by the embodiment of the present invention can determine the refresh mode according to the feature of the memory access request in the current refresh process, so that the determined refresh mode is strongly correlated with the refresh process, thereby being effective. Reduce refresh overhead and improve system performance.
  • the method further includes: when the number of target ranks of the memory access request received in the second time period is not less than a set first threshold, or The memory controller refreshes the first rank according to the time interval of the T when the ratio of the read request or the write request is not greater than the set second threshold.
  • the method further includes: receiving, by the memory controller, the memory controller during the performing the first refresh request Accessing the first access request of the first rank.
  • the memory controller caches the first memory access request in a set cache queue, where the memory controller includes at least a cache queue and a scheduling queue, where the cache queue is used to cache a refresh operation being performed.
  • the method further includes: the memory controller receiving a second access request for accessing a second rank in the DRAM .
  • the memory controller caches the second memory access request in the scheduling queue.
  • the memory controller is configured to perform the time interval of T/N Refreshing the first rank of the plurality of ranks includes: when the number of memory access requests received in the first time period is greater than a third threshold, and accessing the memory access request of the first rank in the received memory access request When less than the fourth threshold, the memory controller refreshes the first rank according to a time interval of T/N. The access request for accessing the first rank is greater than 0 during the first time period.
  • the memory controller is configured to perform the time interval of T/N Performing refreshing of the first rank of the plurality of ranks includes: accessing the memory access request of the first rank in the received memory access request in the first time period is not less than a fourth threshold, and the first rank When the number of delayed refreshes is greater than the set fifth threshold, the memory controller refreshes the first rank of the plurality of ranks according to a time interval of T/N.
  • the fifth threshold is smaller than the set warning value, and the warning value is used to indicate that a refresh operation needs to be performed on the first rank immediately.
  • the multiple ranks are performed at a time interval of T/N
  • the refreshing of the first rank in the middle includes: when the number of the fetch requests received in the first time period is not greater than the set third threshold, the number of the fetch requests of the first rank is greater than 0, and the first When the number of delayed refreshes of the rank is greater than the set fifth threshold, the memory controller refreshes the first rank of the plurality of ranks at a time interval of T/N.
  • the fifth threshold is smaller than the set warning value, and the warning value is used to indicate that a refresh operation needs to be performed on the first rank immediately.
  • the application provides a computer system.
  • the computer system includes a memory controller and a dynamic random access memory DRAM coupled to the memory controller, the DRAM including a plurality of ranks.
  • the memory controller is operative to implement the method described in the first aspect above and any one of the possible implementations of the first aspect.
  • the present application provides a memory controller.
  • the memory controller includes a communication interface and a refresh circuit.
  • the communication interface is configured to receive a memory access request sent by a processor in a computer system.
  • the refresh circuit is configured to: the number of target ranks of the memory access request received in the first time period is less than the set first threshold, and the ratio of the read request or the write request in the memory access request is greater than the set number
  • the threshold is two
  • the first rank of the plurality of ranks is refreshed according to the time interval of T/N.
  • the T is used to indicate a standard average refresh interval, and N is an integer greater than 1.
  • the refreshing circuit is further configured to: when the number of target ranks of the memory access request received in the second time period is not less than the set first threshold, or When the ratio of the read request or the write request is not greater than the set second threshold, the first rank is refreshed according to the time interval of the T.
  • the communication interface is further configured to receive an access point during the execution of the first refresh request.
  • the memory controller also includes a cache.
  • the cache is configured to cache the first memory access request in a set cache queue.
  • the cache includes at least Cache queues and scheduling queues.
  • the cache queue is used to cache a memory access request of a rank that is being subjected to a refresh operation, and the scheduling queue is used to cache a memory access request to be sent to a rank that is not performing a refresh operation.
  • the communications interface is further configured to receive a second access request for accessing a second rank in the DRAM.
  • the cache is further configured to cache the second memory access request in the scheduling queue when the second rank does not perform a refresh operation.
  • the refreshing circuit is specifically configured to: when the first time period When the number of the memory access requests received is greater than the third threshold, and the access request for accessing the first rank in the received memory access request is less than the fourth threshold, the first time is compared according to the time interval of T/N. The rank is refreshed, wherein during the first time period, the access request for accessing the first rank is greater than zero.
  • the refreshing circuit is specifically configured to: when the first time period The access request for accessing the first rank in the received fetch request is not less than a fourth threshold, and when the number of delayed refreshes of the first rank is greater than a set fifth threshold, according to a time interval of T/N Refreshing the first rank of the plurality of ranks.
  • the fifth threshold is smaller than the set warning value, and the warning value is used to indicate that a refresh operation needs to be performed on the first rank immediately.
  • the refresh circuit is specifically configured to:
  • the threshold is five, the first rank of the plurality of ranks is refreshed according to the time interval of T/N.
  • the fifth threshold is smaller than the set warning value, and the warning value is used to indicate that a refresh operation needs to be performed on the first rank immediately.
  • the present application provides a memory refresh device for refreshing a dynamic random access memory DRAM in a computer system, the DRAM including a plurality of ranks.
  • the memory refresh device includes functional modules for implementing the methods of the first aspect and any one of the possible implementations of the first aspect.
  • the present application also provides a computer program product, comprising program code, the program code comprising instructions executed by a computer to implement the first aspect and any one of the first aspects The method described in the implementation.
  • the present application further provides a computer readable storage medium for storing program code, the program code comprising instructions executed by a computer to implement the foregoing first aspect and The method described in any one of the possible implementations of the first aspect.
  • FIG. 1 is a schematic structural diagram of a computer system according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a memory controller according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a memory refreshing method according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of still another method for updating a memory according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a memory refresh apparatus according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a computer system according to an embodiment of the present invention.
  • computer system 100 can include at least processor 102, memory controller 106, and memory 108.
  • memory controller 106 can be integrated into processor 102.
  • the computer system 100 may further include a communication interface and other devices such as a disk that is externally stored, and is not limited herein.
  • the processor 102 is the computing core and control unit of the computer system 100.
  • a plurality of processor cores 104 may be included in the processor 102.
  • Processor 102 can be a very large scale integrated circuit.
  • An operating system and other software programs are installed in the processor 102 such that the processor 102 can implement access to the memory 108, cache, and disk.
  • the core 104 in the processor 102 may be, for example, a central processing unit (CPU), or may be another application specific integrated circuit (ASIC).
  • a memory controller 106 is a bus circuit controller that internally controls the memory 108 of the computer system 100 and that manages and schedules data transfers from the memory 108 to the Core 104. Data can be exchanged between the memory 108 and the Core 104 via the memory controller 106.
  • the memory controller 106 can be a separate chip and is coupled to the Core 104 via a system bus.
  • the memory controller 106 can also be integrated into the processor 102 (as shown in Figure 1) or can be built into the Northbridge.
  • the specific location of the memory controller 20 is not limited in the embodiment of the present invention. In a practical application, the memory controller 106 can control the logic necessary to write data to or read data from the memory 108.
  • Memory 108 is the main memory of computer system 100.
  • the memory 108 is connected to the memory 108 via a double data rate (DDR) bus.
  • the memory 108 is typically used to store various running software, input and output data, and information exchanged with external memory in the operating system.
  • the memory 108 needs to have the advantage of fast access speed.
  • a dynamic random access memory (DRAM) is generally used as the memory 108.
  • the processor 102 can access the memory 108 at a high speed through the memory controller 106 to perform a read operation and a write operation on any one of the memory units 1080.
  • the description is made by taking the memory 108 as a DRAM as an example. Therefore, the memory 108 may also be referred to as the DRAM 108.
  • the data is stored in a memory unit (which may also be referred to as a DRAM cell) of the DRAM 108.
  • the memory unit refers to a minimum memory cell for storing data. Usually, one memory unit can store 1 bit of data. Of course, some storage units can also implement multi-value storage.
  • DRAM uses the amount of capacitance stored to represent data 0 and 1. Due to the leakage of the capacitor, if the charge in the capacitor is insufficient, the stored data will be wrong.
  • the memory controller 106 will flush the data in the DRAM 108 to prevent the DRAM 108 from losing data. Also, the DRAM 108 is volatile, and when the computer system 100 is powered off, the information in the DRAM 108 will no longer be saved.
  • DRAM cells in the DRAM 108 are arranged in a matrix. This matrix is called a DRAM bank.
  • the memory controller 106 can locate any bit in the DRAM bank through the corresponding row and column decoder.
  • Multiple DRAM banks can form a DRAM chip (also known as a memory chip), and multiple DRAM chips can form a DRAM rank.
  • Multiple DRAM ranks can be integrated into a single In-Line-Memory-Modules (DIMM).
  • DIMM In-Line-Memory-Modules
  • DRAM 108 can include a plurality of channels 110. At least one rank may be included in each channel 110, and at least one bank may be included in each rank.
  • Each bank includes a plurality of storage units for storing data.
  • rank refers to a memory chip that is connected to the same chip select signal.
  • the memory controller 106 can write to the chips in the same rank, while the chips of the same rank also share the same control signals.
  • the memory controller 106 can access data in memory cells within each of the DRAMs 108 via a memory bus.
  • the refresh period of the DRAM chip is related to the retention time of each memory cell in the DRAM chip.
  • the standard refresh cycles of current common DRAM chips are fixed. Typically, the standard refresh period is 64ms.
  • the memory controller checks whether the rank needs to be refreshed every tREFI time, and each refresh requires a tRFC segment time. Where tREFI refers to the average refresh interval of the memory. In another way, tREFI is used to indicate the average time interval for the memory controller to send a refresh command. tREFI can be determined based on the refresh cycle and the number of refresh commands to be sent during the refresh cycle.
  • tRFC refers to the row refresh cycle time.
  • tRFC is used to indicate the time required to execute a refresh command in the DRAM rank.
  • the longer tREFI the larger the tRFC; the shorter tREFI, the smaller the tRFC. Since the refreshed rank cannot respond to the request for the rank during the tRFC period during the refresh process. Therefore, you can reduce the impact of refresh on system performance by adjusting the refresh rate.
  • refresh modes have different refresh frequencies.
  • Three refresh modes are specified in the double data rate (DDR) protocol: 1X mode, 2X mode, and 4X mode.
  • the 1X mode the memory chip performs a refresh operation at a time interval of tREFI(base) specified by the DDR protocol, and the time for one refresh request is tRFC1.
  • 2X mode inside The memory chip performs a refresh operation at intervals of tREFI(base)/2, and the time for one refresh request is tRFC2.
  • 4X mode the memory chip performs a refresh operation at intervals of tREFI(base)/4, and the time for one refresh request is tRFC3.
  • tREFI(base) is used to indicate the average refresh time interval of the standard defined by the DDR protocol that the computer system complies with.
  • tREFI(base) is used to indicate the tREFI of the DRAM chip surface temperature in the normal temperature range (0°C-85°C) in 1x mode.
  • the sizes of tREFI and tRFC can be set according to actual conditions. For example, for a DRAM particle with a capacity of 8 Gb, tREFI can be 7.8 us in a 1X configuration and 350 ns in tRFC. In the 4X configuration, tREFI can be 1.95us and tRFC can be 160ns.
  • the dynamic refresh mode adjustment is supported in the DDR4 protocol. According to the DDR4 protocol, during the memory refresh process, the memory refresh mode can be converted between 1X mode, 2X mode, and 4X mode.
  • the memory controller checks whether the rank needs to be refreshed every tREFI time. If the rank is in an idle state, the rank is refreshed. If the rank is not in an idle state, the memory controller may postpone the refresh of the rank. When the delay time exceeds the threshold, the memory controller forces the rank to be refreshed. However, in the case of a large memory flow, the rank is in an idle state, and it is possible that the rank cannot be in an idle state. If you wait until the rank is idle and then refresh the rank, you will need to delay the refresh.
  • the refresh operations for each rank in memory 108 are independent.
  • the refreshing of the DRAM in addition to the refreshing process, the refreshed rank cannot respond to the request, which may cause the refreshing overhead of the system.
  • the scheduling queue is blocked due to the request of the refreshed rank, resulting in other The rank request cannot enter the dispatch queue in time and is sent to other ranks, which is also the reason that affects the overall performance of the system.
  • the embodiment of the invention provides a memory refreshing method, which can improve the memory scheduling strategy and improve the bus utilization rate of the system by dynamically adjusting the refresh frequency. Moreover, it is also possible to avoid that other rank requests cannot be executed because the refresh operation blocks the scheduling queue. Thereby, the refresh overhead can be reduced and the system performance during the refresh process can be improved.
  • the memory refreshing scheme in the computer system provided by the embodiment of the present invention will be described in detail below with reference to FIG.
  • FIG. 2 is a schematic structural diagram of a memory controller 106 according to an embodiment of the present invention.
  • the memory 108 may include a plurality of ranks such as rank0, rank1, and rank2.
  • the memory controller 106 can include a communication interface 1061, a statistics module 1062, a refresh control circuit 1064, a cache queue 1066, a dispatch queue 1068, and a scheduler 1069.
  • the communication interface 1061 in the memory controller 106 may include a front end interface connected to the processor 102 in the computer, and may also include a back end interface connected to the memory 108.
  • the memory controller 106 can receive a memory access request sent by a processor (eg, core 104 in FIG. 1) in the computer system through the communication interface 1061.
  • the memory controller 106 can store data to or read data from the memory 108 via the communication interface 1061.
  • the statistics module 1062 can include statistical functions in two aspects. First, the statistics module 1062 can be used to count the distribution of the target rank in the memory access request received by the memory controller 106 and the type of operation of the memory access request. Wherein, the target rank is the rank to be accessed by the memory access request. The type of operation of the fetch request may include a read operation, a write operation, and the like. Specifically, the statistics module 1062 can count the target rank of each memory access request, and obtain the operation type in each memory access request. Second, the statistics module 1062 can also count the number of memory access requests received by the memory controller 106. Specifically, the statistics module 1062 can count the number of memory access requests to be accessed for each rank and the total number of memory access requests received by the memory controller 106.
  • the statistics module 1062 can perform statistics based on the cache queue 1066 and the memory access requests cached in the dispatch queue 1068. In practical applications, the statistics module 1062 can be implemented using a counter. In another form, the statistics module 1062 can include one or more counters.
  • the memory access request refers to a request for the processor to access the memory.
  • the fetch request may include a read request and a write request.
  • the processor can read data from or write data to memory based on a memory access request.
  • the refresh circuit 1064 is configured to determine whether to generate a refresh request according to the statistical result of the statistics module 1062 every tREFI, and put the generated refresh request into the scheduling queue. For example, when the number of requests for a certain rank's memory access request counted by the statistics module 1062 is less than the set threshold, the refresh circuit 1064 may generate a refresh request for the rank and place the refresh request into the dispatch queue 108. It can be understood that, in an actual application, the refresh request generated by the refresh circuit 1064 may also be directly sent to the scheduler 1069, for the scheduler 1069 to send the generated refresh request to the memory 108, so that the memory 108 responds according to the generated refresh request.
  • the RANK performs a refresh operation.
  • tREFI is used to indicate the average refresh interval.
  • the refresh circuit 1064 can also generate a refresh request at a time interval less than tREFI.
  • the refresh circuit 1064 can generate a refresh request at a time interval less than tREFI.
  • tREFI also varies with the refresh mode.
  • the cache queue 1066 is configured to send a memory access request to the rank during a certain rank refresh operation. In another way, the cache queue 1066 is used to cache the newly received fetch request for the rank of the refresh operation being performed. For example, take rank0 in memory 108 as an example. If the memory controller 106 receives a read request from the core 104 for rank0 during the refresh operation on rank0, the read request may be cached in the cache queue 1066 without sending the read request cache to the dispatch queue. 1068. In actual applications, the memory access request in the cache queue 1066 can also be set. Set the priority of the schedule. For example, a partial memory access request can be set to a priority scheduling or a normal scheduling.
  • the dispatch queue 1068 is used to cache the memory access request to be sent to the rank.
  • the dispatch queue 1068 can be used to cache an operation request such as a memory access request sent by the Core 104 and a refresh request sent by the refresh circuit 1064.
  • the scheduling queue 1068 is configured to cache a memory access request to be sent to a rank that is not performing a refresh operation.
  • the scheduler 1069 is configured to send an operation request (including at least a memory access request and a refresh request) in the scheduling queue 1068 to the memory 108, thereby enabling operations such as accessing or refreshing the memory 108.
  • the cache queue 1066 is a pre-cache of the dispatch queue 1068.
  • the cache queue 1066 can be used to cache the memory access request to be entered into the dispatch queue 1068.
  • the embodiment of the present invention takes the two-level cache of the cache queue 1066 and the scheduling queue 1068 as an example. In an actual application, more levels of cache may be set as needed. For example, a multi-level cache queue 1066 can be set up prior to scheduling queue 1068.
  • the refresh mode may include at least a first refresh mode and a second refresh mode.
  • the memory controller refreshes at a time interval of tREFI(base)/N in the first refresh mode.
  • the second refresh mode the memory controller refreshes at a time interval of tREFI(base).
  • the first refresh type may be a 4X mode and the second refresh type may include a 1X mode.
  • tREFI(base) is used to indicate the average refresh time interval of the standard defined by the DDR protocol, and N is an integer greater than 1.
  • tREFI(base) is used to indicate the tREFI of the DRAM chip surface temperature in the normal temperature range (0°C-85°C) in 1x mode.
  • tREFI(base) may also be represented as T.
  • the refresh rate is more important than reducing the refresh latency to improve system performance. Therefore, under normal circumstances, the performance of the system with 4X mode refresh will be lower than that of the system with 1X mode refresh.
  • the bandwidth utilization of the memory 108 is relatively high.
  • the inventor has found that since the DDR protocol specifies a Four Active Window (tFAW), when a plurality of access requests are to be accessed, the target rank is relatively small, and another expression is used.
  • tFAW Four Active Window
  • tFAW means that within the time window of tFAW, the same rank is allowed to send up to 4 line activation commands. For example, if there are two ranks in the memory 108, when the proportion of read requests or the proportion of write requests is relatively high, if the memory access request centrally accesses one of the ranks, in the case of another rank refresh, the refresh is performed. The longer the time, the longer the duration of a single rank visit, and the more the overall performance of the system drops.
  • the inventors have found that compared with the 1X mode, the single refresh time tRFC3 is shorter due to the 4X mode refresh, and the system is less affected by the tFAW limit during the single refresh process. The overall performance of the system is reduced less. Therefore, in the embodiment of the present invention, in order to improve the overall performance of the system and reduce the limitation of the tFAW to the system, the memory provided by the embodiment of the present invention The refresh method dynamically adjusts the refresh mode to reduce system refresh overhead and improve system performance.
  • FIG. 3 is a flowchart of a memory refreshing method according to an embodiment of the present invention.
  • the memory refresh method shown in FIG. 3 can be performed by the memory controller 106 shown in FIGS. 1 and 2. As shown in FIG. 3, the method can include the following steps.
  • the memory controller 106 receives the memory access request sent by the core 104.
  • the memory access request refers to a request for accessing the memory 108.
  • the memory controller 106 can read data from the memory 108 or write data into the memory 108 in accordance with the memory access request.
  • the type of operation of the fetch request may include a read operation, a write operation, and the like.
  • the memory controller 106 can receive the memory access request sent by the core 104 through the communication interface between the memory controller 106 and the core 104.
  • the memory controller 106 determines whether the number of target ranks of the memory access request received during the first time period is less than the set first threshold.
  • the memory controller checks whether the rank needs to be refreshed every tREFI time, and each refresh requires a tRFC segment time. Where tREFI is used to indicate an average refresh interval; tRFC is used to indicate a refresh cycle time. In another way, tREFI is used to indicate the time interval at which the memory controller sends a refresh command, and tRFC is used to indicate the time required to execute a refresh command in the DRAM rank.
  • the process of checking whether the memory needs to be refreshed by the memory controller 106 is referred to as a refresh polling process.
  • the time of one tREFI is called a time period.
  • the memory controller 106 performs a refresh poll every tREFI time.
  • a refresh polling process will be described as an example.
  • the refresh circuit 1064 in the memory controller 106 can determine the memory in the first time period according to the distribution of the target rank to be accessed by the memory access request 1062. Whether the number of target ranks of the memory access request received by the controller 106 is less than the set first threshold.
  • the target rank refers to the rank to be accessed by the memory access request.
  • the number of target ranks refers to the number of ranks to be accessed by the fetch request.
  • the memory controller 106 can determine whether the number of target ranks is based on the number of target ranks of the memory access requests to be processed cached in the memory controller 106 counted in the statistics module 1062. Less than the set first threshold. In another case, the memory controller 106 can determine whether the number of target ranks of the memory access request received by the memory controller 106 within a set period of time counted by the statistics module 1062 is less than a first threshold.
  • the set period of time may be a period of time not greater than tREFI.
  • the first threshold is greater than 0, and the first threshold is less than the total number of ranks in the memory 108. In practical applications, the first threshold may be determined based on the total number of ranks in the memory 108.
  • the first threshold can be set to half of the total number of all ranks in the DRAM.
  • the method proceeds to step 304.
  • the method proceeds to step 306.
  • the first threshold is used to determine whether the target rank to be accessed by the memory controller received by the memory controller is concentrated.
  • the first threshold may be based on the rank in the memory 108. The total number is determined, for example, when the memory 108 contains 4 ranks, the first threshold may be set to 2.
  • the memory controller 106 determines whether the proportion of the read request or the write request of the received memory access request is greater than a second threshold.
  • a second threshold is used to determine whether the proportion of the read request or the write request in the memory access request is high. Therefore, in practical applications, the ratio of the second threshold may be set higher, for example, when the proportion of the read request is measured as a ratio of the read request to the total number of received memory access requests, the second threshold may be 60%.
  • the proportion of read requests is used to indicate the proportion of read requests in the received memory access request.
  • the proportion of write requests is used to indicate the proportion of write requests in the received fetch request.
  • the proportion of read requests can be expressed as a ratio of the number of read requests to the total number of fetch requests.
  • the proportion of write requests can be expressed as a ratio of the total number of write requests to fetch requests.
  • the proportion of read requests can also be expressed as the ratio of the number of read requests to the number of write requests.
  • the proportion of write requests can also be expressed in terms of the ratio of write requests to read requests. This is not limited as long as it is possible to determine the proportion of the read request or the proportion of the write request.
  • the proportion of the read request in the fetch request is higher than the second threshold, it indicates that the read request is more in the first time period.
  • the proportion of the write request in the memory access request is higher than the second threshold, it indicates that the write request in the first time period is more.
  • the method proceeds to step 306, when the read request has a proportion or write request of the read request.
  • the method proceeds to step 308 when the proportion of the second threshold is not greater than the second threshold.
  • the memory controller 106 In step 306, the memory controller 106 generates a first refresh request according to the first refresh mode.
  • the refreshing circuit 1064 determines, according to the statistical result of the statistical module 1062, the number of target ranks to be accessed by the memory access request is less than the set first threshold, and the proportion of the read request or the write request in the memory access request When the ratio is greater than the set second threshold, the refresh circuit 1064 in the memory controller 106 may determine to refresh the first rank using the first refresh mode.
  • the memory controller is refreshed at a time interval of tREFI(base)/N in the first refresh mode, where tREFI(base) is used to indicate a standard average refresh time interval, and N is an integer greater than one.
  • the first refresh mode may be a 4X mode or a 2X mode.
  • the first rank may be adopted in 4X mode or 2X. Refresh.
  • the memory controller 106 In step 308, the memory controller 106 generates a second refresh request in accordance with the second refresh mode.
  • the refreshing circuit 1064 determines, according to the statistical result of the statistical module 1062, that the number of target ranks to be accessed by the memory access request is not less than the set first threshold, or the proportion of the read request of the received memory access request When the proportion of the write request is not greater than the second threshold, the refresh circuit 1064 in the memory controller 106 may determine to refresh the first rank using the second refresh mode. Specifically, the memory controller 106 can generate a second refresh request according to the second refresh mode.
  • the memory controller is refreshed at intervals of tREFI(base), where tREFI(base) is used to indicate a standard average refresh interval.
  • the second refresh mode may be a 1X mode.
  • the 1X mode pair may be used. The first rank is refreshed.
  • step 310 the memory controller 106 refreshes the first rank in memory according to the first refresh request.
  • the first rank is any rank in memory that is to be refreshed.
  • the memory controller 106 may put the generated first refresh request into the dispatch queue 1068, so in step 310, the scheduler 1069 sends the first refresh request in the dispatch queue 1068 to the memory 108, and the memory 108 can perform a refresh operation on the first rank according to the first refresh request generated by the memory controller 106.
  • step 312 the memory controller 106 refreshes the first rank in memory in accordance with the second refresh request. Specifically, in step 308, after the refresh circuit 1064 in the memory controller 106 generates the second refresh request, the memory controller 106 can place the generated second refresh request into the dispatch queue 1068, so in step 312, the scheduler 1069 sends the second refresh request in the dispatch queue 1068 to the memory 108, and the memory 108 can perform a refresh operation on the first rank according to the second refresh request generated by the memory controller 106.
  • FIG. 3 is only described by taking the first refresh polling process as an example.
  • the refresh mode of the first rank may be dynamically adjusted according to the distribution of the target rank to be accessed in the memory access request and the proportion of the read request or the write request.
  • the memory controller 106 may refresh the first rank using the first refresh mode.
  • the memory controller 106 may refresh the second rank using the second refresh mode.
  • the refresh mode may be dynamically adjusted according to the distribution of the target RANK in the memory access request and the proportion of the read request or the write request in the memory access request, thereby being able to adjust the refresh frequency. It compensates for the performance overhead caused by the tFAW limitation of the system, which in turn improves the performance of the system during the refresh process.
  • the memory refresh method provided by the embodiment of the present invention can determine the refresh mode according to the feature of the memory access request in the current refresh process, so that the determined refresh mode is strongly correlated with the refresh process, thereby being effective. Reduce refresh overhead and improve system performance.
  • the embodiment of the present invention improves the performance of the system during the refresh process from the perspective of adjusting the refresh frequency.
  • the embodiment of the present invention further optimizes the refresh method in the prior art from the perspective of the refresh time point to further improve the overall performance of the system in the memory refresh process.
  • the memory refresh method provided by the embodiment of the present invention will be further described below with reference to FIG.
  • the memory controller 106 determines whether the number of received memory access requests is large. At the third threshold. As previously mentioned, to prevent data loss in memory, the memory controller 106 checks for a need to refresh the rank every tREFI time. Specifically, in a refresh polling process, the memory controller 106 may determine, according to the number of memory access requests cached in the memory controller 106 that are counted in the statistics module 1062, whether the number of memory access requests is greater than a third threshold. . In another case, the memory controller 106 can determine, according to the statistics of the memory module 106, the number of memory access requests received by the memory controller 106 within a set period of time, whether the number of memory access requests is greater than a third threshold.
  • the set period of time may be a period of time not greater than tREFI.
  • the third threshold is an integer greater than 0, and the third threshold may be preset according to the size of the traffic in the actual application. For example, the third threshold can be set to 100.
  • the number of memory access requests received by the memory controller 106 is greater than the third threshold, the number of memory access requests is greater, and the method proceeds to step 404.
  • the method proceeds to step 406.
  • the memory controller 106 determines whether the number of access requests to access the first rank is less than a fourth threshold.
  • the first rank may be any rank in the memory 108.
  • the memory controller 106 may determine whether the number of memory access requests of the first rank calculated according to the statistics module 1062 is less than a fourth threshold.
  • the fourth threshold may be specifically set according to an application scenario, and the fourth threshold is greater than 0.
  • the number of the fetch requests of the first rank may be the number of fetch requests of the first rank received by the memory controller 106 during the time period set in step 402. It may also be the number of memory access requests of the first rank to be processed cached in the memory controller 106.
  • step 406 the memory controller 106 determines if the first rank is in an idle state. Specifically, in step 402, when the memory controller 106 determines that the number of received memory access requests is greater than the third threshold, indicating that the access traffic of the entire memory is large, in which case the memory controller 106 needs It is further determined whether the first rank needs to be refreshed. If the first rank is in an idle state, in another way, if there is no request to access the first rank in the scheduling queue of the memory controller, the method proceeds to step 410. If the first rank is not in the idle state, in another way, the first rank of the memory is requested in the scheduling queue of the memory controller, the method proceeds to step 408.
  • step 408 the memory controller 106 determines whether the number of delayed refreshes of the first rank is greater than a set fifth threshold.
  • the method proceeds to step 410.
  • the memory controller 106 determines that the number of delayed refreshes of the first rank is not greater than the fifth threshold, the method proceeds to step 412.
  • the fifth threshold is not less than 1 and less than the set warning value.
  • the alert value may be determined based on the number of postponing refresh commands that the rank can postpone. For example, in the DDR4 standard, rank can delay up to 8 refresh commands, and in another way, the warning value is 8, and the fifth threshold must be less than 8.
  • the fifth threshold can be set to 6.
  • a delay register (not shown in FIG. 2) may be disposed in the refresh circuit 1064, and the delay register may be used to count the number of delayed refreshes of the first rank.
  • the delay register can also be set independently of the refresh circuit 1064.
  • the delay counter may not be set, and the number of delayed refreshes of the first rank may be counted by software.
  • the manner of how to count the delayed refresh times of the first rank is not limited.
  • the memory controller 106 refreshes the first rank.
  • the refresh circuit 1064 in the memory controller 106 may determine the refresh mode according to the number of memory access requests counted by the statistics module 1062, the distribution of the target rank, and the type of the memory access request. And generating a refresh request according to the determined refresh mode to refresh the first rank according to the generated refresh request.
  • the refresh circuit 1064 generates a corresponding refresh request according to the determined refresh mode (eg, 1X mode or 4X mode).
  • the generated refresh request is placed in the dispatch queue 1068 for dispatcher 1069 to send to the memory 108, such that the memory 108 can perform a refresh operation on the first rank based on the refresh request generated by the memory controller 106.
  • the memory controller 106 may refresh the first rank according to the generated first refresh request. . If the memory controller 106 determines to perform refreshing according to the second refresh mode according to the method shown in FIG. 3 above, in this step, the memory controller 106 may refresh the first rank according to the generated second refresh request.
  • the memory controller 106 determines that a refresh operation needs to be performed on the first rank, if the memory controller 106 is performing the fetch request of the first rank, or The memory accessing request of the first rank may wait for the memory access request currently executed by the first rank and the memory access request of the first rank in the scheduling queue to be processed, and then send a refresh request. So as not to affect system performance.
  • the memory controller 106 defers the refresh operation of the first rank. Specifically, when the memory controller 106 determines in step 408 that the number of delay operations of the first rank is not greater than the fifth threshold, the memory controller delays the refresh operation on the first rank, and The value of the delay counter is incremented by one. In another embodiment, when the memory controller 106 determines in step 406 that the first rank is not in an idle state, that is, the memory access request or the scheduling queue that is currently processing the first rank further includes the first In the case of a rank access request, if the number of delays of the first rank does not reach the fifth threshold, it may be considered that the first rank has a large number of memory access requests.
  • a refresh operation is not performed on the first rank to perform a refresh operation on the first rank in a subsequent polling process.
  • the fifth threshold is smaller than the set warning value.
  • the alert value may be determined based on the number of maximum refresh commands that the first rank can postpone.
  • the warning value is used to indicate that a refresh operation needs to be performed on the first rank immediately. In another embodiment, the warning value is used to instruct the memory controller 106 to perform a forced refresh operation on the first rank.
  • the following operations may be performed on the refresh operation of the first rank.
  • the memory controller 106 may follow the FIG.
  • the refresh mode determined by the memory refresh method performs a refresh operation on the first rank.
  • the memory controller 106 may actively perform a refresh operation on the first rank as long as the number of access requests for accessing the first rank is small. There is no need to wait for the first rank to be in an idle state to perform a refresh operation on the first rank. Because the memory flow of the computer system 100 is large, the first rank is difficult to have an idle state.
  • the number of refreshes in a certain time will increase.
  • the active refresh mode provided by the embodiment of the invention can reduce the impact of the passive refresh caused by the delayed refresh on the performance of the computer system, and improve the flexibility of the memory refresh. Thereby, the performance of the computer system can be improved and the refresh overhead can be reduced. It can be understood that, in the embodiment of the present invention, the number of access requests for accessing the first rank is less than the set fourth threshold, and the first rank is idle.
  • the memory controller 106 may perform a refresh operation on the first rank according to the refresh mode determined by the memory refresh method shown in FIG. 3.
  • the third threshold is a threshold value set in combination with the warning value according to an actual application, which can enable the computer system to delay refreshing within a certain range without affecting performance, thereby improving the flexibility of the memory refresh.
  • the refresh operation on the first rank may be delayed.
  • the refresh operation of the first rank may be suspended.
  • the memory controller 106 may follow the memory refresh method shown in FIG.
  • the determined refresh mode performs a refresh operation on the first rank.
  • Change expression In a manner, when the memory flow of the computer system 100 is small and the first rank is in an idle state, the refresh operation of the first rank has less influence on the performance of the computer system, so the first may be directly Rank performs a refresh operation.
  • the memory controller 106 needs to perform a refresh operation on the first rank actively according to the refresh mode determined by the memory refresh method shown in FIG. 3.
  • the memory of the computer system 100 is small but the first rank is busy, in order to avoid forced refreshing of the first rank, it needs to be in the current polling process.
  • the first rank performs a refresh operation. Therefore, it is possible to prevent the system from increasing the number of passive refreshes due to the delayed refresh times reaching the warning value, and reducing the impact of passive refresh on the performance of the computer system.
  • the memory controller 106 may delay a refresh operation on the first rank.
  • the refresh operation on the first rank may be delayed.
  • the description of the memory refresh method provided by the embodiment of the present invention is described by taking the refresh operation of the first rank in the memory 108 as an example in a refresh refresh polling process.
  • the memory controller may determine whether it is necessary to refresh each rank in the memory 108 according to the method provided above. For example, during the first refresh polling process, the memory controller 106 may determine to refresh the first rank according to the first case described above, and refresh according to the second rank in the memory 108 in the second case. The refresh operation of the third rank in the memory 108 is delayed in accordance with the third case described above.
  • the memory controller 106 may delay the first RANK by delaying the sixth condition described above, and refreshing the second rank according to the fifth case.
  • the memory controller 106 is also unable to respond to the first rank's memory access request during the time period of the tRFC in which the refresh operation is performed on the first rank, in order to avoid the first rank's memory access request blocking scheduling. Queue 1068, while a memory access request causing other ranks (e.g., second rank) cannot enter dispatch queue 1068, affecting system performance.
  • the memory controller 106 may The fetch request is placed in the cache queue 1066.
  • the memory queue 1066 fetches the first rank's memory access request from the cache queue 1066 into the dispatch queue 1068.
  • the memory controller 106 may directly input the newly received access request for the first rank into the scheduling queue 108, and It is no longer necessary to put in the cache queue 1066.
  • the memory controller 106 may receive the received pair.
  • the second rank's fetch request is placed directly into the dispatch queue 1068.
  • the target rank of the memory access request in the scheduling queue may be distributed, so that the memory controller 106 can process different ranks as much as possible during the refresh operation on the first rank.
  • the memory access request can reduce the system overhead of the computer system 100 during the refresh operation and improve the execution efficiency of the computer system 100.
  • the embodiment of the present invention comprehensively considers the situation of the received memory access request and the target rank of the access. Determine if the target rank needs to be refreshed. Therefore, by managing the refresh time of the memory controller, on the basis of being compatible with the existing DDR protocol, the influence of the number of passive forced refresh caused by the delayed refresh on the performance of the computer system is reduced, and the flexibility of the memory refresh is improved. Reduced refresh overhead.
  • different refresh modes may be selected according to the distribution of the target rank and the type distribution of the memory access request to improve the refresh of the memory controller. Efficiency, improve the performance of computer systems.
  • a multi-level cache may be set in the memory controller, for example, The scheduling queue and the cache queue can be set separately.
  • the fetch request of the first rank received during the time period of the tRFC in which the refresh operation of the first rank is performed may be buffered in the buffer queue, thereby being able to prevent reception during the time period of the tRFC
  • the first rank's memory access request blocks the scheduling queue, affecting the processing of the memory controller's memory access request to other ranks during the first rank refresh process. Further improve the processing efficiency of the entire computer system.
  • each step in the embodiment shown in FIG. 4 is not necessarily required to be performed.
  • the memory refresh method is described in combination with the size of the memory access in the entire system.
  • the process may first proceed to step 402 to determine the memory controller 106 receives. Whether the number of fetch requests is greater than a third threshold.
  • the size of the fetching traffic of the entire system may not be distinguished, and the fetching traffic of the rank to be refreshed may be directly processed.
  • step 402 in the embodiment of Figure 4 is not required.
  • the refresh method provided by the embodiment of the present invention can be used in the case where the system has a large amount of memory access or when the system has low memory access. There is no limit here.
  • FIG. 5 is a schematic structural diagram of a memory refresh apparatus according to an embodiment of the present invention.
  • the memory refresh device 500 shown in FIG. 5 is used to refresh the memory 108 shown in FIG. 1.
  • the memory refresh device 500 can include a receiving module 502 and a refresh module 506.
  • the memory 108 includes a plurality of ranks.
  • the receiving module 502 is configured to receive a memory access request. Specifically, the receiving module 502 can receive the memory access request sent by one or more cores 104 in the computer system 100. It can be understood that the receiving module 502 can also be used to receive data returned by the memory 108.
  • the receiving module 502 may specifically include a memory control The communication interface between the controller 106 and the core 104, and the communication interface between the memory controller 102 and the memory 108.
  • the refreshing module 506 is configured to: when the number of target ranks of the memory access request received in the first time period is less than the set first threshold, and the ratio of the read request or the write request in the memory access request is greater than the set At the second threshold, the first rank of the plurality of ranks is refreshed according to a time interval of T/N, wherein the T is used to indicate a standard average refresh time interval, and N is an integer greater than 1.
  • the refreshing module 506 is further configured to: when the number of target ranks of the memory access request received in the second time period is not less than a set first threshold, or in the memory access request When the ratio of the read request or the ratio of the write request is not greater than the set second threshold, the first rank is refreshed according to the time interval of the T.
  • the memory refresh device 500 may further include a statistics module 504.
  • the statistics module 504 is configured to count the number of received memory access requests. In an actual application, the statistics module 404 can also separately count the number of access requests for accessing each rank. It can be understood that, when the memory refresh apparatus 500 includes the statistics module 504, the refresh module 506 can dynamically adjust the refresh mode according to the statistical result of the statistics module 504.
  • the receiving module 502 is further configured to receive a first access request for accessing the first rank in the process of executing the first refresh request.
  • the memory refresh device may further include a cache module 508.
  • the cache module 508 is configured to cache the first memory access request in a set cache queue.
  • the cache module 508 includes at least a cache queue and a scheduling queue. The cache queue is used to cache a memory access request of a rank that is being subjected to a refresh operation, and the scheduling queue is used to cache a memory access request to be sent to a rank that is not performing a refresh operation.
  • the receiving module 502 is further configured to receive a second memory access request for accessing a second rank in the DRAM.
  • the cache module 508 is configured to cache the second memory access request in the scheduling queue when the second rank does not perform a refresh operation.
  • the refreshing module is specifically configured to: when the number of memory access requests received in the first time period is greater than a third threshold, and accessing the When the rank access request is less than the fourth threshold, the first rank is refreshed according to the time interval of T/N, wherein the access request for accessing the first rank is greater than 0 in the first time period.
  • the refreshing module is specifically configured to: when the received fetch request in the first time period, accessing the fetch request of the first rank is not less than a fourth threshold, and When the number of delayed refreshes of the first rank is greater than the set fifth threshold, the first rank of the plurality of ranks is refreshed according to a time interval of T/N.
  • the fifth threshold is smaller than the set warning value, and the warning value is used to indicate that a refresh operation needs to be performed on the first rank immediately.
  • the refreshing module is specifically configured to: when the number of the memory access requests received in the first time period is not greater than the set third threshold, the number of the first rank memory access requests When the number of delayed refreshes of the first rank is greater than the set fifth threshold, the first rank of the plurality of ranks is refreshed according to a time interval of T/N.
  • the fifth threshold is smaller than the set warning value, and the warning value is used to indicate that a refresh operation needs to be performed on the first rank immediately.
  • each module in the memory refresh device 500 shown in FIG. 5 can be located in one or more devices in the memory controller shown in FIG. 2, respectively.
  • some or all of the modules in the embodiment shown in FIG. 5 may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • the device embodiments described above are only schematic.
  • the division of the modules is only a logical function division, and the actual implementation may have another division manner.
  • multiple modules or components may be combined or integrated into another system, or some features may be omitted or not implemented.
  • the connections of the modules discussed in the above embodiments may be electrical, mechanical or other.
  • the modules described as separate components may or may not be physically separate.
  • the components displayed as modules may be physical modules or may not be physical modules.
  • each functional module in each embodiment of the application embodiment may exist independently or may be integrated into one processing module.
  • the functional blocks shown in FIG. 5 can be integrated in the memory controller shown in FIG. 2.
  • the embodiment of the invention further provides a computer program product for data processing, comprising a computer readable storage medium storing program code, the program code comprising instructions for executing the method flow described in any one of the foregoing method embodiments.
  • a person skilled in the art can understand that the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a random access memory (RAM), a solid state disk (SSD), or a nonvolatile.
  • a non-transitory machine readable medium that can store program code, such as a non-volatile memory.

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Abstract

一种内存刷新技术及计算机系统，所述内存刷新技术应用于包括内存控制器（106）以及动态随机存取存储器DRAM的计算机系统中。根据所述内存刷新技术，所述内存控制器（106）接收访存请求。当在第一时间段内接收的访存请求的目标rank的数量小于设置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，所述内存控制器（106）按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述T用于指示标准的平均刷新时间间隔，N为大于1的整数。该内存刷新技术能够提高计算机系统在内存刷新过程中的性能。

Description

内存刷新技术及计算机系统 技术领域
本申请涉及计算机技术领域，尤其涉及一种内存刷新技术及计算机系统。
背景技术
传统的系统主存通常由动态随机存取存储器(Dynamic Random Access Memory,DRAM)组成。DRAM的结构简单并且读取速度快。DRAM的最基本存储单元为DRAM cell，每个DRAM cell包括一个晶体管和一个电容。DRAM cell利用电容存储电量的多寡来代表0和1。根据这种方式，一个DRAM cell可以存储一个比特(bit)。由于电容存在漏电现象，如果电容中的电荷不足，会导致存储的数据出错，因此，实际应用中，需要对电容进行周期性的充电才能保持存储在电容中的信息不丢失。这种给DRAM内部电容充电的动作叫做刷新。
DRAM中的DRAM cell被排列分布成一个矩阵，这个矩阵我们称之为DRAM bank，通过相应的行列解码器可以定位到DRAM bank中的任意一个bit。多个DRAM bank可以组成一个DRAM chip，多个DRAM chip可以组成一个DRAM rank，多个DRAM rank又可以被集成为一个双列直插式存储模块(Dual-Inline-Memory-Modules,DIMM)。DRAM cell的刷新由检测放大器(Sense Amp)按行进行，在刷新过程中，可以根据一个刷新命令刷新一个或者多个bank中的行。实际应用中，一般以rank为单位进行刷新。具体的，在保持时间(retention time)内，该rank内的所有bank的行需要至少刷新一次，其中，保持时间是指DRAM cell中的数据在无刷新操作的情况下能保持数据不丢失的时间。
本领域技术人员可以知道，双倍速率(double data rate,DDR)协议中规定了三种刷新模式：1X模式、2X模式以及4X模式。不同的刷新模式具有不同的刷新频率，而不同的刷新频率使得总线的利用率也不同，因此在刷新过程中，刷新模式的选择也会对系统性能造成影响。现有技术中提供了一种根据历史执行信息来选择刷新模式的方法。该方法每隔M个时间窗口进行一次刷新测试，在测试过程中，分别在连续N个时间窗口采用1X模式和4X模式进行刷新测试，比较两种模式刷新时的总线利用率，并选择总线利用率高的刷新模式作为下一个M个时间窗口使用的刷新模式。这种方法虽然能够动态调整刷新模式，但是，一方面重复测试会浪费系统性能，另一方面，N个时间窗口的测试结果并不与后M个窗口的模式选择有较强的内在联系。从而这种方式也不能有效的降低刷新开销，提高系统性能。
发明内容
本申请中提供的一种内存刷新技术及计算机系统，能够减少系统刷新损耗，在刷新过程中提升计算机系统的性能。
第一方面，本申请提供了一种内存刷新方法。所述内存刷新方法应用于包括内存控制器以及动态随机存取存储器DRAM的计算机系统中，所述DRAM中包含有多个rank。在所述方法中，所述内存控制器接收访存请求。当在第一时间段内接收的访存请求的目标rank的数量小于设置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，所述内存控制器按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述T用于指示标准的平均刷新时间间隔，N为大于1的整数。
在申请提供的内存刷新方法中，为了提高在内存刷新过程中的系统性能，可以根据访存请求中目标rank的分布情况以及访存请求中读请求或写请求的占比情况来动态调整刷新模式，从而能够通过调整刷新频率来弥补系统受tFAW限制造成的性能开销，提高系统总线的利用率，进而能够提高系统在刷新过程中的性能。并且，本发明实施例提供的内存刷新方法与现有技术相比，能够根据当前刷新过程中的访存请求的特征来确定刷新模式，从而确定的刷新模式与刷新过程强相关，从而能够有效的降低刷新开销，提高系统性能。
结合第一方面，在第一种可能的实现方式中，所述方法还包括当在第二时间段内接收的访存请求的目标rank的数量不小于设置的第一阈值，或者，所述访存请求中读请求的比例或写请求的比例不大于设置的第二阈值时，所述内存控制器按照所述T的时间间隔对所述第一rank进行刷新。
结合第一方面或第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述方法还包括在执行所述第一刷新请求的过程中，所述内存控制器接收访问所述第一rank的第一访存请求。所述内存控制器将所述第一访存请求缓存在设置的缓存队列中，其中，所述内存控制器中至少包括缓存队列和调度队列，所述缓存队列用于缓存正在被执行刷新操作的rank的访存请求，所述调度队列用于缓存待发送给未被执行刷新操作的rank的访存请求。根据这种方式，能够防止在第一rank刷新的过程中接收的所述第一rank的访存请求堵塞调度队列，影响内存控制器对其他rank的访存请求的处理。进一步提高整计算机系统的处理效率。
结合第一方面的第二种可能的实现方式，在第三种可能的实现方式中，所述方法还包括，所述内存控制器接收访问所述DRAM中的第二rank的第二访存请求。当所述第二rank没有执行刷新操作时，所述内存控制器将所述第二访存请求缓存在所述调度队列中。
结合第一方面或第一方面的第一种至第三种中任意一种可能的实现方式，在第四种可能的实现方式中，所述内存控制器以T/N的时间间隔对所述多个rank中的第一rank进行刷新包括当所述第一时间段内接收的访存请求的数量大于第三阈值，且所述接收的访存请求中访问所述第一rank的访存请求小于第四阈值时，所述内存控制器按照T/N的时间间隔对所述第一rank进行刷新。其中，在第一时间段内，访问所述第一rank的访存请求大于0。
申请提供所述的内存刷新方法中，为了进一步减少内存刷新过程中 对计算机系统的性能的影响，综合考虑了接收的访存请求的情况以及访问的目标rank的情况来确定是否需要对目标rank进行刷新。根据这种方式，即使第一rank无法处于空闲状态，也能够主动对第一rank进行刷新。从而，在访存流量较大的情况下，即使第一rank无法处于空闲状态，也能够及时得到刷新。降低了因为延迟刷新而产生的被动刷新对计算机系统性能的影响，提高内存刷新的灵活性。从而能够提高系统性能，减少刷新开销。
结合第一方面或第一方面的第一种至第三种中任意一种可能的实现方式，在第五种可能的实现方式中，所述内存控制器以T/N的时间间隔对所述多个rank中的第一rank进行刷新包括：当所述第一时间段内所述接收的访存请求中访问所述第一rank的访存请求不小于第四阈值，并且所述第一rank的延迟刷新次数大于设置的第五阈值时，所述内存控制器按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
结合第一方面或第一方面的第一种至第三种中任意一种可能的实现方式，在第六种可能的实现方式中，所述以T/N的时间间隔对所述多个rank中的第一rank进行刷新包括：当在第一时间段内接收的访存请求的数量不大于设置的第三阈值，所述第一rank的访存请求的数量大于0，且所述第一rank的延迟刷新次数大于设置的第五阈值时，所述内存控制器以T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
第二方面，本申请提供了一种计算机系统。所述计算机系统包括内存控制器以及与所述内存控制器连接的动态随机存取存储器DRAM，所述DRAM中包含有多个rank。所述内存控制器用于实现上述第一方面以及第一方面的任意一种可能的实现方式中描述的方法。
第三方面，本申请提供了一种内存控制器。所述内存控制器包括通信接口以及刷新电路。所述通信接口用于接收计算机系统中的处理器发送的访存请求。所述刷新电路用于在第一时间段内接收的访存请求的目标rank的数量小于设置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述T用于指示标准的平均刷新时间间隔，N为大于1的整数。
结合第三方面，在第一种可能的实现方式中，所述刷新电路还用于当在第二时间段内接收的访存请求的目标rank的数量不小于设置的第一阈值，或者，所述访存请求中读请求的比例或写请求的比例不大于设置的第二阈值时，按照所述T的时间间隔对所述第一rank进行刷新。
结合第三方面以及第三方面的第一种可能的实现方式，在第二种可能的实现方式中，所述通信接口，还用于在执行所述第一刷新请求的过程中，接收访问所述第一rank的第一访存请求。所述内存控制器还包括缓存。所述缓存用于将所述第一访存请求缓存在设置的缓存队列中。其中，所述缓存中至少包括 缓存队列和调度队列。所述缓存队列用于缓存正在被执行刷新操作的rank的访存请求，所述调度队列用于缓存待发送给未被执行刷新操作的rank的访存请求。
结合第三方面的第二种可能的实现方式，在第三种可能的实现方式中，所述通信接口还用于接收访问所述DRAM中的第二rank的第二访存请求。所述缓存还用于当所述第二rank没有执行刷新操作时，将所述第二访存请求缓存在所述调度队列中。
结合第三方面或第三方面的第一种至第三种中任意一种可能的实现方式，在第四种可能的实现方式中，所述刷新电路具体用于：当所述第一时间段内接收的访存请求的数量大于第三阈值，且所述接收的访存请求中访问所述第一rank的访存请求小于第四阈值时，按照T/N的时间间隔对所述第一rank进行刷新，其中，在第一时间段内，访问所述第一rank的访存请求大于0。
结合第三方面或第三方面的第一种至第三种中任意一种可能的实现方式，在第五种可能的实现方式中，所述刷新电路具体用于：当所述第一时间段内所述接收的访存请求中访问所述第一rank的访存请求不小于第四阈值，并且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
结合第三方面或第三方面的第一种至第三种中任意一种可能的实现方式，在第六种可能的实现方式中，所述刷新电路具体用于：
当在第一时间段内接收的访存请求的数量不大于设置的第三阈值，所述第一rank的访存请求的数量大于0，且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
第四方面，本申请提供了一种内存刷新装置，所述内存刷新装置用于对计算机系统中的动态随机存取存储器DRAM进行刷新，所述DRAM中包含有多个rank。所述内存刷新装置包括用于实现上述第一方面以及第一方面的任意一种可能的实现方式中的方法的功能模块。
第五方面，本申请还提供了一种计算机程序产品，包括程序代码，所述程序代码包括的指令被计算机所执行，以实现所述第一方面以及所述第一方面的任意一种可能的实现方式中所述的方法。
第六方面，本申请还提供了一种计算机可读存储介质，所述计算机可读存储介质用于存储程序代码，所述程序代码包括的指令被计算机所执行，以实现前述第一方面以及所述第一方面的任意一种可能的实现方式中所述的方法。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附 图仅仅是本发明的一些实施例。
图1为本发明实施例提供的一种计算机系统架构示意图；
图2为本发明实施例提供的一种内存控制器的结构示意图；
图3为本发明实施例提供的一种内存刷新方法的流程示意图；
图4为本发明实施例提供的又一种内存刷新方法的流程示意图；
图5为本发明实施例提供的一种内存刷新装置的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚地描述。显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。
图1为本发明实施例提供的计算机系统架构示意图。如图1所示，计算机系统100至少可以包括处理器102、内存控制器106以及内存108。通常，内存控制器106可以集成在处理器102中。需要说明的是，本发明实施例提供的计算机系统中，除了图1所示的器件外，计算机系统100还可以包括通信接口以及作为外存的磁盘等其他器件，在此不做限制。
处理器(Processor)102是计算机系统100的运算核心和控制核心(Control Unit)。处理器102中可以包括多个处理器核(core)104。处理器102可以是一块超大规模的集成电路。在处理器102中安装有操作系统和其他软件程序，从而处理器102能够实现对内存108、缓存及磁盘的访问。可以理解的是，在本发明实施例中，处理器102中的Core 104例如可以是中央处理器(Central Processing unit，CPU)，还可以是其他特定集成电路(Application Specific Integrated Circuit，ASIC)。
内存控制器(Memory Controller)106是计算机系统100内部控制内存108并用于管理与规划从内存108到Core 104间的数据传输的总线电路控制器。通过内存控制器106，内存108与Core 104之间可以交换数据。内存控制器106可以是一个单独的芯片,并通过系统总线与Core 104连接。本领域技术人员可以知道，内存控制器106也可以被集成到处理器102中(如图1所示)也可以被内置于北桥中。本发明实施例不对内存控制器20的具体位置进行限定。实际应用中，内存控制器106可以控制必要的逻辑以将数据写入内存108或从内存108中读取数据。
内存108是计算机系统100的主存。内存108通过双倍速率(double data rate,DDR)总线和内存108相连。内存108通常用来存放操作系统中各种正在运行的软件、输入和输出数据以及与外存交换的信息等。为了提高处理器102的访问速度，内存108需要具备访问速度快的优点。在传统的计算机系统架构中，通常采用动态随机存取存储器(Dynamic Random Access Memory,DRAM)作为内存108。处理器102能够通过内存控制器106高速访问内存108，对内存1080中的任意一个存储单元进行读操作和写操作。
在本发明实施例中，以内存108为DRAM为例进行描述，因此，内存108也可以被称为DRAM 108。数据存储于DRAM 108的存储单元(又可以被称为DRAM cell)中，在本发明实施例中，存储单元是指用于存储数据的最小存储单元(cell)。通常，一个存储单元可以存储1位(bit)数据。当然，有的存储单元也可以实现多值存储。如前所述，DRAM是利用电容存储电量的多寡来代表数据0和1。由于电容存在漏电现象，如果电容中的电荷不足，会导致存储的数据出错。因此，每隔一段时间，内存控制器106会刷新DRAM108中的数据，以防止DRAM 108丢失数据。并且，DRAM 108是易失性的，当计算机系统100关闭电源后，DRAM 108中的信息将不再保存。
实际应用中，DRAM 108中的DRAM cell被排列分布成一个矩阵，这个矩阵我们称之为DRAM bank，内存控制器106通过相应的行列解码器可以定位到DRAM bank中的任意一个bit。多个DRAM bank可以组成一个DRAM chip(又可被称为内存芯片)，多个DRAM chip可以组成一个DRAM rank。多个DRAM rank又可以被集成为一个双列直插式存储模块(Dual-Inline-Memory-Modules,DIMM)。例如，如图1所示，DRAM 108可以包括多个通道(channel)110。每个通道110中可以包括至少一个rank，每个rank中可以包括至少一个bank。每个bank都包括多个用于存储数据的存储单元。本领域技术人员可以知道，rank指的是连接到同一个片选(chip select)信号的内存颗粒(chip)。内存控制器106能够对同一个rank中的chip进行写操作，而在同一个rank的chip也共享同样的控制信号。内存控制器106可以通过内存总线分别访问DRAM 108中各个通道内的存储单元中的数据。
本领域技术人员可以知道，DRAM芯片的刷新周期与DRAM芯片中的每个存储单元的保持时间(retention time)有关。目前常见的DRAM芯片的标准刷新周期都是固定的。通常，标准刷新周期为64ms。现有技术的刷新方案中，内存控制器每隔tREFI的时间检查是否需要对rank进行刷新，每次刷新需要消耗tRFC段时间。其中，tREFI是指内存平均刷新时间间隔(average refresh interval)。换一种表达方式，tREFI用于指示内存控制器发送刷新命令的平均时间间隔。tREFI可以根据刷新周期及刷新周期内要发送的刷新命令的数量来确定。例如：tREFI可以为64ms/8192＝7.8us，其中，64ms为刷新周期，8192为刷新周期内发送的刷新命令的数量。tRFC是指行刷新周期时间(row refresh cycle time)。换一种描述方式，tRFC用于指示在DRAM rank中执行一次刷新命令所需的时间。通常，tREFI越长，tRFC越大；tREFI越短，tRFC较小。由于，在刷新过程中的tRFC段时间内，被刷新的rank不能响应对该rank的请求。因此，可以通过调整刷新频率减少刷新对系统性能造成的影响。
并且，本领域技术人员可以知道，不同的刷新模式具有不同的刷新频率。双倍速率(double data rate,DDR)协议中规定了三种刷新模式：1X模式、2X模式以及4X模式。在1X模式下，内存芯片以DDR协议规定的tREFI(base)为时间间隔执行刷新操作，一次刷新请求执行的时间为tRFC1。在2X模式下,内 存芯片以tREFI(base)/2为时间间隔执行刷新操作，一次刷新请求执行的时间为tRFC2。在4X模式下,内存芯片以tREFI(base)/4为时间间隔执行刷新操作，一次刷新请求执行的时间为tRFC3。其中，tRFC1>tRFC2>tFRC3，tREFI(base)用于指示所述计算机系统所遵从的DDR协议定义的标准的平均刷新时间间隔。通常，tREFI(base)用于指示在1x模式下，DRAM芯片表面温度在正常温度范围(0℃-85℃)条件下的tREFI。按照DDR4标准，tREFI和tRFC的大小可以根据实际情况进行设置。例如，对于容量为8Gb的DRAM颗粒,在1X配置下，tREFI可以为7.8us,tRFC可以为350ns。而在4X配置下，tREFI可以为1.95us,tRFC可以为160ns。DDR4协议中支持动态刷新模式的调整。根据DDR4协议，在内存刷新过程中，内存的刷新模式可以在1X模式、2X模式及4X模式之间相互转化。
如前所述，现有技术中，内存控制器每隔tREFI的时间检查是否需要对rank进行刷新。若该rank处于空闲状态，则对该rank进行刷新，若该rank没有处于空闲状态，则内存控制器会推迟对该rank的刷新。当推迟时间超过阈值时，内存控制器会强制对该rank进行刷新。然而，在内存流量较大的情况下，rank处于空闲状态的情况较少，有可能rank无法处于空闲状态。如果一直等到rank空闲后再对该rank进行刷新，则需要不断的推迟的刷新。到最后为避免数据丢失而必须刷新时，不仅需要执行当前时间段内应该进行的刷新，还需要将前面延迟的刷新进行补刷新，从而造成在需要补刷新的时间段内刷新的次数较多。在这种情况下，即使没有达到平均刷新时间间隔tREFI，也需要执行刷新。换一种表达方式，在需要进行补刷新的情况下，会造成被动刷新的次数增多。由于在刷新时访问这个rank的请求无法及时得到响应，因此，在被动刷新次数较多的情况下，访问业务中断的时间变长，可能引起处理器停滞或效率下降。在这种情况下，更加影响系统性能，从而造成较大的刷新开销。
本领域技术人员可以知道，内存108中各个rank的刷新操作是独立的。发明人在研究过程中发现，刷新过程中，由于在不同的刷新模式下刷新频率不同，而不同的刷新频率使得总线的利用率也不同，因此在刷新过程中，刷新模式的选择也会对系统性能造成影响。并且，在对DRAM进行刷新过中，除了在刷新过程中，被刷新的rank不能响应请求会造成系统的刷新开销之外，在刷新过程中，由于被刷新的rank的请求阻塞调度队列，导致其他rank的请求无法及时进入调度队列并被发送到其他rank，也是影响系统整体性能的原因。
为了减少计算机系统的刷新开销，提高计算机系统在刷新过程中的整体性能，本发明实施例提供了一种内存刷新方法，能够改善内存调度策略，通过动态调整刷新频率提高系统的总线利用率。并且，还能够避免因为刷新操作阻塞调度队列而造成其他rank的请求无法被执行。从而能够减少刷新开销，提高刷新过程中的系统性能。下面将结合图1对本发明实施例提供的计算机系统中的内存刷新方案进行详细介绍。
图2为本发明实施例提供的内存控制器106中的结构示意图。为了 描述清楚，图2中也示出了内存控制器106与处理器核104以及内存108的连接示意。其中，内存108中可以包括rank0、rank1以及rank2等多个rank。如图2所示，内存控制器106中可以包括通信接口1061、统计模块1062、刷新控制电路1064、缓存队列1066、调度队列1068以及调度器1069。
在本发明实施例中，内存控制器106中的通信接口1061可以包括与计算机中的处理器102连接的前端接口，也可以包括与内存108连接的后端接口。具体的，内存控制器106可以通过通信接口1061接收计算机系统中的处理器(例如图1中的core104)发送的访存请求。内存控制器106可以通过通信接口1061向内存108中存储数据或者将从内存108中读取数据。
统计模块1062可以包括两个方面的统计功能。第一，统计模块1062可以用于统计内存控制器106接收的访存请求中的目标rank的分布情况以及访存请求的操作类型。其中，目标rank为访存请求待访问的rank。访存请求的操作类型可以包括读操作、写操作等类型。具体的，统计模块1062可以统计各访存请求的目标rank，请获取各访存请中的操作类型。第二，统计模块1062还可以统计内存控制器106接收的访存请求的数量。具体的，统计模块1062可以统计待访问每个rank的访存请求的数量以及内存控制器106接收的访存请求的总数量。统计模块1062可以根据缓存队列1066以及调度队列1068中缓存的访存请求进行统计。实际应用中，统计模块1062可以采用计数器来实现。换一种表达方式，统计模块1062可以包括一个或多个计数器。在本发明实施例中，访存请求是指处理器访问内存的请求。访存请求可以包括读请求及写请求等。换一种表达方式，处理器可以根据访存请求从内存中读取数据或将数据写入内存。
刷新电路1064，用于每隔tREFI的时间根据统计模块1062的统计结果判断是否生成刷新请求，并将生成的刷新请求放入调度队列。例如，当统计模块1062统计的某个rank的访存请求的请求数量小于设置的阈值时，则刷新电路1064可以生成该rank的刷新请求，并将该刷新请求放入调度队列108。可以理解的是，实际应用中，刷新电路1064生成的刷新请求也可以直接发送给调度器1069，以供调度器1069将生成的刷新请求发送给内存108，使得内存108按照生成的刷新请求对相应的RANK执行刷新操作。需要说明的是，tREFI用于指示平均的刷新时间间隔。实际应用中，刷新电路1064也可以以小于tREFI的时间间隔生成刷新请求。例如，在需要进行补刷新时，刷新电路1064可以以小于tREFI的时间间隔生成刷新请求。此外，本领域技术人员可以知道，tREFI也随着刷新模式的不同而不同。
缓存队列1066，用于在某个rank被执行刷新操作过程中，缓存core104发送对该rank的访存请求。换一种表达方式，所述缓存队列1066用于缓存新接收的正在被执行刷新操作的rank的访存请求。例如，以内存108中的rank0为例。若在对rank0执行刷新操作的过程中，内存控制器106接收到core 104对rank0的读请求，则可以将该读请求缓存在缓存队列1066中，而不会将该读请求缓存送入调度队列1068。实际应用中，还可以对缓存队列1066中的访存请求设 置调度的优先级。例如，可以将部分访存请求设置为优先调度或普通调度。
调度队列1068用于缓存待发送给rank的访存请求。例如，调度队列1068可以用于缓存Core 104发送的访存请求以及刷新电路1064发送的刷新请求等操作请求。进一步的，在本发明实施例中，调度队列1068用于缓存待发送给未被执行刷新操作的rank的访存请求。调度器1069用于将调度队列1068中的操作请求(至少包括访存请求和刷新请求)发送给内存108，从而能够实现对内存108的访问或刷新等操作。在本发明实施例中，缓存队列1066为调度队列1068的前置缓存，根据这种方式，缓存队列1066可以用于缓存待进入调度队列1068的访存请求。在本发明实施例中，为了描述方便，本发明实施例以设置缓存队列1066和调度队列1068两级缓存为例，实际应用中，还可以根据需要设置更多级的缓存。例如，在调度队列1068前可以设置多级缓存队列1066。
如前所述双倍速率(double data rate,DDR)协议中规定了三种刷新模式：1X模式、2X模式以及4X模式。在本发明实施例中，刷新模式至少可以包括第一刷新模式和第二刷新模式。其中，在所述第一刷新模式下，所述内存控制器以tREFI(base)/N的时间间隔进行刷新。在所述第二刷新模式下，所述内存控制器按照tREFI(base)的时间间隔进行刷新。例如，第一刷新类型可以为4X模式，第二刷新类型可以包括1X模式。其中，tREFI(base)用于指示DDR协议定义的标准的平均刷新时间间隔，N为大于1的整数。通常，tREFI(base)用于指示在1x模式下，DRAM芯片表面温度在正常温度范围(0℃-85℃)条件下的tREFI。为了描述方便，在本发明实施例中，也可以将tREFI(base)表示为T。
对于内存系统来说，减少刷新频率比减少刷新的延迟对系统性能的提升更重要。因此在通常情况下，采用4X模式刷新时系统的性能会比采用1X模式刷新时的系统的性能更低。并且，当访存请求中的读请求占比或写请求占比较高的情况下，由于读写切换相对较少，内存108的带宽利用率会比较高。然而，在实现本发明的过程中，发明人发现，由于DDR协议规定了四激活时间窗口(Four Active Window，tFAW)，当多个访存请求待访问的目标rank比较少，换一种表达方式，当多个访存请求集中对所述内存108中的少量rank进行访问时，在tFAW的时间窗口内，同一rank能够同时操作的行数会受到限制，因此系统的整体性能反而会下降。其中，tFAW是指在tFAW的时间窗口内，同一rank最多允许发送4个行激活命令。例如，若内存108中有两个rank，当读请求的占比或写请求的占比较高的情况下，若访存请求集中访问其中一个rank，则在另一rank刷新的情况下，刷新的时间越长，单rank访问持续的时间就越长，系统整体性能下降越多。
在实现本发明的过程中，发明人发现，4X模式和1X模式相比，由于采用4X模式刷新时的单次刷新时间tRFC3较短，在单次刷新过程中，系统受tFAW限制的影响较小，系统的整体性能下降较少。因此，在本发明实施例中，为了提高系统的整体性能，减少tFAW对系统的限制，本发明实施例提供的内存 刷新方法能够对刷新方式进行动态调整，以减少系统刷新开销，提升系统性能。
下面将结合图2对本发明实施例提供的内存刷新方法进行详细介绍。图3为本发明实施例提供的内存刷新方法的流程图。图3所示的内存刷新方法可以由图1及图2中所示的内存控制器106来执行。如图3所示，该方法可以包括下述步骤。
在步骤301中，内存控制器106接收core 104发送的访存请求。在本发明实施例中，访存请求是指用于访问内存108的请求。内存控制器106可以根据访存请求从内存108中读取数据，或者将数据写入内存108中。访存请求的操作类型可以包括读操作、写操作等类型。实际应用中，内存控制器106能够通过内存控制器106与core 104之间的通信接口接收core 104发送的访存请求。
在步骤302中,内存控制器106判断在第一时间段内接收的访存请求的目标rank的数量是否小于设置的第一阈值。本领域技术人员可以知道内存控制器每隔tREFI的时间检查是否需要对rank进行刷新，每次刷新需要消耗tRFC段时间。其中，tREFI用于指示平均刷新时间间隔(average refresh interval)；tRFC用于指示行刷新周期时间(Refresh Cycle Time)。换一种表达方式，tREFI用于指示内存控制器发送刷新命令的时间间隔，tRFC用于指示在DRAM rank中执行一次刷新命令所需的时间。本发明实施例中，为了描述方便，将内存控制器106检查是否需要对rank进行刷新的过程称为一个刷新轮询过程。将一个tREFI的时间称为一个时间段。换一种表达方式，内存控制器106每隔tREFI的时间就会执行一次刷新轮询。
在本发明实施例中将以一个刷新轮询过程为例进行描述。在本步骤中，在第一个刷新轮询过程中，内存控制器106中的刷新电路1064可以根据统计模块1062统计的访存请求待访问的目标rank的分布情况来判断第一时间段内内存控制器106接收的访存请求的目标rank的数量是否小于设置的第一阈值。在本发明实施例中，目标rank是指访存请求待访问的rank。目标rank的数量是指访存请求待访问的rank的数量。一种情况下，在一个刷新轮询过程中，内存控制器106可以根据统计模块1062中统计的内存控制器106中缓存的待处理的访存请求的目标rank的数量来判断目标rank的数量是否小于设置的第一阈值。另一种情况下，内存控制器106可以判断统计模块1062统计的在一个设置的时间段内所述内存控制器106接收的访存请求的目标rank的数量是否小于第一阈值。所述设置的时间段可以为不大于tREFI的时间段。其中，第一阈值大于0，且第一阈值小于所述内存108中的rank的总数。实际应用中，第一阈值可以根据内存108中的rank的总数量来确定。例如，第一阈值可以设置为DRAM中所有rank的总数的一半。当访存请求的目标rank的数量小于第一阈值时，该方法进入步骤304。当访存请求的目标rank的数量不小于所述第一阈值时，该方法进入步骤306。
在本步骤中，第一阈值用于确定内存控制器接收的访存请求待访问的目标rank是否集中。在本发明实施例中，第一阈值可以根据内存108中的rank 总数量来确定，例如，当内存108中包含有4个rank时，所述第一阈值可以设置为2。
在步骤304中，内存控制器106判断所述接收的访存请求的中读请求的占比或写请求的占比是否大于第二阈值。如前所述，当访存请求中的读请求占比或写请求占比较高的情况下，由于读写切换相对较少，内存108的带宽利用率会比较高。在本发明实施例中，第二阈值用于判断访存请求中读请求或写请求的比例是否较高。因此，实际应用中，第二阈值的比例可以设置的较高，例如当以读请求与接收的访存请求的总数量的比例来衡量读请求的占比时，第二阈值可以为60％。
在本发明实施例中，读请求的占比用于指示读请求在接收的访存请求中的比例。写请求的占比用于指示写请求在接收的访存请求中的比例。例如，读请求的占比可以采用读请求数量与访存请求的总数量的比例来表示。写请求的占比可以采用写请求与访存请求的总数量的比例来表示。实际应用中，读请求的占比还可以采用读请求的数量与写请求数量的比例来表示。写请求的占比也可以采用写请求与读请求的数量的比例来表示。在此不做限定，只要能够确定出读请求的占比或写请求的占比即可。
可以理解的是，当访存请求中读请求的占比高于所述第二阈值时，说明所述第一时间段内读请求较多。当访存请求中写请求的占比高于所述第二阈值时，说明所述第一时间段内的写请求较多。在本发明实施例中，当访存请求中读请求的占比或写请求的占比大于所述第二阈值时，该方法进入步骤306，当访存请求中读请求的占比或写请求的占比不大于所述第二阈值时，该方法进入步骤308。
在步骤306中，内存控制器106根据第一刷新模式生成第一刷新请求。在本发明实施例中，当刷新电路1064根据统计模块1062统计结果确定访存请求待访问的目标rank的数量小于设置的第一阈值，并且访存请求中读请求的占比或写请求的占比大于设置的第二阈值时，内存控制器106中的刷新电路1064可以确定采用第一刷新模式对所述第一rank进行刷新。其中，在所述第一刷新模式下，所述内存控制器以tREFI(base)/N的时间间隔进行刷新，tREFI(base)用于指示标准的平均刷新时间间隔，N为大于1的整数。例如，所述第一刷新模式可以为4X模式或2X模式。换一种表达方式，当内存控制器106接收的访存请求待访问的目标rank比较集中，且读请求的比例或写请求的比例较高时，可以采用4X模式或2X对所述第一rank进行刷新。
在步骤308中，内存控制器106根据第二刷新模式生成第二刷新请求。在本发明实施例中，当刷新电路1064根据统计模块1062统计结果确定访存请求待访问的目标rank的数量不小于设置的第一阈值，或者当接收的访存请求的中读请求的占比或写请求的占比不大于第二阈值时，内存控制器106中的刷新电路1064可以确定采用第二刷新模式对所述第一rank进行刷新。具体的，内存控制器106可以根据第二刷新模式生成第二刷新请求。在所述第二刷新模式下， 所述内存控制器以tREFI(base)的时间间隔进行刷新，其中，tREFI(base)用于指示标准的平均刷新时间间隔。在本发明实施例中，第二刷新模式可以为1X模式。换一种表达方式，当内存控制器106接收的访存请求待访问的目标rank不集中，且读请求的比例或写请求的比例相当，需要较多的读写切换时，可以采用1X模式对所述第一rank进行刷新。
在步骤310中，内存控制器106按照第一刷新请求对内存中的第一rank进行刷新。其中，所述第一rank为内存中的任意一个待刷新的rank。具体的，在步骤306中，当内存控制器106中刷新电路1064生成第一刷新请求之后，内存控制器106可以将生成的第一刷新请求放入调度队列1068，从而在步骤310中，调度器1069会将调度队列1068中的所述第一刷新请求发送给内存108，内存108可以根据内存控制器106生成的第一刷新请求执行对所述第一rank的刷新操作。
在步骤312中，内存控制器106按照第二刷新请求对内存中的第一rank进行刷新。具体的，在步骤308中，当内存控制器106中刷新电路1064生成第二刷新请求之后，内存控制器106可以将生成的第二刷新请求放入调度队列1068，从而在步骤312中，调度器1069会将调度队列1068中的所述第二刷新请求发送给内存108，内存108可以根据内存控制器106生成的第二刷新请求执行对所述第一rank的刷新操作。
可以理解的是，图3仅仅是以第一刷新轮询过程为例进行描述。实际应用中，在不同的刷新轮询过程中，可以根据访存请求中待访问目标rank的分布情况以及读请求或写请求的占比对第一rank的刷新模式进行动态调整。例如，在第一刷新轮询过程中，内存控制器106可以采用第一刷新模式对第一rank进行刷新。在第二刷新轮询过程中，内存控制器106可以采用第二刷新模式对第二rank进行刷新。
综上所述，考虑到在访存请求待访问的目标rank比较集中，且访存请求中的读请求占比或写请求占比较高的情况下，同一rank能够同时操作的行数会受到tFAW的限制，从而导致系统在刷新过程中的整体性能下降较多。在本发明实施例中，为了提高系统性能，可以根据访存请求中目标RANK的分布情况以及访存请求中读请求或写请求的占比情况来动态调整刷新模式，从而能够通过调整刷新频率来弥补系统受tFAW限制造成的性能开销，进而能够提高系统在刷新过程中的性能。并且，本发明实施例提供的内存刷新方法与现有技术相比，能够根据当前刷新过程中的访存请求的特征来确定刷新模式，从而确定的刷新模式与刷新过程强相关，从而能够有效的降低刷新开销，提高系统性能。
上述实施例是从调整刷新频率的角度来提高系统在刷新过程中的性能。为了进一步的提高系统的刷新性能，本发明实施例还从刷新时间点的角度对现有技术中的刷新方法进行了优化，以进一步提高系统在内存刷新过程中的整体性能。下面将结合图4对本发明实施例提供的内存刷新方法进行进一步的描述。
在步骤402中，内存控制器106判断接收的访存请求的数量是否大 于第三阈值。如前所述，为了防止内存中的数据丢失，内存控制器106会每隔tREFI的时间检查是否需要对rank进行刷新。具体的，在一个刷新轮询过程中，内存控制器106可以根据统计模块1062中统计的内存控制器106中缓存的待处理的访存请求的数量来判断访存请求的数量是否大于第三阈值。另一种情况下，内存控制器106可以根据统计模块1062统计的在一个设置的时间段内所述内存控制器106接收的访存请求的数量判断访存请求的数量是否大于第三阈值。所述设置的时间段可以为不大于tREFI的时间段。其中，第三阈值为大于0的整数，所述第三阈值可以根据实际应用中流量的大小预先设定。例如，第三阈值可以设置为100。当内存控制器106接收的访存请求的数量大于所述第三阈值时，说明访存请求的数量较多，该方法进入步骤404。当内存控制器106接收的访存请求的数量不大于所述第三阈值时，该方法进入步骤406。
在步骤404中，内存控制器106判断访问第一rank的访存请求的数量是否小于第四阈值。其中，第一rank可以为内存108中的任意一个rank。在本发明实施例中，内存控制器106可以根据统计模块1062中统计的第一rank的访存请求的数量是否小于第四阈值。其中，第四阈值可以根据应用场景具体设置，第四阈值大于0。当访问所述第一rank的访存请求的数量小于所述第四阈值时，该方法进入步骤410。当访问所述第一rank的访存请求的数量大于所述第四阈值时，该方法进入步骤408。需要说明的是，所述第一rank的访存请求的数量可以是步骤402中设置的时间段内内存控制器106接收的第一rank的访存请求的数量。也可以是内存控制器106中缓存的待处理的第一rank的访存请求的数量。
在步骤406中，内存控制器106判断第一rank是否处于空闲状态。具体的，当在步骤402中，在内存控制器106确定接收的访存请求的数量大于所述第三阈值时，说明整个内存的访问流量较大，在这种情况下，内存控制器106需要进一步确定是否需要对第一rank进行刷新。如果所述第一rank处于空闲状态，换一种表达方式，如果内存控制器的调度队列中没有访问第一rank的请求，则该方法进入步骤410。如果所述第一rank没有处于空闲状态，换一种表达方式，内存控制器的所述调度队列中还有所述第一rank的访存请求，则该方法进入步骤408。
在步骤408中，内存控制器106判断所述第一rank的延迟刷新次数是否大于设置的第五阈值。当内存控制器106确定所述第一rank的延迟刷新次数大于所述第五阈值时，所述方法进入步骤410。当内存控制器106确定所述第一rank的延迟刷新次数没有大于所述第五阈值时，该方法进入步骤412。在本发明实施例中，第五阈值不小于1且小于设置的预警值。所述预警值可以根据所述rank能够推迟的最大刷新命令(postponing refresh commands)的数量来确定。例如，在DDR4标准中，rank最多能推迟8个刷新命令，换一种表达方式，预警值为8，则所述第五阈值必须小于8。例如，第五阈值可以设置为6。
在本发明实施例中，可以在刷新电路1064中设置延迟寄存器(图2中未图示)，所述延迟寄存器可以用于统计所述第一rank的延迟刷新次数。实际 应用中，延迟寄存器也可以独立于刷新电路1064设置。在另一种情况下，也可以不设置延迟计数器，而通过软件来统计所述第一rank的延迟刷新次数。在本发明实施例中，不对具体如何统计所述第一rank的延迟刷新次数的方式进行限定。
在步骤410中，内存控制器106对所述第一rank进行刷新。具体的，内存控制器106中的刷新电路1064可以根据统计模块1062统计的访存请求的数量、目标rank的分布情况以及访存请求的类型确定刷新模式。并根据确定的刷新模式生成刷新请求，以按照生成的刷新请求对所述第一rank进行刷新。具体的，刷新电路1064会根据确定的刷新模式(例如，1X模式或4X模式)生成相应的刷新请求。并将生成的刷新请求放入调度队列1068以供调度器1069发送给内存108，从而内存108可以根据内存控制器106生成的刷新请求执行对所述第一rank的刷新操作。例如，当内存控制器106按照上述图3所示的方法确定按照第一刷新模式进行刷新时，在本步骤中，内存控制器106可以根据生成的第一刷新请求对所述第一rank进行刷新。若内存控制器106按照上述图3所示的方法确定按照第二刷新模式进行刷新时，在本步骤中，内存控制器106可以根据生成的第二刷新请求对所述第一rank进行刷新。
可以理解的是，当内存控制器106确定需要对所述第一rank执行刷新操作时，若所述内存控制器106正在执行所述第一rank的访存请求，或者所述调度队列中还有所述第一rank的访存请求，则内存控制器106可以等待第一rank当前执行的访存请求以及所述调度队列中的所述第一rank的访存请求均处理完之后再发送刷新请求，以免影响系统性能。
在步骤412中，内存控制器106推迟对所述第一rank的刷新操作。具体的，当在步骤408中，内存控制器106判断所述第一rank的延迟操作次数未大于所述第五阈值时，内存控制器将延迟对所述第一rank的刷新操作，并将所述延迟计数器的值加1。换一种表达方式，当内存控制器106通过步骤406确定所述第一rank未处于空闲状态时，即当前还在处理所述第一rank的访存请求或调度队列中还包含有所述第一rank的访存请求的情况下，若所述第一rank的延迟次数未达到第五阈值，则可以认为第一rank的访存请求较多。为了不影响性能，不对所述第一rank执行刷新操作，以便在后续轮询过程中再对所述第一rank进行刷新操作。其中，如前所述，所述第五阈值小于设置的预警值。所述预警值可以根据所述第一rank能够推迟的最大刷新命令的数量来确定。所述预警值用于指示需要立即对所述第一rank执行刷新操作。换一种表达方式，所述预警值用于指示内存控制器106对所述第一rank进行强制刷新操作。
可以理解的是，当对所述第一rank执行强制刷新操作时，还需要将前面延迟的刷新进行补刷。从而造成在需要进行补刷的时间段内刷新的次数较多。而在补刷的特定时间段内，一方面可能使得已经在所述调度队列中的所述第一rank的访存请求无法得到执行，从而较长时间的占用调度队列1068的空间，使得其他rank的访存请求无法进入调度队列，进而影响整个计算机系统的性能。 另一方面还可能因为短时间内刷新次数增多，造成系统业务中断。总而言之，对所述第一rank进行强制刷新会增加计算机系统100的刷新功耗，影响系统性能。
综上所述，在本发明实施例提供的刷新方法中，在一次tREFI的轮询过程中，对所述第一rank的刷新操作可以存在下述几种情况。
第一种情况，当内存控制器106接收的访存请求的数量大于第三阈值且访问所述第一rank的访存请求的数量小于第四阈值时，内存控制器106可以按照图3所示的内存刷新方法确定的刷新模式对所述第一rank执行刷新操作。换一种表达方式，在计算机系统100的访存流量较大的情况下，只要访问第一rank的访存请求的数量较小，则内存控制器106可以主动对所述第一rank执行刷新操作，而不需要等待第一rank处于空闲状态时再对所述第一rank执行刷新操作。因为在计算机系统100的访存流量较大的情况下，第一rank很难有机会处于空闲状态，如果不断推迟刷新，到后期为避免数据丢失而必须刷新时，会造成特定时间内刷新次数增多，处于被动刷新的状态。本发明实施例提供的这种主动刷新的方式能够降低因为延迟刷新而产生的被动刷新对计算机系统性能的影响，提高内存刷新的灵活性。从而能够提高计算机系统的性能，减少刷新开销。当然可以理解的是，在本发明实施例中，访问第一rank的访存请求的数量小于设置的第四阈值也包括第一rank处于空闲的情形。
第二种情况，当内存控制器106接收的访存请求的数量大于第三阈值，访问所述第一rank的访存请求的数量不小于第四阈值，并且所述第一rank的延迟刷新次数大于第五阈值时，内存控制器106可以按照图3所示的内存刷新方法确定的刷新模式对所述第一rank执行刷新操作。换一种表达方式，当计算机系统100中的内存访问流量较大，且第一rank的访存请求的数量也较大的情况下，如果所述第一rank的延迟次数大于所述第五阈值，则需要立即对所述第一rank执行刷新操作，从而也可以避免因为第一rank的延迟刷新次数到达预警值需要执行强制刷新的可能性，减少因为被动刷新次数增加对计算机系统性能的影响，提高内存刷新的灵活性。可以理解的是，所述第三阈值是根据实际应用中结合预警值设置的一个门限值，能够使得计算机系统在不影响性能的情况下在一定范围内推迟刷新，提高内存刷新的灵活性。
第三种情况，当内存控制器106接收的访存请求的数量大于第三阈值，访问所述第一rank的访存请求的数量不小于第四阈值，并且所述第一rank的延迟刷新次数不大于所述第五阈值时，可以延迟对所述第一rank的刷新操作。换一种表达方式，在本发明实施例中，当计算机系统100中的内存访问流量较大，且第一rank的访存请求的数量也较大的情况下，只要所述第一rank的延迟刷新次数尚未到达预设的所述第五阈值，为了不影响对调度队列108中所述第一rank的访存请求的处理，可以暂缓对所述第一rank的刷新操作。
第四种情况，当内存控制器106接收的访存请求的数量不大于所述第三阈值，且所述第一rank处于空闲状态时，内存控制器106可以按照图3所示的内存刷新方法确定的刷新模式对所述第一rank执行刷新操作。换一种表达 方式，当所述计算机系统100的内存流量较小且所述第一rank处于空闲状态时，所述第一rank的刷新操作对计算机系统的性能的影响较小，因此可以直接对所述第一rank执行刷新操作。
第五种情况，当所述内存控制器106接收的访存请求的数量不大于所述第三阈值，所述第一rank未处于空闲状态，并且，所述第一rank的延迟刷新次数大于所述第五阈值时，所述内存控制器106需要主动按照图3所示的内存刷新方法确定的刷新模式对所述第一rank执行刷新操作。换一种表达方式，当所述计算机系统100的内存流量较小但所述第一rank较忙的情况下，为了避免对所述第一rank进行强制刷新，需要在本次轮询过程中对所述第一rank执行刷新操作。从而能够避免系统因为延迟刷新次数到达预警值而增加被动刷新的次数，减少被动刷新对计算机系统性能的影响。
第六种情况下，当所述内存控制器106接收的访存请求的数量不大于所述第三阈值，所述第一rank未处于空闲状态，并且，所述第一rank的延迟刷新次数不大于所述第五阈值时，所述内存控制器106可以延迟对所述第一rank的刷新操作。换一种表达方式，当所述计算机系统100的内存流量较小但所述第一rank较忙的情况下，为了尽可能多的处理所述第一rank的访存请求，在所述第一rank的延迟次数尚未大于所述第五阈值时，可以延迟对所述第一rank的刷新操作。
可以理解的是，上述对本发明实施例提供的内存刷新方法的描述均是以在一次刷新轮询过程中，对内存108中的第一rank的刷新操作为例进行描述。实际应用中，在每一次刷新轮询过程中，内存控制器均可以根据上述提供的方法确定是否需要对内存108中的各个rank进行刷新。例如，在第一刷新轮询过程中，内存控制器106可能确定按照上述第一种情况对所述第一rank进行刷新，按照上述第二种情况第内存108中的第二rank进行刷新，并按照上述第三种情况延迟对内存108中的第三rank的刷新操作。在第二刷新轮询过程中，内存控制器106可以案子上述第六种情况延迟对所述第一RANK进行刷新，并按照上述第五种情况对所述第二rank进行刷新。
进一步的，由于在对第所述第一rank执行刷新操作的tRFC的时间段内，内存控制器106也无法响应所述第一rank的访存请求，为了避免第一rank的访存请求堵塞调度队列1068，而造成其他rank(例如，第二rank)的访存请求不能进入调度队列1068，影响系统性能。在本发明实施例中，当对所述第一rank进行刷新操作时，若内存控制器106接收到对所述第一rank的访存请求时，内存控制器106可以将所述第一rank的访存请求放入缓存队列1066。当内存控制器1068对所述第一rank执行完刷新操作后，再将缓存队列1066中对所述第一rank的访存请求从缓存队列1066放入所述调度队列1068。并且，在本发明实施例中，当对所述第一rank执行完刷新操作后，内存控制器106可以将后续新接收的对所述第一rank的访存请求直接放入调度队列108，而不必再放入缓存队列1066。
可以理解的是，在本发明实施例中，当对所述第一rank进行刷新操作时，若内存108中的第二rank未执行刷新操作，则内存控制器106可以将接收的对所述第二rank的访存请求直接放入调度队列1068。根据这种调度方式，可以使得调度队列中的访存请求的目标rank分散分布，使得内存控制器106在对所述第一rank执行刷新操作的过程中，也能尽可能多的处理不同rank的访存请求，从而能够减小计算机系统100在刷新操作过程中的系统开销，提高计算机系统100的执行效率。
从本发明实施例提供的上述刷新方法可以看出，本发明实施例为了减少内存刷新过程中对计算机系统的性能的影响，综合考虑了接收的访存请求的情况以及访问的目标rank的情况来确定是否需要对目标rank进行刷新。从而通过对内存控制器的刷新时间的管理，在兼容现有的DDR协议的基础上，降低了因推迟刷新而引起的被动强制刷新次数增多对计算机系统性能的影响，提高内存刷新的灵活性，减少了刷新开销。并且，在本发明实施例中，在需要对第一rank执行刷新操作的过程中，还可以根据目标rank的分布情况以及访存请求的类型分布选择不同的刷新模式，以提高内存控制器的刷新效率，提高计算机系统的性能。
进一步的，在本发明实施例中，为了提高访存请求的并发度，使得第一rank的刷新操作不影响其他rank的访存请求的处理，在内存控制器中可以设置多级缓存，例如，可以分别设置调度队列以及缓存队列。从而，可以将在对所述第一rank执行刷新操作的tRFC的时间段内接收的所述第一rank的访存请求缓存在缓存队列中，从而能够防止在所述tRFC的时间段内接收的所述第一rank的访存请求堵塞调度队列，影响在对所述第一rank刷新过程中内存控制器对其他rank的访存请求的处理。进一步的提高整计算机系统的处理效率。
需要说明的是，实际应用中，图4所示实施例中的每一个步骤并不是必须执行的。例如，在图4所示的实施例中结合整个系统中的访存流量的大小对内存刷新方法进行了描述，例如，在轮询过程中，可以先进入步骤402，判断内存控制器106接收的访存请求的数量是否大于第三阈值。然而，在实际应用中，也可以不区分整个系统的访存流量的大小，而直接按照待刷新rank的访存流量的情况进行处理。在这种情况下，图4实施例中的步骤402并不是必须的。换一种表达方式，本发明实施例提供的刷新方法无论是在系统的访存流量大的情况下或是在系统的访存流量小的情况下均可以使用。在此不做限定。
图5为本发明实施例提供的一种内存刷新装置的结构示意图。图5所示的内存刷新装置500用于对图1所示的内存108进行刷新。如图5所示，内存刷新装置500可以包括接收模块502以及刷新模块506。其中，内存108中包含有多个rank。
接收模块502，用于接收访存请求。具体的，接收模块502可以接收计算机系统100中一个或多个core 104发送的访存请求。可以理解的是，接收模块502还可以用于接收内存108返回的数据。接收模块502具体可以包括内存控 制器106与core 104的通信接口，以及内存控制器102与内存108的通信接口。
刷新模块506，用于当在第一时间段内接收的访存请求的目标rank的数量小于设置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述T用于指示标准的平均刷新时间间隔，N为大于1的整数。
在一种可能的情况下，所述刷新模块506还用于：当在第二时间段内接收的访存请求的目标rank的数量不小于设置的第一阈值，或者，所述访存请求中读请求的比例或写请求的比例不大于设置的第二阈值时，按照所述T的时间间隔对所述第一rank进行刷新。
在又一种可能的情况下，内存刷新装置500还可以包括统计模块504。统计模块504用于统计接收的访存请求的数量。实际应用中，统计模块404还可以分别统计访问各个rank的访存请求的数量。可以理解的是，当内存刷新装置500包括统计模块504的情况下，刷新模块506可以根据统计模块504的统计结果动态调整刷新模式。
在又一种可能的情况下，所述接收模块502还用于在执行所述第一刷新请求的过程中，接收访问所述第一rank的第一访存请求。所述内存刷新装置还可以包括缓存模块508。所述缓存模块508用于将所述第一访存请求缓存在设置的缓存队列中。其中，所述缓存模块508中至少包括缓存队列和调度队列。所述缓存队列用于缓存正在被执行刷新操作的rank的访存请求，所述调度队列用于缓存待发送给未被执行刷新操作的rank的访存请求。
在又一种可能的情况下，所述接收模块502还用于接收访问所述DRAM中的第二rank的第二访存请求。所述缓存模块508用于当所述第二rank没有执行刷新操作时，将所述第二访存请求缓存在所述调度队列中。
在另一种可能的情况下，所述刷新模块具体用于：当所述第一时间段内接收的访存请求的数量大于第三阈值，且所述接收的访存请求中访问所述第一rank的访存请求小于第四阈值时，按照T/N的时间间隔对所述第一rank进行刷新，其中，在第一时间段内，访问所述第一rank的访存请求大于0。
在又一种可能的情况下，所述刷新模块具体用于：当所述第一时间段内所述接收的访存请求中访问所述第一rank的访存请求不小于第四阈值，并且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
在又一种可能的情况下，所述刷新模块具体用于：当在第一时间段内接收的访存请求的数量不大于设置的第三阈值，所述第一rank的访存请求的数量大于0，且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新。其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
可以理解的是，图5所示的内存刷新装置500中各模块可以分别位于图2所示的内存控制器中的一个或多个器件中。在本发明实施例中，可以根据实际的需要选择图5所示的实施例中的部分或者全部模块来实现本实施例方案的目的。图5实施例中没有详细描述的地方可以参考图3及图4中方法实施例中的相关描述。
可以理解的是，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如，多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，上述实施例所讨论的模块相互之间的连接可以是电性、机械或其他形式。所述作为分离部件说明的模块可以是物理上分开的，也可以不是物理上分开的。作为模块显示的部件可以是物理模块或者也可以不是物理模块。另外，在申请实施例各个实施例中的各功能模块可以独立存在，也可以集成在一个处理模块中。例如，图5所示的各功能模块可以集成在图2所示的内存控制器中。
本发明实施例还提供一种数据处理的计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行前述任意一个方法实施例所述的方法流程。本领域普通技术人员可以理解，前述的存储介质包括：U盘、移动硬盘、磁碟、光盘、随机存储器(Random-Access Memory，RAM)、固态硬盘(Solid State Disk，SSD)或者非易失性存储器(non-volatile memory)等各种可以存储程序代码的非短暂性的(non-transitory)机器可读介质。
需要说明的是，本申请所提供的实施例仅仅是示意性的。所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。在本发明实施例、权利要求以及附图中揭示的特征可以独立存在也可以组合存在。在本发明实施例中以硬件形式描述的特征可以通过软件来执行，反之亦然。在此不做限定。

Claims (28)

  1. 一种内存刷新方法，所述方法应用于包括内存控制器以及动态随机存取存储器DRAM的计算机系统中，所述DRAM中包含有多个rank，所述方法包括：
    所述内存控制器接收访存请求；
    当在第一时间段内接收的访存请求的目标rank的数量小于设置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，所述内存控制器按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述T用于指示标准的平均刷新时间间隔，N为大于1的整数。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    当在第二时间段内接收的访存请求的目标rank的数量不小于设置的第一阈值，或者，所述访存请求中读请求的比例或写请求的比例不大于设置的第二阈值时，所述内存控制器按照所述T的时间间隔对所述第一rank进行刷新。
  3. 根据权利要求1-2任意一项所述的方法，其特征在于，还包括：
    在执行所述第一刷新请求的过程中，所述内存控制器接收访问所述第一rank的第一访存请求；
    所述内存控制器将所述第一访存请求缓存在设置的缓存队列中，其中，所述内存控制器中至少包括缓存队列和调度队列，所述缓存队列用于缓存正在被执行刷新操作的rank的访存请求，所述调度队列用于缓存待发送给未被执行刷新操作的rank的访存请求。
  4. 根据权利要求3所述的方法，其特征在于，还包括：
    所述内存控制器接收访问所述DRAM中的第二rank的第二访存请求；
    当所述第二rank没有执行刷新操作时，所述内存控制器将所述第二访存请求缓存在所述调度队列中。
  5. 根据权利要求1-4任意一项所述的方法，其特征在于，所述内存控制器以T/N的时间间隔对所述多个rank中的第一rank进行刷新包括：
    当所述第一时间段内接收的访存请求的数量大于第三阈值，且所述接收的访存请求中访问所述第一rank的访存请求小于第四阈值时，所述内存控制器按照T/N的时间间隔对所述第一rank进行刷新，其中，在第一时间段内，访问所述第一rank的访存请求大于0。
  6. 根据权利要求1-4任意一项所述的方法，其特征在于，所述内存控制器以T/N的时间间隔对所述多个rank中的第一rank进行刷新包括：
    当所述第一时间段内所述接收的访存请求中访问所述第一rank的访存请求不小于第四阈值，并且所述第一rank的延迟刷新次数大于设置的第五阈值时，所 述内存控制器按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
  7. 根据权利要求1-4任意一项所述的方法，其特征在于，所述以T/N的时间间隔对所述多个rank中的第一rank进行刷新包括：
    当在第一时间段内接收的访存请求的数量不大于设置的第三阈值，所述第一rank的访存请求的数量大于0，且所述第一rank的延迟刷新次数大于设置的第五阈值时，所述内存控制器以T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
  8. 一种计算机系统，包括内存控制器以及与所述内存控制器连接的动态随机存取存储器DRAM，所述DRAM中包含有多个rank，所述内存控制器用于：
    接收访存请求；
    当在第一时间段内接收的访存请求的目标rank的数量小于设置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，T用于指示标准的平均刷新时间间隔，N为大于1的整数。
  9. 根据权利要求8所述的计算机系统，其特征在于，所述内存控制器还用于：
    当在第二时间段内接收的访存请求的目标rank的数量不小于设置的第一阈值，或者，所述访存请求中读请求的比例或写请求的比例不大于设置的第二阈值时，按照所述T的时间间隔对所述第一rank进行刷新。
  10. 根据权利要求8-9任意一项所述的计算机系统，其特征在于，所述内存控制器还用于：
    在执行所述第一刷新请求的过程中，接收访问所述第一RANK的第一访存请求；
    将所述第一访存请求放入缓存在缓存队列中，其中，所述内存控制器中至少包括缓存队列和调度队列所述缓存队列用于缓存正在被执行刷新操作的rank的访存请求，所述调度队列用于缓存待发送给未被执行刷新操作的rank的访存请求。
  11. 根据权利要求10所述的计算机系统，其特征在于，所述内存控制器还用于：
    接收访问所述DRAM中的第二rank的第二访存请求；
    当所述第二rank没有执行刷新操作时，将所述第二访存请求缓存在所述调度队列中。
  12. 根据权利要求8-11任意一项所述的计算机系统，其特征在于，所述内存控制器具体用于：
    当所述第一时间段内接收的访存请求的数量大于第三阈值，且所述接收的访存请求中访问所述第一rank的访存请求小于第四阈值时，按照T/N的时间间隔对所述第一rank进行刷新，其中，在所述第一时间段内，访问所述第一rank的访存请求大于0。
  13. 根据权利要求8-11任意一项所述的计算机系统，其特征在于，所述内存控制器具体用于：
    当所述第一时间段内所述接收的访存请求中访问所述第一rank的访存请求不小于第四阈值，并且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
  14. 根据权利要求8-11任意一项所述的计算机系统，其特征在于，所述内存控制器具体用于：
    当在第一时间段内接收的访存请求的数量不大于设置的第三阈值，所述第一rank的访存请求的数量大于0，且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照所述T/N的时间间隔对所述第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一RANK执行刷新操作。
  15. 一种内存控制器，其特征在于，包括：
    通信接口，用于接收计算机系统中的处理器发送的访存请求；
    刷新电路，用于在第一时间段内接收的访存请求的目标rank的数量小于设置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述T用于指示标准的平均刷新时间间隔，N为大于1的整数。
  16. 根据权利要求15所述的内存控制器，其特征在于，所述刷新电路还用于：
    当在第二时间段内接收的访存请求的目标rank的数量不小于设置的第一阈值，或者，所述访存请求中读请求的比例或写请求的比例不大于设置的第二阈值时，按照所述T的时间间隔对所述第一rank进行刷新。
  17. 根据权利要求15或16所述的内存控制器，其特征在于：
    所述通信接口，还用于在执行所述第一刷新请求的过程中，接收访问所述第一rank的第一访存请求；
    所述内存控制器还包括：
    缓存，用于将所述第一访存请求缓存在设置的缓存队列中，其中，所述缓存中至少包括缓存队列和调度队列，所述缓存队列用于缓存正在被执行刷新操作的rank的访存请求，所述调度队列用于缓存待发送给未被执行刷新操作的rank的访存请求。
  18. 根据权利要求17所述的内存控制器，其特征在于：
    所述通信接口，还用于接收访问所述DRAM中的第二rank的第二访存请求；
    所述缓存，还用于当所述第二rank没有执行刷新操作时，将所述第二访存请求缓存在所述调度队列中。
  19. 根据权利要求15-18任意一项所述的内存控制器，其特征在于，所述刷新电路具体用于：
    当所述第一时间段内接收的访存请求的数量大于第三阈值，且所述接收的访存请求中访问所述第一rank的访存请求小于第四阈值时，按照T/N的时间间隔对所述第一rank进行刷新，其中，在第一时间段内，访问所述第一rank的访存请求大于0。
  20. 根据权利要求15-18任意一项所述的内存控制器，其特征在于，所述刷新电路具体用于：
    当所述第一时间段内所述接收的访存请求中访问所述第一rank的访存请求不小于第四阈值，并且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
  21. 根据权利要求15-18任意一项所述的内存控制器，其特征在于，所述刷新电路具体用于：
    当在第一时间段内接收的访存请求的数量不大于设置的第三阈值，所述第一rank的访存请求的数量大于0，且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
  22. 一种内存刷新装置，其特征在于，所述内存刷新装置用于对计算机系统中的动态随机存取存储器DRAM进行刷新，所述DRAM中包含有多个rank，所述内存刷新装置包括：
    接收模块，用于接收访存请求；
    刷新模块，用于当在第一时间段内接收的访存请求的目标rank的数量小于设 置的第一阈值，并且，所述访存请求中读请求的比例或写请求的比例大于设置的第二阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述T用于指示标准的平均刷新时间间隔，N为大于1的整数。
  23. 根据权利要求22所述的内存刷新装置，其特征在于，所述刷新模块还用于：
    当在第二时间段内接收的访存请求的目标rank的数量不小于设置的第一阈值，或者，所述访存请求中读请求的比例或写请求的比例不大于设置的第二阈值时，按照所述T的时间间隔对所述第一rank进行刷新。
  24. 根据权利要求22或23所述的内存刷新装置，其特征在于：
    所述接收模块，还用于在执行所述第一刷新请求的过程中，接收访问所述第一rank的第一访存请求；
    所述内存刷新装置还包括：
    缓存模块，用于将所述第一访存请求缓存在设置的缓存队列中，其中，所述缓存模块中至少包括缓存队列和调度队列，所述缓存队列用于缓存正在被执行刷新操作的rank的访存请求，所述调度队列用于缓存待发送给未被执行刷新操作的rank的访存请求。
  25. 根据权利要求22所述的内存刷新装置，其特征在于：
    所述接收模块，还用于接收访问所述DRAM中的第二rank的第二访存请求；
    所述缓存模块，还用于当所述第二rank没有执行刷新操作时，将所述第二访存请求缓存在所述调度队列中。
  26. 根据权利要求22-25任意一项所述的内存刷新装置，其特征在于，所述刷新模块具体用于：
    当所述第一时间段内接收的访存请求的数量大于第三阈值，且所述接收的访存请求中访问所述第一rank的访存请求小于第四阈值时，按照T/N的时间间隔对所述第一rank进行刷新，其中，在第一时间段内，访问所述第一rank的访存请求大于0。
  27. 根据权利要求22-25任意一项所述的内存刷新装置，其特征在于，所述刷新模块具体用于：
    当所述第一时间段内所述接收的访存请求中访问所述第一rank的访存请求不小于第四阈值，并且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
  28. 根据权利要求22-25任意一项所述的内存刷新装置，其特征在于，所述刷新模块具体用于：
    当在第一时间段内接收的访存请求的数量不大于设置的第三阈值，所述第一rank的访存请求的数量大于0，且所述第一rank的延迟刷新次数大于设置的第五阈值时，按照T/N的时间间隔对所述多个rank中的第一rank进行刷新，其中，所述第五阈值小于设置的预警值，所述预警值用于指示需要立即对所述第一rank执行刷新操作。
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