WO2022155970A1 - 一种内存控制方法及内存控制装置 - Google Patents

一种内存控制方法及内存控制装置 Download PDF

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WO2022155970A1
WO2022155970A1 PCT/CN2021/073656 CN2021073656W WO2022155970A1 WO 2022155970 A1 WO2022155970 A1 WO 2022155970A1 CN 2021073656 W CN2021073656 W CN 2021073656W WO 2022155970 A1 WO2022155970 A1 WO 2022155970A1
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memory
memory controller
write
command
write command
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PCT/CN2021/073656
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English (en)
French (fr)
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梁传增
龙明直
林祥轩
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华为技术有限公司
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Priority to PCT/CN2021/073656 priority Critical patent/WO2022155970A1/zh
Priority to CN202180090740.7A priority patent/CN116724287A/zh
Publication of WO2022155970A1 publication Critical patent/WO2022155970A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

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  • the present application relates to the field of memory technologies, and in particular, to a memory control method and a memory control device.
  • Memory also known as internal memory, is used to temporarily store operation data in the central processing unit (CPU) and exchange data with external memory such as hard disks.
  • the memory controller is used to manage the data exchange from memory to CPU.
  • the memory controller can be a separate chip or integrated into the internal memory or CPU.
  • the performance of the memory controller directly affects the reading and writing speed of the CPU to the data in the memory, and two important parameters that affect the performance of the memory controller are: bandwidth utilization and latency.
  • the bandwidth utilization rate refers to the ratio of the interface data transmission speed of the memory controller to the maximum transmission speed within a certain period of time.
  • the delay refers to the time interval between receiving the read command or write command sent by the CPU and feeding back the memory to the CPU to complete the read command or write command.
  • the memory controller shown in Figure 1A is designed on the premise of ensuring high bandwidth utilization.
  • read commands and write commands will be stored in the command queue after entering the memory controller through the command interface.
  • the command scheduling module will schedule the commands cached in the command queue as soon as possible based on the greedy algorithm to ensure that the memory controller There is a high bandwidth utilization rate.
  • the command scheduling module also informs the timing judgment module after scheduling a command. After the timing judgment module identifies the type of the command, it loads different counters to ensure that each command meets the timing parameters during scheduling.
  • the command scheduling module selects commands from the command queue for scheduling.
  • the write data transmission module is used to receive the write data corresponding to the write command issued by the processor, and when the write command is sent to the memory, the write data is sent to the memory.
  • the data is sent to the memory together, and the read data transmission module is used to receive the read data sent by the memory and send the read data to the processor.
  • the memory controller when the processor issues commands, it usually issues write commands and read commands randomly. In order to ensure high bandwidth utilization, the memory controller still uses a greedy algorithm to schedule commands from the command queue. For example, the memory controller will schedule the write command received first to the memory, and wait for the write command to be executed in the memory before it can continue to schedule the read command to the memory for execution. Commands are scheduled continuously in the queue.
  • This method generally divides the average delay of read commands and write commands equally, but in fact, read commands are more sensitive to delay than write commands. When the average delay of read commands is high, the delay performance of the entire memory system will be poor, and the high average delay of read commands cannot be tolerated by the existing memory system. In view of this, it is an urgent problem to be solved in the art how to reduce the average delay of a read command that is sensitive to delay while taking into account high bandwidth utilization.
  • the present application provides a memory control method and a memory control device. Based on the ingress traffic of the memory controller, when the ingress traffic of the memory controller is high, the priority of the read command is higher than that of the write command, so that the read command is sent, and the read command is sent. When the ingress traffic of the memory controller is low, a part of the cached write commands are issued. At this time, due to the low ingress traffic of the memory controller, the processor sends few read commands and write commands. Therefore, the issued write commands There are also few read commands blocked by the command, so the increase in read command delay caused by blocking can be ignored. On the whole, compared with the existing command scheduling method, the average delay of the read command is significantly reduced. Therefore, the average delay of the read command can be reduced while taking into account the higher utilization rate.
  • an embodiment of the present application provides a memory control method, which can be applied to a memory controller, and mainly includes the following steps: determining a read command cached in the memory controller according to the ingress traffic of the memory controller And the priority of the write command, the ingress flow is the sum of the number of read commands and write commands received by the memory controller within a unit time; Buffered read commands and write commands are sent to memory.
  • the priority of the read command and the write command cached in the memory controller is sent to the memory according to the priority of the read command and the write command. Therefore, when the ingress traffic is high, the read command can be sent to the memory faster, so that the memory can process it as soon as possible.
  • the ingress traffic is low, few read commands and write commands are received, which will be insensitive to latency
  • the write command is sent to ensure that the buffered write command does not accumulate too much, and there are few read commands blocked by the write command. On the whole, among the read commands dispatched by the memory controller, fast dispatching accounts for most of the read commands and only a small portion is blocked.
  • the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller priority.
  • the set condition includes at least one of the following: the ingress traffic of the memory controller is greater than a set threshold; the total number of write commands buffered in the memory controller is not greater than the write command A quantity threshold; the bandwidth utilization of the memory controller is greater than the utilization threshold.
  • the total number of write commands cached in the write command cache queue is not greater than the threshold of the number of write commands, it indicates that at this time, too many write commands have not accumulated in the memory controller, and at this time, the read commands cached in the memory controller
  • the priority is higher than the priority of the write command cached in the memory controller, and it is necessary to ensure the priority scheduling of the read command.
  • the bandwidth utilization rate is the ratio of the current data transmission speed of the memory controller to the maximum data transmission speed.
  • the current data transmission speed is the ratio between the speed at which the current memory controller sends the data corresponding to the read command to the processor and the data corresponding to the write command to the memory.
  • the priority of the write command buffered in the memory controller is higher than the read command buffered in the memory controller priority.
  • the target quantity is determined according to the ingress flow, and the target quantity is selected from the write commands cached in the memory controller.
  • the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller.
  • a target write command is selected from the write commands cached in the memory controller according to a set rule, and the target write command is The priority of the command is higher than the priority of the write command cached in the memory controller.
  • the write command selected from the write commands cached in the memory controller according to the set rule is faster than the randomly selected write command, and can also significantly reduce the delay of the read command blocked by the write command. Time.
  • the setting rule may include at least one of the following:
  • the quantity belonging to the same memory address set in the selected target write command is less than the set quantity threshold, wherein the memory includes a plurality of memory spaces, each memory space corresponds to a memory address set, and each write command includes a memory address;
  • the selected target write command is located in the same memory row, wherein the write command further includes memory row information, and the memory row corresponding to the write command is determined according to the memory row information included in the write command.
  • the selected target write command is located in the same memory row, which can ensure that the row address of the memory row in the memory address corresponding to the write command sent to the memory within a period of time is the same, thereby saving the time for opening the memory row and achieving performance gain.
  • the method further includes: increasing the priority of the first write command, the memory address included in the first write command cached in the memory controller is the same as the first write command cached in the memory controller.
  • a read command contains the same memory address.
  • the method further includes: taking the to-be-written data corresponding to the second write command as the to-be-read of the second read command
  • the memory address contained in the second write command cached in the memory controller is the same as the memory address contained in the second read command cached in the memory controller.
  • the method further includes: when the total number of write commands buffered in the memory controller is greater than a total number threshold, no longer buffering the write commands.
  • sending the read command and the write command buffered in the memory controller to the memory includes: according to a first sending cycle, sending the write command buffered in the memory controller to the memory; According to the second sending cycle, the read command buffered in the memory controller is sent to the memory.
  • different command sending cycles can be configured according to different memory protocols or different system business scenarios, thereby ensuring the bandwidth of the memory controller.
  • an embodiment of the present application provides a memory control device, and the memory control device can implement the memory control method provided in any one of the above-mentioned first aspects.
  • the memory control device can implement the memory control method provided in any one of the above-mentioned first aspects.
  • the memory control device includes: an ingress traffic judging module and a command issuing module;
  • the ingress traffic judging module is configured to determine the priority of read commands and write commands cached in the memory controller according to the ingress traffic of the memory controller, where the ingress traffic is the memory controller per unit time The sum of the number of read and write commands received;
  • the command issuing module is configured to send the read command and the write command buffered in the memory controller to the memory according to the order from high to low of the priority.
  • the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller class.
  • the set conditions include at least one of the following:
  • the ingress flow of the memory controller is greater than the set threshold
  • the total number of write commands cached in the memory controller is not greater than the write command number threshold
  • the bandwidth utilization of the memory controller is greater than the utilization threshold.
  • the ingress flow judgment module is further configured to determine the target quantity according to the ingress flow when the ingress flow of the memory controller does not meet a set condition, and cache the data from the memory controller.
  • a target number of write commands is selected from the write commands, and the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller.
  • the ingress traffic judging module is further configured to select from write commands cached in the memory controller according to a set rule when the ingress traffic of the memory controller does not meet a set condition A target write command, the priority of the target write command is higher than the priority of the write command cached in the memory controller.
  • the setting rule includes at least one of the following:
  • the quantity belonging to the same memory address set in the selected target write command is less than the set quantity threshold, wherein the memory includes a plurality of memory spaces, each memory space corresponds to a memory address set, and each write command includes a memory address;
  • the selected target write command is located in the same memory row, wherein the write command further includes memory row information, and the memory row corresponding to the write command is determined according to the memory row information included in the write command.
  • the memory control apparatus further includes a priority adjustment module; the priority adjustment module is configured to increase the priority of the first write command, and the first write command cached in the memory controller
  • the included memory address is the same as the memory address included in the first read command cached in the memory controller.
  • the memory control device further includes a read data determination module, the read data determination module is configured to use the to-be-written data corresponding to the second write command as the to-be-read data of the second read command , the memory address included in the second write command cached in the memory controller is the same as the memory address included in the second read command cached in the memory controller.
  • the memory control device further includes a write command quantity judgment module, the write command quantity judgment module is used for when the total quantity of write commands buffered in the memory controller is greater than a total quantity threshold , write commands are no longer cached.
  • the command issuing module is further configured to send the write command buffered in the memory controller to the memory according to the first sending cycle; and send the memory controller to the memory according to the second sending cycle Buffered read commands are sent to memory.
  • an embodiment of the present application further provides a processor, where the processor may include a processor core and the memory controller involved in the first aspect, and the processor core may send a write command and a read command to the memory controller, The memory controller can send the write and read commands to the memory after receiving the write and read commands.
  • an embodiment of the present application provides an electronic device, the electronic device includes a processor, a memory controller, and a memory, and the memory controller on the electronic device is configured to execute the memory control method provided in any one of the first aspects.
  • embodiments of the present application further provide a computer-readable storage medium, where an instruction is stored in the computer-readable storage medium, and when the computer-readable storage medium runs on the memory controller, the memory controller executes the methods of the above aspects.
  • embodiments of the present application further provide a computer program product including instructions, which, when executed on a memory controller, cause the memory controller to execute the methods of the above aspects.
  • an embodiment of the present application further provides a chip, where the chip is used to read a computer program stored in a memory, and when the computer program is executed, the methods of the above aspects can be implemented.
  • 1A is a schematic diagram of a conventional memory controller
  • 1B is a schematic diagram of a memory array and a peripheral control circuit
  • 2 is a schematic structural diagram of an electronic device
  • FIG. 3 is a schematic diagram of a memory control method
  • FIG. 5 is a schematic flowchart of determining the target number according to the bandwidth utilization of the memory controller
  • FIG. 6 is a schematic flowchart of determining the target number according to the total number of write commands cached by the memory controller
  • FIG. 7 is a schematic diagram of a memory control device
  • FIG. 8 is a schematic structural diagram of an example of a memory controller.
  • the memory controller is used to manage the data exchange from the memory to the processor. It can be a separate chip, or integrated into memory or a processor.
  • Memory also known as internal memory, is used to temporarily store operational data in the processor and exchange data with external memory such as hard disks.
  • the working principle of memory is to use its capacitance to store charge, and use the amount of charge to represent whether a binary bit is 1 or 0.
  • the repeated arrangement of multiple single-bit memory cells constitutes a memory array.
  • the memory array shown in FIG. 1B and the peripheral control circuit constitute a memory.
  • BA Dynamic random access memory bank address
  • bank is the meaning of memory space.
  • a piece of memory can be divided into multiple memory spaces. When accessing, specify the memory space number to access the specified memory space. How many banks are divided in the specific memory depends on how many BA addresses are in the address line. For example, if the BA address is 2 bits, it means there are 4 banks; if the BA address is 3 bits, it means there are 8 banks.
  • BG Dynamic random access memory bank group
  • a piece of memory can be divided into multiple bank groups, and each bank group can independently read and write data, so that the internal data throughput is greatly improved, and a large amount of data can be read at the same time, and the equivalent frequency of the memory has also been improved.
  • two or four selectable independent groupings are used on the DDR4 architecture.
  • the northbridge is the most important part of the motherboard chipset that plays a leading role. It is the chip closest to the processor on the motherboard. It is responsible for contacting the processor and controlling the memory.
  • a communication interface is established between the PCI bus, memory, AGP (accelerated graphics port, graphics acceleration port) and the second level cache.
  • the greedy algorithm means that when solving the problem, it always makes the best choice in the current view. That is to say, it does not consider the overall optimality, and only makes a local optimal solution in a certain sense.
  • the greedy algorithm cannot obtain the overall optimal solution for all problems.
  • the key is the choice of the greedy strategy.
  • the selected greedy strategy must have no aftereffect, that is, the previous process of a certain state will not affect the future state, only the same as the current state. related.
  • memory is the basis for processors to perform operations, and processors can be coupled with memory through memory controllers.
  • the memory controller can be connected with the processor, and can also be integrated inside the processor.
  • FIG. 2 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application.
  • the electronic device 20 mainly includes a processor 21 , a memory controller 22 and a memory 23 .
  • the memory controller 22 can also be integrated into the processor 21 or the memory 23, and can also be built into the north bridge.
  • the embodiment of the present application does not limit the specific location of the memory controller 22 .
  • the memory controller 22 and the memory 23 are not integrated together, the memory controller 22 and the memory 23 are connected through a memory bus 25 .
  • the processor 21 is a computing core (core) and a control core (control unit) of the electronic device 20, and the processor 21 may also be an ultra-large-scale integrated circuit.
  • An operating system and other software programs are installed in the processor 21 so that the processor 21 can access the memory 23 of the electronic device 20 .
  • the processor 21 may be a central processing unit (CPU), a network processor (NP) or a combination of CPU and NP.
  • the processor 21 may further include a hardware chip.
  • the above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general-purpose array logic (generic array logic, GAL) or any combination thereof.
  • CPLD complex programmable logic device
  • FPGA field-programmable gate array
  • GAL general-purpose array logic
  • more and more processor cores (cores) can be integrated in the processor 21 .
  • the multiple processor cores can be interconnected through an on-chip network.
  • the electronic device 20 may further include multiple processors 21 .
  • This embodiment of the present application uses a processor as an example for example.
  • the number of processors and the number of processor cores in one processor are not limited in this embodiment of the present application.
  • the memory controller 22 may include a communication interface and a control circuit, and the memory controller 22 may communicate with the processor 21 and the memory 23 through the communication interface.
  • the memory controller 22 can write data into the memory 23 or read data from the memory 23 .
  • the memory 23 may be a memory chip that supports double data rate synchronous dynamic random access memory (DDR SDRAM), wherein, DDR SDRAM is usually abbreviated as DDR, exemplarily, the memory 23 It can also support the 4th generation DDR (4th DDR, DDR4), such as low power DDR4 (low power DDR4, LPDDR4).
  • the memory 23 can support the 5th generation DDR (5th DDR, DDR5), such as low power DDR5 (low power DDR5, LPDDR5).
  • a cache 24 may also be provided in the memory controller 22.
  • the cache 24 is a temporary storage located between the processor 21 and the memory 23 in the electronic device 20.
  • the cache 24 is located in the memory controller 22.
  • the cache 24 may consist of static random access memory (SRAM).
  • SRAM static random access memory
  • the cache 24 is used for temporarily storing write data sent by the processor 21 to the memory 23 and read data sent by the memory 23 to the processor 21 .
  • the memory bus 25 may include a data bus, a command/address bus, and a read data ready feedback line.
  • the data bus is used to transmit data
  • the command/address bus is used to transmit memory access commands such as read commands and write commands. It should be pointed out that the bidirectional data transmission between the memory controller 22 and the memory 23 can be realized through the memory bus 25 .
  • the memory controller 22 sends a write command to the memory 23 and sends write data to the memory 23, and the memory 23 writes the write data based on the received write command; the memory control The controller 22 can also send a read command to the memory 23 , and the memory 23 reads the read data from the inside based on the received read command, and returns the read data to the memory controller 22 .
  • the electronic device 20 may also include other devices such as a communication interface and a magnetic disk used as external storage, which is not limited here.
  • the memory controller still uses the greedy algorithm to schedule commands from the command queue. For example, the memory controller will schedule the write command received first to the memory, and wait for the write command to be executed in the memory before it can continue to schedule the read command to the memory for execution. Commands are scheduled continuously in the queue.
  • This method generally divides the average delay of read commands and write commands equally, but in fact, read commands are more sensitive to delay than write commands.
  • the read data can be read from the memory as quickly as possible, and the read data can be returned to the processor as quickly as possible, since the write command is not sensitive to delay.
  • the memory controller can send the write command and write data to the memory within a period of time after receiving the write command.
  • the average latency of read commands is still high, and when the average latency of read commands is high, the latency performance of the entire memory system will be poor.
  • the embodiments of the present application provide a memory control method and a memory control device, which can reduce the average delay of read commands while taking into account high bandwidth utilization, so as to solve the problem that when the average delay of read commands is high, the The problem of poor latency performance of the entire memory system.
  • the ingress traffic of the memory controller is first identified, and for different ingress traffic, the priorities of the read commands and write commands cached in the memory controller are determined. The priority of commands is increased to ensure that the read commands that are more sensitive to delay can be quickly scheduled, while the write commands are temporarily cached; when the ingress traffic is low, the received read commands and write commands are few, and some of the cached write commands are stored.
  • the priority is increased, and the write commands that are not sensitive to the delay will be sent to ensure that the buffered write commands are not backlogged too much, and the read commands blocked by the write commands are also few.
  • fast dispatching accounts for most of the read commands and only a small portion is blocked. Therefore, using the method provided by the present application can significantly reduce the average delay of the read command while taking into account high bandwidth utilization.
  • FIG. 3 is a flowchart of a memory control method provided by an embodiment of the present application. The method is described in detail below with reference to the method flowchart shown in FIG. 3 .
  • a memory control method provided by the present application includes steps S301-S303:
  • the memory controller 22 receives the read command and the write command from the processor 21, and caches the read command and the write command.
  • the read command is used to read the read data in the memory 23 .
  • Each read command issued by the processor 21 includes the address where the read data is located in the memory 23, and the read data is the data to be read corresponding to the read command; and the write command is used to Write data is stored in the internal memory 23, and each write command includes an address where the write data is stored in the internal memory 23, and the write data is the data to be stored corresponding to the write command;
  • the memory controller 22 can buffer the read command to the read command buffer queue according to the type of the read command and the write command, and buffer the write command to the write command buffer queue; or , both the read command and the write command may be cached in the command cache queue.
  • the specific cache method is not limited here, and those skilled in the art should know that, and will not be repeated here.
  • an upper limit of the number of write commands may be set in the write command buffer queue.
  • the write commands sent by the processor 21 are no longer stored in the write command buffer queue.
  • the memory controller 22 determines the priority of the read command and the write command cached in the memory controller 22 according to the ingress traffic of the memory controller 22;
  • the ingress traffic is the sum of the number of read commands and write commands received by the memory controller per unit time; we understand that the traffic of commands issued to the memory controller is not uniform, but there are peaks with high ingress traffic and troughs with low inlet flow.
  • the ingress traffic of the memory controller 22 is relatively large, that is, a peak, it means that the memory controller receives a large number of read commands and write commands. Therefore, when the commands are scheduled by the greedy algorithm in the existing way, there will be a large number of read commands and write commands. Scheduling the write command without considering the read command, the read command is more sensitive to the delay, and the average delay of the read command is high, which will lead to poor delay performance of the entire memory controller.
  • the method of determining the ingress traffic of the memory controller can be based on statistics on the number of commands currently received. For example, the greater the number of received commands, the greater the current ingress traffic. Alternatively, it can also be based on the bandwidth of the memory controller 22.
  • the utilization rate is determined, and the higher the bandwidth utilization rate, the higher the ingress traffic.
  • the bandwidth utilization rate refers to the ratio of the data transmission speed of the memory controller 22 to the maximum transmission speed within a certain period of time.
  • the memory controller 22 may schedule as many read commands as possible when the ingress traffic is large to ensure low latency of the read commands, and when the ingress traffic of the memory controller 22 is small. , scheduling a part of the write commands to ensure that there is no backlog of too many write commands in the memory controller 22, and because the ingress traffic is low, there will be few read commands blocked by the write commands.
  • the read command and write command received by the memory controller 22 may include the initial priority set by the processor 21, and the memory controller 22 may combine the initial priority and the ingress traffic of the memory controller to comprehensively determine the Priority of read and write commands cached in the memory controller.
  • the memory controller 22 receives 4 commands, including two read commands and two write commands (the smaller the number corresponding to the priority, the higher the priority): the priority of read command A is 2, and the priority of read command B is 2.
  • the priority is 4, the priority of the write command C is 1, and the priority of the write command D is 3.
  • the priority of the read command A is reset to 1
  • the priority of the read command B is reset to 1.
  • the priority is reset to 2
  • the priority of the write command C is reset to 3
  • the priority of the write command D is reset to 4, so that the read command is scheduled preferentially, thereby ensuring low latency of the read command.
  • the order of sending may also be determined according to the size of the read data corresponding to the read commands.
  • the corresponding read data may be sent first, because the memory executes the corresponding data.
  • the read command speed for reading data is faster, so the average delay of the read command can be further reduced.
  • the memory controller 22 sends the read command and the write command buffered in the memory controller 22 to the memory 23 according to the order of the priorities from high to low.
  • Read commands as well as write commands are sent to memory.
  • the cache 24 of the electronic device 20 may be provided with a read data cache space, and the memory controller 22 may cache the read data in the read data cache space after receiving the acquired read data sent by the memory.
  • the order in which the read data is sent may be related to the priority of the read command corresponding to the read data, and the read data corresponding to the read command with a higher priority is preferentially sent from the read data buffer space.
  • the cache 24 of the electronic device 20 may further be provided with a write data cache space, and the memory controller 22 may also receive the write data sent by the processor 21, and cache the write data in the write data In the buffer space, when a write command is sent to the memory 23, the write data corresponding to the write command is sent to the memory 23 together.
  • the write data cache space may also have an upper limit of cache data, and when the write data occupied space in the write data cache space reaches the upper limit of the cache data size, the write data sent by the processor 21 will no longer be cached in the write data cache. In the data cache space, at the same time, the write command sent by the processor 21 is no longer cached in the memory controller.
  • the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller priority.
  • the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller 22, so that the read command Prioritize scheduling, thereby reducing the average latency of read commands.
  • the setting condition may be the ingress traffic of the memory controller 22, or may be other parameters used to indirectly represent the ingress traffic, such as bandwidth utilization, etc. Those skilled in the art should know that any parameter that can be used to determine the current memory The parameters of the ingress flow of the controller 22 can all be applied to the embodiments of the present application, and details are not repeated here.
  • the set conditions include at least one of the following:
  • the inlet flow of the memory controller 22 is greater than the set threshold
  • the total number of write commands cached in the memory controller 22 is not greater than the write command number threshold
  • the bandwidth utilization of the memory controller 22 is greater than the utilization threshold.
  • the total number of write commands cached in the memory controller 22 can be used to indirectly represent the ingress traffic of the memory controller 22. Specifically, when the ingress traffic of the memory controller 22 is high, the memory controller 22 The priority of the read command cached in the memory controller is higher than the priority of the write command cached in the memory controller. Therefore, each time the processor 21 issues a read command and a write command, the write command will be cached in the memory controller. Therefore, when the total number of cache accumulations of the memory controller 22 is greater than the threshold of the number of write commands, it means that the ingress traffic of the memory controller 22 is low at this time. Exemplarily, the threshold for the number of write commands may be preset as 50, and when the total number of write commands is not greater than 50, the set condition is satisfied.
  • the bandwidth utilization rate cached in the memory controller 22 can also be used to indirectly represent the ingress traffic of the memory controller 22, wherein the bandwidth utilization rate is the current data transmission speed and the maximum data transmission rate of the memory controller 22.
  • the current data transmission speed is the sum of the current speed of the memory controller 22 sending the data corresponding to the read command to the processor 21 and the speed of sending the data corresponding to the write command to the memory 23 .
  • the utilization threshold can be correspondingly set in the memory controller 22, and when the bandwidth utilization is greater than the utilization threshold, it means the ingress traffic of the memory controller 22 at this time. larger, that is, to meet the set conditions.
  • the write commands cached in the memory controller 22 The priority of the command is higher than the priority of the read command buffered in the memory controller 22 .
  • the target number is determined according to the ingress traffic, and the A target number of write commands is selected from the write commands cached in the memory controller, and the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller.
  • the ingress traffic When the ingress traffic is low, the number of received commands is small, and the read commands blocked by write commands are also few. Therefore, the lower the ingress traffic, the larger the target number.
  • determining the number of targets may also include the following methods:
  • the memory controller 22 determines the target number according to the bandwidth utilization rate; the lower the bandwidth utilization rate, the larger the target number. In this embodiment, the memory controller 22 may first determine the bandwidth utilization, and determine the target number corresponding to the bandwidth utilization. Because the flow sizes of read commands and write commands entering the memory controller 22 are not the same, correspondingly, corresponding target numbers can be set corresponding to different bandwidth utilization rates.
  • FIG. 5 is a schematic flowchart of determining the target number according to the bandwidth utilization of the memory controller 22. Referring to FIG. 5, the above method may include steps S501-S503:
  • the memory controller 22 determines the bandwidth utilization rate; wherein, the bandwidth utilization rate may be collected in real time, or collected at regular intervals.
  • step S502 The memory controller 22 judges whether the bandwidth utilization is not greater than the utilization threshold, and when the bandwidth utilization is not greater than the utilization threshold, step S503 is performed.
  • the utilization threshold may be set to 50%, and when the bandwidth utilization is not greater than 50%, the target number is determined.
  • the memory controller 22 determines the target number according to the bandwidth utilization rate. The lower the bandwidth utilization, the larger the target number. Exemplarily, when the bandwidth utilization of the memory controller is 40%, the target number is 10, and when the bandwidth utilization of the memory controller is 30%, the target number is 20.
  • the memory controller 22 determines the target number according to the total number of cached write commands; the greater the total number of write commands, the greater the target number.
  • FIG. 6 is a schematic flowchart of the memory controller 22 determining the target number according to the total number of cached write commands.
  • the above method may include steps S601-S603:
  • S601 The memory controller 22 determines the total number of buffered write commands.
  • step S602 The memory controller 22 determines whether the total number of cached write commands is greater than the write command number threshold, and when the total number of cached write commands is greater than the write command number threshold, step S603 is performed; exemplarily, the write command number threshold can be set is 40, when the total number of write commands is greater than 40, the target number is determined.
  • the memory controller 22 determines the target number according to the total number of cached write commands. Exemplarily, a value range of the total number of write commands may be set, and each value range corresponds to a value of a target number. When the total number of write commands is 40-50, the target number is determined to be 10, and when the total number of write commands is 50-60, the target number is determined to be 15.
  • a set rule may be used to select a target write command from the write commands buffered in the memory controller 22, so as to improve the speed of continuously sending the target write command.
  • a target write command is selected from the write commands cached in the memory controller according to a set rule, and the target write command is The priority of the command is higher than the priority of the write command cached in the memory controller.
  • the setting rules can be freely set by those skilled in the art, the purpose of which is to improve the speed at which the memory 23 continuously processes write commands. Specifically, the continuous execution of the write commands selected from the write commands cached in the memory controller according to the set rule in the memory 23 is faster than the random selection of write commands, thereby reducing the delays for read commands blocked by write commands.
  • the setting rule includes at least one of the following:
  • the quantity belonging to the same memory address set in the selected target write command is less than the set quantity threshold, wherein the memory includes a plurality of memory spaces, each memory space corresponds to a memory address set, and each write command includes a memory address;
  • the selected target write command is located in the same memory row, wherein the write command further includes memory row information, and the memory row corresponding to the write command is determined according to the memory row information included in the write command.
  • Setting rule 1 The number of the selected target write commands belonging to the same memory address set is less than the set number threshold.
  • the data in the memory is written into a large matrix in units of bits, and each unit is called CELL.
  • the memory executes a read command or a write command
  • the bank of the memory chip also called the logic bank. Due to the memory manufacturing process, it is difficult to make the row-column array very large. Therefore, in general memory, the memory capacity is divided into several row-column arrays to manufacture, that is, there are multiple logical banks in the memory.
  • BG logical group bank groups
  • the memory controller 22 selects the write commands cached in the memory controller from the write commands in the memory controller.
  • the write command whose number belonging to the same memory address set is less than the set quantity threshold is selected as the target write command.
  • one or more write commands respectively located in each memory address set may be selected from the write commands cached in the memory controller, and the number of the plurality of write commands is less than the set number threshold.
  • the operation on the address needs to open the memory line in the above memory address, and it also takes a certain time to open the memory line in the memory address. If the memory 23 continuously processes write commands, the memory corresponding to the address of each write command processed is different. , it will slow down the execution speed of the write command.
  • the memory 23 can save the time for opening the memory rows, thereby improving the execution speed of the write commands.
  • the memory controller 22 when selecting a write command from the write commands cached in the memory controller, the memory controller 22 first determines whether there is a write command corresponding to the same memory row, and if so, caches it from the memory controller Among the write commands, select a write command corresponding to the same memory row and send it to the memory 23 .
  • the method may include:
  • the priority of the first write command is increased, and the memory address included in the first write command cached in the memory controller is the same as the memory address included in the first read command cached in the memory controller.
  • the memory controller 22 may first determine the memory address corresponding to the first read command; Find out whether there is a first write command with the same memory address as the read command in the write command cached in the memory controller.
  • the priority of the first write command is increased, thereby indirectly improving the processing speed of the first read command.
  • the memory controller 22 may raise the priority of the first write command to be higher than the first read command, so that the memory 23 processes the first write command before the first read command, or may also The priority of the first write command is raised to the highest, and the first write command is directly sent to the memory 23 for execution.
  • the method may further include:
  • the memory address included in the second write command cached in the memory controller is the same as the second read data cached in the memory controller.
  • the commands contain the same memory addresses.
  • the memory controller 22 After receiving the second read command from the processor, according to the memory address corresponding to the second read command, find out whether there is a memory address corresponding to the second read command in the write command cached in the memory controller The same second write command. When there is a first write command with the same memory address as the data corresponding to the second read command, the memory controller 22 returns the write data corresponding to the second write command to the processor 21 as the read data of the second read command, and further Improved average latency of read commands.
  • sending the read command and the write command buffered in the memory controller to the memory including: according to the first sending cycle, sending the write command buffered in the memory controller to the memory; according to the second sending cycle, sending all the The read command buffered in the memory controller described above is sent to the memory.
  • the memory 23 may support different memory protocols or be in different system business scenarios, and different memory protocols correspond to different memory 23 processing read commands and write commands at different speeds.
  • the memory controller 22 according to the first sending cycle, The write command buffered in the memory controller is sent to the memory 23; the memory controller 22 sends the read command buffered in the memory controller to the memory according to the second sending cycle.
  • the first transmission period and the second transmission period may be the same or different. Exemplarily, if the target write command selected based on the set rule is continuously sent to the memory 23, the interval for issuing the target write command can be shortened to improve the bandwidth utilization of the memory controller.
  • both the first sending period and the second sending period may be 0, that is, when each read command or write command is issued, it is sent without interval.
  • the method further includes: :
  • the memory controller 22 will no longer buffer the received write command in the memory controller, and the memory controller 22 will not buffer the received write command until the memory control
  • the memory controller 22 continues to buffer the write commands.
  • the embodiment of the present application provides a memory control method, which can reduce the average delay of read commands while taking into account high bandwidth utilization, so as to solve the problem that when the average delay of read commands is high, the delay performance of the entire memory system is caused worse problem.
  • the average latency of read commands is reduced by identifying the ingress traffic of the memory controller. Specifically, when the ingress traffic is high, the priority of the cached read commands will be increased to ensure that the latency-sensitive read commands can be executed quickly. Scheduling, while the write commands are temporarily cached; when the ingress traffic is low, the received read commands and write commands are few, and the write commands that are not sensitive to the delay will be sent to ensure that the cached write commands are not backlogged. There are also very few read commands blocked by write commands.
  • the embodiments of the present application can increase the priority of the target number of write commands, which not only ensures that too many write commands are not accumulated in the memory controller, but also prevents the read commands from being blocked by the write commands for too long.
  • the rules to select and increase the priority of the target write command the speed at which the memory continuously processes the write command can be accelerated, so the time that the read command is blocked by the write command can also be reduced.
  • FIG. 7 is a schematic diagram of a memory control device 700 provided by an embodiment of the present application, the functions of each module in the memory control device 700 are described below with reference to FIG. 7 :
  • the memory control device 700 includes: an ingress traffic judging module 701 and a command issuing module 702;
  • the ingress traffic judging module 701 is configured to determine the priority of the read command and the write command cached in the memory controller according to the ingress traffic of the memory controller, where the ingress traffic is the memory control per unit time The sum of the number of read commands and write commands received by the receiver;
  • the command issuing module 702 is configured to send the read command and the write command buffered in the memory controller to the memory according to the order of the priority from high to low.
  • the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller class.
  • the set conditions include at least one of the following:
  • the ingress flow of the memory controller is greater than the set threshold
  • the total number of write commands cached in the memory controller is not greater than the write command number threshold
  • the bandwidth utilization of the memory controller is greater than the utilization threshold.
  • the ingress flow determination module 701 is further configured to determine the target quantity according to the ingress flow when the ingress flow of the memory controller does not meet the set condition, and select the target quantity from the memory controller.
  • a target number of write commands is selected from the cached write commands, and the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller.
  • the ingress flow determination module 701 is further configured to, when the ingress flow of the memory controller does not meet a set condition, select from the write command cached in the memory controller according to a set rule A target write command is selected, the priority of the target write command is higher than the priority of the write command cached in the memory controller.
  • the setting rule includes at least one of the following:
  • the quantity belonging to the same memory address set in the selected target write command is less than the set quantity threshold, wherein the memory includes a plurality of memory spaces, each memory space corresponds to a memory address set, and each write command includes a memory address;
  • the selected target write command is located in the same memory row, wherein the write command also includes memory row information, and the memory row corresponding to the write command is determined according to the memory row information included in the write command.
  • the memory control apparatus further includes a priority adjustment module 703; the priority adjustment module is configured to increase the priority of the first write command, the first write command cached in the memory controller
  • the memory address included in the command is the same as the memory address included in the first read command cached in the memory controller.
  • the memory control apparatus further includes a read data determination module 704, which is configured to use the to-be-written data corresponding to the second write command as the second For the data to be read of the read command, the memory address included in the second write command cached in the memory controller is the same as the memory address included in the second read command cached in the memory controller.
  • the memory control apparatus further includes a write command quantity judgment module 705, the write command quantity judgment module 705 is configured to have a total quantity of write commands cached in the memory controller greater than the total quantity When the threshold is exceeded, write commands are no longer cached.
  • the command issuing module 702 is further configured to send the write command buffered in the memory controller to the memory according to the first sending cycle; according to the second sending cycle, send the memory control The read command buffered in the server is sent to memory.
  • each functional module in each embodiment of the present application It can be integrated in one processing unit, or it can exist physically alone, or two or more modules can be integrated in one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .
  • FIG. 8 is a schematic diagram of an example of a memory controller.
  • the memory controller 800 includes the following modules: a read command storage module 801, a write command storage module 801, a A command storage module 802 , a command scheduling module 803 , a command conflict management module 804 , a write data storage module 805 and a read data storage module 806 .
  • the read command storage module 801 is used for receiving and buffering the read command from the processor;
  • the write command storage module 802 is used for receiving and buffering the write command from the processor
  • the command scheduling module 803 is configured to send the read command and the write command buffered in the memory controller to the memory according to the order of the priority from high to low;
  • the command conflict management module 804 is configured to determine the priority of read commands and write commands cached in the memory controller according to the ingress traffic of the memory controller, where the ingress traffic is the memory control per unit time The sum of the number of read commands and write commands received by the receiver;
  • the write data storage module 805 is used to store the write data corresponding to the write command
  • the read data storage module 806 is used to store the read data corresponding to the read command
  • the priority of the read command buffered in the memory controller is higher than the priority of the write command buffered in the memory controller class.
  • the set conditions include at least one of the following:
  • the ingress flow of the memory controller is greater than the set threshold
  • the total number of write commands cached in the memory controller is not greater than the write command number threshold
  • the bandwidth utilization of the memory controller is greater than the utilization threshold.
  • the command conflict management module 804 is further configured to determine the target quantity according to the ingress traffic when the ingress traffic of the memory controller does not meet the set condition, and extract the target quantity from the cached data from the memory controller.
  • a target number of write commands is selected from the write commands, and the priority of the target number of write commands is higher than the priority of the write commands cached in the memory controller.
  • the command conflict management module 804 is further configured to select a target from the write commands cached in the memory controller according to a set rule when the ingress traffic of the memory controller does not meet a set condition A write command, the priority of the target write command is higher than the priority of the write command cached in the memory controller.
  • the setting rule includes at least one of the following:
  • the quantity belonging to the same memory address set in the selected target write command is less than the set quantity threshold, wherein the memory includes a plurality of memory spaces, each memory space corresponds to a memory address set, and each write command includes a memory address;
  • the selected target write command is located in the same memory row, wherein the write command further includes memory row information, and the memory row corresponding to the write command is determined according to the memory row information included in the write command.
  • command conflict management module 804 is also used to:
  • the priority of the first write command is increased, and the memory address included in the first write command cached in the memory controller is the same as the memory address included in the first read command cached in the memory controller.
  • command conflict management module 804 is also used to:
  • the memory address included in the second write command cached in the memory controller is the same as the second read data cached in the memory controller.
  • the commands contain the same memory addresses.
  • the write command storage module 802 is further configured to:
  • command scheduling module 803 is further configured to:
  • Sending the read command and write command buffered in the memory controller to the memory includes: according to a first sending cycle, sending the write command buffered in the memory controller to the memory; according to a second sending cycle, sending the Read commands buffered in the memory controller are sent to memory.
  • the memory controller 800 further includes a configuration information storage module 807, and the configuration information storage module 807 is configured to store relevant parameters for judging ingress traffic, for example, the set threshold, write Command count thresholds, utilization thresholds, and so on.
  • the configuration information storage module 807 is further configured to store content such as the type of protocol supported by the memory connected to the memory controller 800 .
  • command conflict management module 804 is used to:
  • the read command storage module 801 receives a read command and the write command storage module 802 receives a write command, the module is activated to determine the read command buffered by the read command storage module 801 and the write command buffered by the write command storage module 802 priority between;
  • the read command storage module 801 is hibernated at other times to reduce the power consumption of the entire memory controller.
  • the embodiments of the present application provide an electronic device, the electronic device includes a processor, a memory controller, and a memory, and the memory controller on the electronic device is configured to execute the memory control methods provided by the above embodiments.
  • the embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a computer, the computer executes the memory provided by the above embodiments. Control Method.
  • the embodiments of the present application further provide a computer program product, which, when the computer program runs on a computer, enables the computer to execute the memory control method provided by the above embodiments.
  • the storage medium may be any available medium that the computer can access.
  • computer readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or be capable of carrying or storing instructions or data structures in the form of desired program code and any other medium that can be accessed by a computer.
  • the embodiments of the present application further provide a chip, where the chip is used to read a computer program stored in a memory to implement the memory control methods provided by the above embodiments.
  • the use of a memory control method and a memory control device provided by the present application can reduce the average delay of read commands while taking into account high bandwidth utilization, so as to solve the problem that when the average delay of read commands is high, the The problem of poor latency performance of the entire memory system.
  • the average delay of read commands is reduced by identifying the ingress traffic of the memory controller. When the ingress traffic is high, the priority of the cached read commands will be increased to ensure that the read commands that are more sensitive to the delay can be quickly scheduled.
  • Write commands are temporarily cached; when the ingress traffic is low, few read commands and write commands are received, and write commands that are not sensitive to delay are sent to ensure that the cached write commands are not backlogged and blocked by write commands. There are also very few read commands.
  • the embodiments of the present application can increase the priority of the target number of write commands, which not only ensures that too many write commands are not accumulated in the memory controller, but also prevents the read commands from being blocked by the write commands for too long.
  • the speed at which the memory continuously processes the write command can be accelerated, so the time that the read command is blocked by the write command can also be reduced.
  • each module in the memory controller can choose to perform read commands and write commands when the traffic is not large according to business needs, so the circuit overhead is small, which can reduce the power consumption of the entire system.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

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Abstract

本申请公开了一种内存控制方法及内存控制装置，所述方法包括：根据所述内存控制器的入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级；根据所述优先级从高到低的顺序，将所述内存控制器中缓存的读命令以及写命令发送到内存。利用本申请提供的方法能在兼顾较高带宽利用率的同时能降低读命令的平均延时，以解决在读命令平均延时较高时，导致整个内存系统的延时性能较差的问题。

Description

一种内存控制方法及内存控制装置 技术领域
本申请涉及内存技术领域，特别涉及一种内存控制方法及内存控制装置。
背景技术
内存又称为内部存储器，其作用是用于暂时存放中央处理器(central processing unit，CPU)中的运算数据，以及与硬盘等外部存储器交换数据。而内存控制器(memory controller)用于管理从内存到CPU之间的数据交换。内存控制器可以是一个单独的芯片，也可以集成到内部存储器或CPU中。内存控制器的性能直接影响CPU对内存中数据的读写速度，而影响内存控制器的性能的两个重要参数为：带宽利用率和延时。其中，带宽利用率是指在一定时间内，内存控制器的接口数据传输速度与最大传输速度的比值。而延时是指从接收CPU发送的读命令或写命令，到向CPU反馈内存完成读命令或写命令之间的时间间隔。
有鉴于此，随着计算机技术的发展，内存的传输速度也越来越高，内存控制器为了匹配带宽利用率，在设计上也越来越复杂。图1A所示的内存控制器是以保证高带宽利用率为前提设计的。参阅图1A所示：读命令以及写命令通过命令接口进入内存控制器后均会存放在命令队列中，命令调度模块会基于贪心算法，尽快的调度命令队列中缓存的命令，以保证内存控制器有较高的带宽利用率，命令调度模块还在调度一个命令后告知时序判断模块，由时序判断模块识别命令的类型后，加载不同的计数器，以保证各个命令在调度时满足时序参数，待计数器计数完毕后，由命令调度模块再从命令队列中选择命令进行调度，写数据传输模块用于接收由处理器下发的与写命令对应的写数据，并在写命令发送到内存时，将写数据一起发送到内存中，读数据传输模块用于接收由内存发送的读数据，并将读数据发送给处理器。
实际上，处理器在下发命令时，通常会随机的下发写命令和读命令，内存控制器为了保证高带宽利用率，仍会采用贪心算法从命令队列调度命令。例如：内存控制器会将先收到的写命令调度到内存，等待写命令在内存执行完毕后才能继续将读命令调度到内存执行，相当于内存控制器按处理器随机下发的顺序从命令队列中连续调度命令，此种方式总体上均分了读命令和写命令的平均延时，但实际上读命令相比写命令对于延时更加敏感。在读命令的平均延时较高时，会导致整个内存系统的延时性能较差，而读命令的平均延时过高是现有的内存系统难以容忍的。有鉴于此，如何在兼顾较高带宽利用率的同时降低对延时比较敏感的读命令的平均延时，是本领域亟待解决的问题。
发明内容
有鉴于此，本申请提供一种内存控制方法及内存控制装置，基于内存控制器的入口流量，在内存控制器入口流量较高时，使读命令优先级高于写命令从而发送读命令，并在内存控制器入口流量较低时，下发一部分缓存的写命令，此时，由于内存控制器入口流量较低，处理器下发的读命令以及写命令很少，因此，被下发的写命令阻塞的读命令也很少，所以因阻塞导致的读命令延时增加可以忽略。从总体上来看，相比于现有的命令调度方式，读命令的平均延时明显降低，因此，能够在兼顾较高利用率的同时降低读命令的平均延时。
第一方面，本申请实施例提供一种内存控制方法，该方法可以应用于内存控制器，主要包括以下步骤：根据所述内存控制器的入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级，所述入口流量为单位时间内所述内存控制器接收的读命令与写命令的数量之和；根据所述优先级从高到低的顺序，将所述内存控制器中缓存的读命令以及写命令发送到内存。
其中，为了解决读命令平均延时较高，导致整个内存系统的延时性能较差的问题，首先需要识别内存控制器的入口流量，基于不同的内存控制器入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级，根据所述读命令以及写命令的优先级，将所述内存控制器中缓存的读命令以及写命令发送到内存。因此，在入口流量较高时，能越快的将读命令发送至内存，使内存尽快处理，在入口流量较低时，接收到的读命令以及写命令很少，将对于延时不敏感的写命令进行发送，保证缓存的写命令不积压过多的同时被写命令阻塞的读命令也很少。从总体来看，在内存控制器调度的读命令中，快速调度的占大多数而被阻塞仅占很少一部分。
接下来，将对本方法进行进一步的说明：
在一种可能的实施方式中，在所述内存控制器的入口流量满足设定条件时，所述内存控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级。利用此方法，在入口流量较高时，在所述内存控制器中缓存的读命令的优先级要高于所述内存控制器中缓存的写命令的优先级，因此能够在所述内存控制器的入口流量满足设定条件时，保证读命令的低延时。
在一种可能的实施方式中，所述设定条件，包括以下至少一项：所述内存控制器的入口流量大于设定阈值；所述内存控制器中缓存的写命令总数量不大于写命令数量阈值；所述内存控制器的带宽利用率大于利用率阈值。
在写命令缓存队列中缓存的写命令的总数量不大于写命令数量阈值时，表明此时，内存控制器中还未堆积过多写命令，此时，所述内存控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级，需要优先保证读命令的优先调度。
带宽利用率为内存控制器的当前数据传输速度与最大数据传输速度的比值，当前数据传输速度为当前内存控制器向处理器发送读命令对应的数据的速度与向内存发送写命令对应的数据的速度之和，在内存控制器的带宽利用率大于利用率阈值时，表示此时内存控制器的入口流量较大，需要优先保证读命令的优先调度。
在一种可能的实施方式中，在所述内存控制器的入口流量不满足设定条件时，所述内存控制器中缓存的写命令的优先级高于所述内存控制器中缓存的读命令的优先级。利用此方法能够使得内存控制器中不堆积过多的写命令，缓存在内存控制器的写命令的延时不会过大。
在一种可能的实施方式中，在所述内存控制器的入口流量不满足设定条件时，根据所述入口流量确定目标数量，从所述内存控制器中缓存的写命令中选择目标数量的写命令，所述目标数量的写命令的优先级高于所述内存控制器中缓存的写命令的优先级。利用此方法，使得内存控制器不发送过多的写命令到内存，因发送的写命令数量不多，从而阻塞读命令的数量更少，保证读命令的平均延时始终保持在较低的水平。
在一种可能的实施方式中，在所述内存控制器的入口流量不满足设定条件时，根据设定规则从所述内存控制器中缓存的写命令中选择目标写命令，所述目标写命令的优先级高 于所述内存控制器中缓存的写命令的优先级。利用依据的设定规则从所述内存控制器中缓存的写命令中选择的写命令，相比于无规则选择的写命令的速度更快，也能够显著降低被写命令阻塞的读命令的延时。
其中，所述设定规则可以包括以下至少一项：
选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值，其中，所述内存包含多个内存空间，每个内存空间对应一个内存地址集合，每个写命令包含内存地址；
利用此种规则，能够避免在集中处理写命令缓存队列中的目标写命令时，大量调度归属于同一内存地址集合写命令，从而影响执行效率；
选择的目标写命令位于同一内存行，其中，所述写命令还包含内存行信息，根据写命令包含的内存行信息，确定写命令对应的内存行。
而利用此种规则，使得选择的目标写命令位于同一内存行，能够保证在一段时间内向内存发送的写命令对应内存地址中的内存行的行地址均相同，从而节约内存打开行的时间，达到性能的收益。
在一种可能的实施方式中，所述方法还包括：提高第一写命令的优先级，所述内存控制器中缓存的第一写命令包含的内存地址与所述内存控制器中缓存的第一读命令包含的内存地址相同。利用上述方式能防止将第一读命令发送到内存后，因内存中未写入该第一读命令对应的数据，使得第一读命令无法执行或延迟执行的问题。使得对于延时敏感的读命令在发送到内存后，内存能顺利的执行该读命令，以降低读命令的平均延时。
进一步的，为了提升对于延时敏感的读命令的执行速度，在一种可能的实施方式中，所述方法还包括：将第二写命令对应的待写入数据作为第二读命令的待读取数据，所述内存控制器中缓存的第二写命令包含的内存地址与所述内存控制器中缓存的第二读命令包含的内存地址相同。利用上述方式同样能防止将读命令发送到内存后，因内存中未写入第二读命令对应的数据，使得第二读命令无法执行或延迟执行的问题。并且，由于无需内存处理第二读命令，内存控制器就已经得到了第二读命令对应的读数据，因此，可以提升对于第二读命令的调度速度，进一步降低读命令的平均延时。
在一种可能的实施方式中，所述方法还包括：在所述内存控制器中缓存的写命令的总数量大于总数量阈值时，不再缓存写命令。利用上述方式，能够保证写命令缓存队列中不缓存过多的写命令，保证内存控制器正常运行。
在一种可能的实施方式中，将所述内存控制器中缓存的读命令以及写命令发送到内存，包括：按照第一发送周期，将所述内存控制器中缓存的写命令发送到内存；按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。利用上述方式，可以根据不同内存协议或者不同系统业务场景来配置不同的命令发送周期，从而保证了内存控制器的带宽。
第二方面，本申请实施例提供一种内存控制装置，该内存控制装置可以实现上述第一方面中任一项所提供的内存控制方法。第二方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。
所述内存控制装置包括：入口流量判断模块以及命令下发模块；
所述入口流量判断模块，用于根据所述内存控制器的入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级，所述入口流量为单位时间内所述内存控制器接收的读命令与写命令的数量之和；
所述命令下发模块，用于根据所述优先级从高到低的顺序，将所述内存控制器中缓存 的读命令以及写命令发送到内存。
在一些可能的实施方式中，在所述内存控制器的入口流量满足设定条件时，所述内存控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述设定条件，包括以下至少一项：
所述内存控制器的入口流量大于设定阈值；
所述内存控制器中缓存的写命令总数量不大于写命令数量阈值；
所述内存控制器的带宽利用率大于利用率阈值。
在一些可能的实施方式中，所述入口流量判断模块还用于在所述内存控制器的入口流量不满足设定条件时，根据所述入口流量确定目标数量，从所述内存控制器中缓存的写命令中选择目标数量的写命令，所述目标数量的写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述入口流量判断模块还用于在所述内存控制器的入口流量不满足设定条件时，根据设定规则从所述内存控制器中缓存的写命令中选择目标写命令，所述目标写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述设定规则包括以下至少一项：
选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值，其中，所述内存包含多个内存空间，每个内存空间对应一个内存地址集合，每个写命令包含内存地址；
选择的目标写命令位于同一内存行，其中，所述写命令还包含内存行信息，根据写命令包含的内存行信息，确定写命令对应的内存行。
在一些可能的实施方式中，所述内存控制装置还包括优先级调整模块；所述优先级调整模块，用于提高第一写命令的优先级，所述内存控制器中缓存的第一写命令包含的内存地址与所述内存控制器中缓存的第一读命令包含的内存地址相同。
在一些可能的实施方式中，所述内存控制装置还包括读数据确定模块，所述读数据确定模块，用于将第二写命令对应的待写入数据作为第二读命令的待读取数据，所述内存控制器中缓存的第二写命令包含的内存地址与所述内存控制器中缓存的第二读命令包含的内存地址相同。
在一些可能的实施方式中，所述内存控制装置还包括写命令数量判断模块，所述写命令数量判断模块，用于在所述内存控制器中缓存的写命令的总数量大于总数量阈值时，不再缓存写命令。
在一些可能的实施方式中，所述命令下发模块还用于按照第一发送周期，将所述内存控制器中缓存的写命令发送到内存；按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。
第三方面，本申请实施例还提供一种处理器，该处理器可以包括处理器核和上述第一方面所涉及的内存控制器，处理器核可以向内存控制器发送写命令和读命令，内存控制器可以在接收到写命令和读命令后，将写命令和读命令发送到内存。
第四方面，本申请实施例提供一种电子设备，该电子设备包括处理器、内存控制器以及内存，电子设备上的内存控制器用于执行第一方面中任一项所提供的内存控制方法。
第五方面，本申请实施例还提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当其在内存控制器上运行时，使得内存控制器执行上述各方面的方法。
第六方面，本申请实施例还提供一种包括指令的计算机程序产品，当其在内存控制器 上运行时，使得内存控制器执行上述各方面的方法。
第七方面，本申请实施例还提供了一种芯片，芯片用于读取存储器中存储的计算机程序，当计算机程序被执行时，能实现上述各方面的方法。
本申请的这些方面或其它方面在以下实施例的描述中会更加简明易懂。
附图说明
图1A为一种现有的内存控制器的示意图；
图1B为存储阵列及外围的控制电路的示意图；
图2为一种电子设备的结构示意图；
图3为一种内存控制方法的示意图；
图4为内存控制器的入口流量示意图；
图5为根据内存控制器的带宽利用率确定目标数量的流程示意图；
图6为根据内存控制器缓存的写命令的总数量确定目标数量的流程示意图；
图7为一种内存控制装置的示意图；
图8为一种内存控制器实例的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，示例性的，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
以下，先对本申请实施例中涉及的部分用语进行解释说明，以便于本领域技术人员容易理解。
(1)内存控制器(memory controller)用于管理从内存到处理器间的数据交换。它可以是一个单独的芯片，或者集成到内存或处理器中。
(2)内存，又叫内部存储器，其作用是用于暂时存放处理器中的运算数据，以及与硬盘等外部存储器交换数据。内存的工作原理是利用其电容来存储电荷，利用电荷的多寡来代表一个二进制比特是1还是0。多个单比特存储单元的重复排列构成了存储阵列。图1B所示的存储阵列加上外围的控制电路，构成了内存。
(3)动态随机存储器堆块地址(dynamic random access memory bank address，BA)。其中，bank为内存空间的含义，一块内存可以划分为多个内存空间，访问的时候指定内存空间编号，就可以访问指定的内存空间。具体内存中划分了多少个bank，取决于地址线中有几位BA地址。例如，如果BA地址为两位，说明有4个bank；如果BA地址为3位，说明有8个bank。
(4)动态随机存储器堆块组(dynamic random access memory bank group，BG)。一块内存可以划分为多个分组bank group，而每个bank group可以独立的读写数据，这样内部的数据吞吐量大幅提升，同时可以读取大量的数据，内存的等效频率也得到了提升。示例性的，在DDR4的架构上使用了两个或四个可选择的独立分组。
(5)北桥(northbridge)，是主板芯片组中起主导作用的最重要的组成部分，就是主板上离处理器最近的一块芯片，负责与处理器的联系并控制内存，作用是在处理器与PCI总线、内存、AGP(accelerated graphics port，图形加速端口)和二级缓存之间建立通信接口。
(6)贪心算法，是指在对问题求解时，总是做出在当前看来是最好的选择。也就是说，不从整体最优上加以考虑，只做出在某种意义上的局部最优解。贪心算法不是对所有问题都能得到整体最优解，关键是贪心策略的选择，选择的贪心策略必须具备无后效性，即某个状态以前的过程不会影响以后的状态，只与当前状态有关。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
在电子设备(例如智能手机、平板电脑、基站、智能摄像机、自动驾驶车辆的控制器等)中，内存是处理器进行运算的基础，处理器可以通过内存控制器与内存耦合。其中，内存控制器可以与处理器连接，也可以集成在处理器内部。
示例性的，图2为本申请实施例提供的一种电子设备20的结构示意图。电子设备20主要包括处理器21、内存控制器22和内存23。本领域技术人员可以知道，内存控制器22也可以被集成到处理器21或内存23中，也可以被内置于北桥中。本申请实施例不对内存控制器22的具体位置进行限定。当内存控制器22和内存23未集成在一起的情况下，内存控制器22和内存23之间通过内存总线25连接。
处理器21是电子设备20的运算核心(core)和控制核心(control unit)，处理器21还可以是一块超大规模的集成电路。在处理器21中安装有操作系统和其他软件程序，从而处理器21能够实现对电子设备20的内存23的访问。本领域技术人员可以知道，处理器21可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合。处理器21还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。随着集成电路工艺的发展，处理器21中可以集成越来越多的处理器核(core)。当处理器21中集成有多个处理器核时，多个处理器核之间可以通过片上网络来实现互连。可以理解的是，实际应用中，电子设备20还可以包括多个处理器21。本申请实施例以一个处理器为例进行示例。在本申请实施例中不对处理器的数量以及一个处理器中处理器核的数量进行限定。
本申请实施例中，内存控制器22可以包括通信接口和控制电路，内存控制器22可以通过通信接口与处理器21和内存23进行通信。内存控制器22可以将数据写入内存23或从内存23中读取数据。
本申请实施例中，内存23可以是支持双倍速率同步动态随机存储(double data rate synchronous dynamic random access memory，DDR SDRAM)的内存芯片，其中，DDR  SDRAM通常简称为DDR，示例性的，内存23也可以支持第4代DDR(4th DDR，DDR4)，具体如低功耗DDR4(low power DDR4，LPDDR4)。内存23可以支持第5代DDR(5th DDR，DDR5)，具体如低功耗DDR5(low power DDR5，LPDDR5)。
在所述内存控制器22中还可以设置缓存24，缓存24是电子设备20中位于处理器21与内存23之间的临时存储器，在本申请中，缓存24位于内存控制器22中。通常，缓存24可以由静态随机存取存储器(static random access memory，SRAM)组成。缓存24用于暂时存储由处理器21向内存23发送的写数据，以及由内存23向处理器21发送的读数据。
本申请实施例中，内存总线25可以包括数据总线、命令/地址总线以及读数据准备(ready)反馈线。其中，数据总线用于传输数据，命令/地址总线用于传输读命令、写命令等访存命令。需要指出的是，通过内存总线25能够实现内存控制器22与内存23之间双向的数据传输。示例性的，内存控制器22通过向所述内存23发送写命令，并向所述内存23发送写数据，并由所述内存23基于接收的写命令，将所述写数据写入；内存控制器22还可以通过向内存23发送读命令，并由内存23基于接收的读命令，从内部读取读数据，并将所述读数据返回给所述内存控制器22。
需要说明的是，本申请实施例提供的电子设备20中，除了图2所示的器件外，电子设备20还可以包括通信接口以及作为外存的磁盘等其他器件，在此不做限制。
在现有场景下，内存控制器为了保证高带宽利用率，仍会采用贪心算法从命令队列调度命令。例如：内存控制器会将先收到的写命令调度到内存，等待写命令在内存执行完毕后才能继续将读命令调度到内存执行，相当于内存控制器按处理器随机下发的顺序从命令队列中连续调度命令，此种方式总体上均分了读命令和写命令的平均延时，但实际上读命令相比写命令对于延时更加敏感。在理想情况下，在所述内存控制器接到读命令后，能够越快从内存读取读数据，并越快将所述读数据返回处理器越好，而由于写命令对于延时不敏感，所以内存控制器在接收到写命令后的一段时间内，将写命令及写数据发送至内存即可。在目前的调度方式下，读命令的平均延时仍然较高，而在读命令的平均延时较高时，会导致整个内存系统的延时性能较差。
有鉴于此，本申请实施例提供一种内存控制方法及内存控制装置，能在兼顾较高带宽利用率的同时能降低读命令的平均延时，以解决在读命令平均延时较高时，导致整个内存系统的延时性能较差的问题。本实施例中，首先对于内存控制器的入口流量进行识别，针对不同的入口流量，确定在内存控制器中缓存的读命令以及写命令的优先级，在入口流量较高时，将缓存的读命令的优先级提高，保证对延时较为敏感的读命令能够快速调度，而写命令暂时缓存；在入口流量较低时，接收到的读命令以及写命令很少，将一部分缓存的写命令的优先级提高，将对于延时不敏感的写命令进行发送，保证缓存的写命令不积压过多的同时，被写命令阻塞的读命令也很少。从总体来看，在内存控制器调度的读命令中，快速调度的占大多数而被阻塞仅占很少一部分。因此，利用本申请提供的方法能在兼顾较高带宽利用率的同时显著降低读命令的平均延时。
以下结合上述图2所示的电子设备20对本申请实施例提供的一种内存控制方法进行详细介绍。图3为本申请实施例提供的一种内存控制方法的流程图，下面参阅图3所示的方法流程图对该方法进行详细说明。
其中，为了解决读命令平均延时较高时，导致整个内存系统的延时性能较差的问题， 首先需要识别内存控制器的入口流量，基于不同的内存控制器入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级后，将所述内存控制器中缓存的读命令以及写命令发送到内存。
参阅图3所示，本申请提供的一种内存控制方法，包括步骤S301～S303：
S301：内存控制器22接收来自处理器21的读命令以及写命令，将所述读命令以及写命令进行缓存。
其中，所述读命令用于读取内存23中的读数据。由处理器21下发的每个读命令中包含在内存23中所述读数据所在的地址，所述读数据为所述读命令对应的待读取的数据；而所述写命令用于向内存23中存储写数据，每个写命令中包含在内存23中所述写数据被存储的地址，所述写数据为所述写命令对应的待存储的数据；
可选的，内存控制器22在接收来自处理器21发送的命令后，可以按照读命令和写命令的类型，将读命令缓存到读命令缓存队列，将写命令缓存到写命令缓存队列；或者，还可以将读命令以及写命令都缓存到命令缓存队列中，具体缓存的方式这里不做限定，本领域技术人员应当知晓，这里不再赘述。
此外，为了保证内存控制器22中不积压过多的写命令，在一些可能的实施方式中，在所述写命令缓存队列可以设置有写命令数量上限，当所述写命令缓存队列中的写命令数量达到写命令数量上限时，不再将处理器21发送的写命令存储在写命令缓存队列中。
S302：内存控制器22根据所述内存控制器22的入口流量，确定所述内存控制器22中缓存的读命令以及写命令的优先级；
所述入口流量为单位时间内所述内存控制器接收的读命令与写命令的数量之和；我们了解，下发到内存控制器的命令的流量不是均匀的，而是存在入口流量高的波峰和入口流量低的波谷的。而在所述内存控制器22的入口流量较大即波峰时，表示所述内存控制器接收的读命令与写命令的数量很多，因此，按现有方式以贪心算法调度命令时，会出现大量调度写命令而不考虑读命令的情况，读命令对于延时更为敏感，读命令的平均延时较高，会导致整个内存控制器的延时性能较差。
其中，确定内存控制器的入口流量的方式可以对当前接收到的命令数量进行统计，例如：接收到的命令数量越多，当前的入口流量越大，或者，还可以基于内存控制器22的带宽利用率进行确定，带宽利用率越高，入口流量越高。所述带宽利用率是指在一定的时间内，内存控制器22的数据传输速度与最大传输速度的比值。
可选的，在本申请实施例中，内存控制器22可以在入口流量较大时，尽量多的调度读命令，以保证读命令的低延时，而在内存控制器22的入口流量较小时，调度一部分写命令保证在内存控制器22中不积压过多写命令，并且因入口流量较低，被写命令阻塞的读命令也会很少。
此外，内存控制器22接收到的读命令和写命令中可以包含被处理器21设置的初始优先级，内存控制器22可以结合初始优先级以及所述内存控制器的入口流量，综合确定所述内存控制器中缓存的读命令以及写命令的优先级。示例性的：内存控制器22接收到4个命令，包括两个读命令和两个写命令(优先级对应数字越小优先级越高)：读命令A的优先级为2、读命令B的优先级为4、写命令C的优先级为1、写命令D的优先级为3，在当前在入口流量较大时，所述读命令A的优先级被重新设置为1、读命令B的优先级被重新设置为2、写命令C的优先级被重新设置为3、写命令D的优先级被重新设置为4， 以使读命令优先调度，从而保证读命令的低延时。
在多个读命令的优先级相同时，还可以根据所述读命令对应的读数据大小来确定发送的顺序，示例性的，可以优先发送读命令中对应读数据较小的，因内存执行对应读数据的读命令速度较快，因此可以进一步的降低读命令平均延时。
S303：内存控制器22根据所述优先级从高到低的顺序，将所述内存控制器22中缓存的读命令以及写命令发送到内存23。
在根据内存控制器22的入口流量，确定所述内存控制器22中的读命令以及写命令的优先级后，根据所述优先级从高到低的顺序，将所述内存控制器中缓存的读命令以及写命令发送到内存。
在一些可能的实施方式中，在电子设备20的缓存24中可以设置有读数据缓存空间，内存控制器22可以在接收内存发送的获取读数据后，将读数据缓存在读数据缓存空间中。其中，读数据的发送顺序可以与读数据对应的读命令的优先级相关，优先从读数据缓存空间中发送优先级高的读命令对应的读数据。
在另一些可能的实施方式中，在电子设备20的缓存24中还可以设置有写数据缓存空间，内存控制器22还可以接收处理器21发送的写数据，将所述写数据缓存在写数据缓存空间中，在向内存23发送写命令时，将与所述写命令对应的写数据一同发送至内存23。
此外，所述写数据缓存空间也可以有缓存数据的上限，当所述写数据缓存空间中的写数据占用空间达到缓存数据大小上限时，也不再将处理器21发送的写数据缓存在写数据缓存空间中，同时，不再将处理器21发送的写命令缓存在内存控制器中。
在一些可能的实施方式中，在所述内存控制器22的入口流量满足设定条件时，所述内存控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级。
为了保证读命令的低延时，在满足设定条件时，在所述内存控制器中缓存的读命令的优先级高于所述内存控制器22中缓存的写命令的优先级，使读命令优先调度，从而能降低读命令平均延时。其中，所述设定条件即可以是内存控制器22的入口流量，也可以是用于间接表示入口流量的其他参数，如带宽利用率等，本领域人员应当知晓，任何可以用于确定当前内存控制器22的入口流量的参数均可以应用于本申请实施例中，这里不再赘述。
在一些可能的实施方式中，所述设定条件，包括以下至少一项：
所述内存控制器22的入口流量大于设定阈值；
所述内存控制器22中缓存的写命令总数量不大于写命令数量阈值；
所述内存控制器22的带宽利用率大于利用率阈值。
其中，所述内存控制器22中缓存的写命令总数量，可以用于间接表示内存控制器22的入口流量，具体的，在内存控制器22的入口流量较高时，所述内存控制器22中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级，因此，每次处理器21在下发读命令以及写命令后，写命令都会缓存在内存控制器中，所以在所述内存控制器22的缓存堆积的总数量大于写命令数量阈值时，表示此时内存控制器22的入口流量较低。示例性的，可以预先设定写命令数量阈值为50，当写命令总数量不大于50，即满足设定条件。
所述内存控制器22中缓存的带宽利用率，也可以用于间接表示内存控制器22的入口流量，其中，所述带宽利用率为所述内存控制器22的当前数据传输速度与最大数据传输 速度的比值，所述当前数据传输速度为当前所述内存控制器22向所述处理器21发送读命令对应的数据的速度与向所述内存23发送写命令对应的数据的速度之和。参阅图4所示的内存控制器上的入口流量示意图可知，内存控制器22中可以对应设置利用率阈值，当所述带宽利用率大于利用率阈值时，表示此时内存控制器22的入口流量较大，即满足设定条件。
为了使内存控制器22中不堆积过多的写命令，在一些可能的实施方式中，在所述内存控制器22的入口流量不满足设定条件时，所述内存控制器22中缓存的写命令的优先级高于所述内存控制器22中缓存的读命令的优先级。
进而，为了保证一次不发送过多的写命令，从而阻塞较多的读命令的调度，在所述内存控制器的入口流量不满足设定条件时，根据所述入口流量确定目标数量，从所述内存控制器中缓存的写命令中选择目标数量的写命令，所述目标数量的写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
因入口流量低时，接收的命令数量少，被写命令阻塞的读命令也很少，因此，入口流量越低，目标数量也就越大。
具体的，确定目标数量还可以包括如下方式：
方式一：内存控制器22根据带宽利用率，确定所述目标数量；所述带宽利用率越低，目标数量越大。在本实施例中，内存控制器22可以首先确定带宽利用率，并且确定与所述带宽利用率对应的目标数量。因为进入内存控制器22读命令以及写命令的流量大小并不相同，相应的，对应不同的带宽利用率可以设置对应的目标数量。
图5为根据所述内存控制器22的带宽利用率确定所述目标数量的流程示意图，参阅图5所示，上述方式可以包括步骤S501-S503：
S501：内存控制器22确定带宽利用率；其中，带宽利用率可以是进行实时采集的，或者每隔一定时间进行采集的。
S502：内存控制器22判断带宽利用率是否不大于利用率阈值，当所述带宽利用率不大于利用率阈值时，执行步骤S503。示例性的，利用率阈值可以设置为50％，当所述带宽利用率不大于50％时，确定所述目标数量。
S503：内存控制器22根据所述带宽利用率，确定所述目标数量。带宽利用率越低，所述目标数量也就越大。示例性的，当所述内存控制器的带宽利用率为40％时，所述目标数量为10，当所述内存控制器的带宽利用率为30％时，所述目标数量为20。
方式二：内存控制器22根据缓存的写命令的总数量，确定所述目标数量；所述写命令的总数量越大，目标数量越大。
参阅图6所示，图6为内存控制器22根据缓存的写命令的总数量，确定所述目标数量的流程示意图，上述方式可以包括步骤S601-S603：
S601：内存控制器22确定缓存的写命令的总数量。
S602：内存控制器22判断缓存的写命令的总数量是否大于写命令数量阈值，当缓存的写命令的总数量大于写命令数量阈值时，执行步骤S603；示例性的，写命令数量阈值可以设置为40，当所述写命令的总数量大于40时，确定所述目标数量。
S603：内存控制器22根据缓存的写命令的总数量，确定所述目标数量。示例性的，可以设置写命令的总数量的取值范围，每个取值范围对应一个目标数量的取值。当所述写命令的总数量处于40-50时，确定所述目标数量为10，当所述写命令的总数量处于50-60 时，确定所述目标数量为15。
为了降低被阻塞的读命令的延时，可以采用设定规则从所述内存控制器22中缓存的写命令中选择目标写命令，以提升连续发送目标写命令的速度。在一些可能的实施方式中，在所述内存控制器22的入口流量不满足设定条件时，根据设定规则从所述内存控制器中缓存的写命令中选择目标写命令，所述目标写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
所述设定规则可以由本领域技术人员自由设定，其目的是为提升内存23连续处理写命令的速度。具体的，在所述内存23中连续执行依据所述设定规则从所述内存控制器中缓存的写命令中选择的写命令，相比于无规则选择的写命令的速度更快，从而降低了被写命令阻塞的读命令的延时。
在一些可能的实施方式中，所述设定规则包括以下至少一项：
选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值，其中，所述内存包含多个内存空间，每个内存空间对应一个内存地址集合，每个写命令包含内存地址；
选择的目标写命令位于同一内存行，其中，所述写命令还包含内存行信息，根据写命令包含的内存行信息，确定写命令对应的内存行。
设定规则一：选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值。
我们了解，在内存内部，内存的数据是以位(bit)为单位写入到一张大的矩阵中的，每个单元我们称为CELL，在所述内存执行读命令或写命令时，确定读命令或写命令的所对应的行(row)，以及对应的列(column)后，即可准确的定位到某个CELL。该行列阵列称为内存芯片的bank，也称作逻辑bank。由于内存制造工艺的原因，行列阵列很难做到很大，因此，一般内存中都是将内存容量分为几个行列阵列来制造，也即，在内存中存在多个逻辑bank。因此，在某些内存协议标准中，可能设置划分出了多个分组逻辑分组bank group(BG)，而每个bank group可以独立的读写数据。对于内存23来说，如果大量的处理归属同一个bank或者同一个bank group的写命令，对内存23的执行命令的效率会有影响。因此，需要避免在让内存23一段时间内大量执行同一个bank或者同一个bank group的命令。
具体的，为了避免发送至内存23的目标写命令中归属于同一内存地址集合(bank或bank gruop)的写命令的数量过多，内存控制器22从所述内存控制器中缓存的写命令中选择目标写命令时，需要首先确定每个写命令包含的内存地址所属的内存地址集合。根据每个写命令包含的内存地址所属的内存地址集合，选择归属同一内存地址集合的数量小于集合数量阈值的写命令为目标写命令。例如，可以从所述内存控制器中缓存的写命令中选择分别位于每个内存地址集合的一个或多个写命令，所述多个写命令的数量小于集合数量阈值。
设定规则二：选择的目标写命令位于同一内存行。
在地址上操作需要打开上述内存地址中的内存行，而打开内存地址中的内存行同样需要一定时间，若内存23在连续处理写命令时，每次处理的写命令对应的地址所在的内存不同，则会降低写命令的执行速度。
那么，若在一段时间内向所述内存23发送对应内存地址中的内存行的行地址均为相同的写命令，则可以使内存23节省打开内存行的时间，从而提高写命令的执行速度。
因此，在从所述内存控制器中缓存的写命令中选择写命令时，由内存控制器22首先 确定是否存在有对应同一内存行的写命令，若存在，则从所述内存控制器中缓存的写命令中选择对应同一内存行的写命令发送至内存23中。
为了提升对于延时敏感的读命令的执行速度，在一些可能的实施方式中，所述方法可以包括：
提高第一写命令的优先级，所述内存控制器中缓存的第一写命令包含的内存地址与所述内存控制器中缓存的第一读命令包含的内存地址相同。
具体的，在接收来自处理器21的发送的第一读命令后，内存控制器22可以首先确定该第一读命令对应的内存地址；并根据所述第一读命令对应的内存地址，在所述内存控制器中缓存的写命令中寻找是否存在与该读命令对应的内存地址相同的第一写命令。当所述写命令缓存队列中存在与该读命令对应的数据的内存地址相同的第一写命令时，提高第一写命令的优先级，间接提升了第一读命令的处理速度。具体的，内存控制器22可以将所述第一写命令优先级提升至第一读命令之上，以使内存23在第一读命令处理之前先处理第一写命令，或者，还可以将所述第一写命令的优先级提升至最高，直接将所述第一写命令发送至内存23进行执行。
为了进一步提升对于延时敏感的读命令的执行速度，在另一些可能的实施方式中，所述方法还可以包括：
将第二写命令对应的待写入数据作为第二读命令的待读取数据，所述内存控制器中缓存的第二写命令包含的内存地址与所述内存控制器中缓存的第二读命令包含的内存地址相同。
具体的，在接收来自处理器的第二读命令后，根据所述第二读命令对应的内存地址，所述内存控制器中缓存的写命令中寻找是否存在与第二读命令对应的内存地址相同的第二写命令。当存在与第二读命令对应的数据的内存地址相同的第一写命令时，内存控制器22将所述第二写命令对应的写数据作为第二读命令的读数据返回处理器21，进一步提升了读命令的平均延时。
目前存在不同内存协议或者不同系统业务场景，对应不同的不同内存协议或者不同系统业务场景需要配置不同的发送周期，将所述读命令以及写命令发送到内存23中，在一些可能的实施方式中，将所述内存控制器中缓存的读命令以及写命令发送到内存，包括：按照第一发送周期，将所述内存控制器中缓存的写命令发送到内存；按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。
其中，所述内存23可能支持不同的内存协议或处于不同的系统业务场景下，而不同的内存协议对应内存23处理读命令以及写命令的速度也不同，内存控制器22按照第一发送周期，将所述内存控制器中缓存的写命令发送到所述内存23；内存控制器22按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。所述第一发送周期和所述第二发送周期既可以相同，也可以不同。示例性的，若向所述内存23连续发送基于所述设定规则选择的目标写命令，则可以将下发所述目标写命令的间隔缩短，以提高内存控制器的带宽利用率。此外，所述第一发送周期和所述第二发送周期均可以为0，即下发每个读命令或写命令时，以无间隔进行发送。
当处理器下发的写命令的速度过快或下发的数量过多时，内存控制器无法快速处理下发的写命令，为了解决该问题，在一些可能的实施方式中，所述方法还包括：
在所述内存控制器中缓存的写命令的总数量大于总数量阈值时，不再缓存写命令。
具体的，当处理器21下发的写命令的速度过快或下发的数量过多时，所述内存控制器22则不再将接收的写命令缓存到内存控制器中，待所述内存控制器中缓存的写命令的总数量大于总数量阈值时，内存控制器22再继续缓存写命令。
本申请实施例提供了一种内存控制方法，能在兼顾较高带宽利用率的同时能降低读命令的平均延时，以解决在读命令平均延时较高时，导致整个内存系统的延时性能较差的问题。以识别内存控制器的入口流量的方式，来降低读命令的平均延时，具体在入口流量较高时，将确定缓存的读命令的优先级提高，保证对延时较为敏感的读命令能够快速调度，而写命令暂时缓存；在入口流量较低时，接收到的读命令以及写命令很少，将对于延时不敏感的写命令进行发送，保证缓存的写命令不积压过多的同时被写命令阻塞的读命令也很少。从总体来看，在内存控制器调度的读命令中，快速调度的占大多数而被阻塞仅占很少一部分。此外，本申请实施例可以提升目标数量的写命令的优先级，既保证内存控制器中不堆积过多的写命令，又使得读命令不被写命令阻塞过久。并且，通过设定规则选择并提升目标写命令的优先级，能加快内存连续处理写命令的速度，因此也能降低读命令被写命令阻塞的时间，综上所述，利用本申请提供的方法能在兼顾较高带宽利用率的同时，能显著降低读命令的平均延时。
参阅图7所示，本申请实施例提供的一种内存控制装置700的示意图，下面结合图7，对内存控制装置700中的各个模块的功能进行介绍：
所述内存控制装置700包括：入口流量判断模块701以及命令下发模块702；
所述入口流量判断模块701，用于根据所述内存控制器的入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级，所述入口流量为单位时间内所述内存控制器接收的读命令与写命令的数量之和；
所述命令下发模块702，用于根据所述优先级从高到低的顺序，将所述内存控制器中缓存的读命令以及写命令发送到内存。
在一些可能的实施方式中，在所述内存控制器的入口流量满足设定条件时，所述内存控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述设定条件，包括以下至少一项：
所述内存控制器的入口流量大于设定阈值；
所述内存控制器中缓存的写命令总数量不大于写命令数量阈值；
所述内存控制器的带宽利用率大于利用率阈值。
在一些可能的实施方式中，所述入口流量判断模块701还用于在所述内存控制器的入口流量不满足设定条件时，根据所述入口流量确定目标数量，从所述内存控制器中缓存的写命令中选择目标数量的写命令，所述目标数量的写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述入口流量判断模块701还用于在所述内存控制器的入口流量不满足设定条件时，根据设定规则从所述内存控制器中缓存的写命令中选择目标写命令，所述目标写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述设定规则包括以下至少一项：
选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值，其中，所述内存包含多个内存空间，每个内存空间对应一个内存地址集合，每个写命令包含内存地址；
选择的目标写命令位于同一内存行，其中，所述写命令还包含内存行信息，根据写命 令包含的内存行信息，确定写命令对应的内存行。
在一些可能的实施方式中，所述内存控制装置还包括优先级调整模块703；所述优先级调整模块，用于提高第一写命令的优先级，所述内存控制器中缓存的第一写命令包含的内存地址与所述内存控制器中缓存的第一读命令包含的内存地址相同。
在一些可能的实施方式中，远端资源管理，所述内存控制装置还包括读数据确定模块704，所述读数据确定模块704，用于将第二写命令对应的待写入数据作为第二读命令的待读取数据，所述内存控制器中缓存的第二写命令包含的内存地址与所述内存控制器中缓存的第二读命令包含的内存地址相同。
在一些可能的实施方式中，所述内存控制装置还包括写命令数量判断模块705，所述写命令数量判断模块705，用于在所述内存控制器中缓存的写命令的总数量大于总数量阈值时，不再缓存写命令。
在一些可能的实施方式中，所述命令下发模块702还用于按照第一发送周期，将所述内存控制器中缓存的写命令发送到内存；按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。
需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，另外，在本申请各个实施例中的各功能模块可以集成在一个处理单元中，也可以是单独物理存在，也可以两个或两个以上模块集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
基于上述实施例提供的内存控制方法以及内存控制器，参阅图8所示，图8为一种内存控制器的实例示意图，具体的，内存控制器800包括如下模块：读命令存储模块801、写命令存储模块802、命令调度模块803、命令冲突管理模块804、写数据存储模块805以及读数据存储模块806。
具体的，所述读命令存储模块801，用于接收并缓存来自处理器的读命令；
所述写命令存储模块802，用于接收并缓存来自处理器的写命令；
所述命令调度模块803，用于根据所述优先级从高到低的顺序，将所述内存控制器中缓存的读命令以及写命令发送到内存；
所述命令冲突管理模块804，用于根据所述内存控制器的入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级，所述入口流量为单位时间内所述内存控制器接收的读命令与写命令的数量之和；
所述写数据存储模块805，用于存储所述写命令对应的写数据；
所述读数据存储模块806，用于存储所述读命令对应的读数据；
在一些可能的实施方式中，在所述内存控制器的入口流量满足设定条件时，所述内存 控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述设定条件，包括以下至少一项：
所述内存控制器的入口流量大于设定阈值；
所述内存控制器中缓存的写命令总数量不大于写命令数量阈值；
所述内存控制器的带宽利用率大于利用率阈值。
在一些可能的实施方式中，命令冲突管理模块804还用于在所述内存控制器的入口流量不满足设定条件时，根据所述入口流量确定目标数量，从所述内存控制器中缓存的写命令中选择目标数量的写命令，所述目标数量的写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，命令冲突管理模块804还用于在所述内存控制器的入口流量不满足设定条件时，根据设定规则从所述内存控制器中缓存的写命令中选择目标写命令，所述目标写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
在一些可能的实施方式中，所述设定规则包括以下至少一项：
选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值，其中，所述内存包含多个内存空间，每个内存空间对应一个内存地址集合，每个写命令包含内存地址；
选择的目标写命令位于同一内存行，其中，所述写命令还包含内存行信息，根据写命令包含的内存行信息，确定写命令对应的内存行。
在一些可能的实施方式中，命令冲突管理模块804还用于：
提高第一写命令的优先级，所述内存控制器中缓存的第一写命令包含的内存地址与所述内存控制器中缓存的第一读命令包含的内存地址相同。
在一些可能的实施方式中，命令冲突管理模块804还用于：
将第二写命令对应的待写入数据作为第二读命令的待读取数据，所述内存控制器中缓存的第二写命令包含的内存地址与所述内存控制器中缓存的第二读命令包含的内存地址相同。
在一些可能的实施方式中，所述写命令存储模块802还用于：
在所述内存控制器中缓存的写命令的总数量大于总数量阈值时，不再缓存写命令。
在一些可能的实施方式中，所述命令调度模块803还用于：
将所述内存控制器中缓存的读命令以及写命令发送到内存，包括：按照第一发送周期，将所述内存控制器中缓存的写命令发送到内存；按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。
在一些可能的实施方式中，所述内存控制器800还包括配置信息存储模块807，所述配置信息存储模块807用于存储用于判断入口流量的相关参数，例如，所述设定阈值、写命令数量阈值以及利用率阈值等等。
在另一些可能的实施方式中，所述配置信息存储模块807还用于存储与该内存控制器800连接的所述内存支持的协议种类等等内容。
此外，所述命令冲突管理模块804用于：
在所述读命令存储模块801接收到读命令以及写命令存储模块802接收到写命令时启动该模块，以确定所述读命令存储模块801缓存的读命令以及写命令存储模块802缓存的写命令之间的优先级；
并在向内存发送命令时启动所述读命令存储模块801，根据所述优先级从高到低的顺 序，将所述内存控制器中缓存的读命令以及写命令发送到内存；
在其他时候休眠所述读命令存储模块801，以降低整个内存控制器的功耗。
基于以上实施例，本申请实施例提供一种电子设备，该电子设备包括处理器、内存控制器以及内存，电子设备上的内存控制器用于执行以上实施例提供的内存控制方法。
基于以上实施例，本申请实施例还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序，所述计算机程序被计算机执行时，使得计算机执行以上实施例提供的内存控制方法。
基于以上实施例，本申请实施例还提供了一种计算机程序产品，当所述计算机程序在计算机上运行时，使得所述计算机执行以上实施例提供的内存控制方法。
其中，存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。
基于以上实施例，本申请实施例还提供了一种芯片，所述芯片用于读取存储器中存储的计算机程序，实现以上实施例提供的内存控制方法。
综上所述，利用本申请提供的一种内存控制方法及内存控制装置能在兼顾较高带宽利用率的同时能降低读命令的平均延时，以解决在读命令平均延时较高时，导致整个内存系统的延时性能较差的问题。以识别内存控制器的入口流量的方式降低读命令的平均延时，在入口流量较高时，将确定缓存的读命令的优先级提高，保证对延时较为敏感的读命令能够快速调度，而写命令暂时缓存；在入口流量较低时，接收到的读命令以及写命令很少，将对于延时不敏感的写命令进行发送，保证缓存的写命令不积压过多的同时被写命令阻塞的读命令也很少。从总体来看，在内存控制器调度的读命令中，快速调度的占大多数而被阻塞仅占很少一部分。此外，本申请实施例可以提升目标数量的写命令的优先级，既保证内存控制器中不堆积过多的写命令，又使得读命令不被写命令阻塞过久。并且，通过设定规则选择并提升目标写命令的优先级，能加快内存连续处理写命令的速度，因此也能降低读命令被写命令阻塞的时间，综上所述，利用本申请提供的方法能在兼顾较高带宽利用率的同时，能显著降低读命令的平均延时。并且内存控制器中的每个模块都可以根据业务需要，选择在读命令以及写命令流量不大的时候进行，因此电路的开销小，从而能够降低整个系统的功耗。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (20)

  1. 一种内存控制方法，应用于内存控制器，其特征在于，所述方法包括：
    根据所述内存控制器的入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级，所述入口流量为单位时间内所述内存控制器接收的读命令与写命令的数量之和；
    根据所述优先级从高到低的顺序，将所述内存控制器中缓存的读命令以及写命令发送到内存。
  2. 根据权利要求1所述的方法，其特征在于，在所述内存控制器的入口流量满足设定条件时，所述内存控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级。
  3. 根据权利要求2所述的方法，其特征在于，所述设定条件，包括以下至少一项：
    所述内存控制器的入口流量大于设定阈值；
    所述内存控制器中缓存的写命令总数量不大于写命令数量阈值；
    所述内存控制器的带宽利用率大于利用率阈值。
  4. 根据权利要求1-3任一所述的方法，其特征在于，在所述内存控制器的入口流量不满足设定条件时，根据所述入口流量确定目标数量，从所述内存控制器中缓存的写命令中选择目标数量的写命令，所述目标数量的写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
  5. 根据权利要求1-3任一所述的方法，其特征在于，在所述内存控制器的入口流量不满足设定条件时，根据设定规则从所述内存控制器中缓存的写命令中选择目标写命令，所述目标写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
  6. 根据权利要求5所述的方法，其特征在于，所述设定规则包括以下至少一项：
    选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值，其中，所述内存包含多个内存空间，每个内存空间对应一个内存地址集合，每个写命令包含内存地址；
    选择的目标写命令位于同一内存行，其中，所述写命令还包含内存行信息，根据写命令包含的内存行信息，确定写命令对应的内存行。
  7. 根据权利要求1-6任一所述的方法，其特征在于，所述方法还包括：
    提高第一写命令的优先级，所述内存控制器中缓存的第一写命令包含的内存地址与所述内存控制器中缓存的第一读命令包含的内存地址相同。
  8. 根据权利要求1-7任一所述的方法，其特征在于，所述方法还包括：
    将第二写命令对应的待写入数据作为第二读命令的待读取数据，所述内存控制器中缓存的第二写命令包含的内存地址与所述内存控制器中缓存的第二读命令包含的内存地址相同。
  9. 根据权利要求1-8任一所述的方法，其特征在于，所述方法还包括：
    在所述内存控制器中缓存的写命令的总数量大于总数量阈值时，不再缓存写命令。
  10. 根据权利要求1-9任一所述的方法，其特征在于，将所述内存控制器中缓存的读命令以及写命令发送到内存，包括：按照第一发送周期，将所述内存控制器中缓存的写命令发送到内存；按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。
  11. 一种内存控制装置，其特征在于，所述装置包括：入口流量判断模块以及命令下发模块；
    所述入口流量判断模块，用于根据所述内存控制器的入口流量，确定所述内存控制器中缓存的读命令以及写命令的优先级，所述入口流量为单位时间内所述内存控制器接收的读命令与写命令的数量之和；
    所述命令下发模块，用于根据所述优先级从高到低的顺序，将所述内存控制器中缓存的读命令以及写命令发送到内存。
  12. 根据权利要求11所述的装置，其特征在于，在所述内存控制器的入口流量满足设定条件时，所述内存控制器中缓存的读命令的优先级高于所述内存控制器中缓存的写命令的优先级。
  13. 根据权利要求12所述的装置，其特征在于，所述设定条件，包括以下至少一项：
    所述内存控制器的入口流量大于设定阈值；
    所述内存控制器中缓存的写命令总数量不大于写命令数量阈值；
    所述内存控制器的带宽利用率大于利用率阈值。
  14. 根据权利要求11-13任一所述的装置，其特征在于，所述入口流量判断模块还用于在所述内存控制器的入口流量不满足设定条件时，根据所述入口流量确定目标数量，从所述内存控制器中缓存的写命令中选择目标数量的写命令，所述目标数量的写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
  15. 根据权利要求11-14任一所述的装置，其特征在于，所述入口流量判断模块还用于在所述内存控制器的入口流量不满足设定条件时，根据设定规则从所述内存控制器中缓存的写命令中选择目标写命令，所述目标写命令的优先级高于所述内存控制器中缓存的写命令的优先级。
  16. 根据权利要求15所述的装置，其特征在于，所述设定规则包括以下至少一项：
    选择的目标写命令中归属同一内存地址集合的数量小于集合数量阈值，其中，所述内存包含多个内存空间，每个内存空间对应一个内存地址集合，每个写命令包含内存地址；
    选择的目标写命令位于同一内存行，其中，所述写命令还包含内存行信息，根据写命令包含的内存行信息，确定写命令对应的内存行。
  17. 根据权利要求11-16任一所述的装置，其特征在于，所述内存控制装置还包括优先级调整模块；所述优先级调整模块，用于提高第一写命令的优先级，所述内存控制器中缓存的第一写命令包含的内存地址与所述内存控制器中缓存的第一读命令包含的内存地址相同。
  18. 根据权利要求11-17任一所述的装置，其特征在于，所述内存控制装置还包括读数据确定模块，所述读数据确定模块，用于将第二写命令对应的待写入数据作为第二读命令的待读取数据，所述内存控制器中缓存的第二写命令包含的内存地址与所述内存控制器中缓存的第二读命令包含的内存地址相同。
  19. 根据权利要求11-18任一所述的装置，其特征在于，所述内存控制装置还包括写命令数量判断模块，所述写命令数量判断模块，用于在所述内存控制器中缓存的写命令的总数量大于总数量阈值时，不再缓存写命令。
  20. 根据权利要求11-19任一所述的装置，其特征在于，所述命令下发模块还用于按照第一发送周期，将所述内存控制器中缓存的写命令发送到内存；按第二发送周期，将所述内存控制器中缓存的读命令发送到内存。
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