WO2018171141A1 - 一种单相电压数字锁相方法 - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
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- the invention relates to a single phase voltage digital phase locking method.
- the three-phase power source forms a vector form in space, it can conveniently use mathematical tools such as spatial coordinate rotation transformation, and form a three-phase digital inverter power phase-locking technology with the principle of digital phase-locked loop.
- mathematical tools such as spatial coordinate rotation transformation, and form a three-phase digital inverter power phase-locking technology with the principle of digital phase-locked loop.
- the power supply voltage has only one phase, it is difficult to directly utilize the characteristics of the space vector for digital phase-locked loop control.
- phase-detection and phase-locked loop control of the existing single-phase power supply voltage it is common to delay the voltage to be measured by 90° to form an orthogonal two-phase voltage signal, and the voltage to be measured and the delayed voltage signal are exactly at ⁇ .
- ⁇ coordinate system two-phase signals perpendicular to each other are formed, and after the plane is rotated, a vector circle is formed, and then a plane coordinate rotation transformation is performed to realize single-phase voltage phase discrimination.
- This method is simple to calculate, but at least one quarter of the data needs to be retained, and the system memory is large.
- the technical solution of the present invention is: a single-phase voltage digital phase-locking method, comprising the following steps:
- Step S1 discretely sampling the voltage signal to be tested u 0 at a sampling frequency f s and constructing a level vector
- u 0 (k) represents the sampled value of the voltage signal u 0 to be tested in the current sampling period
- u 0 (kn) represents that the voltage signal u 0 to be tested is in the nth sampling period before the current sampling period.
- Sampled value, n is a positive integer
- Step S2 constructing a level signal u 1 of frequency f 1 in the current sampling period with f s as the sampling frequency, and constructing a level vector Where u 1 (k) represents a corresponding constructed value in the current sampling period, and u 1 (kn) represents a constructed value corresponding to the nth sampling period of the level signal u 1 before the current sampling period;
- Step S3 Level vector And level vector Performing an orthogonal product operation to obtain a phase difference component V q ; inputting the obtained phase difference component V q into a PI controller, and controlling the loop through the PI controller to adjust the phase difference component V q to 0;
- the incremental angular frequency ⁇ output by the controller and a reference angular frequency ⁇ 0 are cumulatively obtained to obtain an angular frequency ⁇ ′, and are integrated by an integrator to output a phase angle ⁇ ′, and after reaching a steady state, the output phase angle ⁇ ′ is a phase of the voltage signal to be measured;
- the reference angular frequency ⁇ 0 is an angular frequency of the voltage signal u 0 to be measured, and the frequency in the step S2
- the level signal u 1 is a sinusoidal level signal or a cosine level signal.
- the value range of the n is: 1 ⁇ n ⁇ 10.
- the initial value of the f 1 is
- the frequency of the voltage signal u 0 to be measured is f 0
- the sampling frequency f s ranges as follows: f s ⁇ 100f 0 .
- the level vector And level vector The orthogonal product operation is as follows:
- the invention provides a single-phase voltage digital phase-locking method, and constructs a sinusoidal level signal similar to the voltage signal to be measured and having a frequency f 1 , and the initial value of f 1 is
- the control makes the phase difference component V q of the two vectors approach 0, and when the control reaches the steady state, the output phase angle ⁇ ′ tracks the signal to be tested.
- Figure 1 is a schematic diagram of the control of the present invention.
- Figure 3 is an embodiment of the present invention Vector magnitude.
- Figure 4 is an embodiment of the present invention Vector phase angle.
- Figure 5 is an embodiment of the present invention Schematic diagram.
- the invention relates to a single-phase voltage digital phase-locking method.
- the control principle is shown in FIG. 1 and includes the following steps:
- Step S1 discretely sampling the voltage signal to be tested u 0 at a sampling frequency f s and constructing a level vector
- u 0 (k) represents the sampled value of the voltage signal u 0 to be tested in the current sampling period
- u 0 (kn) represents that the voltage signal u 0 to be tested is in the nth sampling period before the current sampling period.
- Sampled value, n is a positive integer
- Step S2 construct a level signal u 1 of frequency f 1 in the current sampling period with f s as the sampling frequency, and construct a level vector Where u 1 (k) represents a corresponding constructed value in the current sampling period, and u 1 (kn) represents a constructed value corresponding to the nth sampling period of the level signal u 1 before the current sampling period;
- Step S3 Level vector And level vector Performing an orthogonal product operation to obtain a phase difference component V q ; inputting the obtained phase difference component V q into a PI controller, and controlling the loop through the PI controller to adjust the phase difference component V q to 0;
- the incremental angular frequency ⁇ output by the controller and a reference angular frequency ⁇ 0 are cumulatively obtained to obtain an angular frequency ⁇ ′, and are integrated by an integrator to output a phase angle ⁇ ′, and after reaching a steady state, the output phase angle ⁇ ′ is a phase of the voltage signal to be measured;
- the reference angular frequency ⁇ 0 is an angular frequency of the voltage signal u 0 to be measured, and the frequency in the step S2
- the level signal u 1 is a sinusoidal level signal or a cosine level signal.
- the value range of the n is: 1 ⁇ n ⁇ 10.
- the initial value f 1 in the step S2, the initial value f 1
- the frequency of the voltage signal u 0 to be measured is f 0
- the sampling frequency f s ranges as follows: f s ⁇ 100f 0 .
- the voltage to be measured is a sinusoidal voltage signal whose initial phase angle is 0 and does not contain harmonic components, but the present invention is to be
- the voltage measurement signal is not limited to this, and is also applicable to a sinusoidal voltage signal having a different number of harmonic interferences and/or an initial phase angle of not 0, or other voltage signals to be tested which can be equivalently converted into a sinusoidal voltage signal.
- level value of the current sampling period is compared with the level value of the previous sampling period to form a level vector, that is:
- a level signal u 1 having the same frequency as f 1 and the same voltage to be measured is constructed in the sampling period, and the level signal constructed by the current sampling period is:
- level vector formed by the current constructed level value and the previous sampling period constitutes a level vector, namely:
- the obtained V q is input to a PI controller, and the PI controller adjusts the phase difference amount V q by the control loop to adjust to 0, and accumulates the output incremental angular frequency ⁇ and a reference angular frequency ⁇ 0 to obtain an angle.
- the frequency ⁇ ' is integrated by an integrator to output a phase angle ⁇ '. Since the frequency f 1 is adjusted according to the output ⁇ ′ in the control process, f 1 constantly approaches the frequency u 0 of the voltage signal u 0 to be tested, and the error between the two is small, especially when the control is close to the steady state, it can be considered f 1 ⁇ f 0 , then in the above formula (7) Neglect, then
- the integrator outputs the phase of the voltage signal to be measured or the phase that is delayed by 180° from the phase of the signal to be measured.
- the phase lag of 180° with the signal to be measured is an unstable equilibrium point, so the ⁇ ′ of the integrator output is the phase ⁇ of the voltage signal to be measured.
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Measuring Phase Differences (AREA)
Abstract
本发明涉及一种单相电压数字锁相方法,构建一个与待测电压信号相似的预设电平信号;在控制过程中,根据PI控制器输出的增量角频率与基准角频率累加获取的角频率调整预设频率,控制使得两个电压信号对应的电平矢量的相位差分量趋近为0,在控制达到稳态时,输出的相位角跟踪待测信号的相位,完成锁相功能。本发明利用待测电压信号的当前采样点和之前的第k-n个采样点构成电平矢量,控制过程中,只需保留n个采样点,当n=1时,只需保留1个采样周期的采样值,占用的存储空间极少,且计算简便实用,可应用于产品开发。
Description
本发明涉及一种单相电压数字锁相方法。
三相电源由于三相电压在空间形成矢量形式,则可以方便的利用空间坐标旋转变换等数学工具,配合数字锁相环原理形成三相数字逆变电源锁相技术。然而,对于单相电源电压,由于电源电压只有一相,难以直接利用空间矢量的特点进行数字锁相环控制。
现有的单相电源电压的鉴相、锁相环控制中,常见的是将待测电压延时90°构成正交的两相电压信号,待测电压和经延时的电压信号正好在α-β坐标系中构成互相垂直的两相信号,在平面旋转后构成矢量圆,然后通过平面坐标旋转变换,实现单相电压鉴相。
这种方法计算简单,但至少需要保留四分之一周期以上的数据,系统内存占用量大。
本发明的目的在于提供一种单相电压数字锁相方法,以克服现有技术中存在的缺陷。
为实现上述目的,本发明的技术方案是:一种单相电压数字锁相方法,包括以下步骤:
步骤S1:将待测电压信号u0以采样频率fs进行离散采样,并构建电平矢量其中,u0(k)表示所述待测电压信号u0在当前采样周期内的采样值,u0(k-n)表示所述待测电压信号u0在当前采样周期之前第n个采样周期的采样值,n为正整数;
步骤S2:以fs为采样频率,在当前采样周期中构建一个频率为f1的电平信号u1,并构建一电平矢量其中,u1(k)表示在当
前采样周期内对应的构造值,u1(k-n)表示所述电平信号u1在当前采样周期之前第n个采样周期对应的构造值;
步骤S3:将电平矢量和电平矢量作正交积运算获取相位差分量Vq;将所得的相位差分量Vq输入一PI控制器,并通过该PI控制器控制环路,将相位差分量Vq调节趋向0;将所述PI控制器输出的增量角频率Δω和一基准角频率ω0累加获得一角频率ω′,并经一积分器积分输出相位角θ′,且达到稳态后,所述输出相位角θ′即为待测电压信号的相位;其中,所述基准角频率ω0为所述待测电压信号u0的角频率,所述步骤S2中频率
在本发明一实施例中,在所述步骤S2中,所述电平信号u1为正弦电平信号或余弦电平信号。
在本发明一实施例中,在所述步骤S1中,所述n的取值范围为:1≤n≤10。
在本发明一实施例中,所述待测电压信号u0的频率为f0,且所述采样频率fs的取值范围如下:fs≥100f0。
本发明提出的一种单相电压数字锁相方法,构建一个与待测电压信号
相似、频率为f1的正弦电平信号,f1的初始值为在控制过程中,根据角频率ω′(或相位角θ′)调整f1,控制使得两个矢量的相位差分量Vq趋近为0,在控制达到稳态时,输出的相位角θ′跟踪待测信号的相位,完成锁相功能。本发明利用待测电压信号的当前采样点u0(k)和之前的第k-n个采样点u0(k-n)构成电平矢量,控制过程中,只需保留n个采样点,当n=1时,只需保留1个采样周期的采样值,占用的存储空间极少,且计算简便实用,可应用于产品开发。
图1为本发明的控制原理图。
下面结合附图,对本发明的技术方案进行具体说明。
本发明一种单相电压数字锁相方法,控制原理如图1所示,包括以下步骤:
步骤S1:将待测电压信号u0以采样频率fs进行离散采样,并构建电平矢量其中,u0(k)表示所述待测电压信号u0在当前采样周期内的采样值,u0(k-n)表示所述待测电压信号u0在当前采样周期之前第n个采样周期的采样值,n为正整数;
步骤S2:以fs为采样频率,在当前采样周期中构建一个频率为f1的电
平信号u1,并构建一电平矢量其中,u1(k)表示在当前采样周期内对应的构造值,u1(k-n)表示所述电平信号u1在当前采样周期之前第n个采样周期对应的构造值;
步骤S3:将电平矢量和电平矢量作正交积运算获取相位差分量Vq;将所得的相位差分量Vq输入一PI控制器,并通过该PI控制器控制环路,将相位差分量Vq调节趋向0;将所述PI控制器输出的增量角频率Δω和一基准角频率ω0累加获得一角频率ω′,并经一积分器积分输出相位角θ′,且达到稳态后,所述输出相位角θ′即为待测电压信号的相位;其中,所述基准角频率ω0为所述待测电压信号u0的角频率,所述步骤S2中频率
在本发明一实施例中,在所述步骤S2中,所述电平信号u1为正弦电平信号或余弦电平信号。
在本发明一实施例中,在所述步骤S1中,所述n的取值范围为:1≤n≤10。
在本发明一实施例中,所述待测电压信号u0的频率为f0,且所述采样频率fs的取值范围如下:fs≥100f0。
为便于计算和具体说明,以及让本领域技术人员理解本发明所提出的方法,以下假定待测电压是一个初始相角为0,且不含有谐波分量的正弦电压信号,但本发明的待测电压信号不局限于此,同样适用于含有不同次数谐波干扰和/或初始相位角不为0的正弦电压信号,或其他可等效变换为正弦电压信号的待测电压信号。
假定待测电压信号的表达式为:
u0(t)=U0∠0°=U0sin(ω0t) (1)
其中,U0为待测电压幅值,f0为待测电压的频率,ω0=2πf0。
记采样频率为fs,则离散采样后的电压信号为:
进一步的,利用当前采样周期的电平值与前一采样周期的电平值组成电平矢量,即:
则该矢量在平面上形成一个扁圆形轨迹,如错误!未找到引用源。所示。在本实施例中,令f0=50Hz,fs=20Hz,式(3)的矢量幅值和矢量相角分别如图3和图4所示。
进一步的,以fs为采样频率,在采样周期中构造一个频率为f1、与待测电压相同的电平信号u1,则当前采样周期构造的电平信号为:
进一步的,利用当前构造的电平值与前一采样周期构造的电平值组成电平矢量,即:
进一步的,将得到的Vq输入一PI控制器,PI控制器通过控制环路控制相位差分量Vq调节趋向0,并将输出的增量角频率Δω和一基准角频率ω0累加获得角频率ω′;经一积分器积分输出相位角θ′。由于在控制过程中根据输出的θ′调整频率f1,f1不断趋近待测电压信号u0的频率u0,二者之间误差很小,特别是在控制接近稳态时,可以认为f1≈f0,则上式(7)中忽略不计,则
且处于稳态时,
则
θ=θ′ (11)
或者
θ-θ′=180° (12)
因此积分器积分输出的是待测电压信号的相位或与待测信号相位滞后180°的相位。但与待测信号相位滞后180°是一个不稳定平衡点,因此积分器输出的θ′即为待测电压信号的相位θ。
以上仅为本发明实施例中一个较佳的实施方案。但是,本发明并不限于上述实施方案,凡按本发明所做的任何均等变化和修饰,所产生的功能作用未超出本方案的范围时,均属于本发明的保护范围。
Claims (6)
- 一种单相电压数字锁相方法,其特征在于:包括以下步骤:步骤S1:将待测电压信号u0以采样频率fs进行离散采样,并构建电平矢量其中,u0(k)表示所述待测电压信号u0在当前采样周期内的采样值,u0(k-n)表示所述待测电压信号u0在当前采样周期之前第n个采样周期的采样值,n为正整数;步骤S2:以fs为采样频率,在当前采样周期中构建一个频率为f1的电平信号u1,并构建一电平矢量其中,u1(k)表示在当前采样周期内对应的构造值,u1(k-n)表示所述电平信号u1在当前采样周期之前第n个采样周期对应的构造值;
- 根据权利要求1所述的一种单相电压数字锁相方法,其特征在于,所述步骤S2中,所述电平信号u1为正弦电平信号或余弦电平信号。
- 根据权利要求1所述的一种单相电压数字锁相方法,其特征在于,在所述步骤S1中,所述n的取值范围为:1≤n≤10。
- 根据权利要求1所述的一种单相电压数字锁相方法,其特征在于,所述待测电压信号u0的频率为f0,且所述采样频率fs的取值范围如下:fs≥100f0。
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