WO2019228054A1 - 一种锁相装置及锁相方法 - Google Patents

一种锁相装置及锁相方法 Download PDF

Info

Publication number
WO2019228054A1
WO2019228054A1 PCT/CN2019/080687 CN2019080687W WO2019228054A1 WO 2019228054 A1 WO2019228054 A1 WO 2019228054A1 CN 2019080687 W CN2019080687 W CN 2019080687W WO 2019228054 A1 WO2019228054 A1 WO 2019228054A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
amplitude
voltage signal
oscillator
loop filter
Prior art date
Application number
PCT/CN2019/080687
Other languages
English (en)
French (fr)
Inventor
杨东升
刘方诚
王雄飞
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19812631.0A priority Critical patent/EP3793091A4/en
Publication of WO2019228054A1 publication Critical patent/WO2019228054A1/zh
Priority to US17/105,029 priority patent/US11038512B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/28—Arrangements for balancing of the load in a network by storage of energy
    • H02J3/32—Arrangements for balancing of the load in a network by storage of energy using batteries with converting means

Definitions

  • the present application relates to the technical field of basic electronic circuits, and in particular, to a phase locked device and a phase locked method.
  • Phase-lock technology is a widely used automatic feedback control technology in communication, navigation, broadcasting and television communication, instrumentation measurement, and digital signal processing. It is used to achieve mutual synchronization between different devices.
  • Figure 1 is a schematic structural diagram of a typical three-phase grid-connected converter. The AC port of each grid-connected converter is connected to a common connection point (PCC) through a respective filter, thereby performing power transmission with the power grid.
  • PCC connection point
  • phase locked loop (PLL) in the grid-connected converter is used to obtain the AC voltage at the PCC (v a , v b , v c ) and input it to the current controller of the grid-connected converter to control the converter based on the phase ⁇ .
  • Control based on phase ⁇ includes: power factor control, island detection, and so on.
  • phase-locked loop Synchronous Reference Frame PLL (SRF-PLL)
  • SRF-PLL Synchronous Reference Frame PLL
  • the phase-locked loop includes a phase detector, loop filter, and voltage-controlled oscillation.
  • the principle of the phase-locked loop to obtain the phase ⁇ required for control is as follows: First, the AC voltage (v a , v b , v c ) obtained from the PCC is subjected to coordinate transformation to obtain a two-phase voltage in a stationary coordinate system. The signals v ⁇ and v ⁇ are 90 ° out of phase with each other.
  • the phase detector performs coordinate transformation on v ⁇ and v ⁇ to obtain the quadrature axis (also called q axis) signal v q and the straight axis (also called d axis) signal v d in the rotating coordinate system.
  • the reference phase used is the phase estimate ⁇ 0 output by the SRF-PLL.
  • the quadrature axis signal Vq is filtered by a loop filter to implement precision control and speed control.
  • the output of the loop filter and the preset initial frequency ⁇ 0 are superimposed and input to the voltage-controlled oscillator, and the voltage-controlled oscillator performs integration processing to obtain a phase estimation value ⁇ 0 , and then the phase estimation value ⁇ 0 As the phase ⁇ for control.
  • the SRF-PLL can obtain relatively ideal phase estimation value ⁇ 0 through feedback adjustment.
  • the structure of the SRF-PLL is prone to frequency coupling problems.
  • the embodiment of the present application discloses a phase-locking device and a phase-locking method, which can attenuate the frequency coupling problem between a positive sequence component generated by the phase-locked device and a negative sequence component generated by the phase-locked device to a certain extent.
  • an embodiment of the present application provides a phase-locking device.
  • the phase-locking device includes an amplitude adjustment unit, an amplitude detector and a phase detector connected to the amplitude adjustment unit, and a phase detector connected to the amplitude detector.
  • the amplitude adjustment unit, amplitude discriminator, first loop filter, and first oscillator constitute a loop of the phase-locked device; the amplitude discriminator, second loop filter, and The two oscillators form the other loop of the phase-locked device.
  • the two loops of the phase-locked device form a symmetrical structure, which suppresses the generation of negative sequence components. Therefore, the positive sequence components generated by the phase-locked device and the lock can be weakened. Phase coupling between the negative sequence components generated by the phase device.
  • the amplitude adjustment amount output by the first oscillator plays a feedback adjustment role on the amplitude of the voltage signal input to the phase-locked device, the working voltage amplitude of the phase-locked device can be maintained in a relatively stable state. The working performance of the phase-locking device is greatly improved.
  • an amplitude difference value is determined according to the second AC voltage signal and a preset reference voltage amplitude, and according to the second AC voltage
  • the signal and the phase estimate value output by the second oscillator determine aspects of the phase difference value
  • the amplitude detector and phase detector are configured to perform coordinate transformation on the second voltage signal according to the phase estimate value output by the second oscillator
  • determine an amplitude difference value according to the straight axis signal and a preset reference voltage amplitude value determine a phase difference value according to the quadrature axis signal.
  • the amplitude detector and phase detector include an amplitude detector and a phase detector; and according to the second AC voltage signal and a preset reference voltage The amplitude determines an amplitude difference value, and an aspect of determining a phase difference value according to the second AC voltage signal and a phase estimation value output by the second oscillator, the discriminator is configured to extract the second AC voltage signal And the amplitude difference is determined according to the extracted amplitude and a preset reference voltage amplitude; the phase detector is used to extract the phase of the second AC voltage signal or the phase of the first AC voltage signal A phase, and a phase difference value is determined according to the extracted phase and a phase estimation value output by the second oscillator.
  • the first loop filter is configured to perform filtering processing on the input amplitude difference value to obtain an amplitude control amount.
  • a second loop filter is configured to perform filtering processing on the input phase difference value to obtain a phase control amount, and the first loop filter is specifically configured to filter high frequency on the input amplitude difference value. Interference and scaling processing to obtain an amplitude control amount; the second loop filter is specifically configured to filter high-frequency interference on the input phase difference value and perform scaling processing to obtain a phase control amount.
  • an embodiment of the present application provides a phase-locking method.
  • the phase-locking method is applied to a phase-locking device.
  • the phase-locking device includes an amplitude adjustment unit and an amplitude detection and phase detection connected to the amplitude adjustment unit.
  • the first AC voltage signal is an AC voltage signal from an AC connection point, and the AC connection point is an access point for accessing an AC system; according to the second AC voltage signal and a preset reference voltage amplitude Determining an amplitude difference value, and determining a phase difference value according to the second AC voltage signal and a phase estimate value output by the second oscillator; outputting the amplitude difference value to a first loop filter and the second loop filter Loop filter output phase difference Value, wherein the amplitude difference value is used to characterize an offset of the amplitude of the second AC voltage signal from the reference voltage amplitude, and the phase difference value is used to characterize the second AC
  • the amplitude adjustment unit, amplitude discriminator, first loop filter, and first oscillator constitute a loop of the phase-locked device; the amplitude discriminator, second loop filter, and The two oscillators form the other loop of the phase-locked device.
  • the two loops of the phase-locked device form a symmetrical structure, which suppresses the generation of negative sequence components. Therefore, the positive sequence components generated by the phase-locked device and the lock can be weakened. Phase coupling between the negative sequence components generated by the phase device.
  • the amplitude adjustment amount output by the first oscillator plays a feedback adjustment role on the amplitude of the voltage signal input to the phase-locked device, the working voltage amplitude of the phase-locked device can be maintained in a relatively stable state. The working performance of the phase-locking device is greatly improved.
  • the determining an amplitude difference according to the second AC voltage signal and a preset reference voltage amplitude, and according to the second AC Determining a phase difference value between the voltage signal and a phase estimate value output by the second oscillator includes: performing coordinate transformation on the second voltage signal according to the phase estimate value output by the second oscillator to obtain a rotation coordinate system.
  • a straight axis signal and a quadrature axis signal determining an amplitude difference value according to the straight axis signal and a preset reference voltage amplitude value, and determining a phase difference value according to the quadrature axis signal.
  • determining an amplitude difference value according to the second AC voltage signal and a preset reference voltage amplitude, and according to the second AC voltage signal And determining a phase difference value with a phase estimation value output by the second oscillator includes: extracting an amplitude value of the second AC voltage signal, and determining an amplitude difference according to the extracted amplitude value and a preset reference voltage amplitude value Value; extracting a phase of the second AC voltage signal or a phase of the first AC voltage signal, and determining a phase difference value according to the extracted phase and a phase estimation value output by the second oscillator.
  • the filtering processing is performed on the input amplitude difference value to obtain an amplitude control amount, and the input phase difference value is filtered.
  • the processing to obtain a phase control amount includes: filtering high-frequency interference on the input amplitude difference value and performing a scaling process to obtain an amplitude control amount; filtering the high-frequency interference on the input phase difference value and performing Scaling process to obtain the amount of phase control.
  • a first parameter of the first loop filter configuration Is the same as the first parameter of the second loop filter configuration, and / or the second parameter of the first oscillator configuration is the same as the second parameter of the second oscillator configuration; wherein The first parameter includes one or more of a proportional parameter, a low-frequency gain, and a cutoff frequency, and the second parameter includes an integration coefficient.
  • the first parameter of the first loop filter configuration is the same as the first parameter of the second loop filter configuration, and / or, the first parameter of the first oscillator configuration is
  • the two parameters are the same as the second parameter configured by the second oscillator, the symmetry of the two loops in the phase locked device is stronger, and the problem of frequency coupling can be solved more effectively.
  • the first AC voltage signal is a two-phase stationary obtained by transforming a three-phase voltage collected at the AC connection point. AC voltage signal in the coordinate system.
  • the first AC voltage signal is a single-phase voltage collected at the AC connection point, and two channels are superimposed on each other.
  • the first AC voltage signal or the second AC voltage signal is a positive-sequence component after positive-sequence extraction. This eliminates the negative effects of negative sequence components.
  • a ratio between the first AC voltage signal and the second AC voltage signal and an amplitude output of the first oscillator is controlled.
  • the quantities have an exponential or linear function relationship.
  • an embodiment of the present application provides a controller.
  • the controller includes a phase-locking device and a current control unit.
  • the phase-locking device is described in the foregoing first aspect or any possible implementation manner of the first aspect.
  • a phase-locking device; the current control unit is configured to output a control signal through a phase parameter output by the phase-locking device, and the control signal is used to control an AC-DC converter to perform power conversion.
  • an embodiment of the present application provides a grid-connected system.
  • the grid-connected system includes an AC-DC converter and a controller connected to the AC-DC converter.
  • the controller includes a phase lock.
  • a device and a current control unit wherein the phase-locking device is the phase-locking device described in the first aspect or any possible implementation manner of the first aspect; the current-controlling unit is configured to pass the phase output by the phase-locking device
  • the parameter outputs a control signal, which is used to control the AC-DC converter to perform power conversion.
  • an embodiment of the present application provides a readable storage medium including program instructions.
  • the program instructions run on a processor, the second aspect or any possible implementation of the second aspect is implemented. The way described.
  • the amplitude adjustment unit, the amplitude discriminator, the first loop filter, and the first oscillator constitute a loop of the phase locked device; the amplitude discriminator and the second loop filter And the second oscillator constitute another loop of the phase-locked device.
  • the two loops of the phase-locked device form a symmetrical structure, which eliminates the problem of frequency coupling.
  • the amplitude adjustment amount output by the first oscillator plays a feedback adjustment role on the amplitude of the voltage signal input to the phase-locked device, the working voltage amplitude of the phase-locked device can be maintained in a relatively stable state. The working performance of the phase-locking device is greatly improved.
  • FIG. 1 is a schematic structural diagram of a three-phase grid-connected converter in the prior art
  • FIG. 2 is a schematic structural diagram of a phase-locked loop in a synchronous rotation coordinate system in the prior art
  • FIG. 3 is a schematic structural diagram of a grid-connected system according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an AC-DC converter according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a scenario of a battery energy storage system provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a scenario of a photovoltaic power generation system according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a phase lock device according to an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a phase lock method according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a scenario of a three-phase converter grid-connected system provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a Kraka transform provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a scenario for obtaining two-phase voltage according to an embodiment of the present application.
  • FIG. 12 is another schematic diagram of obtaining a two-phase voltage according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a positive sequence extraction scenario provided by an embodiment of the present application.
  • 14A is a schematic diagram of a scenario for determining a phase difference provided by an embodiment of the present application.
  • 14B is a schematic diagram of determining a phase difference according to an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of still another phase-locking device according to an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of still another phase-locking device according to an embodiment of the present application.
  • 17 is a voltage waveform diagram provided by an embodiment of the present application.
  • FIG. 18 is a voltage waveform diagram provided by an embodiment of the present application.
  • FIG. 19 is a current spectrum diagram provided by an embodiment of the present application.
  • FIG. 20 is a current spectrum diagram provided by an embodiment of the present application.
  • 21 is a simulation waveform diagram provided by an embodiment of the present application.
  • FIG. 24 is another simulation waveform diagram provided by an embodiment of the present application.
  • FIG. 26 is another simulation waveform diagram provided by an embodiment of the present application.
  • FIG. 28 is another simulation waveform diagram provided by an embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of a phase lock device according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a grid-connected system 30 according to an embodiment of the present application.
  • the grid-connected system (also referred to as an AC-DC grid-connected system and a converter system) includes an AC-DC converter 301 And a controller 302, which is connected to the AC-DC converter 301, and the controller 302 is configured to control the AC-DC converter 301 to perform power conversion, wherein:
  • the AC-DC converter 301 is used to connect the DC power system 10 and the AC power system 20 and implement power transmission between the two power systems. If the power is transferred from the DC power system 10 to the AC power system 20, it is referred to as an inverter mode. At this time, the AC-DC converter 301 is also referred to as an inverter. If the power is transferred from the AC power system 20 to the DC power system 10, it is called a rectification mode. At this time, the AC-DC converter 301 is also called a rectifier.
  • the structure of the AC-DC converter 301 is shown in Figure 4 As shown. In order to ensure stable power transmission, it is necessary to perform power control on the two types of power systems according to the respective characteristics of the DC power system 10 and the AC power system 20.
  • the voltage polarity of the DC power system 10 does not change with time, so the amplitude of the current transmitted by the DC power system 10 can be adjusted when performing power control; and the magnitude and polarity of the voltage and current of the AC power system 20 Changes with time.
  • Basic AC signals (including voltage and current) have three characteristic quantities, namely amplitude, frequency, and phase. Therefore, in addition to the amplitude of the current transmitted to the AC power system 20 during power control, In addition to the adjustment, the frequency and phase of the current need to be controlled. Controlling the current frequency of the AC power system 20 is the same as the voltage frequency of the AC power system 20, and the two maintain a fixed phase difference, which is referred to as "synchronization" of the AC power system.
  • the AC-DC converter 301 may include a single-phase converter and a three-phase converter. Regardless of the single-phase converter or the three-phase converter, the AC power system needs to be kept "synchronized”. Generally, single-phase converters have small transmission power, so they are common in small-scale distributed power systems, such as domestic power systems, battery energy storage systems, and so on. Three-phase converters have large transmission power and are commonly used in large-scale power systems, such as large-scale wind power generation systems, photovoltaic power generation systems, and so on.
  • Figure 5 illustrates a battery energy storage system.
  • Figure 6 illustrates a photovoltaic power generation system. It should be noted that the hardware structure of the AC-DC converter 301 in the rectification mode and the inverter mode is the same.
  • the charging and discharging of the battery energy storage system correspond to the rectification and inverter modes, but
  • the hardware structure of the battery energy storage system depends on the same charging and discharging processes. Therefore, the embodiment of the present application is not limited to a certain mode.
  • the power grid in the embodiment of the present application is not limited in size, and may be a large-scale power grid or a micro-grid with independent power supply.
  • the controller 302 includes a current sampling unit 3021, a voltage sampling unit 3022, a voltage processing unit 3023, a phase lock device 3024, a current control unit 3025, and a modulation unit 3026.
  • the current sampling unit 3021 is used to connect the current control unit 3025.
  • the voltage sampling unit 3022 is used to connect the voltage processing unit 3023.
  • the voltage processing unit 3023 is used to connect the phase-locking device 3024.
  • the phase-locking device uses 3024 to connect to the current control unit 3025.
  • the current control unit 3025 is used to connect to the modulation unit. 3026, the description of each unit or device is as follows:
  • the current sampling unit 3021 is configured to collect the current signal i g from the AC side of the main circuit of the AC-DC converter 301 and input the collected current signal i g to the current control unit 3025.
  • the voltage sampling unit 3022 is configured to receive The AC side of the main circuit of the AC-DC converter 301 collects a voltage signal, and inputs the collected voltage signal to the voltage processing unit 3023. It is used to collect the current signal i g from the AC side of the main circuit of the AC-DC converter 301 and input the collected current signal i g to the current control unit 3025.
  • the voltage sampling unit 3022 is used to convert the current from the AC-DC converter.
  • the AC side of the main circuit of the converter 301 collects a voltage signal, and inputs the collected voltage signal to the voltage processing unit 3023.
  • the input and output of the voltage processing unit 3023 are voltage signals and are used to perform functions such as positive sequence extraction or coordinate transformation.
  • the positive sequence extraction function is to extract the positive sequence components in the sampled voltage signal to suppress harmonic and negative sequence components.
  • the coordinate transformation is to convert a single-phase or three-phase voltage signal into a signal in a two-phase stationary coordinate system to match the input of the phase-locked device.
  • the phase-locking device 3024 is configured to generate a current amplitude ⁇ m and a phase ⁇ p according to the input voltage signal.
  • the current-amplitude reference value i M output by the phase-locking device 3024 to the current control unit 3025 is input to the phase-locking by an external element Transposed 3024 or configured in the phase-locking device 3024 directly by a program.
  • the current control unit 3025 is configured to adjust the current signal i g collected by the current sampling unit 3021 to generate a control signal according to the current amplitude reference value i M and the phase ⁇ p and amplitude ⁇ m generated by the phase-locking device 3024.
  • the modulation unit 3026 converts the control signal into a semiconductor switch driving signal matching the AC-DC converter 301, and directly controls the on or off state of the semiconductor in the AC-DC converter 301, thereby realizing the AC-DC conversion Control of the flow device 301.
  • FIG. 7 is a schematic structural diagram of a phase-locking device 3024 according to an embodiment of the present application.
  • the phase-locking device 3024 includes an amplitude adjustment unit 701, an amplitude discriminator and phase detector 702, and a first loop filter 703.
  • a second loop filter 706, a first oscillator 704, and a second oscillator 705 the input of the amplitude adjustment unit 701 is connected to the output of the first oscillator 704, and the output of the amplitude adjustment unit 701 Connected to the input of the amplitude detector phase detector 702, the input of the amplitude detector phase detector 702 is connected to the output of the second oscillator 705, and the output terminal of the amplitude detector phase detector 702 is connected to the first loop filter An input terminal of the filter 703 and an input terminal of the second loop filter 706. An output terminal of the first loop filter 703 is connected to an input terminal of the first oscillator 704, and an output terminal of the second loop filter 706. An input terminal of the second oscillator 705 is connected.
  • FIG. 8 is a schematic flowchart of a phase-locking method according to an embodiment of the present application. The flow may be implemented based on the phase-locking device 3024 of the structure shown in FIG. 7. The method includes but is not limited to the following steps:
  • Step S801 The amplitude adjustment unit compensates a first AC voltage signal to obtain a second AC voltage signal according to an output amplitude adjustment amount of the first oscillator.
  • the first AC voltage signal is an AC voltage signal collected from an AC connection point (for example, a common connection point (PCC)) or a converted AC voltage signal collected from the AC connection point.
  • Voltage signal, the AC connection point is an access point for accessing an AC system.
  • the first AC voltage signal is an AC voltage signal in a two-phase stationary coordinate system obtained by transforming the three-phase voltage collected at the AC connection point.
  • the phase locked device is applied to a three-phase converter grid-connected system.
  • the sampling unit in the three-phase converter grid-connected system collects three-phase voltages v a , v b , and v c .
  • the three-phase voltage is obtained by Clarke transformation to obtain the voltage (v ⁇ , v ⁇ ) in the two-phase stationary coordinate system.
  • Clarke transformation is a brief introduction to the basic principle of Clarke Clarke transformation.
  • a coordinate system is a three-phase stationary coordinate system with the a-axis, b-axis, C-axis total of three axes, the three axes are an angle of 120 °, v s of the three projection axes are V a , v b , v c .
  • Another coordinate system is a two-phase stationary coordinate system, [alpha] axis and has two co-axial shafts beta], [alpha] beta] axis perpendicular to the axis, v s v ⁇ respectively in both the projection axes, v ⁇ .
  • Clarke transformation is a voltage space vector v s in the three-phase stationary coordinate system projection v a, v b, v c converted to two-phase stationary coordinate projection line thereof by mathematical relationship v ⁇ , v ⁇ .
  • Equation 1-1 is an optional mathematical equation used in the transformation:
  • the first AC voltage signal is an AC voltage signal in a two-phase static coordinate system in which the single-phase voltage collected at the AC connection point is divided into two and superimposed; as shown in FIG. 11
  • One of the two voltage signals has undergone delay processing, and the delay length of the delay processing is 1/4 power frequency period.
  • the basic idea is that a complete power frequency period corresponds to 360 °, then a quarter of the power frequency period corresponds to 90 °, which can just meet the mathematical relationship that the two coordinate axes of the two-phase stationary coordinate system are perpendicular to 90 °.
  • one of the two channels that has not undergone delay processing is the voltage signal v ⁇ and the one that has undergone delay processing is the voltage signal v ⁇ .
  • These two channels constitute the first AC voltage signal (v ⁇ , v ⁇ ).
  • the above describes the method for obtaining the first AC voltage.
  • the following describes how to compensate the first AC voltage signal to obtain the second AC voltage signal according to the amplitude adjustment amount. Because the amplitude of the AC voltage signal collected at the AC connection point is affected by the grid impedance Zg and the amount of current flowing through Zg, the amplitude of the first voltage signal (v ⁇ , v ⁇ ) obtained by the transformation will also be affected, causing instability. Case. Therefore, the amplitude adjustment unit adjusts the first AC voltage signal according to the amplitude adjustment amount ⁇ m output by the first oscillator, so that the amplitude of the second voltage signal (v ⁇ 0 , v ⁇ 0 ) obtained after the adjustment is stabilized at a relatively high level. Ideal interval.
  • the method of compensating the first AC voltage signal (v ⁇ , v ⁇ ) to the second AC voltage signal (v ⁇ 0 , v ⁇ 0 ) according to the amplitude adjustment amount ⁇ m may be as follows:
  • a is a preset constant greater than 0, for example, set to e, the gain relationship at this time is shown in formula 1-3:
  • a is a preset constant greater than 0.
  • the first AC voltage signal or the second AC voltage signal is a positive sequence component after being extracted in a positive sequence, so that a negative impact generated by a negative sequence component can be eliminated.
  • the first AC voltage signal in the two-phase stationary coordinate system obtained by Clarke transformation of the three-phase voltage collected by the acquisition unit is firstly compared to the first AC voltage signal according to the first AC voltage signal.
  • An AC voltage signal is extracted in positive sequence to obtain a positive sequence component, and then the amplitude adjustment value output by the first oscillator is used to compensate the positive sequence component of the first AC voltage signal to obtain a second AC voltage signal.
  • the second AC voltage signal belongs to the positive sequence component after the positive sequence extraction.
  • FIG. 13 is a schematic diagram of the positive sequence extraction.
  • the first AC voltage signal (v ⁇ , v ⁇ ) and the positive-sequence component (v ⁇ + , v ⁇ + ) of the first AC voltage signal satisfy the mathematical relationships shown in formulas 1-5 and 1-6.
  • k is the damping ratio of the second-order generalized integral
  • ⁇ is the resonance frequency
  • s is the complex frequency. It is a characteristic variable generated by the Laplace transform of the time domain function in classical control theory.
  • the amplitude adjustment unit outputs the second AC voltage signal (v ⁇ 0 , v ⁇ 0 ) to the amplitude discriminator and phase detector.
  • Step S802 the amplitude and phase detector determines an amplitude difference value according to the second AC voltage signal and a preset reference voltage amplitude, and according to the second AC voltage signal and the output of the second oscillator The phase estimate determines the phase difference.
  • an amplitude difference can be calculated according to the amplitude of the second AC voltage signal and the preset reference voltage amplitude, and the amplitude difference is used to characterize the relative amplitude of the second AC voltage signal.
  • the offset of the reference voltage amplitude; optionally, the preset reference voltage amplitude may be a rated voltage value of an AC power system connected to the phase-locked device.
  • a feedback adjustment loop is formed between the second oscillator and the amplitude detector phase detector.
  • phase estimation value output from the second oscillator is input to the amplitude detector phase detector, and then the amplitude detector phase detector A phase difference value is calculated according to the phase of the second AC voltage signal and the phase estimation value, and the phase difference value is used to characterize an offset of the phase of the second AC voltage signal relative to the phase estimation value.
  • phase difference value is used to characterize an offset of the phase of the second AC voltage signal relative to the phase estimation value.
  • the amplitude discriminator and phase detector determine an amplitude difference according to the second AC voltage signal and a preset reference voltage amplitude, and according to the second AC voltage signal and the output of the second oscillator.
  • the phase estimation value determining the phase difference value may include: the amplitude discriminator phase detector performs coordinate transformation on the second voltage signal (v ⁇ 0 , v ⁇ 0 ) according to the phase estimation value ⁇ p output by the second oscillator to obtain rotation.
  • Equation 1-7 illustrates the phase estimation value ⁇ p , the second voltage signal (v ⁇ 0 , v ⁇ 0 ), the straight-axis signal v d, and the quadrature-axis signal v.
  • ⁇ p the phase estimation value
  • v ⁇ 0 the second voltage signal
  • v d the straight-axis signal
  • v d the straight-axis signal
  • v d the straight-axis signal
  • the basic principle of the synchronous rotating coordinate system can be drawn, at steady state, is equal to V D (v ⁇ 0, v ⁇ 0) consisting of a space-related vector magnitude v s0, and the phase is equal to ⁇ p v q and v s0 are Therefore, the amplitude detector and phase detector further determines an amplitude difference value e m according to the straight-axis signal v d and a preset reference voltage amplitude m ref , and determines a phase according to the quadrature-axis signal v q The difference e p .
  • the reference voltage amplitude m ref is a preset value for reference comparison
  • Formula 1-8 illustrates a possible relationship between the straight-axis signal v d , the reference voltage amplitude m ref, and the amplitude difference e m
  • Equation 1-9 illustrates a possible mathematical relationship between the quadrature axis signal v q and the phase difference value p .
  • the amplitude detector phase detector 702 includes an amplitude detector 7021 and a phase detector 7022, that is, the amplitude detector 7021 and the phase detector 7022 are relatively independent.
  • the amplitude discriminator and phase detector 702 determines an amplitude difference according to the second AC voltage signal and a preset reference voltage amplitude, and according to the second AC voltage signal and the second AC voltage signal.
  • the phase detector 7022 extracts a phase of the second AC voltage signal or a phase of the first AC voltage signal, and determines a phase difference according to the extracted phase and a phase estimation value output by the second oscillator. value. For example, the phase detector compares the zero crossings of the signal to determine the phase difference.
  • the main function of the zero crossing comparison phase detector is to obtain the characteristic phase of the input signal based on zero crossing detection, and then obtain the characteristic by timing comparison.
  • the time difference ⁇ t between the appearance time t1 of the phase and the phase estimation value is equal to the characteristic phase time t2, and then the time difference ⁇ t is converted into a phase difference ⁇ through measurement conversion.
  • the characteristic phase corresponding to the time when the input signal changes from positive to negative crossing zero is ⁇
  • record this time as t1 and then record the time when the phase estimation value is equal to ⁇ as t2.
  • the time difference between the two times is obtained by timing comparison.
  • the amplitude adjustment unit 701 does not necessarily need to It is connected to the phase detector 7022. Therefore, the position of the amplitude adjustment unit 701 in the phase lock device 3024 can be as shown in FIG. 15 or FIG. 16.
  • Step S803 The amplitude and phase detector outputs an amplitude difference value to a first loop filter and a phase difference value to the second loop filter.
  • Step S804 the first loop filter performs filtering processing on the input amplitude difference value to obtain the amplitude control amount, and the second loop filter performs filtering processing on the input phase difference value to obtain the phase control amount .
  • precision control can be achieved by filtering out high-frequency interference
  • speed control can be achieved by scaling processing of amplitude or phase.
  • the first loop filter is used to input the difference in amplitude Filter high-frequency interference and perform scaling processing to obtain the amplitude control amount
  • the second loop filter is used to filter high-frequency interference on the input phase difference value and perform scaling processing to obtain the phase control amount.
  • the first loop filter and the second loop filter may both adopt the PI adjustment principle.
  • the first loop filter and the second loop filter are configured with the same first parameter (for example, the first parameter may include a scale parameter, low frequency gain, cut-off frequency of a parameter or more), the magnitude of the difference equation 1-10 schematically e m d between the control amount and the magnitude m, and the retardation value An optional mathematical relationship between d p and the phase control amount e p .
  • K p is a preset ratio parameter
  • K i is a preset integration parameter
  • s is a complex frequency
  • the first loop filter outputs the amplitude control amount to the first oscillator after obtaining the amplitude control amount
  • the second loop filter outputs the phase control amount to the second oscillator after obtaining the phase control amount
  • Step S805 the first oscillator converts the amplitude control amount output by the first loop filter to obtain an amplitude adjustment amount, and the second oscillator controls the phase output by the second filter The amount is converted to obtain a phase estimate.
  • converting the amplitude control amount may include integrating the input amplitude control amount
  • converting the phase control amount may include integrating the input phase control amount. That is, the first oscillator and the second oscillator both use the integration principle.
  • the second parameter configured by the first oscillator and the second oscillator is the same (for example, the second parameter may include an integration coefficient), Equation 1 -11 illustrates an optional mathematical relationship between the amplitude control amount d m and the amplitude adjustment amount ⁇ m , and the phase control amount e p and the phase adjustment amount ⁇ p .
  • the first parameter of the first loop filter configuration may be the same as the first parameter of the second loop filter configuration
  • the second parameter of the first oscillator configuration may be the same as the first parameter of the second loop filter configuration.
  • the second parameter of the second oscillator configuration is the same. It is also possible that the first parameter of the first loop filter configuration is the same as the first parameter of the second loop filter configuration, but the second parameter of the first oscillator configuration is the same as the second oscillation
  • the second parameter of the controller configuration is different. It is also possible that the first parameter of the first loop filter configuration is different from the first parameter of the second loop filter configuration, but the second parameter of the first oscillator configuration is different from the second parameter The second parameter of the oscillator configuration is the same.
  • the first parameter configured by the first loop filter is different from the first parameter configured by the second loop filter
  • the second parameter configured by the first oscillator is different from the second parameter
  • the second parameter of the oscillator configuration is different. It can be understood that the first parameter of the first loop filter configuration is the same as the first parameter of the second loop filter configuration, which can further improve the symmetry of the phase-locked device, and thus can further weaken the frequency coupling. problem.
  • the second parameter of the first oscillator configuration is the same as the second parameter of the second oscillator configuration, which can further improve the symmetry of the phase locked device, and thus can further reduce the frequency coupling problem.
  • the voltage waveform of the PCC point after the disturbance is shown in Figure 17, the two waveforms in Figure 17 are the waveforms of v ⁇ and v ⁇ in the two-phase stationary coordinate system. It can be seen that the two voltage signals differ by 1/4 in time. Power frequency cycles (i.e. the corresponding phase angle is ), And the waveform has obvious harmonic components, as shown in FIG. 18, with obvious 50Hz and 300Hz components.
  • the disturbance voltage was input to an inverter (grid-connected system) equipped with a phase-locked device with an asymmetric structure and a phase-locked device according to the embodiment of the present application, and the output current was subjected to spectrum analysis.
  • the results are shown in FIG. .
  • the 50Hz component of the asymmetric structure phase-locked device has an additional 200Hz frequency component, which explains the obvious frequency in the phase-locked device.
  • Coupling characteristics In the corresponding FIG. 20, the frequency components in the dual-loop symmetrical structure phase-locking device shown in the embodiment of the present application are only 50 Hz and 300 Hz, which are the same as the frequency components of the PCC point voltage. Therefore, the lock of the embodiment of the present application can be explained Due to the symmetrical structure of the phase device, the frequency coupling characteristic is eliminated.
  • phase-locked device In order to compare the effect of the input signal amplitude on different phase-locked devices, two operating conditions are set in each phase-locked device.
  • t 0.5s.
  • the effect of input signal amplitude on the performance of different systems is compared by observing the dynamic response.
  • the simulation waveforms of the existing asymmetric phase-locked device are shown in Figure 21, Figure 22, Figure 23, and Figure 24. Because there is no amplitude compensation unit, the input signal of the phase-locked device and the input signal of the phase detector are the same. 21 an input signal corresponding to 100% v condition of ⁇ , v ⁇ , FIG. 22 corresponds to 70% v input signal condition of ⁇ , v ⁇ .
  • FIG. 22 corresponds to 70% v input signal condition of ⁇ , v ⁇ .
  • FIG. 25 corresponds to the input signal v condition after 100% compensation ⁇ o, v ⁇ o, v input signal condition corresponding to FIG. 26 after 70% compensation ⁇ o, v ⁇ o, the input signal to compensate the two conditions
  • the amplitude is 100% in the steady state, and at the moment when the system is disturbed, since the amplitude adjustment loop of the phase-locked device in the embodiment of the present application requires a certain time to perform closed-loop adjustment, the voltage after compensation will be shorter. Instantaneous is not equal to 100%.
  • phase locked device in the embodiment of the present application can automatically compensate the amplitude of the system input signal, thereby eliminating the influence of the input signal amplitude change on the performance of the phase locked device.
  • the amplitude adjustment unit, amplitude detector, phase detector, first loop filter, and first oscillator constitute a loop of the phase-locked device; the amplitude detector, second loop filter, The second oscillator constitutes another loop of the phase-locked device.
  • the two loops of the phase-locked device form a symmetrical structure, which suppresses the generation of negative sequence components. Therefore, the positive sequence component and the The problem of frequency coupling between the negative sequence components generated by the phase locked device.
  • the amplitude adjustment amount output by the first oscillator plays a feedback adjustment role on the amplitude of the voltage signal input to the phase-locked device, the working voltage amplitude of the phase-locked device can be maintained in a relatively stable state. The working performance of the phase-locking device is greatly improved.
  • the phase-locked transposition included in the embodiment of the present application includes an amplitude adjustment unit, an amplitude discriminator, a first loop filter, a second loop filter, a first oscillator, and a second oscillation.
  • some units (or devices) may be implemented by hardware circuits and another part (or devices) may be implemented by software, or all units (or devices) may be implemented by hardware circuits.
  • Units (or devices) are implemented by software.
  • the phase-locking device includes a processor, and the processor implements the unit (or device) by running program instructions.
  • the phase-locking device can complete the amplitude adjustment task by running a program instruction, which is equivalent to virtualizing an amplitude adjustment unit based on the processor.
  • the structure of the phase-locked transpose can be as shown in FIG. 29.
  • the phase-locked device includes a memory 2901, a processor 2902 is a communication interface 2903.
  • the processor 2902, the communication interface 2903, and the memory 2901 may be connected to each other, for example, through a bus 2904.
  • the memory 2901 is used to store code and data of a phase-locked device.
  • the memory 2901 stores a code for implementing an amplitude adjustment unit, a code for implementing an amplitude detector and a phase detector, a code for implementing a first loop filter, and implementation. Code for the second loop filter, code for implementing the first oscillator, code for implementing the second oscillator, and so on.
  • the processor 2901 executes these codes to virtually generate functional units such as an amplitude adjustment unit, an amplitude phase detector, a first loop filter, a second loop filter, a first oscillator, and a second oscillator.
  • the communication interface 2903 is used to support signal transmission between the phase-locked device and an external device. For example, it is used to support the phase-locked device to access the AC voltage signals (v ⁇ , v ⁇ ) output by the voltage processing unit, and support the The phase-locking device outputs the phase and amplitude for control to the voltage control unit.
  • the processor 2902 may be a central processing unit, a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute various exemplary logical blocks, modules, and circuits described in connection with the disclosure of this application.
  • the processor may also be a combination that implements computing functions, such as a combination including one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so on.
  • the memory may include various media that can store program codes, such as a ROM or a random storage memory RAM, a magnetic disk, or an optical disc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Inverter Devices (AREA)

Abstract

本申请实施例提供一种锁相装置及锁相方法，该锁相装置包括幅值调节单元、与所述幅值调节单元连接的鉴幅鉴相器、与所述鉴幅鉴相器连接的第一环路滤波器、与所述鉴幅鉴相器连接的第二环路滤波器、与所述第一环路滤波器连接的第一振荡器和与所述第二环路滤波器连接的第二振荡器。其中，所述幅值调节单元、所述鉴幅鉴相器、所述第一环路滤波器和所述第一振荡器构成一个环路，所述鉴幅鉴相器、所述第二环路滤波器和所述第二振荡器构成另外一个环路。采用本申请实施例，该锁相装置的双环结构能够减弱锁相装置产生的正序分量与该锁相装置产生的负序分量之间的频率耦合问题。

Description

一种锁相装置及锁相方法 技术领域
本申请涉及基本电子电路技术领域，尤其涉及一种锁相装置及锁相方法。
背景技术
锁相技术是通信、导航、广播与电视通信、仪器仪表测量、数字信号处理等技术中应用比较广泛的自动反馈控制技术，其用于实现不同设备之间的相互同步。图1为典型三相并网变流器的结构示意图，每台并网变流器的交流端口通过各自的滤波器连接在公共连接点(Point of Common Coupling，PCC)，从而和电网进行功率传输(Z g为PCC点至远端无穷大电网的电网等效阻抗)，并网变流器中的锁相环(Phase locked loop，PLL)用于获取PCC处的交流电压(v a，v b，v c)中的相位θ并将其输入到并网变流器的电流控制器中，以便以相位θ为基础对变流器进行控制。基于相位θ进行的控制包括：功率因数控制、孤岛检测等。
最常见的锁相环是同步旋转坐标系下的锁相环(Synchronous Reference Frame PLL，SRF-PLL)，如图2所示，该锁相环包括鉴相器、环路滤波器和压控振荡器，该锁相环获取控制所需的相位θ的原理如下：首先，对从PCC处获取的交流电压(v a，v b，v c)进行坐标变换，得到静止坐标系下的两相电压信号v α和v β，这两相电压信号的相位相差为90°。然后，通过鉴相器对v α和v β进行坐标变换以得到旋转坐标系下的交轴(也称为q轴)信号v q和直轴(也称为d轴)信号v d，变换时使用的参考相位为SRF-PLL输出的相位估计值θ 0。然后，通过环路滤波器对该交轴信号Vq进行滤波以实现精度控制和速度控制。接着，环路滤波器的输出和预设的初始频率ω 0叠加后输入到压控振荡器中，由压控振荡器进行积分处理以得到相位估计值θ 0，之后将该相位估计值θ 0作为用于控制的相位θ。可以看出，SRF-PLL通过反馈调节可得到相对较理想的相位估计值θ 0，然而SRF-PLL的结构容易出现频率耦合的问题。
发明内容
本申请实施例公开了一种锁相装置及锁相方法，能够一定程度上减弱锁相装置产生的正序分量与该锁相装置产生的负序分量之间的频率耦合问题。
第一方面，本申请实施例提供一种锁相装置，该锁相装置包括幅值调节单元、与所述幅值调节单元连接的鉴幅鉴相器、与所述鉴幅鉴相器连接的第一环路滤波器、与所述鉴幅鉴相器连接的第二环路滤波器、与所述第一环路滤波器连接的第一振荡器和与所述第二环路滤波器连接的第二振荡器，其中：所述幅值调节单元用于根据所述第一振荡器的输出幅值调节量补偿第一交流电压信号以得到第二交流电压信号，所述第一交流电压信号为来自交流连接点的交流电压信号，所述交流连接点为用于接入交流系统的接入点；所述鉴幅鉴相器用于根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值；所述鉴幅鉴相器还用于向第一环路滤波器输出幅值差值以及向所述第二环路滤波器输出相位差值，其中，所 述幅值差值用于表征所述第二交流电压信号的幅值相对于所述参考电压幅值的偏移，所述相位差值用于表征所述第二交流电压信号的相位相对于所述相位估计值的偏移；所述第一环路滤波器用于对输入的所述幅值差值进行滤波处理以得到幅值控制量，所述第二环路滤波器用于对输入的所述相位差值进行滤波处理以得到相位控制量；所述第一振荡器用于对所述第一环路滤波器输出的幅值控制量进行转换以得到幅值调节量，所述第二振荡器用于对所述第二滤波器输出的相位控制量进行转换以得到相位估计值。
可以看出，幅值调节单元、鉴幅鉴相器、第一环路滤波器、第一振荡器构成了锁相装置的一个环路；鉴幅鉴相器、第二环路滤波器、第二振荡器构成了锁相装置的另一个环路，锁相装置的这两个环路形成了对称结构，抑制了负序分量的产生，因此能够减弱锁相装置产生的正序分量与该锁相装置产生的负序分量之间的频率耦合问题。另外，由于第一振荡器输出的幅值调节量对输入到该锁相装置的电压信号的幅值起到了反馈调节的作用，能够使锁相装置的工作电压幅值保持一个相对稳定地状态，大大提升了该锁相装置的工作性能。
结合第一方面，在第一方面的第一种可能的实现方式中，在根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值的方面，所述鉴幅鉴相器用于根据所述第二振荡器输出的相位估计值对所述第二电压信号进行坐标变换以得到旋转坐标系下的直轴信号和交轴信号，以及根据所述直轴信号与预设的参考电压幅值确定幅值差值，以及根据所述交轴信号确定相位差值。
结合第一方面，在第一方面的第二种可能的实现方式中，所述鉴幅鉴相器包括鉴幅器和鉴相器；在根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值的方面，所述鉴幅器用于提取所述第二交流电压信号的幅值，并根据提取出的幅值和预设的参考电压幅值确定幅值差值；所述鉴相器用于提取所述第二交流电压信号的相位或者所述第一交流电压信号的相位，并根据提取出的相位和所述第二振荡器输出的相位估计值确定相位差值。
结合第一方面，在第一方面的第三种可能的实现方式中，在所述第一环路滤波器用于对输入的所述幅值差值进行滤波处理以得到幅值控制量，所述第二环路滤波器用于对输入的所述相位差值进行滤波处理以得到相位控制量的方面，所述第一环路滤波器具体用于对输入的所述幅值差值滤除高频干扰以及进行缩放处理，以得到幅值控制量；所述第二环路滤波器具体用于对输入的所述相位差值滤除高频干扰以及进行缩放处理，以得到相位控制量。
第二方面，本申请实施例提供一种锁相方法，所述锁相方法应用于锁相装置，所述锁相装置包括幅值调节单元、与所述幅值调节单元连接的鉴幅鉴相器、与所述鉴幅鉴相器连接的第一环路滤波器、与所述鉴幅鉴相器连接的第二环路滤波器、与所述第一环路滤波器连接的第一振荡器和与所述第二环路滤波器连接的第二振荡器，所述方法包括：根据所述第一振荡器的输出幅值调节量补偿第一交流电压信号以得到第二交流电压信号，所述第一交流电压信号为来自交流连接点的交流电压信号，所述交流连接点为用于接入交流系统的接入点；根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值；向第一环路滤波器 输出幅值差值以及向所述第二环路滤波器输出相位差值，其中，所述幅值差值用于表征所述第二交流电压信号的幅值相对于所述参考电压幅值的偏移，所述相位差值用于表征所述第二交流电压信号的相位相对于所述相位估计值的偏移；对输入的所述幅值差值进行滤波处理以得到幅值控制量，对输入的所述相位差值进行滤波处理以得到相位控制量；对所述第一环路滤波器输出的幅值控制量进行转换以得到幅值调节量，对所述第二滤波器输出的相位控制量进行转换以得到相位估计值。
可以看出，幅值调节单元、鉴幅鉴相器、第一环路滤波器、第一振荡器构成了锁相装置的一个环路；鉴幅鉴相器、第二环路滤波器、第二振荡器构成了锁相装置的另一个环路，锁相装置的这两个环路形成了对称结构，抑制了负序分量的产生，因此能够减弱锁相装置产生的正序分量与该锁相装置产生的负序分量之间的频率耦合问题。另外，由于第一振荡器输出的幅值调节量对输入到该锁相装置的电压信号的幅值起到了反馈调节的作用，能够使锁相装置的工作电压幅值保持一个相对稳定地状态，大大提升了该锁相装置的工作性能。
结合第二方面，在第二方面的第一种可能的实现方式中，所述根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值，包括：根据所述第二振荡器输出的相位估计值对所述第二电压信号进行坐标变换以得到旋转坐标系下的直轴信号和交轴信号；根据所述直轴信号与预设的参考电压幅值确定幅值差值，以及根据所述交轴信号确定相位差值。
结合第二方面，在第二方面的第二种可能的实现方式中，根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值，包括：提取所述第二交流电压信号的幅值，并根据提取出的幅值和预设的参考电压幅值确定幅值差值；提取所述第二交流电压信号的相位或者所述第一交流电压信号的相位，并根据提取出的相位和所述第二振荡器输出的相位估计值确定相位差值。
结合第二方面，在第二方面的第三种可能的实现方式中，所述对输入的所述幅值差值进行滤波处理以得到幅值控制量，对输入的所述相位差值进行滤波处理以得到相位控制量，包括：对输入的所述幅值差值滤除高频干扰以及进行缩放处理，以得到幅值控制量；对输入的所述相位差值滤除高频干扰以及进行缩放处理，以得到相位控制量。
结合以上任一方面的任一可能的实现方式，在又一种可能的实现方式中，在第一方面的第三种可能的实现方式中：所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的所述第一参数相同，和/或，所述第一振荡器配置的第二参数与所述第二振荡器配置的所述第二参数相同；其中，所述第一参数包括比例参数、低频增益和截止频率中的一项或者多项，所述第二参数包括积分系数。可以理解的是，当所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的所述第一参数相同，和/或，所述第一振荡器配置的第二参数与所述第二振荡器配置的所述第二参数相同时，该锁相装置中的两个环路的对称性更强，能够更有效地解决频率耦合的问题。
结合以上任一方面的任一可能的实现方式，在又一种可能的实现方式中，所述第一交流电压信号为对所述交流连接点处采集的三相电压进行变换得到的两相静止坐标系下的交流电压信号。
结合以上任一方面的任一可能的实现方式，在又一种可能的实现方式中，所述第一交流电压信号为对所述交流连接点处采集的单相电压为由两路相互叠加而成的两相静止坐标系下的交流电压信号；所述两路中的一路电压信号经过了延时处理，且所述延时处理的延时长度为1/4个工频周期。
结合以上任一方面的任一可能的实现方式，在又一种可能的实现方式中，所述第一交流电压信号或者所述第二交流电压信号为经过正序提取之后的正序分量。这样可以消除负序分量产生的负面影响。
结合以上任一方面的任一可能的实现方式，在又一种可能的实现方式中，所述第一交流电压信号和第二交流电压信号的比值与所述第一振荡器输出的幅值控制量之间呈指数函数或者一次函数关系。
第三方面，本申请实施例提供一种控制器，该控制器包括锁相装置和电流控制单元，其中，该锁相装置为上述第一方面或者第一方面的任一可能的实现方式所描述的锁相装置；该电流控制单元用于通过所述锁相装置输出的相位参数输出控制信号，所述控制信号用于控制交流-直流变流器进行功率转换。
第四方面，本申请实施例提供一种并网系统，该并网系统包括交流-直流变流器，和与所述交流直流变流器相连接的控制器，其中：该控制器包括锁相装置和电流控制单元，其中，该锁相装置为上述第一方面或者第一方面的任一可能的实现方式所描述的锁相装置；该电流控制单元用于通过所述锁相装置输出的相位参数输出控制信号，所述控制信号用于控制交流-直流变流器进行功率转换。
第五方面，本申请实施例提供一种可读存储介质，该可读存储介质包括程序指令，所述程序指令在处理器上运行时，实现第二方面或者第二方面的任一可能的实现方式所描述方法。
在本申请实施例中，幅值调节单元、鉴幅鉴相器、第一环路滤波器、第一振荡器构成了锁相装置的一个环路；鉴幅鉴相器、第二环路滤波器、第二振荡器构成了锁相装置的另一个环路，锁相装置的这两个环路形成了对称结构，消除了频率耦合的问题。另外，由于第一振荡器输出的幅值调节量对输入到该锁相装置的电压信号的幅值起到了反馈调节的作用，能够使锁相装置的工作电压幅值保持一个相对稳定地状态，大大提升了该锁相装置的工作性能。
附图说明
以下对本申请实施例用到的附图进行介绍。
图1是现有技术中的一种三相并网变流器的结构示意图；
图2是现有技术中的一种同步旋转坐标系下的锁相环的结构示意图；
图3是本申请实施例提供的一种并网系统的结构示意图；
图4是本申请实施例提供的一种交流-直流变流器的结构示意图；
图5是本申请实施例提供的一种蓄电池储能系统的场景示意图；
图6是本申请实施例提供的一种光伏发电系统的场景示意图；
图7是本申请实施例提供的一种锁相装置的结构示意图；
图8是本申请实施例提供的一种锁相方法的流程示意图；
图9是本申请实施例提供的一种三相变流器并网系统的场景示意图；
图10是本申请实施例提供的一种克拉卡变换的原理示意图；
图11是本申请实施例提供的一种获得两相电压的场景示意图；
图12是本申请实施例提供的又一种获得两相电压的场景示意图；
图13是本申请实施例提供的一种正序提取的场景示意图；
图14A是本申请实施例提供的一种确定相位差的场景示意图；
图14B是本申请实施例提供的一种确定相位差的原理示意图；
图15是本申请实施例提供的又一种锁相装置的结构示意图；
图16是本申请实施例提供的又一种锁相装置的结构示意图；
图17是本申请实施例提供的一种电压波形图；
图18是本申请实施例提供的一种电压波形图；
图19是本申请实施例提供的一种电流频谱图；
图20是本申请实施例提供的一种电流频谱图；
图21是本申请实施例提供的一种仿真波形图；
图22是本申请实施例提供的又一种仿真波形图；
图23是本申请实施例提供的又一种仿真波形图；
图24是本申请实施例提供的又一种仿真波形图；
图25是本申请实施例提供的又一种仿真波形图；
图26是本申请实施例提供的又一种仿真波形图；
图27是本申请实施例提供的又一种仿真波形图；
图28是本申请实施例提供的又一种仿真波形图；
图29是本申请实施例提供的一种锁相装置的结构示意图。
具体实施方式
请参见图3，图3是本申请实施例提供的一种并网系统30的结构示意图，该并网系统(也称交流-直流并网系统、变流系统)包含交流-直流变流器301和控制器302，该控制器302与该交流-直流变流器301相连，该控制器302用于控制所述交流-直流变流器301进行功率变换，其中：
交流-直流变流器301用于连接直流电力系统10和交流电力系统20，并实现两个电力系统之间的功率传输。若功率是从直流电力系统10向交流电力系统20传递，则称为逆变模式，此时交流-直流变流器301又称为逆变器(Inverter)。若功率是从交流电力系统20向直流电力系统10传递，则称为整流模式，此时交流-直流变流器301又称为整流器(Rectifier)，交流-直流变流器301的结构如图4所示。为了保证功率的稳定传输，需要根据直流电力系统10和交流电力系统20的各自的特性对这两种电力系统进行功率控制。例如，直流电力系统10电压极性不随时间变化而变化，因此在进行功率控制时对直流电力系统10传输的电流的幅值进行调节即可；而交流电力系统20电压和电流的大小和极性随时间变化而变化，基本的交流信号(包括电压、电流)具备三个特征量，分别是幅值、频 率和相位，因此，在进行功率控制时除了对交流电力系统20传输的电流的幅值进行调节外以外，还需要对该电流的频率和相位进行控制。控制交流电力系统20电流频率与交流电力系统20电压频率相同，且两者保持固定相位差，即称为交流电力系统“同步”。
交流-直流变流器301可包括单相变流器和三相变流器，无论单相变流器还是三相变流器，均需要保持交流电力系统“同步”。通常，单相变流器传输功率较小，因此常见于小规模分布式电力系统，例如家用电力系统、蓄电池储能系统，等等。三相变流器传输功率较大，常见于大规模电力系统，例如大规模风力发电系统、光伏发电系统，等等。图5示意了一种蓄电池储能系统。图6示意了一种光伏发电系统。需要说明的是，交流-直流变流器301在整流模式和逆变模式下的硬件结构相同，以图5所示场景为例，蓄电池储能系统充电和放电分别对应整流和逆变模式，但蓄电池储能系统充电过程和放电过程所依赖的硬件结构相同。因此本申请实施例不限于某一种模式，另外，本申请实施例中的电网并不限制规模，可以为大型电网，也可以为独立供电的微网。
该控制器302包括电流采样单元3021、电压采样单元3022、电压处理单元3023、锁相装置3024、电流控制单元3025以及调制单元3026，其中，该电流采样单元3021用于连接电流控制单元3025，该电压采样单元3022用于连接电压处理单元3023，该电压处理单元3023用于连接该锁相装置3024，该锁相装置用3024于连接该电流控制单元3025，该电流控制单元3025用于连接调制单元3026，各个单元或者装置的描述如下：
该电流采样单元3021用于从交流-直流变流器301的主电路的交流侧采集电流信号i g，并将采集的电流信号i g输入到电流控制单元3025；该电压采样单元3022用于从交流-直流变流器301的主电路的交流侧采集电压信号，并将采集的电压信号输入到电压处理单元3023。用于从交流-直流变流器301的主电路的交流侧采集电流信号i g，并将采集的电流信号i g输入到电流控制单元3025；该电压采样单元3022用于从交流-直流变流器301的主电路的交流侧采集电压信号，并将采集的电压信号输入到电压处理单元3023。
该电压处理单元3023的输入和输出均为电压信号，用于执行正序提取或坐标变换等功能，其中正序提取功能为提取采样电压信号中的正序分量，以抑制谐波和负序分量的干扰，而坐标变换则是将单相或三相的电压信号转换为两相静止坐标系下的信号，匹配锁相装置的输入。
锁相装置3024用于根据输入的电压信号产生电流的幅值θ m和相位θ p，另外，锁相装置3024输出到电流控制单元3025的电流幅值参考值i M为外部原件输入到锁相转置3024的或者直接通过程序配置在该锁相装置3024中的。
电流控制单元3025用于根据电流幅值参考值i M、以及锁相装置3024产生的相位θ p和幅值θ m对电流采样单元3021采集的电流信号i g进行调节，产生控制信号。
调制单元3026将控制信号转化为与交流-直流变流器301相匹配的半导体开关驱动信号，直接控制交流-直流变流器301中半导体的开通或关断状态，从而实现了对交流-直流变流器301的控制。
需要说明的是，本申请实施例将重点讲述该锁相装置3024的结构和该锁相装置3024的工作原理。
请参见图7，图7是本申请实施例提供的一种锁相装置3024的结构示意图，该锁相装 置3024包括幅值调节单元701、鉴幅鉴相器702、第一环路滤波器703、第二环路滤波器706、第一振荡器704和第二振荡器705，该幅值调节单元701的输入端连接该第一振荡器704的输出端，该幅值调节单元701的输出端连接该鉴幅鉴相器702的输入端，该鉴幅鉴相器702的输入端连接该第二振荡器705的输出端，该鉴幅鉴相器702的输出端连接该第一环路滤波器703的输入端和该第二环路滤波器706的输入端，该第一环路滤波器703的输出端连接该第一振荡器704的输入端，第二环路滤波器706的输出端连接该第二振荡器705的输入端。
请参见图8，图8是本申请实施例提供的一种锁相方法的流程示意图，该流程可以基于图7所示的结构的锁相装置3024来实现，该方法包括但不限于如下步骤：
步骤S801:所述幅值调节单元根据所述第一振荡器的输出幅值调节量补偿第一交流电压信号以得到第二交流电压信号。
具体地，该第一振荡器与该幅值调节单元之间形成了一个反馈调节的环路，该第一振荡器输出的幅值调节量反过来输入到幅值调节单元以用于对第一交流电压进行补偿，而后续对补偿所得到的第二交流电压信号进行一系列处理(具体处理流程在后面描述中体现)又可以得到新的幅值调节量。另外，所述第一交流电压信号为从交流连接点(例如，公共连接点(Point of Common Coupling，PCC))采集的交流电压信号或者从所述交流连接点采集的交流电压信号经变换后的电压信号，所述交流连接点为用于接入交流系统的接入点。下面例举第一交流电压信号的两种可能的情况：
第一种情况，所述第一交流电压信号为对所述交流连接点处采集的三相电压进行变换得到的两相静止坐标系下的交流电压信号。如图9所示，锁相装置应用于一个三相变流器并网系统，该三相变流器并网系统中的采样单元采集三相电压v a、v b、v c，通过将该三相电压经过Clarke变换，获得两相静止坐标系下的电压(v α，v β)，这里简单地介绍一下克拉克Clarke变换的基本原理，如图10所示，存在电压空间矢量v s和两个坐标系，一个坐标系是三相静止坐标系，有a轴，b轴，c轴共三个轴，这三个轴相互夹角为120°，v s在这三个轴上的投影分别为v a、v b、v c。另一个坐标系是两相静止坐标系，有α轴和β轴共两个轴，β轴垂直于α轴，v s在这两个轴上的投影分别为v α，v β。因此，Clarke变换就是将电压空间矢量v s在三相静止坐标系中的投影v a、v b、v c通过数学关系转换到两相静止坐标系种的投影v α，v β。公式1-1为变换时采用的一种可选的数学方程：
Figure PCTCN2019080687-appb-000001
第二种情况，所述第一交流电压信号为对所述交流连接点处采集的单相电压分为两路所叠加而成的两相静止坐标系下的交流电压信号；如图11所示，所述两路中的一路电压信号经过了延时处理，且所述延时处理的延时长度为1/4个工频周期。基本思路是一个完整的工频周期对应360°，则1/4个工频周期对应90°，刚好能够满足两相静止坐标系的两个坐标轴垂直90°的数学关系。在这种情况中，两路中未经过时延处理的一路为电压信号v α，经过时延处理的一路为电压信号v β，这两路即构成第一交流电压信号(v α，v β)。
以上举例介绍了第一交流电压的获取方式，下面讲述如何根据幅值调节量补偿第一交 流电压信号以得到第二交流电压信号。由于交流连接点采集的交流电压信号的幅值受电网阻抗Zg和流经Zg的电流大小影响，因此变换得到第一电压信号(v α，v β)的幅值也会受到影响，出现不稳定的情况。因此幅值调节单元根据第一振荡器输出的幅值调节量θ m对第一交流电压信号进行调节，使得调节后得到的第二电压信号(v α0，v β0)的幅值稳定在一个较理想的区间。根据幅值调节量θ m补偿第一交流电压信号(v α，v β)到第二交流电压信号(v α0，v β0)的方式可以如下：
方式一：指数实现方式，具体的增益关系参照公式1-2所示：
Figure PCTCN2019080687-appb-000002
其中，a为预先设定的大于0的常数，例如，设置为e，此时的增益关系如公式1-3所示：
Figure PCTCN2019080687-appb-000003
方式二：分数实现方式，具体的增益关系参照公式1-4所示：
Figure PCTCN2019080687-appb-000004
其中，a为预先设定的大于0的常数。
在一种可选的方案中，所述第一交流电压信号或者所述第二交流电压信号为经过正序提取之后的正序分量，这样可以消除负序分量产生的负面影响。如图12所示，采集单元采集的三相电压经过Clarke变换得到的两相静止坐标系下的第一交流电压信号，在根据第一交流电压信号得到第二交流电压信号的过程中先对第一交流电压信号进行正序提取得到正序分量，然后使用第一振荡器输出的幅值调节量对该第一交流电压信号的正序分量进行补偿，从而得到第二交流电压信号，因此此时的第二交流电压信号属于经过正序提取之后的正序分量。目前通常采用双二阶广义积分的正交生成器(DSOGI-QSG)和正序计算(Positive Sequence Calculator，PSC)来提取正序分量，图13为正序提取的示意图，第一交流电压信号(v α，v β)与第一交流电压信号的正序分量(v α +，v β +)之间满足公式1-5和1-6所示数学关系。
Figure PCTCN2019080687-appb-000005
Figure PCTCN2019080687-appb-000006
其中，k为二阶广义积分的阻尼比，ω为谐振频率，s为复频率，是经典控制理论中，由于对时域函数进行拉普拉斯变换产生的特征变量。
之后，该幅值调节单元向鉴幅鉴相器输出该第二交流电压信号(v α0，v β0)。
步骤S802：所述鉴幅鉴相器根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值。
具体地，根据第二交流电压信号的幅值和该预设的参考电压幅值即可计算出幅值差值，所述幅值差值用于表征所述第二交流电压信号的幅值相对于所述参考电压幅值的偏移；可选的，该预设的参考电压幅值可以为锁相装置所连接交流电力系统的额定电压值。另外，该第二振荡器与该鉴幅鉴相器之间形成了一个反馈调节的环路，从第二振荡器输出的相位估计值输入到鉴幅鉴相器，然后由鉴幅鉴相器根据第二交流电压信号的相位和该相位估计值计算出相位差值，所述相位差值用于表征所述第二交流电压信号的相位相对于所述相位估计值的偏移。下面举例介绍鉴幅鉴相器确定幅值差值和相位差值的几种可选方案。
第一种可选的方案中，鉴幅鉴相器根据第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和第二振荡器输出的相位估计值确定相位差值，可以包括：所述鉴幅鉴相器根据所述第二振荡器输出的相位估计值θ p对第二电压信号(v α0，v β0)进行坐标变换以得到旋转坐标系下的直轴信号v d和交轴信号v q，公式1-7示意了相位估计值θ p、第二电压信号(v α0，v β0)和直轴信号v d和交轴信号v q之间的一种可能的数学关系。
Figure PCTCN2019080687-appb-000007
根据同步旋转坐标系的基本原理可以得出，在稳态时，v d等于(v α0，v β0)组成的空间矢量v s0的幅值相关，而v q等于θ p与v s0的相位的差值，因此，所述鉴幅鉴相器进一步根据所述直轴信号v d与预设的参考电压幅值m ref确定幅值差值e m，以及根据所述交轴信号v q确定相位差值e p。其中，参考电压幅值m ref为预先设置的用于参考对比的值，公式1-8示意了直轴信号v d、参考电压幅值m ref和幅值差值e m之间的一种可能的数学关系，公式1-9示意了交轴信号v q和相位差值e p之间的一种可能的数学关系。
e m＝v d-m ref    1-8
e p＝v q      1-9
第二种可选的方案中，所述鉴幅鉴相器702包括鉴幅器7021和鉴相器7022，即鉴幅器7021与鉴相器7022相对独立。在这种情况下，所述鉴幅鉴相器702根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器705输出的相位估计值确定相位差值，可以包括：所述鉴幅器7021提取所述第二交流电压信号的幅值，并根据提取出的幅值v n和预设的参考电压幅值m ref确定幅值差值e m，例如，e m＝v n-m ref。另外，所述鉴相器7022提取所述第二交流电压信号的相位或者所述第一交流电压信号的相位，并根据提取出的相位和所述第二振荡器输出的相位估计值确定相位差值。例如，鉴相器通过信号过零点进行比较以确定相位差，如图14A所示，过零比较鉴相器的主要功能是基于过零检测获取输入信号的特征相位，然后通过计时比较得到该特征相位的出现时间t1与相位估计值等于该特征相位时间t2的时间差Δt，再通过测量转换，将时间差Δt转换成相位差Δθ输出。以图14B为例，定义输入信号由正变负穿越零点的时刻对应特征相位为π，记录该时刻为t1，再记录相位估计值等于π的时刻为t2，通过计时比较得到两个时刻的时间差为Δt，再根据公式Δθ＝2π*Δt/T计算得到相位差Δθ，其中，T为为输入信号的周期时间。在这种可选的方案中，因为幅值调节单元701需要调节的是第一电压信号的幅值，但不需要也不能调整第一电压信号的相位，因此幅值调 节单元701并不一定要连接到鉴相器7022，因此，幅值调节单元701在锁相装置3024中的位置既可以如图15所示，也可以如图16所示。
步骤S803：所述鉴幅鉴相器向第一环路滤波器输出幅值差值以及向所述第二环路滤波器输出相位差值。
步骤S804：所述第一环路滤波器对输入的幅值差值进行滤波处理以得到幅值控制量，所述第二环路滤波器对输入的相位差值进行滤波处理以得到相位控制量。
具体地，滤波过程中，可以通过滤除高频干扰来实现精度控制，可以通过对幅值或者相位进行缩放处理来实现速度控制，例如，第一环路滤波器用于对输入的幅值差值滤除高频干扰以及进行缩放处理，以得到幅值控制量；第二环路滤波器用于对输入的相位差值滤除高频干扰以及进行缩放处理，以得到相位控制量。该第一环路滤波器和第二环路滤波器均可以采用PI调节原理，可选的，该第一环路滤波器和该第二环路滤波器所配置的第一参数相同(例如，第一参数可以包括比例参数、低频增益、截止频率等参数中的一项或者多项)，公式1-10示意了幅值差值e m与幅值控制量d m之间，以及相位差值d p与相位控制量e p之间的一种可选的数学关系。
Figure PCTCN2019080687-appb-000008
其中，K p为预设的比例参数，K i为预设的积分参数，s为复频率。
该第一环路滤波器得到幅值控制量之后向第一振荡器输出该幅值控制量，该第二环路滤波器得到相位控制量之后向第二振荡器输出该相位控制量。
步骤S805：所述第一振荡器对所述第一环路滤波器输出的幅值控制量进行转换以得到幅值调节量，所述第二振荡器对所述第二滤波器输出的相位控制量进行转换以得到相位估计值。
具体地，对幅值控制量进行转换可以包括对输入的幅值控制量进行积分处理，对相位控制量进行转换可以包括对输入的相位控制量进行积分处理。即第一振荡器和第二振荡器均采用积分原理，可选的，第一振荡器和第二振荡器所配置的第二参数相同(例如，该第二参数可以包括积分系数)，公式1-11示意了幅值控制量d m与幅值调节量θ m之间，以及相位控制量e p与相位调节量θ p之间的一种可选的数学关系。
Figure PCTCN2019080687-appb-000009
需要说明的是，可能所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的第一参数相同，并且所述第一振荡器配置的第二参数与所述第二振荡器配置的第二参数相同。也可能，所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的第一参数相同，但所述第一振荡器配置的第二参数与所述第二振荡器配置的第二参数不相同。也可能，所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的第一参数不相同，但所述第一振荡器配置的第二参数与所述第二振荡器配置的第二参数相同。也可能，所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的第一参数不相同，并且所述第一振荡器配置的第二参数与所述第二振荡器配置的第二参数不相同。可以理解的是，所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的第一参数相同，能够进一 步提升锁相装置的对称性，因此能够进一步减弱频率耦合问题。所述第一振荡器配置的第二参数与所述第二振荡器配置的第二参数相同，能够进一步提升锁相装置的对称性，因此能够进一步减弱频率耦合问题。
下面结合仿真图讲述本申请实施例相对于现有技术的两个主要的有益效果。
一、消除频率耦合问题。
为了验证现有技术中的不对称结构锁相装置与本申请实施例锁相装置在频率耦合方面的性能差异，在仿真过程中，在PCC点电压中加入300Hz的扰动，幅值为50Hz电压的10％。
加入扰动后的PCC点电压波形如图17所示，图17中两个波形分别是两相静止坐标系中v α,v β的波形，可以看出两个电压信号在时间上相差1/4个工频周期(即对应相角为
Figure PCTCN2019080687-appb-000010
)，且波形存在明显的谐波分量，如图18所示，具有明显的50Hz与300Hz分量。
将扰动电压输入到分别装有不对称结构锁相装置和本申请实施例锁相装置的逆变器(并网系统)中，对输出电流分别进行频谱分析，结果如图19和图20所示。从图19可以看出不对称结构锁相装置中除了工频50Hz分量与原有扰动对应的300Hz分量以外，还多出了200Hz的频率分量，由此解释了该锁相装置中存在明显的频率耦合特性。而对应的图20中，本申请实施例所示的双环路对称结构锁相装置中的频率分量仅有50Hz和300Hz，与PCC点电压的频率分量相同，由此可以说明本申请实施例的锁相装置由于结构对称，消除频率耦合特性。
二、为锁相装置提供更稳定地电压信号。
为了对比不同锁相装置受输入信号幅值的影响，在每种锁相装置设置两个工况，输入信号幅值分别为100％和70％，在t＝0.5s时，输入信号的相位发生30°的跳变，通过观测动态响应来比较输入信号幅值对不同系统的性能影响。
首先，现有不对称锁相装置的仿真波形如图21、图22、图23、图24所示，由于不具备幅值补偿单元，则锁相装置输入信号和鉴相器输入信号相同，图21对应100％输入信号工况的v α,v β，图22对应70％输入信号工况的v α,v β。通过对比图23所示的100％输入信号工况和图24所示的70％输入信号工况下环路滤波器的输出量变化情况，可以看出在不同的输入信号工况下，环路滤波器输出量的动态幅值变化存在明显差异。
其次，本申请实施例锁相装置的仿真波形如图25、图26、图27、图28所示，由于具有幅值调节环路，则鉴幅鉴相器输入信号的幅值能够通过调节而基本保持一致，图25对应100％补偿后输入信号工况的v αo,v βo，图26对应70％补偿后输入信号工况的v αo,v βo，两种工况中补偿后的输入信号幅值在稳态均为100％，而在系统发生扰动的瞬间，由于本申请实施例锁相装置的幅值调节环路需要一定的时间进行闭环调节，因此补偿后的电压会在较短的瞬间不等于100％。通过对比图27所示的100％补偿后输入信号和图28所示的70％补偿后输入信号下环路滤波器的输出量变化情况，可以看出在不同的输入信号工况下，环路滤波器输出量的动态幅值变化几乎没有差异。
通过对比可以看出，本申请实施例锁相装置能够对系统输入信号的幅值进行自动补偿，消除了输入信号幅值变化对锁相装置性能的影响。
综上所述，幅值调节单元、鉴幅鉴相器、第一环路滤波器、第一振荡器构成了锁相装置的一个环路；鉴幅鉴相器、第二环路滤波器、第二振荡器构成了锁相装置的另一个环路， 锁相装置的这两个环路形成了对称结构，抑制了负序分量的产生，因此能够减弱锁相装置产生的正序分量与该锁相装置产生的负序分量之间的频率耦合问题。另外，由于第一振荡器输出的幅值调节量对输入到该锁相装置的电压信号的幅值起到了反馈调节的作用，能够使锁相装置的工作电压幅值保持一个相对稳定地状态，大大提升了该锁相装置的工作性能。
需要说明的是，本申请实施例中的锁相转置包括的幅值调节单元、鉴幅鉴相器、第一环路滤波器、第二环路滤波器、第一振荡器和第二振荡器中，可能有部分单元(或器件)为通过硬件电路来实现而另一部分单元(或器件)通过软件来实现，也可能其中所有单元(或器件)都通过硬件电路来实现，还可能其中所有单元(或器件)都通过软件来实现。当有某个(或某些)单元(或器件)通过软件来实现时，该锁相装置包括处理器，该处理器通过运行程序指令来实现该某个(或某些)单元(或器件)，例如，假若该幅值调节单元是通过软件的方式来实现，那么该锁相装置通过运行程序指令可以完成幅值调节任务，相当于基于处理器虚拟出了一个幅值调节单元。可以理解的是，当其中所有单元(或器件)都通过软件来实现时，该锁相转置的结构可以如图29所示，如图29所示，该锁相装置包括存储器2901，处理器2902，通信接口2903，其中，处理器2902、通信接口2903以及存储器2901可以相互连接，例如，通过总线2904相互连接。其中，该存储器2901用于存储锁相装置的代码和数据，例如，存储了用于实现幅值调节单元的代码、实现鉴幅鉴相器的代码、实现第一环路滤波器的代码、实现第二环路滤波器的代码、实现第一振荡器的代码、实现第二振荡器的代码，等等。该处理器2901执行这些代码便可以虚拟出幅值调节单元、鉴幅鉴相器、第一环路滤波器、第二环路滤波器、第一振荡器和第二振荡器这些功能单元。另外，通信接口2903用于支持该锁相装置与外部设备之间进行信号传递，例如，用于支持锁相装置接入上述电压处理单元输出的交流电压信号(v α,v β)，支持该锁相装置向上述电压控制单元输出用于控制的相位和幅值。
另外，该处理器2902可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。另外，该存储器可以包括：ROM或随机存储记忆体RAM、磁碟或者光盘等各种可存储程序代码的介质。

Claims (20)

  1. 一种锁相装置，其特征在于，包括幅值调节单元、与所述幅值调节单元连接的鉴幅鉴相器、与所述鉴幅鉴相器连接的第一环路滤波器、与所述鉴幅鉴相器连接的第二环路滤波器、与所述第一环路滤波器连接的第一振荡器和与所述第二环路滤波器连接的第二振荡器，其中：
    所述幅值调节单元用于根据所述第一振荡器的输出幅值调节量补偿第一交流电压信号以得到第二交流电压信号，所述第一交流电压信号为来自交流连接点的交流电压信号，所述交流连接点为用于接入交流系统的接入点；
    所述鉴幅鉴相器用于根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值；所述鉴幅鉴相器还用于向第一环路滤波器输出幅值差值以及向所述第二环路滤波器输出相位差值，其中，所述幅值差值用于表征所述第二交流电压信号的幅值相对于所述参考电压幅值的偏移，所述相位差值用于表征所述第二交流电压信号的相位相对于所述相位估计值的偏移；
    所述第一环路滤波器用于对输入的所述幅值差值进行滤波处理以得到幅值控制量，所述第二环路滤波器用于对输入的所述相位差值进行滤波处理以得到相位控制量；
    所述第一振荡器用于对所述第一环路滤波器输出的幅值控制量进行转换以得到幅值调节量，所述第二振荡器用于对所述第二滤波器输出的相位控制量进行转换以得到相位估计值。
  2. 根据权利要求1所述的锁相装置，其特征在于，在根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值的方面，
    所述鉴幅鉴相器具体用于根据所述第二振荡器输出的相位估计值对所述第二电压信号进行坐标变换以得到旋转坐标系下的直轴信号和交轴信号，以及根据所述直轴信号与预设的参考电压幅值确定幅值差值，以及根据所述交轴信号确定相位差值。
  3. 根据权利要求1所述的锁相装置，其特征在于，所述鉴幅鉴相器包括鉴幅器和鉴相器；在根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值的方面，
    所述鉴幅器用于提取所述第二交流电压信号的幅值，并根据提取出的幅值和预设的参考电压幅值确定幅值差值；
    所述鉴相器用于提取所述第二交流电压信号的相位或者所述第一交流电压信号的相位，并根据提取出的相位和所述第二振荡器输出的相位估计值确定相位差值。
  4. 根据权利要求1-3任一项所述的锁相装置，其特征在于：
    所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的所述第一参数相同， 和/或，
    所述第一振荡器配置的第二参数与所述第二振荡器配置的所述第二参数相同；
    其中，所述第一参数包括比例参数、低频增益和截止频率中的一项或者多项，所述第二参数包括积分系数。
  5. 根据权利要求1-4任一项所述的锁相装置，其特征在于，所述第一交流电压信号为对所述交流连接点处采集的三相电压进行变换得到的两相静止坐标系下的交流电压信号。
  6. 根据权利要求1-4任一项所述的锁相装置，其特征在于，所述第一交流电压信号为对所述交流连接点处采集的单相电压为由两路相互叠加而成的两相静止坐标系下的交流电压信号，其中所述两路中的一路电压信号经过了延时处理，且所述延时处理的延时长度为1/4个工频周期。
  7. 根据权利要求1-6任一项所述的锁相装置，其特征在于，所述第一交流电压信号或者所述第二交流电压信号为经过正序提取之后的正序分量。
  8. 根据权利要求1-7任一项所述的锁相装置，其特征在于，所述第一交流电压信号和第二交流电压信号的比值与所述第一振荡器输出的幅值控制量之间呈指数函数或者一次函数关系。
  9. 根据权利要求1-8任一项所述的锁相装置，其特征在于，在所述第一环路滤波器用于对输入的所述幅值差值进行滤波处理以得到幅值控制量，所对输入的所述相位差值进行滤波处理以得到相位控制量的方面，
    所述第一环路滤波器具体用于对输入的所述幅值差值滤除高频干扰以及进行缩放处理，以得到幅值控制量；所述第二环路滤波器具体用于对输入的所述相位差值滤除高频干扰以及进行缩放处理，以得到相位控制量。
  10. 一种锁相方法，其特征在于，所述锁相方法应用于锁相装置，所述锁相装置包括幅值调节单元、与所述幅值调节单元连接的鉴幅鉴相器、与所述鉴幅鉴相器连接的第一环路滤波器、与所述鉴幅鉴相器连接的第二环路滤波器、与所述第一环路滤波器连接的第一振荡器和与所述第二环路滤波器连接的第二振荡器，所述方法包括：
    根据所述第一振荡器的输出幅值调节量补偿第一交流电压信号以得到第二交流电压信号，所述第一交流电压信号为来自交流连接点的交流电压信号，所述交流连接点为用于接入交流系统的接入点；
    根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值；向第一环路滤波器输出幅值差值以及向所述第二环路滤波器输出相位差值，其中，所述幅值差值用于表征所述第二交流电压信号的幅值相对于所述参考电压幅值的偏移，所述相位差值用于表征所述第二 交流电压信号的相位相对于所述相位估计值的偏移；
    对输入的所述幅值差值进行滤波处理以得到幅值控制量，对输入的所述相位差值进行滤波处理以得到相位控制量；
    对所述第一环路滤波器输出的幅值控制量进行转换以得到幅值调节量，对所述第二滤波器输出的相位控制量进行转换以得到相位估计值。
  11. 根据权利要求10所述的方法，其特征在于，所述根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值，包括：
    根据所述第二振荡器输出的相位估计值对所述第二电压信号进行坐标变换以得到旋转坐标系下的直轴信号和交轴信号；
    根据所述直轴信号与预设的参考电压幅值确定幅值差值，以及根据所述交轴信号确定相位差值。
  12. 根据权利要求10所述的方法，其特征在于，所述根据所述第二交流电压信号和预设的参考电压幅值确定幅值差值，以及根据所述第二交流电压信号和所述第二振荡器输出的相位估计值确定相位差值，包括：
    提取所述第二交流电压信号的幅值，并根据提取出的幅值和预设的参考电压幅值确定幅值差值；
    提取所述第二交流电压信号的相位或者所述第一交流电压信号的相位，并根据提取出的相位和所述第二振荡器输出的相位估计值确定相位差值。
  13. 根据权利要求10-12任一项所述的方法，其特征在于：
    所述第一环路滤波器配置的第一参数与所述第二环路滤波器配置的所述第一参数相同，和/或，
    所述第一振荡器配置的第二参数与所述第二振荡器配置的所述第二参数相同
    其中，所述第一参数包括比例参数、低频增益和截止频率中的一项或者多项，所述第二参数包括积分系数。
  14. 根据权利要求10-13任一项所述的方法，其特征在于，所述第一交流电压信号为对所述交流连接点处采集的三相电压进行变换得到的两相静止坐标系下的交流电压信号。
  15. 根据权利要求10-13任一项所述的方法，其特征在于，所述第一交流电压信号为对所述交流连接点处采集的单相电压为由两路相互叠加而成的两相静止坐标系下的交流电压信号，其中，所述两路中的一路电压信号经过了延时处理，且所述延时处理的延时长度为1/4个工频周期。
  16. 根据权利要求10-15任一项所述的方法，其特征在于，所述第一交流电压信号或 者所述第二交流电压信号为经过正序提取之后的正序分量。
  17. 根据权利要求10-16任一项所述的方法，其特征在于，所述第一交流电压信号和第二交流电压信号的比值与所述第一振荡器输出的幅值控制量之间呈指数函数或者一次函数关系。
  18. 根据权利要求10-17任一项所述的方法，其特征在于，所述对输入的所述幅值差值进行滤波处理以得到幅值控制量，对输入的所述相位差值进行滤波处理以得到相位控制量，包括：
    对输入的所述幅值差值滤除高频干扰以及进行缩放处理，以得到幅值控制量；对输入的所述相位差值滤除高频干扰以及进行缩放处理，以得到相位控制量。
  19. 一种控制器，其特征在于，所述控制器包括：
    锁相装置，所述锁相装置为权利要求1-9任一项所述的锁相装置；和，
    电流控制单元，用于通过所述锁相装置输出的相位参数输出控制信号，所述控制信号用于控制交流-直流变流器进行功率转换。
  20. 一种并网系统，其特征在于，所述并网系统包括交流-直流变流器，和与所述交流直流变流器相连接的控制器，其中：
    所述控制器包括：
    锁相装置，所述锁相装置为权利要求1-9任一项所述的锁相装置；以及
    电流控制单元，用于通过所述锁相装置输出的相位参数控制所述交流-直流变流器进行功率转换。
PCT/CN2019/080687 2018-05-31 2019-03-30 一种锁相装置及锁相方法 WO2019228054A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19812631.0A EP3793091A4 (en) 2018-05-31 2019-03-30 PHASE LOCK DEVICE AND PHASE LOCK METHOD
US17/105,029 US11038512B2 (en) 2018-05-31 2020-11-25 Phase-locking apparatus and phase-locking method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810553555.7A CN110557118B (zh) 2018-05-31 2018-05-31 一种锁相装置及锁相方法
CN201810553555.7 2018-05-31

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/105,029 Continuation US11038512B2 (en) 2018-05-31 2020-11-25 Phase-locking apparatus and phase-locking method

Publications (1)

Publication Number Publication Date
WO2019228054A1 true WO2019228054A1 (zh) 2019-12-05

Family

ID=68698696

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/080687 WO2019228054A1 (zh) 2018-05-31 2019-03-30 一种锁相装置及锁相方法

Country Status (4)

Country Link
US (1) US11038512B2 (zh)
EP (1) EP3793091A4 (zh)
CN (1) CN110557118B (zh)
WO (1) WO2019228054A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117318163A (zh) * 2023-11-30 2023-12-29 广东电网有限责任公司 一种基于对称锁相环结构的并网变流器运行控制方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102200554B1 (ko) * 2019-05-28 2021-01-08 효성중공업 주식회사 계통 전압 위상 검출 장치
US11761994B2 (en) * 2020-09-18 2023-09-19 Smart Wires Inc. Method and apparatus for detecting faults using current unbalance
CN115498642B (zh) * 2022-11-18 2023-03-17 深圳市首航新能源股份有限公司 一种阻抗建模方法、稳定性分析方法及逆变器
CN115955135A (zh) * 2023-03-15 2023-04-11 南昌工程学院 逆变器控制方法、系统、计算机及可读存储介质
CN117614020B (zh) * 2024-01-24 2024-03-29 浙江日风电气股份有限公司 一种软件锁相环的方法、装置以及介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003052936A1 (en) * 2001-12-19 2003-06-26 Tait Electronics Limited Improvements relating to frequency synthesis
CN101841327A (zh) * 2010-03-05 2010-09-22 中兴通讯股份有限公司 一种信号处理系统和方法
CN101944910A (zh) * 2009-07-07 2011-01-12 晨星软件研发(深圳)有限公司 双锁相环电路及其控制方法
CN201830237U (zh) * 2010-06-30 2011-05-11 中国电力科学研究院 一种基于滤波器的软锁相环

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723718A (en) * 1970-11-09 1973-03-27 Syst De Corp Simulation through rotating coordinate transformation
US4095255A (en) * 1977-04-07 1978-06-13 Rca Corporation Controlled oscillator with increased immunity to parasitic capacitance
US5093847A (en) * 1990-12-21 1992-03-03 Silicon Systems, Inc. Adaptive phase lock loop
US5438591A (en) * 1991-07-31 1995-08-01 Kabushiki Kaisha Toshiba Quadrature amplitude modulation type digital radio communication device and method for preventing abnormal synchronization in demodulation system
US5105168A (en) * 1991-08-28 1992-04-14 Hewlett-Packard Company Vector locked loop
JPH09224059A (ja) * 1996-02-15 1997-08-26 General Res Of Electron Inc 直接変換ｆｓｋ受信機
US6194929B1 (en) * 1997-06-25 2001-02-27 Sun Microsystems, Inc. Delay locking using multiple control signals
US6232835B1 (en) * 1998-02-13 2001-05-15 Nortel Networks Limited System and method of linearizing the gain error of a power amplifier
CN1802828A (zh) * 2003-06-11 2006-07-12 皇家飞利浦电子股份有限公司 用于多载波通信系统的接收机
US7397300B2 (en) * 2003-09-09 2008-07-08 Analog Devices, Inc. FSK demodulator system and method
US7342980B2 (en) * 2003-12-30 2008-03-11 Intel Corporation Estimating carrier phase in communication systems
US7208908B2 (en) * 2004-07-12 2007-04-24 Honeywell International Inc. Apparatus and method to control torque and voltage of an AC machine
JP4514616B2 (ja) * 2005-02-01 2010-07-28 富士通セミコンダクター株式会社 周波数同期または位相同期を自動確立する無線受信装置
US8170130B2 (en) * 2005-03-28 2012-05-01 Panasonic Corporation Transmission method and transmission system
WO2007114049A1 (ja) * 2006-03-29 2007-10-11 Matsushita Electric Industrial Co., Ltd. 無線伝送システム並びにそれに用いられる無線局及び方法
US7719330B2 (en) * 2007-12-26 2010-05-18 Ali Corporation Phase locked loop device and control method thereof
JP5672683B2 (ja) * 2009-09-29 2015-02-18 ソニー株式会社 無線伝送システム、無線通信装置
US8831073B2 (en) * 2009-08-31 2014-09-09 Sony Corporation Wireless transmission system, wireless communication device, and wireless communication method
CN101807918B (zh) * 2010-04-15 2012-01-04 西安交通大学 基于同步坐标系的单相锁相环及其实现方法
KR101313662B1 (ko) * 2010-08-27 2013-10-02 한양대학교 산학협력단 지연 고정 루프를 이용한 능동형 정류기, 능동형 정류기를 포함하는 무선전력 수신 장치
US8866519B1 (en) * 2013-02-28 2014-10-21 Pmc-Sierra Us, Inc. System and method for reducing spectral pollution in a signal
CN103297042A (zh) * 2013-06-24 2013-09-11 中国科学院微电子研究所 一种可快速锁定的电荷泵锁相环电路
JP5929874B2 (ja) * 2013-11-05 2016-06-08 株式会社デンソー 交流電動機の制御装置
US9270286B2 (en) * 2014-06-30 2016-02-23 Rockwell Automation Technologies, Inc. Phase lock loop with cascade tracking filters for synchronizing an electric grid
JP6390337B2 (ja) * 2014-10-21 2018-09-19 株式会社デンソー 回転電機の制御装置
CN104320137B (zh) * 2014-10-22 2015-10-21 华中科技大学 一种锁相环频率合成器
US10404064B2 (en) * 2015-08-18 2019-09-03 Virginia Tech Intellectual Properties, Inc. Modular multilevel converter capacitor voltage ripple reduction
JP6583000B2 (ja) * 2016-01-07 2019-10-02 株式会社デンソー 回転電機の制御装置
US10148322B2 (en) * 2016-04-01 2018-12-04 Intel IP Corporation Demodulator of a wireless communication reader
EP3451557B1 (en) * 2016-04-25 2020-09-16 Kyowa Electronic Instruments Co, Ltd Radio communication system
US9960774B2 (en) * 2016-07-07 2018-05-01 Samsung Display Co., Ltd. Spread spectrum clocking phase error cancellation for analog CDR/PLL
TWI616047B (zh) * 2017-03-10 2018-02-21 雙向電源轉換裝置
JP6958234B2 (ja) * 2017-10-26 2021-11-02 株式会社デンソー 電流検出装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003052936A1 (en) * 2001-12-19 2003-06-26 Tait Electronics Limited Improvements relating to frequency synthesis
CN101944910A (zh) * 2009-07-07 2011-01-12 晨星软件研发(深圳)有限公司 双锁相环电路及其控制方法
CN101841327A (zh) * 2010-03-05 2010-09-22 中兴通讯股份有限公司 一种信号处理系统和方法
CN201830237U (zh) * 2010-06-30 2011-05-11 中国电力科学研究院 一种基于滤波器的软锁相环

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3793091A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117318163A (zh) * 2023-11-30 2023-12-29 广东电网有限责任公司 一种基于对称锁相环结构的并网变流器运行控制方法
CN117318163B (zh) * 2023-11-30 2024-03-08 广东电网有限责任公司 一种基于对称锁相环结构的并网变流器运行控制方法

Also Published As

Publication number Publication date
US20210083679A1 (en) 2021-03-18
US11038512B2 (en) 2021-06-15
CN110557118B (zh) 2022-12-27
CN110557118A (zh) 2019-12-10
EP3793091A1 (en) 2021-03-17
EP3793091A4 (en) 2021-07-07

Similar Documents

Publication Publication Date Title
WO2019228054A1 (zh) 一种锁相装置及锁相方法
CN106655276B (zh) 一种适用于三相电网电压的锁相方法
CN102305886B (zh) 电网电压谐波畸变及不平衡时基波电压同步信号检测方法
US10084403B2 (en) Power supply system and control method therefor
CN108599261B (zh) 基于非线性pi和解耦双同步坐标系锁相环的锁相方法
Xiong et al. A novel PLL for grid synchronization of power electronic converters in unbalanced and variable-frequency environment
CN107623522B (zh) 一种基于d-q变换的双二阶广义积分锁相环控制方法
CN103267897B (zh) 一种基于反Park变换的三相锁相环
CN102401858A (zh) 一种电网电压基波分量及谐波分量的检测方法
CN107591809A (zh) 多周期并联重复控制谐波和间谐波指定次补偿方法
CN107423261B (zh) 非理想微电网条件下基于ovpr的正负序分量的分离方法
CN103986458A (zh) 一种基于重复控制的微电网单相并网锁相环控制方法
CN109193793B (zh) 一种变流器免电压检测的并网控制系统和方法
CN109358228B (zh) 基于双增强型锁相环的电网电压正负序分量实时估计方法
CN108809301B (zh) 一种基于滑动dft滤波原理的三相软件锁相方法
CN113014250A (zh) 一种可消除直流偏移电压的锁相环及其锁相控制方法
CN103546149A (zh) 一种三相电力系统的锁相方法
Arricibita et al. Simple and robust PLL algorithm for accurate phase tracking under grid disturbances
CN111431210B (zh) 三相并网型变流器的锁相环控制方法及系统
Zhu et al. Research and analysis of SOGI-QSG integral saturation in the application of grid synchronization
CN109861227A (zh) 一种用于低次谐波消除的锁相环电路
CN109524963A (zh) 一种基于微分消谐的dsogi锁相环
Xu et al. An Improved High Bandwidth DSOGI-PLL and its Optimized Digital Implementation
Wang et al. Phase-lock loop of Grid-connected Voltage Source Converter under non-ideal grid condition
Wang Optimization strategy of DSOGI-PLL precision under harmonic interference conditions

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19812631

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019812631

Country of ref document: EP

Effective date: 20201210