WO2018166178A1 - 一种阵列基板及其制作方法、显示面板和显示装置 - Google Patents

一种阵列基板及其制作方法、显示面板和显示装置 Download PDF

Info

Publication number
WO2018166178A1
WO2018166178A1 PCT/CN2017/104162 CN2017104162W WO2018166178A1 WO 2018166178 A1 WO2018166178 A1 WO 2018166178A1 CN 2017104162 W CN2017104162 W CN 2017104162W WO 2018166178 A1 WO2018166178 A1 WO 2018166178A1
Authority
WO
WIPO (PCT)
Prior art keywords
common electrode
lines
array substrate
disposed
line
Prior art date
Application number
PCT/CN2017/104162
Other languages
English (en)
French (fr)
Inventor
朱宁
苏秋杰
赵重阳
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020197025115A priority Critical patent/KR102259202B1/ko
Priority to EP17900750.5A priority patent/EP3598495B1/en
Priority to JP2019548476A priority patent/JP7180841B2/ja
Priority to US15/779,222 priority patent/US11296123B2/en
Priority to KR1020217016003A priority patent/KR102397834B1/ko
Publication of WO2018166178A1 publication Critical patent/WO2018166178A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method for fabricating the same, a display panel, and a display device.
  • a metal common electrode line (also referred to as a gate layer common electrode line) parallel to the gate line is disposed in the gate metal layer.
  • the gate layer common electrode line is connected to the transparent common electrode through the via hole.
  • the present disclosure provides an array substrate, a method for fabricating the same, a display panel, and a display device for solving the problem of uneven distribution of common voltage of the display panel in the related art, and the common voltage is unstable, resulting in poor display.
  • the present disclosure provides an array substrate including a transparent common electrode, a plurality of first common electrode lines, and a plurality of second common electrode lines, the plurality of first common electrode lines and a plurality of second The common electrode lines are alternately arranged to form a grid shape, the first common electrode line is connected to the common electrode through a first via hole, and the second common electrode line is connected to the common electrode through a second via hole.
  • the first common electrode line and the second common electrode line are disposed in different layers.
  • the array substrate further includes a plurality of gate lines, and the first common electrode lines are disposed in parallel and in parallel with the gate lines.
  • the array substrate further includes a plurality of data lines, the second common electrode line and the The data lines are arranged in the same layer and in parallel.
  • the array substrate is a double-gate line type array substrate, two gate lines are disposed between adjacent two rows of sub-pixels, and a data line is disposed in a spaced column of adjacent two columns of sub-pixels.
  • the two common electrode lines are disposed between two columns of sub-pixels in which the data lines are not disposed.
  • the common electrodes of each sub-pixel are separately disposed, the common electrodes in the same row are connected by the first common electrode line, and the common electrodes in the same column are connected by the second common electrode line.
  • the first via is a deep via compared to the second via.
  • the array substrate further includes: a base substrate, a gate insulating layer, a pixel electrode, and an insulating layer.
  • the first common electrode line is disposed on the base substrate;
  • the gate insulating layer is disposed on the base substrate and covers the plurality of first common electrode lines;
  • the pixel electrode and the plurality of a second common electrode line is disposed on the gate insulating layer;
  • the insulating layer is disposed on the gate insulating layer and covers the pixel electrode and the plurality of second common electrode lines;
  • the transparent common electrode Provided on the insulating layer; the first via penetrates through the insulating layer and the gate insulating layer; and the second via penetrates through the insulating layer.
  • the present disclosure also provides a display panel including the above array substrate.
  • the present disclosure also provides a display device including the above display panel.
  • the present disclosure also provides a method for fabricating an array substrate, comprising forming a grid shape by intersecting a plurality of first common electrode lines and a plurality of second common electrode lines, and passing the first common electrode lines through the first via holes. Forming the transparent common electrode, the plurality of first common electrode lines, and the plurality of second commons by connecting to the transparent common electrode and connecting the second common electrode line to the transparent common electrode through the second via hole Electrode wire.
  • the first common electrode line and the second common electrode line are disposed in different layers.
  • the forming the transparent common electrode, the plurality of first common electrode lines, and the plurality of second common electrode lines comprises: forming the plurality of first common electrode lines by one patterning process and parallel to the a plurality of gate lines of the plurality of first common electrode lines.
  • the forming the transparent common electrode, the plurality of first common electrode lines, and the plurality of second common electrode lines comprises: forming the plurality of second common electrode lines by one patterning process and parallel to the a plurality of data lines of the plurality of second common electrode lines.
  • FIG. 1 is a top plan view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure.
  • An embodiment of the present disclosure provides an array substrate, including: a transparent common electrode, a plurality of first common electrode lines, and a plurality of second common electrode lines, the plurality of first common electrode lines and the plurality of second common electrode lines The crosswise arrangement is formed in a grid shape, the first common electrode line is connected to the common electrode through a first via hole, and the second common electrode line is connected to the common electrode through a second via hole.
  • the grid-shaped common electrode line connected to the common electrode of the array substrate is disposed, which can effectively reduce the resistance of the common electrode.
  • the common electrode line is distributed in a grid shape, it is not simply a horizontal arrangement.
  • the gate layer common electrode line can ensure the uniformity of the common voltage of the entire panel.
  • the grid-like common electrode line can effectively reduce the resistance of the common electrode, the line width of each common electrode line can be correspondingly reduced. To increase the aperture ratio.
  • the common electrode is usually made of a transparent conductive material such as ITO.
  • first common electrode line and the second common electrode line may be made of a metal conductive material to facilitate reduction of the resistance of the common electrode.
  • the first common electrode line and the second common electrode line are made of a transparent conductive material to increase the aperture ratio.
  • the grid structure formed by the first common electrode line and the second common electrode line covers a region where the common electrode is located.
  • the first common electrode line and the second common electrode line may be disposed in the same layer. It can also be set in different layers.
  • the first common electrode line and the second common electrode line are disposed in the same layer, the first common electrode line and the second common electrode line are connected, in order to avoid interference with patterns on other functional film layers of the array substrate, the species In this case, the first common electrode line and the second common electrode line usually need to be provided in a single layer.
  • the first common electrode line and the second common electrode line may be disposed in the same layer as other functional film layers on the array substrate to reduce
  • the thickness of the film layer optionally, may also be disposed in the same layer as the functional film layer of other conductive layers, so that the conductive functional film layer can be formed by one patterning process, which saves the number of masks and reduces the cost.
  • the array substrate further includes a plurality of gate lines.
  • the first common electrode lines may be disposed in the same layer as the gate lines to save the number of masks and reduce costs. Further optionally, the first common electrode line may be disposed in parallel with the gate line. Of course, in some other embodiments of the present disclosure, the first common electrode line may not be in the same layer as the gate line, and may be disposed perpendicular to the gate line. In this case, each first common electrode line needs to be The position crossing the gate line is broken.
  • one row of sub-pixels may correspond to one first common electrode line, or a plurality of rows of sub-pixels may correspond to one first common electrode line.
  • the array substrate further includes a plurality of data lines.
  • the second common electrode lines may be disposed in the same layer as the data lines to save the number of masks and reduce costs. Further optionally, the second common electrode line may be disposed in parallel with the data line. Of course, in some other embodiments of the present disclosure, the second common electrode line may not be in the same layer as the data line, and may be disposed perpendicular to the data line. At this time, each second common electrode line needs to be Disconnected from the position where the data line intersects.
  • the second common electrode line When the second common electrode line is disposed in the same layer and in parallel with the data line, it may be that one column of sub-pixels corresponds to one second common electrode line, or a plurality of columns of sub-pixels may correspond to one second common electrode line.
  • FIG. 1 is a top view of an array substrate according to an embodiment of the present disclosure.
  • the array substrate in the embodiment of the present disclosure is a double-gate array substrate, including: a plurality of gate lines 101 and a plurality of data lines 102, adjacent to each other. Two gate lines 101 are disposed between the two rows of sub-pixels, and one data line 102 is disposed between the adjacent two columns of sub-pixels, and the common electrodes 103 of each sub-pixel are separately disposed.
  • the array substrate further includes: a plurality of first common electrode lines 104 and a plurality of second common electrode lines 105, the first The common electrode line 104 is disposed in parallel and parallel with the gate line 101.
  • the second common electrode line 105 is disposed in parallel and parallel with the data line, and the second common electrode line 105 is disposed not to be set with the data. Between the two columns of sub-pixels of line 102.
  • the first common electrode line 104 and the second common electrode line 105 form a grid shape.
  • the first common electrode line 104 is connected to the common electrode 103 through a first via 106
  • the second common electrode line 105 is connected to the common electrode 103 through a second via 107.
  • a special structure of one data line is disposed by using a double gate line type array substrate, and a second common electrode line is disposed in one column of the data line not disposed, and a grid-shaped common electrode is formed with the first common electrode line.
  • the line can ensure the uniformity of the common voltage of the entire panel.
  • the grid-like common electrode line can effectively reduce the resistance of the common electrode, the line width of each common electrode line can be correspondingly reduced to increase the aperture ratio. .
  • the common electrodes 103 of each sub-pixel are separately disposed, the common electrodes 103 in the same row are connected through the first common electrode line 104, and the common electrodes 103 in the same column are connected through the second common electrode lines 105, thereby The entire surface common electrode 103 is turned on.
  • An array substrate is provided separately from a common electrode of each sub-pixel.
  • a common electrode of an adjacent sub-pixel must be turned on by a via and an upper metal (such as a source/drain metal layer or a common electrode layer). Turning on the entire surface of the common electrode, this design not only increases the trace but also increases the overlap and lateral capacitance of the trace with other electrodes (such as source and drain electrodes, gate electrodes, etc.), and the increase in capacitance causes the load to increase. The same effect on sub-pixel charging.
  • the common electrodes of the peers can be connected in the lateral direction through the first common electrode line, and the common electrodes in the same row can be connected in the longitudinal direction through the second common electrode line.
  • the common electrodes in the same row can be connected in the longitudinal direction through the second common electrode line.
  • it also effectively reduces the capacitance of the common electrode and the peripheral electrode, making sub-pixel charging easier.
  • FIG. 2 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure.
  • the array substrate in the embodiment is different from the array substrate in the embodiment shown in FIG. 1 in that the common electrode 103 is strip-shaped.
  • the common electrode, and in the embodiment shown in FIG. 1, the common electrode 103 is a bulk common electrode.
  • 100 is a base substrate
  • 108 is a gate insulating layer
  • 109 is a pixel electrode
  • 110 is an insulating layer.
  • the first via 106 and the second via 107 are common.
  • the electrode 103 may be connected to the first common electrode line 104 located at the gate metal layer and the second common electrode line 105 located at the source/drain metal layer.
  • the first via 106 is a deep via and the second via 107 is a shallow via.
  • the array substrate in the embodiment of the present disclosure may be a HADS array substrate, or an IPS array substrate, or another type of array substrate including a common electrode.
  • the embodiment of the present disclosure further provides a display panel, including the array substrate in any of the above embodiments.
  • Embodiments of the present disclosure also provide a display device including the above display panel.
  • the display device in the embodiment of the present disclosure may further include a driving chip, and the driving chip may be connected to the first common electrode line and/or the second common electrode line for passing the first common electrode line and/or the second common electrode The line transmits a common voltage signal to the common electrode.
  • the embodiment of the present disclosure further provides a method of fabricating an array substrate, including the steps of forming a transparent common electrode, and forming a plurality of first common electrode lines and a plurality of second common electrode lines.
  • the plurality of first common electrode lines and the plurality of second common electrode lines are disposed to form a grid shape, and the first common electrode line is connected to the common electrode through a first via hole, the second common electrode The wire is connected to the common electrode through a second via.
  • the first common electrode line and the second common electrode line are disposed in different layers.
  • the method for fabricating the array substrate further includes the step of forming a plurality of gate lines.
  • the first common electrode lines and the gate lines are formed by one patterning process and parallel to the gate lines.
  • the method for fabricating the array substrate further includes the step of forming a plurality of data lines, wherein, optionally, the second common electrode lines and the data lines are formed by one patterning process and parallel to the data lines.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及其制作方法、显示面板和显示装置，阵列基板包括透明的公共电极（103）、多条第一公共电极线（104）和多条第二公共电极线（105）。多条第一公共电极线和多条第二公共电极线交叉设置，形成网格状。第一公共电极线通过第一过孔（106）与公共电极连接，第二公共电极线通过第二过孔（107）与公共电极连接。

Description

一种阵列基板及其制作方法、显示面板和显示装置
相关申请的交叉引用
本申请主张在2017年3月17日在中国提交的中国专利申请号No.201710159841.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示面板和显示装置。
背景技术
相关技术中的包括公共电极的阵列基板，为了减小透明公共电极的电阻以及为公共电极传递信号，会在栅金属层设置与栅线平行的金属公共电极线(也称为gate层公共电极线)，gate层公共电极线通过过孔与透明公共电极连接。
发明内容
本公开提供一种阵列基板及其制作方法、显示面板和显示装置，用于解决相关技术中显示面板的公共电压的分布不均，公共电压不稳定，造成显示不良的问题。
为解决上述技术问题，本公开提供一种阵列基板，包括透明的公共电极、多条第一公共电极线和多条第二公共电极线，所述多条第一公共电极线和多条第二公共电极线交叉设置形成网格状，所述第一公共电极线通过第一过孔与所述公共电极连接，所述第二公共电极线通过第二过孔与所述公共电极连接。
可选地，所述第一公共电极线和第二公共电极线异层设置。
可选地，所述阵列基板还包括多条栅线，所述第一公共电极线与所述栅线同层且平行设置。
可选地，所述阵列基板还包括多条数据线，所述第二公共电极线与所述 数据线同层且平行设置。
可选地，所述阵列基板为双栅线型阵列基板，相邻的两行亚像素之间设置有两条栅线，相邻的两列亚像素之间隔列设置一条数据线，所述第二公共电极线设置于未设置所述数据线的两列亚像素之间。
可选地，每一亚像素的公共电极分开设置，处于同一行的公共电极通过第一公共电极线连通，处于同一列的公共电极通过第二公共电极线连通。
可选地，与所述第二过孔相比，所述第一过孔为深过孔。
可选地，所述的阵列基板还包括：衬底基板、栅绝缘层、像素电极和绝缘层。其中，所述第一公共电极线设置在所述衬底基板上；所述栅绝缘层设置在所述衬底基板并覆盖所述多条第一公共电极线；所述像素电极和所述多条第二公共电极线设置在所述栅绝缘层上；所述绝缘层设置在所述栅绝缘层上并覆盖所述像素电极和所述多条第二公共电极线；所述透明的公共电极设置在所述绝缘层上；所述第一过孔贯穿所述绝缘层和所述栅绝缘层；所述第二过孔贯穿所述绝缘层。
本公开还提供一种显示面板，包括上述阵列基板。
本公开还提供一种显示装置，包括上述显示面板。
本公开还提供一种阵列基板的制作方法，包括以多条第一公共电极线和多条第二公共电极线交叉设置形成网格状、并令所述第一公共电极线通过第一过孔与透明的公共电极连接且所述第二公共电极线通过第二过孔与所述透明的公共电极连接的方式形成所述透明的公共电极、多条第一公共电极线和多条第二公共电极线。
可选地，所述第一公共电极线和第二公共电极线异层设置。
可选地，所述形成所述透明的公共电极、多条第一公共电极线和多条第二公共电极线包括：通过一次构图工艺形成所述多条第一公共电极线以及平行于所述多条第一公共电极线的多条栅线。
可选地，所述形成所述透明的公共电极、多条第一公共电极线和多条第二公共电极线包括：通过一次构图工艺形成所述多条第二公共电极线以及平行于所述多条第二公共电极线的多条数据线。
附图说明
图1为本公开一实施例的阵列基板的俯视图；
图2为本公开另一实施例的阵列基板的剖视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
相关技术中的阵列基板由于只在横向上具有gate层公共电极线，整个面板的公共电压的分布相对不均，公共电压不稳定，从而会造成显示不良。本公开实施例提供一种阵列基板，包括：透明的公共电极，多条第一公共电极线和多条第二公共电极线，所述多条第一公共电极线和多条第二公共电极线交叉设置，形成网格状，所述第一公共电极线通过第一过孔与所述公共电极连接，所述第二公共电极线通过第二过孔与所述公共电极连接。
本公开实施例中，为阵列基板的公共电极设置与其连接的网格状的公共电极线，能够有效降低公共电极的电阻，同时，由于公共电极线呈网格状分布，不是单纯的只有横向设置的gate层公共电极线，从而可以保证整个面板的公共电压的稳定均一，此外，由于网格状的公共电极线能够有效降低公共电极的电阻，从而可以相应减小每一条公共电极线的线宽，以提高开口率。
公共电极通常采用ITO等透明导电材料制成。
可选地，第一公共电极线和第二公共电极线可以采用金属导电材料制成，以有利于公共电极的电阻的减少。
然而，在本公开的其他一些实施例中，也不排除第一公共电极线和第二公共电极线采用透明导电材料制成，以提高开口率。
可选地，所述第一公共电极线和第二公共电极线形成的网格状结构覆盖公共电极所在区域。
本公开实施例中，所述第一公共电极线和第二公共电极线可以同层设置， 也可以异层设置。
当第一公共电极线和第二公共电极线同层设置时，所述第一公共电极线和第二公共电极线连接，为了避免与阵列基板的其他功能膜层上的图形造成干扰，该种情况下，第一公共电极线和第二公共电极线通常需要单独一层设置。
当所述第一公共电极线和第二公共电极线异层设置时，所述第一公共电极线和/或第二公共电极线可以与阵列基板上的其他功能膜层同层设置，以降低膜层厚度，可选地，还可以与其他导电层功能膜层同层设置，从而可以与该导电功能膜层通过一次构图工艺形成，节省mask数量，降低成本。
所述阵列基板还包括多条栅线，可选地，所述第一公共电极线可以与所述栅线同层设置，以节省mask数量，降低成本。进一步可选地，所述第一公共电极线可以与栅线平行设置。当然，在本公开的其他一些实施例中，也不排除所述第一公共电极线可以与栅线同层，且与栅线垂直设置的可能，此时，每一第一公共电极线需要在与栅线交叉的位置处断开。
所述第一公共电极线与所述栅线同层且平行设置时，可以是一行亚像素对应一条第一公共电极线，也可以是多行亚像素对应一条第一公共电极线。
所述阵列基板还包括多条数据线，可选地，所述第二公共电极线可以与所述数据线同层设置，以节省mask数量，降低成本。进一步可选地，所述第二公共电极线可以与数据线平行设置。当然，在本公开的其他一些实施例中，也不排除所述第二公共电极线可以与数据线同层，且与数据线垂直设置的可能，此时，每一第二公共电极线需要在与数据线交叉的位置处断开。
所述第二公共电极线与所述数据线线同层且平行设置时，可以是一列亚像素对应一条第二公共电极线，也可以是多列亚像素对应一条第二公共电极线。
请参考图，图1为本公开一实施例的阵列基板的俯视图，本公开实施例中的阵列基板为双栅型阵列基板，包括：多条栅线101和多条数据线102，相邻的两行亚像素之间设置有两条栅线101，相邻的两列亚像素之间，隔列设置一条数据线102，每一亚像素的公共电极103均分开设置。所述阵列基板还包括：多条第一公共电极线104和多条第二公共电极线105，所述第一 公共电极线104与所述栅线101同层且平行设置，所述第二公共电极线105与所述数据线同层且平行设置，所述第二公共电极线105设置于未设置所述数据线102的两列亚像素之间。所述第一公共电极线104和第二公共电极线105形成网格状。所述第一公共电极线104通过第一过孔106与所述公共电极103连接，所述第二公共电极线105通过第二过孔107与所述公共电极103连接。
本公开实施例中，利用双栅线型阵列基板隔列设置一条数据线的特殊结构，在未设置数据线的一列设置第二公共电极线，与第一公共电极线形成网格状的公共电极线，从而可以保证整个面板的公共电压的稳定均一，此外，由于网格状的公共电极线能够有效降低公共电极的电阻，从而可以相应减小每一条公共电极线的线宽，以提高开口率。
本公开实施例中，每一亚像素的公共电极103分开设置，处于同一行的公共电极103通过第一公共电极线104连通，处于同一列的公共电极103通过第二公共电极线105连通，从而使得整面公共电极103全部导通。
每一亚像素的公共电极分开设置的阵列基板，相关技术中，必须通过过孔以及上层金属(如源漏金属层或公共电极层)跨接布线使得相邻亚像素的公共电极导通，进而导通整面公共电极，这种设计不但增加了走线而且增加了走线与其它电极(如源漏电极、栅电极等)的交叠和侧向电容，电容的增加会使得负载增大，对亚像素充电同样造成影响。
本公开实施例中，无需设置跨接布线，在横向上通过第一公共电极线可将同行的公共电极连接起来，在纵向上通过第二公共电极线便可将同列的公共电极连接起来，结构简单，此外，还有效降低了公共电极与周边电极的电容，使得亚像素的充电更加容易。
请参考图2，图2为本公开另一实施例的阵列基板的剖面示意图，该实施例中的阵列基板与图1所示的实施例中的阵列基板的区别在于，公共电极103为条状公共电极，而图1所示的实施例中，公共电极103为块状公共电极。图2中，100为衬底基板，108为栅绝缘层，109为像素电极，110为绝缘层。
从图2中可以很明显的看出，通过第一过孔106和第二过孔107，公共 电极103可以与位于栅金属层的第一公共电极线104和位于源漏金属层的第二公共电极线105连接起来。其中第一过孔106为深过孔，第二过孔107为浅过孔。
本公开实施例中的阵列基板可以为HADS阵列基板，也可以为IPS阵列基板，或者其他类型的包括公共电极的阵列基板。
本公开实施例还提供一种显示面板，包括上述任一实施例中的阵列基板。
本公开实施例还提供一种显示装置，包括上述显示面板。
本公开实施例中的显示装置还可以包括驱动芯片，所述驱动芯片可以与第一公共电极线和/或第二公共电极线连接，用于通过第一公共电极线和/或第二公共电极线向公共电极传输公共电压信号。
本公开实施例还提供一种阵列基板的制作方法，包括形成透明的公共电极的步骤，以及形成多条第一公共电极线和多条第二公共电极线的步骤。所述多条第一公共电极线和多条第二公共电极线交叉设置，形成网格状，所述第一公共电极线通过第一过孔与所述公共电极连接，所述第二公共电极线通过第二过孔与所述公共电极连接。
可选地，所述第一公共电极线和第二公共电极线异层设置。
所述的阵列基板的制作方法，还包括形成多条栅线的步骤，可选地，所述第一公共电极线与所述栅线通过一次构图工艺形成，且平行于所述栅线。
所述的阵列基板的制作方法还包括形成多条数据线的步骤，其中，可选地，所述第二公共电极线与所述数据线通过一次构图工艺形成，且平行于所述数据线。
除非另作定义，本公开中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (14)

  1. 一种阵列基板，包括透明的公共电极、多条第一公共电极线和多条第二公共电极线；其中，所述多条第一公共电极线和多条第二公共电极线交叉设置形成网格状，所述第一公共电极线通过第一过孔与所述公共电极连接，所述第二公共电极线通过第二过孔与所述公共电极连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一公共电极线和第二公共电极线异层设置。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括多条栅线，所述第一公共电极线与所述栅线同层且平行设置。
  4. 根据权利要求2或3所述的阵列基板，其中，所述阵列基板还包括多条数据线，所述第二公共电极线与所述数据线同层且平行设置。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板为双栅线型阵列基板，相邻的两行亚像素之间设置有两条栅线，相邻的两列亚像素之间隔列设置一条数据线，所述第二公共电极线设置于未设置所述数据线的两列亚像素之间。
  6. 根据权利要求2所述的阵列基板，其中，每一亚像素的公共电极分开设置，处于同一行的公共电极通过第一公共电极线连通，处于同一列的公共电极通过第二公共电极线连通。
  7. 根据权利要求1所述的阵列基板，其中，与所述第二过孔相比，所述第一过孔为深过孔。
  8. 根据权利要求1所述的阵列基板，还包括：衬底基板、栅绝缘层、像素电极和绝缘层；
    其中，所述第一公共电极线设置在所述衬底基板上；
    所述栅绝缘层设置在所述衬底基板并覆盖所述多条第一公共电极线；
    所述像素电极和所述多条第二公共电极线设置在所述栅绝缘层上；
    所述绝缘层设置在所述栅绝缘层上并覆盖所述像素电极和所述多条第二公共电极线；
    所述透明的公共电极设置在所述绝缘层上；
    所述第一过孔贯穿所述绝缘层和所述栅绝缘层；
    所述第二过孔贯穿所述绝缘层。
  9. 一种显示面板，包括如权利要求1-8任一项所述的阵列基板。
  10. 一种显示装置，包括如权利要求9所述的显示面板。
  11. 一种阵列基板的制作方法，包括：
    以多条第一公共电极线和多条第二公共电极线交叉设置形成网格状、并令所述第一公共电极线通过第一过孔与透明的公共电极连接且所述第二公共电极线通过第二过孔与所述透明的公共电极连接的方式形成所述透明的公共电极、多条第一公共电极线和多条第二公共电极线。
  12. 根据权利要求11所述的阵列基板的制作方法，其中，所述第一公共电极线和第二公共电极线异层设置。
  13. 根据权利要求12所述的阵列基板的制作方法，其中，所述形成所述透明的公共电极、多条第一公共电极线和多条第二公共电极线包括：通过一次构图工艺形成所述多条第一公共电极线以及平行于所述多条第一公共电极线的多条栅线。
  14. 根据权利要求12或13所述的阵列基板的制作方法，其中，所述形成所述透明的公共电极、多条第一公共电极线和多条第二公共电极线包括：通过一次构图工艺形成所述多条第二公共电极线以及平行于所述多条第二公共电极线的多条数据线。
PCT/CN2017/104162 2017-03-17 2017-09-29 一种阵列基板及其制作方法、显示面板和显示装置 WO2018166178A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020197025115A KR102259202B1 (ko) 2017-03-17 2017-09-29 어레이 기판, 어레이 기판의 제조 방법, 표시 패널 및 표시 장치
EP17900750.5A EP3598495B1 (en) 2017-03-17 2017-09-29 Array substrate and manufacturing method therefor, display panel and display apparatus
JP2019548476A JP7180841B2 (ja) 2017-03-17 2017-09-29 アレイ基板およびその製造方法、表示パネルおよび表示装置
US15/779,222 US11296123B2 (en) 2017-03-17 2017-09-29 Array substrate and manufacturing method thereof, display panel and display device
KR1020217016003A KR102397834B1 (ko) 2017-03-17 2017-09-29 어레이 기판, 어레이 기판의 제조 방법, 표시 패널 및 표시 장치

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710159841.0 2017-03-17
CN201710159841.0A CN106876413A (zh) 2017-03-17 2017-03-17 一种阵列基板及其制作方法、显示面板和显示装置

Publications (1)

Publication Number Publication Date
WO2018166178A1 true WO2018166178A1 (zh) 2018-09-20

Family

ID=59171483

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/104162 WO2018166178A1 (zh) 2017-03-17 2017-09-29 一种阵列基板及其制作方法、显示面板和显示装置

Country Status (6)

Country Link
US (1) US11296123B2 (zh)
EP (1) EP3598495B1 (zh)
JP (1) JP7180841B2 (zh)
KR (2) KR102259202B1 (zh)
CN (1) CN106876413A (zh)
WO (1) WO2018166178A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876413A (zh) * 2017-03-17 2017-06-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板和显示装置
CN208580546U (zh) * 2018-06-21 2019-03-05 祺虹电子科技（深圳）有限公司 透明基板及透明显示屏
CN109375431A (zh) * 2018-10-26 2019-02-22 深圳市华星光电技术有限公司 一种显示面板及显示装置
CN110058468A (zh) * 2019-04-18 2019-07-26 深圳市华星光电半导体显示技术有限公司 像素驱动电路及液晶显示面板
CN110579913B (zh) * 2019-08-09 2020-12-04 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN110543039B (zh) * 2019-09-10 2022-09-02 京东方科技集团股份有限公司 显示面板和显示装置
CN111899699A (zh) * 2020-08-19 2020-11-06 惠科股份有限公司 显示装置及其驱动方法
CN114690490A (zh) * 2022-03-18 2022-07-01 武汉华星光电技术有限公司 阵列基板及其显示面板
CN114690496B (zh) * 2022-03-25 2023-08-22 Tcl华星光电技术有限公司 显示面板、阵列基板及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103926759A (zh) * 2014-04-28 2014-07-16 昆山龙腾光电有限公司 液晶显示装置
CN105093750A (zh) * 2015-08-14 2015-11-25 深圳市华星光电技术有限公司 Tft阵列基板结构及其制作方法
CN106876413A (zh) * 2017-03-17 2017-06-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板和显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006113376A (ja) * 2004-10-15 2006-04-27 Toshiba Matsushita Display Technology Co Ltd 有機ｅｌ表示装置及びアレイ基板
KR100661725B1 (ko) 2004-12-30 2006-12-26 엘지.필립스 엘시디 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
KR100692091B1 (ko) * 2005-05-11 2007-03-12 엘지전자 주식회사 탑―이미션 방식의 유기전계발광소자 및 그 제조방법
KR101147267B1 (ko) * 2005-12-10 2012-05-18 엘지디스플레이 주식회사 수평 전계형 박막 트랜지스터 기판 및 그 제조 방법
KR20080013163A (ko) 2006-08-07 2008-02-13 삼성전자주식회사 마스크, 이를 이용한 표시기판 및 표시기판 제조 방법
CN101334564A (zh) * 2007-06-28 2008-12-31 上海广电Nec液晶显示器有限公司 一种液晶显示装置及其制造方法
KR20110013159A (ko) * 2009-07-30 2011-02-09 엘지디스플레이 주식회사 박막 트랜지스터 어레이 기판의 제조방법
CN102135691B (zh) 2010-09-17 2012-05-23 京东方科技集团股份有限公司 阵列基板及其制造方法和液晶显示器
KR20120136239A (ko) * 2011-06-08 2012-12-18 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
CN102790012A (zh) 2012-07-20 2012-11-21 京东方科技集团股份有限公司 阵列基板的制造方法及阵列基板、显示装置
KR102009319B1 (ko) * 2012-11-22 2019-08-09 엘지디스플레이 주식회사 액정표시장치와 그의 제조방법
CN103077944B (zh) * 2013-01-18 2016-03-09 京东方科技集团股份有限公司 显示装置、阵列基板及其制作方法
CN103278987B (zh) * 2013-05-24 2015-07-01 京东方科技集团股份有限公司 阵列基板、该阵列基板断线修复方法及显示装置
CN103943627B (zh) 2013-07-30 2017-06-06 上海中航光电子有限公司 一种tft阵列基板
KR102062913B1 (ko) * 2013-09-30 2020-03-02 엘지디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 그 제조방법
CN104880871B (zh) 2015-06-23 2018-05-11 合肥鑫晟光电科技有限公司 显示面板和显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103926759A (zh) * 2014-04-28 2014-07-16 昆山龙腾光电有限公司 液晶显示装置
CN105093750A (zh) * 2015-08-14 2015-11-25 深圳市华星光电技术有限公司 Tft阵列基板结构及其制作方法
CN106876413A (zh) * 2017-03-17 2017-06-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3598495A4 *

Also Published As

Publication number Publication date
JP2020514808A (ja) 2020-05-21
JP7180841B2 (ja) 2022-11-30
CN106876413A (zh) 2017-06-20
EP3598495B1 (en) 2022-07-20
KR102259202B1 (ko) 2021-06-01
EP3598495A4 (en) 2020-11-25
KR20210064430A (ko) 2021-06-02
US20210193685A1 (en) 2021-06-24
US11296123B2 (en) 2022-04-05
KR20190109504A (ko) 2019-09-25
KR102397834B1 (ko) 2022-05-13
EP3598495A1 (en) 2020-01-22

Similar Documents

Publication Publication Date Title
WO2018166178A1 (zh) 一种阵列基板及其制作方法、显示面板和显示装置
JP7425426B2 (ja) タッチモジュール、タッチ表示基板及びタッチ表示装置
US9927911B2 (en) Touch display panel and fabrication method thereof, and touch display apparatus
US9846325B2 (en) Array substrate, touch display panel and touch display device
TWI550494B (zh) 內嵌式觸控顯示面板
KR102609423B1 (ko) 터치 센서 일체형 표시 장치 및 이의 제조 방법
US9261750B2 (en) Array substrate, method for fabricating the same and liquid crystal panel
US10978493B2 (en) Display substrate and manufacturing method thereof, and display device
TWI465819B (zh) 液晶顯示面板
JP2014186844A5 (zh)
CN104880873B (zh) 像素结构、显示面板和像素结构的制作方法
WO2015180288A1 (zh) 内嵌式触控面板及显示装置
WO2017152581A1 (zh) 阵列基板及其制作方法以及显示装置
US10139965B2 (en) Touch panel, manufacturing method thereof and display device
WO2016173340A1 (zh) 触控显示面板及其制备方法、触摸检测方法
US9627416B2 (en) Array substrate and method for manufacturing the same, display device
WO2017004948A1 (zh) 阵列基板及其制作方法和显示装置
WO2022047763A1 (zh) 触控显示面板、触控显示装置和制造方法
WO2014176876A1 (zh) 显示面板及其制作方法、液晶显示器
WO2021031352A1 (zh) 一种触控结构及显示面板
CN109085942B (zh) 一种阵列基板及其制作方法、触控显示装置
TWI545479B (zh) 觸控面板
KR102290684B1 (ko) 내장형 터치 스크린
US10156756B2 (en) Liquid crystal panel and pixel structure thereof
KR102233622B1 (ko) Tft 어레이 기판 및 액정 디스플레이 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17900750

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20197025115

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2019548476

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2017900750

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2017900750

Country of ref document: EP

Effective date: 20191017