WO2018163944A1 - Dispositif à semiconducteur, procédé de fabrication d'un dispositif à semiconducteur et affichage à cristaux liquides - Google Patents

Dispositif à semiconducteur, procédé de fabrication d'un dispositif à semiconducteur et affichage à cristaux liquides Download PDF

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WO2018163944A1
WO2018163944A1 PCT/JP2018/007668 JP2018007668W WO2018163944A1 WO 2018163944 A1 WO2018163944 A1 WO 2018163944A1 JP 2018007668 W JP2018007668 W JP 2018007668W WO 2018163944 A1 WO2018163944 A1 WO 2018163944A1
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oxide semiconductor
source
substrate
semiconductor device
contact region
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PCT/JP2018/007668
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Japanese (ja)
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博章 古川
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シャープ株式会社
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a semiconductor device including a thin film transistor (TFT), a method for manufacturing the semiconductor device, and a liquid crystal display device including the semiconductor device.
  • TFT thin film transistor
  • a display device including an active matrix substrate provided with a switching element for each pixel is widely used.
  • An active matrix substrate including a thin film transistor (hereinafter, “TFT”) as a switching element is also referred to as a TFT substrate.
  • a TFT substrate generally includes a TFT supported on the substrate and a pixel electrode electrically connected to a drain electrode of the TFT for each pixel.
  • the TFT is usually covered with an interlayer insulating layer.
  • the pixel electrode is provided on the interlayer insulating layer, and is connected to the drain electrode of the TFT in a contact hole formed in the interlayer insulating layer.
  • Patent Document 1 Such a configuration of the TFT substrate is disclosed in Patent Document 1, for example.
  • an oxide semiconductor instead of amorphous silicon or polycrystalline silicon as a material for an active layer of a TFT (see, for example, Patent Documents 1, 2, and 3).
  • An oxide semiconductor has higher electron mobility than amorphous silicon. Therefore, a TFT using a layer containing an oxide semiconductor as an active layer of the TFT (hereinafter also referred to as an “oxide semiconductor TFT”) can operate at a higher speed than a TFT using amorphous silicon.
  • the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area.
  • JP 2013-105136 A Japanese Patent No. 5330603 JP 2014-007399 A JP 2012-134475 A JP 2014-209727 A
  • Patent Document 2 in a cross-sectional view of the thin film transistor T R, the pixel contact hole 27a is provided in the protective film 26, the pixel electrode 28, the oxide in the drain section DR It is in contact with the semiconductor film 24a.
  • the pixel contact hole 27a and the gate electrode 22a are half-overlapped, and when a TFT substrate having such a configuration is used for a display device, Light from a light source such as a backlight may pass through the contact hole and light leakage may occur.
  • the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device capable of ensuring high reliability while achieving high definition and a manufacturing method thereof. It is another object of the present invention to provide a liquid crystal display device including the semiconductor device, which achieves high definition and has good contrast.
  • the present inventor examined a method for reducing light leakage from a contact hole in a semiconductor device having a structure in which a semiconductor layer constituting a TFT and a pixel electrode are in contact with each other in a drain contact region of the semiconductor layer in a contact hole. . And it discovered that generation
  • one embodiment of the present invention is a semiconductor device including a substrate and a thin film transistor supported by the substrate, and the thin film transistor includes a first conductive portion formed over the substrate and the first conductive portion.
  • the outer edge is
  • Another aspect of the present invention is a method for manufacturing a semiconductor device including a thin film transistor, the step of forming a first conductive portion on a substrate, and the step of forming a first insulating layer covering the first conductive portion.
  • Forming an oxide semiconductor film on the first insulating layer, and patterning the oxide semiconductor film so that the oxide semiconductor layer at least partially overlaps the first conductive portion with the first insulating layer interposed therebetween Forming a second conductive portion in contact with the source contact region of the oxide semiconductor layer, forming a second insulating layer covering the oxide semiconductor layer, and forming the oxidation on the second insulating layer
  • Still another embodiment of the present invention is a liquid crystal display device including the semiconductor device of the present invention, a liquid crystal panel having a liquid crystal layer and a counter substrate in this order, and a backlight disposed on the back surface of the liquid crystal panel. is there.
  • the semiconductor device of the present invention high reliability can be ensured while realizing high definition.
  • the method for manufacturing a semiconductor device of the present invention it is possible to manufacture a semiconductor device capable of ensuring high reliability while realizing high definition. Since the liquid crystal display device of the present invention includes the semiconductor device of the present invention, light leakage hardly occurs. Therefore, according to the liquid crystal display device of the present invention, it is possible to improve the contrast while achieving high definition.
  • FIG. 1 is a schematic plan view of a semiconductor device according to Embodiment 1.
  • FIG. FIG. 2 is a schematic cross-sectional view taken along the line A-A ′ of FIG. 1.
  • FIG. 2 is a schematic cross-sectional view taken along line B-B ′ of FIG. 1.
  • 6 is a schematic plan view of a semiconductor device according to Embodiment 2.
  • FIG. FIG. 5 is a schematic sectional view taken along line C-C ′ of FIG. 4.
  • FIG. 5 is a schematic cross-sectional view taken along line D-D ′ in FIG. 4.
  • FIG. 10 is a schematic plan view of a semiconductor device according to Modification 1.
  • FIG. 8 is a schematic cross-sectional view taken along line E-E ′ of FIG. 7.
  • FIG. 6 is a schematic plan view of a semiconductor device according to a third embodiment.
  • FIG. FIG. 10 is a schematic cross-sectional view taken along the line F-F ′ of FIG. 9.
  • FIG. 6 is a schematic plan view of a semiconductor device according to a fourth embodiment.
  • FIG. 12 is a schematic cross-sectional view taken along the line H-H ′ of FIG. 11.
  • 1 is a schematic cross-sectional view illustrating a semiconductor device including an etch stop type TFT.
  • 6 is a schematic plan view of a semiconductor device according to a comparative embodiment 1.
  • FIG. FIG. 15 is a schematic sectional view taken along line I-I ′ of FIG. 14.
  • the semiconductor device 1001 according to the first embodiment will be described below with reference to FIGS.
  • the semiconductor device of Embodiment 1 may be any device provided with a thin film transistor on a substrate, and widely includes various circuit boards, TFT substrates, and display devices provided with TFT substrates.
  • a TFT substrate will be described as an example.
  • FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment.
  • FIG. 2 is a schematic sectional view taken along the line A-A ′ of FIG.
  • FIG. 3 is a schematic cross-sectional view taken along line B-B ′ of FIG.
  • the semiconductor device 1001 according to the first embodiment includes a plurality of gate lines G and a plurality of source lines S formed on a substrate (not shown).
  • the gate line G extends along the first direction X
  • the source line S extends along a second direction Y different from the first direction X.
  • the first direction X and the second direction Y may be orthogonal to each other.
  • each of the plurality of gate wirings G has a gate protruding portion G ⁇ b> 1 extending in the second direction Y from the gate wiring G.
  • each of the plurality of source lines S when viewed from the normal direction of the substrate 11, has a source protruding portion S 1 extending from the source line S in the first direction X.
  • the semiconductor device 1001 includes a plurality of pixels Pix arranged in a matrix in the first direction X and the second direction Y on the substrate 11.
  • the TFT 101 and the transparent electrode 20 are disposed in each of the plurality of pixels Pix.
  • an area including a plurality of pixels Pix is referred to as a “display area”, and an area other than the display area is referred to as a “non-display area” or a “frame area”.
  • a terminal portion, a drive circuit, and the like may be provided in the non-display area.
  • the TFT 101 is, for example, a bottom gate type TFT.
  • the TFT 101 may be a bottom gate type TFT having a top contact structure.
  • the TFT 101 includes a substrate 11, a first conductive portion 12 disposed on the substrate 11, a first insulating layer 13 covering the first conductive portion 12, and a first insulating layer 13.
  • the oxide semiconductor layer 14, the second conductive portion 15, and the second insulating layer 16 are provided.
  • the first insulating layer 13 is a gate insulating layer.
  • the oxide semiconductor layer 14 is disposed so as to at least partially overlap the first conductive portion 12 with the first insulating layer 13 interposed therebetween.
  • the second insulating layer 16 is disposed so as to cover the oxide semiconductor layer 14, and the second insulating layer 16 is provided with a contact hole CH exposing the drain contact region 14d.
  • the oxide semiconductor layer 14 includes a channel region 14c and a source contact region 14s and a drain contact region 14d disposed on both sides of the channel region 14c.
  • the second conductive portion 15 is in contact with the source contact region 14 s of the oxide semiconductor layer 14.
  • a portion 14 s of the oxide semiconductor layer 14 that is in contact with the second conductive portion 15 is referred to as a “source contact region”.
  • a portion 14 d of the oxide semiconductor layer 14 exposed through the contact hole CH and in contact with the transparent electrode 20 is referred to as a “drain contact region”.
  • a portion 14 c located between the source contact region 14 s and the drain contact region 14 d and overlapping the first conductive portion 12 with the first insulating layer 13 interposed therebetween becomes a “channel region”.
  • the source contact region 14s, the channel region 14c, and the drain contact region 14d may be arranged side by side in the second direction Y.
  • each pixel when a gate signal is sent from the gate wiring G through the first conductive portion 12 and the TFT 101 is turned on, the transparent electrode 20 is transferred from the source wiring S through the second conductive portion 15 and the drain contact region 14d. A predetermined charge is written in
  • the gate protruding part G1 is the first conductive part 12, and at least a part of the source protruding part S1 is the second conductive part 15.
  • at least a part of the gate protruding part G1 overlaps with the drain contact region 14d, and at least a part of the source protruding part S1 is in contact with the source contact region 14s.
  • part or the whole of the source protrusion S ⁇ b> 1 may be disposed so as to be in contact with the oxide semiconductor layer 14 (source contact region 14 s).
  • the width of the source protrusion S1 in the first direction X is not particularly limited, and may be a length that does not reach the source line S adjacent to the first direction X.
  • the outer edge of the drain contact region 14 d is disposed inside the outer edge of the first conductive portion 12. Further, as shown in FIG. 2, the first conductive portion 12 is formed so as to overlap the entire contact hole CH.
  • the oxide semiconductor layer 14 is arranged so that the outer edge of the drain contact region 14d is inside the outer edge of the first conductive part 12 when viewed from the normal direction of the substrate 11, the first conductive part However, the oxide semiconductor layer 14 may be disposed so as to cover the first conductive portion 12 with the first insulating layer 13 interposed therebetween.
  • the width W 14 of the oxide semiconductor layer 14 is wider than the width W 12 of the first conductive portion 12 in an arbitrary cross section crossing the drain contact region 14 d in the first direction X, and the first conductive The portion 12 is covered with the oxide semiconductor layer 14 with the first insulating layer 13 interposed therebetween. For this reason, even when the alignment deviation of the contact hole CH occurs, the first conductive portion 12 is not exposed by the contact hole CH. Therefore, since the defect by the short circuit between the 1st electroconductive part 12 and the transparent electrode 20 can be suppressed, high reliability is securable.
  • Width W 14 of the oxide semiconductor layer 14 in the first direction X is not particularly limited, and may be for example 3 ⁇ m or more.
  • Width W 12 of the first conductive portion 12 in the first direction X is not particularly limited, and may be for example 2 ⁇ m or more.
  • the width W 14 may be set to be narrower than the distance between the source line S of two adjacent.
  • the width of the bottom surface of the contact hole CH is not particularly limited, but is set to 2 ⁇ m or more, for example, due to process restrictions (process rules).
  • the oxide semiconductor layer 14 may be disposed so as to cover the gate protruding portion G1 and exceed the gate wiring G along the second direction Y. Specifically, as shown in FIG. 1, when viewed from the normal direction of the substrate 11, a part of the gate wiring G and the whole gate protruding part G ⁇ b> 1 are arranged so as to overlap with the oxide semiconductor layer 14. May be.
  • the transparent electrode 20 is formed so as to cover the second insulating layer 16 and the contact hole CH, and is in contact with the drain contact region 14d in the contact hole CH.
  • the contact hole CH is a pixel contact hole that connects the transparent electrode 20 and the oxide semiconductor layer 14.
  • the shape of the contact hole CH shown in the plan view of FIG. 1 or the like refers to the shape of the bottom surface of the contact hole CH (that is, the underlying surface exposed by the contact hole CH) regardless of the inclination angle of the side wall of the contact hole CH. Shall. That is, the shape of the contact hole CH is the same as the shape of the drain contact region 14d.
  • the width of the source wiring S and the width of the contact hole CH in the first direction X are each the minimum processing dimension 1F.
  • the distance from the end of the source line S to the outer edge of the contact hole CH may be a minimum distance that does not overlap the source line S and the contact hole CH, and can be reduced to, for example, 0.75F.
  • the pixel pitch P of Embodiment 1 is 3.5F. If the distance from the end of the source line S to the outer edge of the contact hole CH is made smaller than 0.75F, the pixel pitch can be further reduced. *
  • the minimum processing dimension F is 2.5 ⁇ m
  • the minimum pixel pitch is 8.75 ⁇ m
  • the pixel density can be 968 ppi.
  • the minimum processing dimension F is 2.0 ⁇ m, which is close to the processing limit
  • the minimum pixel pitch is 7.0 ⁇ m
  • the pixel density can be 1210 ppi.
  • the dielectric layer 21 disposed on the transparent electrode 20 and the common electrode 22 disposed on the dielectric layer 21 are further provided.
  • the common electrode 22 is disposed so as to at least partially overlap the transparent electrode 20 via the dielectric layer 21.
  • the common electrode 22 may be disposed separately for each pixel, or may be disposed so as to cover the entire display area in which the plurality of pixels Pix are provided. When the common electrode 22 is disposed so as to cover the entire display region, an opening may be provided at a position overlapping the TFT 101 or the drain contact region 14d. When applied to an FFS mode liquid crystal display device, the common electrode 22 is provided with at least one opening 22a or notch for each pixel. A part of the common electrode 22 may overlap with the transparent electrode 20 via the dielectric layer 21 to constitute an auxiliary capacitor.
  • an “oxide semiconductor layer” is a layer including a semiconductor region that functions as an active layer of an oxide semiconductor TFT.
  • the oxide semiconductor layer may include a region whose resistance is partially reduced (a low-resistance region or a conductor region).
  • a conductive layer such as a metal layer or a reducing insulating layer
  • the portion of the surface of the oxide semiconductor layer that is in contact with the conductive layer is a low resistance whose electrical resistance is lower than that of the semiconductor region. It becomes an area.
  • the resistance is reduced along the thickness direction of the oxide semiconductor layer.
  • the oxide semiconductor included in the semiconductor region of the oxide semiconductor layer 14 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion.
  • Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
  • the oxide semiconductor layer 14 may have a stacked structure of two or more layers.
  • the oxide semiconductor layer 14 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer.
  • the oxide semiconductor layer 14 may include a plurality of crystalline oxide semiconductor layers having different crystal structures, or may include a plurality of amorphous oxide semiconductor layers.
  • the energy gap of the oxide semiconductor included in the upper layer is preferably larger than the energy gap of the oxide semiconductor included in the lower layer.
  • the energy gap of the lower oxide semiconductor may be larger than the energy gap of the upper oxide semiconductor.
  • the oxide semiconductor layer 14 preferably contains at least one of indium, gallium, zinc, or cadmium.
  • the oxide semiconductor layer 14 includes an In—Ga—Zn—O-based semiconductor, an In—Sn—Zn—O-based semiconductor (eg, In 2 O 3 —SnO 2 —ZnO; InSnZnO), In—Al—Zn—.
  • the oxide semiconductor layer 14 contains an oxide of indium, gallium, and zinc.
  • the semiconductor containing an oxide of indium, gallium, and zinc (hereinafter also referred to as an In—Ga—Zn—O-based semiconductor) is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc).
  • a channel-etch TFT having an active layer containing an oxide semiconductor such as an In—Ga—Zn—O-based semiconductor may be referred to as a “CE-OS-TFT”.
  • the In—Ga—Zn—O-based semiconductor may be amorphous or crystalline.
  • a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • a TFT having an In—Ga—Zn—O-based semiconductor layer has high electron mobility and a small amount of leakage current.
  • a TFT having an In—Ga—Zn—O-based semiconductor layer has an electron mobility exceeding 20 times that of a TFT using amorphous silicon (a-Si TFT), and the amount of leakage current is 1/100. Is less than. Therefore, it is suitably used not only as a pixel TFT but also as a driving TFT.
  • the pixel TFT is a TFT provided in a pixel, and the TFT 101 is a pixel TFT.
  • the driving TFT is, for example, a TFT included in a driving circuit provided on the same substrate as the display area around the display area including a plurality of pixels.
  • a TFT included in a driving circuit provided on the same substrate as the display area around the display area including a plurality of pixels.
  • the crystal structure of a crystalline In—Ga—Zn—O-based semiconductor is disclosed in, for example, the above Patent Documents 3 to 5, and can be applied to the present invention.
  • Another embodiment of the present invention is a method of manufacturing a semiconductor device including a thin film transistor, in which a step (a) of forming a first conductive portion on a substrate and a first insulating layer covering the first conductive portion are formed. And (b) forming an oxide semiconductor film on the first insulating layer and patterning the oxide semiconductor film, so that at least a part of the first conductive portion is interposed through the first insulating layer.
  • hole (F) forming a transparent electrode in contact with the drain contact region of the oxide semiconductor layer, and when viewed from the normal direction of the substrate, the outer edge of the drain contact region is This is a method of manufacturing a semiconductor device that overlaps with a part of the outer edge of the part or is arranged inside the outer edge of the first conductive part.
  • the first conductive portion 12 is formed on the substrate 11.
  • at least a part of the gate protruding portion G1 is the first conductive portion 12.
  • the gate wiring G extending in the first direction and the gate protrusion G1 extending in the second direction from the gate wiring G are formed on the substrate 11.
  • the gate wiring G and the gate protruding portion G1 may be integrally formed.
  • the gate protrusion G1 and the gate wiring G are formed by forming a metal film for gate wiring on the substrate 11 by sputtering or the like, and then processing the metal film for gate wiring into a desired shape by photolithography or the like. By doing so, it can be formed.
  • the thickness of the gate wiring metal film is, for example, not less than 50 nm and not more than 500 nm.
  • the substrate 11 is preferably a transparent substrate. Moreover, it is preferable that it is a board
  • a glass substrate for example, a glass substrate; a silicon substrate; a resin substrate such as plastic or polycarbonate can be used.
  • the gate wiring metal film examples include metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), and the like. Or a film containing these metal nitrides can be used. Alternatively, a stacked film in which a plurality of films containing the above metals, alloys thereof, or metal nitrides are stacked may be used.
  • a specific example of the metal film for gate wiring is, for example, a molybdenum tungsten alloy (MoW) film having a thickness of 300 nm.
  • the first insulating layer 13 that covers the first conductive portion 12 is formed.
  • the first insulating layer 13 is formed so as to cover the gate wiring G and the gate protruding portion G1.
  • a silicon oxide (SiO 2 ) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy: x> y) layer, a silicon nitride oxide (SiNxOy; x> y) layer, or the like is used. Can do.
  • the first insulating layer 13 may have a stacked structure in which a lower layer and an upper layer are stacked from the substrate 11 side.
  • a silicon nitride layer, a silicon nitride oxide layer, or the like may be used for the first insulating layer 13.
  • the first insulating layer 13 is oxidized.
  • a silicon layer, a silicon oxynitride layer, or the like may be used.
  • oxygen deficiency can be recovered by oxygen contained in oxygen, oxygen deficiency in the oxide semiconductor layer 14 can be effectively reduced.
  • the first insulating layer 13 for example, a first insulating layer having a laminated structure in which a silicon nitride (SiNx) layer having a thickness of 325 nm is a lower layer and a silicon oxide (SiO 2 ) layer having a thickness of 50 nm is an upper layer. 13 is mentioned.
  • the first insulating layer 13 can be formed by using a chemical vapor deposition (CVD) method.
  • an oxide semiconductor film is formed on the first insulating layer 13, and the oxide semiconductor film is patterned, so that at least a part of the first conductive portion 12 is interposed through the first insulating layer 13. Is obtained.
  • the oxide semiconductor film can be formed by a sputtering method, for example.
  • the thickness of the oxide semiconductor film is, for example, 20 nm or more and 200 nm or less.
  • the oxide semiconductor layer 14 is preferably an island-shaped oxide semiconductor layer. When viewed from the normal direction of the substrate 11, at least a part of the oxide semiconductor layer 14 is disposed so as to overlap the first conductive portion 12 with the first insulating layer 13 interposed therebetween.
  • the oxide semiconductor layer 14 is formed, for example, by patterning an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor containing In, Ga, and Zn at a ratio of 1: 1: 1.
  • the oxide semiconductor layer 14 has a thickness of, for example, 50 nm.
  • the oxide semiconductor layer 14 is made of an oxide semiconductor, the resistance may be partially reduced by contacting the conductor in a subsequent process.
  • the second conductive portion 15 in contact with the source contact region 14s of the oxide semiconductor layer 14 is formed.
  • at least a part of the source protruding portion S1 is the second conductive portion 15.
  • a metal film for source wiring is formed on the oxide semiconductor layer 14 and the first insulating layer 13 by sputtering or the like, and then the metal film for source wiring is processed into a desired shape by photolithography or the like.
  • the source line S extending in the second direction and the source protruding part S1 extending from the source line S in the first direction are formed.
  • the source wiring S and the source protruding portion S1 may be integrally formed.
  • the thickness of the metal film for source wiring is, for example, not less than 50 nm and not more than 500 nm.
  • the source protruding portion S1 is disposed so as to be in contact with the upper surface of the oxide semiconductor layer 14. A portion of the oxide semiconductor layer 14 that is in contact with the source protruding portion S1 becomes a source contact region 14s.
  • Examples of the source wiring metal film include metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), chromium (Cr), titanium (Ti), and the like.
  • An alloy or a film containing these metal nitrides can be used.
  • a stacked film in which a plurality of films containing the above metals, alloys thereof, or metal nitrides are stacked may be used.
  • a titanium (Ti) film having a thickness of 30 nm is used as a lower layer, and an aluminum (Al) film having a thickness of 200 nm and a titanium (Ti) film having a thickness of 100 nm are formed on the substrate 11 side.
  • the second insulating layer 16 that covers the oxide semiconductor layer 14 is formed, and the contact hole CH that exposes the drain contact region 14 d of the oxide semiconductor layer 14 is formed in the second insulating layer 16.
  • the second insulating layer 16 is formed so as to cover the source wiring S and the source protruding portion S1.
  • an opening that exposes part of the oxide semiconductor layer 14 is formed in the second insulating layer 16. It becomes an opening provided in the second insulating layer 16 and a contact hole CH.
  • the second insulating layer 16 As the material of the second insulating layer 16, the same material as that of the first insulating layer 13 can be used.
  • the second insulating layer 16 may be a single layer or may have a laminated structure.
  • the second insulating layer 16 may be an inorganic insulating layer, an organic insulating layer film, or a laminated film of an organic insulating film and an inorganic insulating film.
  • Specific examples of the second insulating layer 16 include a SiO 2 film having a thickness of 300 nm, a positive photosensitive resin film having a thickness of 2000 nm, and the like.
  • the SiO 2 film can be formed by the CVD method.
  • the etching method and conditions for the contact hole CH are selected so that the etching rate of the oxide semiconductor layer 14 is lower than the etching rate of the second insulating layer 16.
  • the oxide semiconductor layer 14 can be exposed to the bottom surface of the contact hole CH with almost no etching.
  • the entire bottom surface of the contact hole CH is preferably located on the oxide semiconductor layer 14.
  • the width of the bottom surface of the contact hole CH is set to be narrower than the width of the oxide semiconductor layer 14.
  • the width of the bottom surface of the contact hole CH is set to be narrower than the width of the oxide semiconductor layer 14.
  • the transparent electrode 20 in contact with the drain contact region 14d of the oxide semiconductor layer 14 is formed in the contact hole CH so as to cover the second insulating layer 16 and the contact hole CH.
  • a first transparent electrode film is formed so as to cover the second insulating layer 16 and the contact hole CH, and then the transparent electrode 20 is formed by patterning the first transparent electrode film.
  • the transparent electrode 20 may be a pixel electrode.
  • an oxide semiconductor such as indium tin oxide (Indium Tin Oxide: ITO), indium zinc oxide (Indium Zinc Oxide: IZO), zinc oxide (ZnO), or the like can be used. .
  • the thickness of the first transparent electrode film is, for example, 20 to 300 nm.
  • an IZO film having a thickness of 100 nm is formed as the first transparent electrode film by sputtering.
  • the transparent electrode 20 is formed by patterning the first transparent electrode film by photolithography.
  • the transparent electrode 20 is disposed in contact with the upper surface of the oxide semiconductor layer 14 in the contact hole CH.
  • a portion of the oxide semiconductor layer 14 that is in contact with the transparent electrode 20 becomes a drain contact region 14d.
  • the entire contact hole CH is located on the oxide semiconductor layer 14. Therefore, when viewed from the normal direction of the substrate 11, the outer edge of the drain contact region 14 d is disposed inside the outer edge of the first conductive portion 12.
  • a step of forming a dielectric layer 21 and a common electrode 22 on the transparent electrode 20 may be further included.
  • a silicon oxide (SiO 2 ) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy: x> y) layer, a silicon nitride oxide (SiNxOy; x> y) layer, or the like is used. be able to.
  • a specific example of the dielectric layer 21 is, for example, a SiNx film having a thickness of 100 nm.
  • the dielectric layer 21 can be formed using a CVD method.
  • the common electrode 22 is obtained by forming a second transparent electrode film on the dielectric layer 21 and patterning the second transparent electrode film.
  • the material of the second transparent electrode film the same material as the first transparent electrode film can be used. Specifically, for example, an ITO film having a thickness of 100 nm is formed on the dielectric layer 21 as the second transparent electrode by a sputtering method. Thereafter, the common electrode 22 is formed by patterning the second transparent electrode film by photolithography.
  • the common electrode 22 may be provided with at least one opening 22a or notch for each pixel. In this way, the semiconductor device 1001 is manufactured.
  • FIG. 4 is a schematic plan view of the semiconductor device according to the second embodiment.
  • FIG. 5 is a schematic sectional view taken along the line CC ′ of FIG. 6 is a schematic cross-sectional view taken along the line DD ′ of FIG.
  • the semiconductor device 2001 includes a TFT 201.
  • each of the plurality of gate wirings G has a gate protrusion G ⁇ b> 1 extending in the second direction Y from the gate wiring G.
  • the gate protruding portion G1 is the first conductive portion 12.
  • the source protruding portion S ⁇ b> 1 is not provided and a part of the source wiring S becomes the second conductive portion 15.
  • the entire source contact region 14 s may be formed to fit in the width direction of the source wiring.
  • the source contact region 14s and the channel region 14c may be arranged in the first direction X, and the channel region 14c and the drain contact region 14d may be arranged in the second direction Y.
  • the oxide semiconductor layer 14 may be formed in an L shape.
  • the TFT 201 can form a fine pixel because the transparent electrode 20 is in contact with the drain contact region 14d of the oxide semiconductor layer 14 as in the first embodiment.
  • the minimum processing dimension of the source wiring S is defined as F, as shown in FIG. 4, the width of the source wiring S and the width of the contact hole CH in the first direction X is 1F, and contact from the end of the source wiring S
  • the pixel pitch P is minimum.
  • the minimum value of the pixel pitch P in the second embodiment is 3.5F.
  • the minimum processing dimension F is 2.5 ⁇ m
  • the minimum pixel pitch is 8.75 ⁇ m
  • the pixel density can be 968 ppi.
  • the minimum processing dimension F is 2.0 ⁇ m, which is close to the processing limit
  • the minimum pixel pitch is 7.0 ⁇ m
  • the pixel density can be 1210 ppi.
  • the TFT 201 is arranged such that the outer edge of the drain contact region 14 d is located inside the outer edge of the first conductive portion 12 when viewed from the normal direction of the substrate 11. Further, as shown in FIG. 5, the first conductive portion 12 is formed so as to overlap the entire contact hole CH. Accordingly, when the semiconductor device 2001 is applied to a display device such as a liquid crystal display device, light leakage is suppressed, so that a display device with favorable contrast can be obtained.
  • FIG. 7 is a schematic plan view of the semiconductor device according to the first modification.
  • FIG. 8 is a schematic sectional view taken along line EE ′ of FIG.
  • the semiconductor device 2002 includes a TFT 301.
  • the outer edge of the drain contact region 14 d overlaps a part of the outer edge of the first conductive portion 12 when viewed from the normal direction of the substrate 11.
  • the width of the gate protrusion G1 in the first direction X is the same as the width of the drain contact region 14d in the first direction X.
  • the minimum processing dimension of the source wiring S is defined as F, as shown in FIG. 7, the width of the source wiring S and the width of the contact hole CH in the first direction X is 1F, and the contact from the end of the source wiring S
  • the pixel pitch P is minimum.
  • the minimum value of the pixel pitch P in Modification 1 is 3.5F.
  • the width of the gate protrusion G1 in the first direction X and the width of the drain contact region 14d in the first direction X the same, the distance from the end of the source line S to the outer edge of the contact hole CH is set to 0. It becomes easy to make it narrower than 75F, and the minimum value of the pixel pitch P can be made smaller than 3.5F.
  • the minimum processing dimension F is 2.5 ⁇ m
  • the minimum pixel pitch is 8.75 ⁇ m and the pixel density can be 968 ppi, as in the first embodiment.
  • the minimum processing dimension F is 2.0 ⁇ m close to the processing limit
  • the minimum pixel pitch is 7.0 ⁇ m, and the pixel density can be 1210 ppi.
  • the entire bottom surface of the contact hole CH is preferably located on the oxide semiconductor layer 14.
  • the width of the bottom surface of the contact hole CH is set to be narrower than the width of the oxide semiconductor layer 14.
  • the width of the bottom surface of the contact hole CH is set to be narrower than the width of the oxide semiconductor layer 14 also in the first direction X.
  • FIG. 9 is a schematic plan view of the semiconductor device according to the third embodiment.
  • FIG. 10 is a schematic cross-sectional view taken along the line FF ′ of FIG.
  • the semiconductor device 3001 includes a TFT 401.
  • the gate conductive part G does not have the gate protruding part G 1 and a part of the gate wiring G becomes the first conductive part 12.
  • each of the plurality of source lines S extends from the source line S in the first direction X when viewed from the normal direction of the substrate 11.
  • S1 is included.
  • at least a part of the source protruding portion S1 is the second conductive portion 15.
  • at least a part of the gate wiring G overlaps with the drain contact region 14d, and at least a part of the source protrusion S1 is in contact with the source contact region 14s.
  • the source contact region 14s may be formed so as to overlap the source line S and the source protrusion S1. Since the third embodiment does not have the gate protruding portion G1, the contact hole CH is formed on the gate wiring G. Therefore, the pixel aperture ratio can be improved.
  • the source contact region 14s, the channel region 14c, and the drain contact region 14d may be arranged side by side in the first direction X.
  • the width of the source protrusion S1 in the first direction X may be narrower than the width of the source wiring S in the first direction X, or may be 1/2 or less of the width of the source wiring.
  • the width of the source protrusion S1 in the second direction Y may be wider than the width of the gate line G in the second direction Y, and may be formed so as to cover the gate line G.
  • the channel length can be increased while suppressing variations in the width of the channel region 14c of the TFT 401.
  • the TFT 401 can form a fine pixel because the transparent electrode 20 is in contact with the drain contact region 14d of the oxide semiconductor layer 14 as in the first embodiment.
  • the minimum processing dimension of the source wiring S is defined as F
  • the width of the source wiring S and the width of the contact hole CH in the first direction X is 1F
  • the width of the source protrusion S1 is
  • the pixel pitch P is minimum.
  • the minimum value of the pixel pitch P in the third embodiment is 4F.
  • the minimum processing dimension F is 2.5 ⁇ m
  • the minimum pixel pitch is 10 ⁇ m
  • the pixel density can be 847 ppi.
  • the minimum processing dimension F is 2.0 ⁇ m which is close to the processing limit
  • the minimum pixel pitch is 8.0 ⁇ m and the pixel density can be 1059 ppi.
  • the TFT 401 is arranged such that the outer edge of the drain contact region 14 d is located inside the outer edge of the first conductive portion 12 when viewed from the normal direction of the substrate 11. Further, as shown in FIG. 10, the first conductive portion 12 is formed so as to overlap the entire contact hole CH. Accordingly, when the semiconductor device 3001 is applied to a display device such as a liquid crystal display device, light leakage is suppressed, so that a display device with favorable contrast can be obtained.
  • FIG. 11 is a schematic plan view of a semiconductor device according to the fourth embodiment.
  • 12 is a schematic cross-sectional view taken along the line HH ′ of FIG.
  • the semiconductor device 4001 includes a TFT 501.
  • the gate conductive portion 12 does not have the gate protruding portion G 1 and a part of the gate wiring G becomes the first conductive portion 12.
  • at least a part of the source wiring S is the second conductive portion 15.
  • the gate wiring G When viewed from the normal direction of the substrate 11, at least a part of the gate wiring G overlaps with the drain contact region 14d, and at least a part of the source wiring S is in contact with the source contact region 14s.
  • the contact hole CH is formed on the gate wiring G. Accordingly, in the fourth embodiment, the pixel aperture ratio can be further improved.
  • the TFT 501 can form fine pixels because the transparent electrode 20 is in contact with the drain contact region 14d of the oxide semiconductor layer 14 as in the first embodiment.
  • the fourth embodiment does not have the source protrusion S1, and as shown in FIGS. 11 and 12, the entire source contact region 14s is formed to fit in the width direction of the source wiring. Can be further refined. If the minimum processing dimension of the source wiring S is defined as F, as shown in FIG. 11, the width of the source wiring S and the width of the contact hole CH in the first direction X is 1F, and contact is made from the end of the source wiring S. The distance to the outer edge of the hole CH can be 0.75F. The minimum value of the pixel pitch P in the fourth embodiment is 3.5F.
  • the minimum processing dimension F is 2.5 ⁇ m
  • the minimum pixel pitch is 8.75 ⁇ m
  • the pixel density can be 968 ppi.
  • the minimum processing dimension F is 2.0 ⁇ m, which is close to the processing limit
  • the minimum pixel pitch is 7.0 ⁇ m
  • the pixel density can be 1210 ppi.
  • the TFT having the channel etch structure is illustrated, but the TFT in each embodiment may have the channel etch structure or have an etch stop that covers the channel region. It may have an etch stop structure.
  • the “channel etch type TFT” has no etch stop layer formed on the channel region 14c, and the lower surface of the end of the second conductive portion 15 on the channel side is an oxide semiconductor.
  • the upper surface of the layer 14 is disposed so as to be in contact therewith.
  • the second conductive portion 15 of the channel etch type TFT is formed, for example, by forming a conductive film for a source on the oxide semiconductor layer 14 and patterning the conductive film.
  • FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device including an etch stop type TFT.
  • the semiconductor device 1002 provided with the etch stop type TFT is the same as the semiconductor device 1001 according to the first embodiment except that the etch stop layer 23 is provided.
  • FIG. 13 corresponds to a schematic cross-sectional view taken along the line A-A ′ of FIG. 1.
  • the etch stop type TFT has an etch stop layer 23 covering the channel region 14c of the oxide semiconductor layer 14 as shown in FIG.
  • the etch stop layer 23 is provided with an opening that exposes a portion to be the source contact region 14 s of the oxide semiconductor layer 14.
  • a metal film for source wiring is formed so as to cover the etch stop layer 23 and the opening, and patterning is performed to form the source wiring S and / or the source protrusion S1.
  • the contact hole CH may be formed by simultaneously etching the second insulating layer 16 and the etch stop layer 23. In this case, as shown in FIG.
  • the contact hole CH is composed of an opening of the second insulating layer 16 and an opening of the etch stop layer 23. Thereafter, the transparent electrode 20, the dielectric layer 21, and the common electrode 22 are formed by a method similar to that of the semiconductor device 1001 to obtain the semiconductor device 1002.
  • FIG. 14 is a schematic plan view of the semiconductor device according to the first comparative embodiment.
  • FIG. 15 is a schematic cross-sectional view taken along the line II ′ of FIG.
  • the semiconductor device 5001 includes a TFT 601.
  • the TFT 601 has at least one first conductive portion 612 (gate lead portion G1) formed on the substrate 11 and the first conductive portion 612 via the first insulating layer 13.
  • An oxide semiconductor layer 614 is provided so that the portions overlap each other.
  • the oxide semiconductor layer 614 includes a channel region 614c and a source contact region 614s and a drain contact region 614d disposed on both sides of the channel region 614c.
  • a part of the outer edge of the drain contact region 614 d is disposed outside the outer edge of the first conductive portion 614.
  • the contact holes CH are aligned so that only a part of the contact holes CH overlaps the first conductive portion 612.
  • the semiconductor device 5001 according to the comparative example 1 when applied to a display device such as a liquid crystal display device, light from a light source such as a backlight leaks from the contact hole CH and light leakage occurs. Therefore, the contrast of the liquid crystal display device is lowered.
  • the FFS mode liquid crystal display device has been described as an example.
  • the semiconductor device of the present invention can also be applied to an IPS mode liquid crystal display device.
  • the semiconductor device of the present invention may not have the dielectric layer 21 and the common electrode 22 on the transparent electrode 20.
  • an alignment film (not shown) may be formed on the transparent electrode 20, and for example, a TN (Twisted Nematic) mode is obtained by bonding the counter substrate with a common electrode through a liquid crystal layer.
  • the liquid crystal display device can be used in a vertical electric field mode liquid crystal display device such as a VA (Vertical Alignment) mode.
  • VA Vertical Alignment
  • the semiconductor device of the present invention can be applied to various circuit boards having oxide semiconductor TFTs.
  • the circuit board can be applied to various electronic devices such as an imaging device such as an image sensor device; an image input device; a fingerprint reading device; a semiconductor memory.
  • the semiconductor device of the present invention can be applied to, for example, an active matrix substrate (TFT substrate).
  • TFT substrate can be used in display devices such as liquid crystal display devices, electrophoretic display devices, MEMS (Micro Electro Mechanical System) display devices, and organic EL (Electroluminescence) display devices.
  • the semiconductor device 1001 is preferably applied to a liquid crystal display device.
  • Still another embodiment of the present invention is a liquid crystal display device including the semiconductor device of the present invention, a liquid crystal panel having a liquid crystal layer and a counter substrate in this order, and a backlight disposed on the back surface of the liquid crystal panel. is there.
  • the semiconductor device 1001 is a thin layer transistor substrate (TFT substrate). Since the alignment of liquid crystal molecules is likely to be disturbed around the contact hole, if a light leak occurs in the contact hole, it is easily recognized as a display defect. Therefore, when the semiconductor device 1001 is applied particularly to a liquid crystal display device, the occurrence of light leakage can be effectively suppressed and a liquid crystal display device excellent in contrast can be obtained.
  • TFT substrate thin layer transistor substrate
  • a light shielding film is formed on the substrate and patterned into a desired shape to form a black matrix.
  • the substrate used for the counter substrate include the same substrates as those described above.
  • Specific examples of the light shielding film include a titanium (Ti) film having a thickness of 200 nm.
  • color filters including red (R), green (G), and blue (B) are respectively formed at desired positions to form a counter substrate.
  • TFT substrate the semiconductor device
  • the TFT substrate 1001 and the counter substrate are bonded together.
  • liquid crystal is injected between these substrates to obtain a liquid crystal layer.
  • the substrate is divided into a desired size to obtain a liquid crystal panel.
  • a liquid crystal display device is obtained by arranging a backlight on the back surface of the liquid crystal panel.
  • the back surface of the liquid crystal panel may be on the TFT substrate side or on the counter substrate side.
  • One embodiment of the present invention is a semiconductor device including a substrate and a thin film transistor supported by the substrate, and the thin film transistor covers a first conductive portion formed on the substrate and the first conductive portion.
  • a second insulating layer disposed so as to cover, the second insulating layer provided with a contact hole exposing the drain contact region of the oxide semiconductor layer;
  • a transparent electrode that is formed on the insulating layer and covers the contact hole and is in contact with the drain contact region in the contact hole, and when viewed from the normal direction of the substrate, the outer edge of the drain contact region is It is a semiconductor device which overlaps with a part of the outer edge of the first conductive part or is arranged inside the outer edge of the first conductive part.
  • a plurality of pixels arranged in a matrix in the first direction and the second direction on the substrate, a plurality of gate wirings extending in the first direction, and a plurality of source wirings extending in the second direction are provided.
  • the thin film transistor and the transparent electrode are disposed in each of the plurality of pixels, and when viewed from the normal direction of the substrate, each of the plurality of gate wirings extends from the gate wiring in the second direction.
  • at least a portion of the gate protrusion is the first conductive portion, and when viewed from the normal direction of the substrate, at least a portion of the gate protrusion is the drain contact. It may overlap with the area.
  • the width of the gate protrusion in the first direction may be the same as the width of the drain contact region in the first direction.
  • the source contact region, the channel region, and the drain contact region may be arranged side by side in the second direction.
  • the source contact region and the channel region may be arranged in the first direction, and the channel region and the drain contact region may be arranged in the second direction.
  • a plurality of pixels arranged in a matrix in the first direction and the second direction on the substrate, a plurality of gate wirings extending in the first direction, and a plurality of source wirings extending in the second direction are provided.
  • the thin film transistor and the transparent electrode are disposed in each of the plurality of pixels, and a part of the gate wiring is the first conductive portion, and when viewed from the normal direction of the substrate, the gate wiring A portion may overlap the drain contact region.
  • the source contact region, the channel region, and the drain contact region may be arranged side by side in the first direction.
  • each of the plurality of source wirings has a source protrusion extending from the source wiring in the first direction, and at least a part of the source protrusion is When the second conductive portion is viewed from the normal direction of the substrate, at least a part of the source protruding portion may be in contact with the source contact region.
  • the width of the source protrusion in the first direction may be narrower than the width of the source wiring in the first direction.
  • the width of the source protrusion in the first direction may be less than or equal to 1 ⁇ 2 of the width of the source wiring in the first direction.
  • a part of the source wiring is the second conductive portion, and when viewed from the normal direction of the substrate, a part of the source wiring may be in contact with the source contact region.
  • the oxide semiconductor layer may include at least one of indium, gallium, zinc, or cadmium. More preferably, the oxide semiconductor layer includes an oxide of indium, gallium, and zinc.
  • Another aspect of the present invention is a method for manufacturing a semiconductor device including a thin film transistor, the step of forming a first conductive portion on a substrate, and the step of forming a first insulating layer covering the first conductive portion.
  • Forming an oxide semiconductor film on the first insulating layer, and patterning the oxide semiconductor film so that the oxide semiconductor layer at least partially overlaps the first conductive portion with the first insulating layer interposed therebetween Forming a second conductive portion in contact with the source contact region of the oxide semiconductor layer, forming a second insulating layer covering the oxide semiconductor layer, and forming the oxidation on the second insulating layer
  • Still another embodiment of the present invention is a liquid crystal display device including the semiconductor device of the present invention, a liquid crystal panel having a liquid crystal layer and a counter substrate in this order, and a backlight disposed on the back surface of the liquid crystal panel. is there.
  • Second insulating layer 20 Transparent electrode (pixel electrode) 21: Dielectric layer 22: Common electrode 22a: Opening 23: Etch stop layer 101, 201, 301, 401, 501, 601: Thin film transistor (TFT) 1001, 1002, 2001, 2002, 3001, 4001, 5001: Semiconductor device CH: Contact hole G: Gate wiring G1: Gate protruding portion S: Source wiring S1: Source protruding portion P: Pixel pitch Pix: Pixel

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Abstract

La présente invention concerne un dispositif à semiconducteur capable d'assurer un niveau élevé de fiabilité tout en réalisant une définition plus élevée. Ce dispositif à semiconducteur comprend un substrat et un transistor à couches minces supporté par le substrat, le transistor à couches minces comprenant : une première section conductrice formée sur le substrat; une première couche d'isolation; une couche semiconductrice d'oxyde; une seconde section conductrice qui entre en contact avec une région de contact de source de la couche semiconductrice d'oxyde; une seconde couche d'isolation comprend un trou de contact pour exposer une région de contact de drain de la couche semiconductrice d'oxyde; et une électrode transparente en contact avec la région de contact de drain au niveau du trou de contact; et lorsqu'elle est vue depuis la direction normale du substrat, un bord externe de la région de contact de drain chevauche une partie d'un bord externe de la première section conductrice, ou est disposé davantage vers l'intérieur que le bord externe de la première section conductrice.
PCT/JP2018/007668 2017-03-08 2018-03-01 Dispositif à semiconducteur, procédé de fabrication d'un dispositif à semiconducteur et affichage à cristaux liquides WO2018163944A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110931507A (zh) * 2018-09-19 2020-03-27 夏普株式会社 有源矩阵基板及其制造方法、液晶显示装置的制造方法

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JP2014232824A (ja) * 2013-05-30 2014-12-11 三菱電機株式会社 薄膜トランジスタ、表示パネル用基板、表示パネル、表示装置および薄膜トランジスタの製造方法
US20160118504A1 (en) * 2014-10-01 2016-04-28 Chunghwa Picture Tubes, Ltd. Thin film transistor
JP2016122683A (ja) * 2014-12-24 2016-07-07 三菱電機株式会社 薄膜トランジスタ基板およびその製造方法
WO2016128860A1 (fr) * 2015-02-12 2016-08-18 株式会社半導体エネルギー研究所 Dispositif d'affichage

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JP2014232824A (ja) * 2013-05-30 2014-12-11 三菱電機株式会社 薄膜トランジスタ、表示パネル用基板、表示パネル、表示装置および薄膜トランジスタの製造方法
US20160118504A1 (en) * 2014-10-01 2016-04-28 Chunghwa Picture Tubes, Ltd. Thin film transistor
JP2016122683A (ja) * 2014-12-24 2016-07-07 三菱電機株式会社 薄膜トランジスタ基板およびその製造方法
WO2016128860A1 (fr) * 2015-02-12 2016-08-18 株式会社半導体エネルギー研究所 Dispositif d'affichage

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110931507A (zh) * 2018-09-19 2020-03-27 夏普株式会社 有源矩阵基板及其制造方法、液晶显示装置的制造方法
CN110931507B (zh) * 2018-09-19 2023-06-06 夏普株式会社 有源矩阵基板及其制造方法、液晶显示装置的制造方法

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