WO2018161393A1 - 阵列基板测试电路及其制作方法 - Google Patents

阵列基板测试电路及其制作方法 Download PDF

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Publication number
WO2018161393A1
WO2018161393A1 PCT/CN2017/079555 CN2017079555W WO2018161393A1 WO 2018161393 A1 WO2018161393 A1 WO 2018161393A1 CN 2017079555 W CN2017079555 W CN 2017079555W WO 2018161393 A1 WO2018161393 A1 WO 2018161393A1
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Prior art keywords
display unit
test
display
array
electrodes
Prior art date
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PCT/CN2017/079555
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English (en)
French (fr)
Inventor
王倩
虞晓江
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Publication of WO2018161393A1 publication Critical patent/WO2018161393A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate test circuit and a method of fabricating the same.
  • LTPS Low Temperature Poly Silicon
  • TFT LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • LTPS TFT The LCD has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, etc.
  • LTPS TFT The array process in the LCD is uniformly arranged on a large glass substrate to form an array circuit. After the array test item is passed and the standard is reached, the glass substrate is cut into a cutting section in the subsequent box process. Batch display units, each display unit has a separate array circuit for controlling the display of the final finished LCD panel.
  • LTPS TFT LCD panel in one of the array circuit structure design, for a single display unit (as shown in Figure 1 and Figure 2), through several vertical metal traces running through the left and right sides of the display area (collectively referred to as array substrate test) Aligning the array test circuit related signals located above the display area to the boxed test circuit located below the display area to drive the output of the vertical display signal by using part of the line of the test circuit of the box to complete the array test project.
  • the longitudinal array substrate test traces and the horizontal metal traces at the edge of the display area are always vertically staggered.
  • the staggered positional relationship causes the lateral display signals to be affected by the coupling, causing Display differences on the left and right sides of the display panel; in addition, leakage may occur in staggered positions, and even abnormal problems such as damage may occur, which may affect the yield of the display panel.
  • the technical problem to be solved by the present invention is to provide an array substrate test circuit and a method thereof, which avoids staggering the metal traces of the array substrate test traces and the edge of the display area, thereby reducing the occurrence of coupling, leakage, and damage, thereby improving The purpose of the display panel production yield.
  • a technical solution adopted by the present invention is to provide an array substrate test circuit, the array substrate test circuit is disposed on a substrate, the substrate includes at least two display units, and the at least two displays
  • the unit includes a first display unit and a second display unit disposed adjacent to the first display unit, the first and second display units each including an array test electrode region and a boxed test electrode region, the array test electrode
  • the area includes a plurality of array test electrodes
  • the packaged test electrode area includes a plurality of cassette test electrodes
  • the plurality of array test electrodes of the second display unit are electrically connected to each other through the periphery of the first display unit.
  • a plurality of cassette test electrodes of the two display units are configured to drive an output of the display signal through the cassette test electrode region of the second display unit.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate test circuit, and the method includes:
  • the at least two display units comprising a first display unit and a second display unit disposed adjacent to the first display unit;
  • the first and second display units each include an array test electrode region and a boxed test electrode region, the array test electrode region includes a plurality of array test electrodes, and the packaged test electrode region includes a plurality of boxed test electrodes;
  • the plurality of array test electrodes of the second display unit are electrically connected to the plurality of cassette test electrodes of the second display unit through the periphery of the first display unit to pass through the second display unit.
  • the box test electrode area drives the output of the display signal.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate test circuit, and the method includes:
  • the at least two display units including a first display unit, a second display unit, and a third display unit, the second display unit being located at the first and third displays Between units;
  • Each of the first to third display units includes an array test electrode region and a boxed test electrode region, the array test electrode region includes a plurality of first array test electrodes and a plurality of second array test electrodes, and the boxed test electrode regions Including a plurality of first boxed test electrodes and a plurality of second array test electrodes;
  • the first display test electrodes of the second display unit are electrically connected to the first plurality of box test electrodes of the second display unit through the periphery of the first display unit, and the second display is The plurality of second array test electrodes of the unit are electrically connected to the plurality of second box test electrodes of the second display unit through the periphery of the third display unit to form a box test by the second display unit.
  • the electrode area drives the output of the display signal.
  • the array substrate testing circuit of the present invention connects the array test electrodes of the second display unit to the second display unit through the periphery of the first display unit. Forming the test electrode, or connecting the first array test electrode of the second display unit to the first package test electrode of the second display unit through the periphery of the first display unit, and the second display unit.
  • the array test electrodes are connected to the second box-shaped test electrodes of the second display unit one by one through the periphery of the third display unit to avoid a staggered positional relationship between the longitudinal array test traces and the lateral metal traces at the edges of the display area.
  • the output of the display signal is controlled by the box-shaped test electrode of the second display unit, thereby completing the array test item of the second display unit, thereby reducing the occurrence of coupling, leakage and damage, thereby improving the production yield of the display panel. purpose.
  • FIG. 1 is a schematic structural view of a display unit of the prior art
  • FIG. 2 is a schematic structural view of a prior art array substrate test circuit
  • FIG. 3 is a schematic structural view of a first embodiment of an array substrate test circuit of the present invention.
  • FIG. 4 is a schematic structural view of a second embodiment of an array substrate test circuit of the present invention.
  • FIG. 5 is a schematic flow chart of a first embodiment of a method for fabricating an array substrate test circuit of the present invention
  • FIG. 6 is a flow chart showing a second embodiment of a method for fabricating an array substrate test circuit of the present invention.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of an array substrate test circuit of a display unit in the prior art.
  • a plurality of array test electrodes located above the display area of each display unit in FIG. 1 such as four array test electrodes 1 respectively connected to display areas located in the same display unit via longitudinal metal traces 3 running through the left and right sides of the display area
  • the lower four test boxes 2, the four metal wires 3 ie, the array substrate test traces
  • the lateral metal traces not shown
  • the staggered positional relationship causes the horizontal display signals to be affected by the coupling, causing display differences on the left and right sides of the display panel, and the staggered positions may also leak, and may even cause abnormal problems such as damage, so that the display panel The yield is affected.
  • FIG. 3 is a schematic structural diagram of a first embodiment of the array substrate test circuit of the present invention.
  • the array substrate test circuit is disposed on the substrate 20, the substrate 20 includes at least two display units 10, and the at least two display units 10 include a first display unit and a first portion disposed adjacent to the first display unit a second display unit, each of the first and second display units includes an array test electrode region 11 and a cassette test electrode region 12, the array test electrode region 11 includes a plurality of array test electrodes 111, and the package test electrode regions 12
  • the plurality of arrayed test electrodes 121 of the second display unit are electrically connected to the plurality of the box-shaped test electrodes 121 of the second display unit through the periphery of the first display unit.
  • the output of the display signal is driven by the cassette test electrode region 12 of the second display unit.
  • the at least two display units 10 each include a display area 13 and scan driving circuits on the left and right sides of the display area 13.
  • the array test electrode area 11 is located above the display area 13, and the The cassette test electrode region 12 is located below the display area 13.
  • the periphery of the first display unit is an area of the first display unit that is away from the left side scan driving circuit and close to the second display unit.
  • the display area 13 refers to an area of the array substrate which is inside the sealant when the cassette is formed, and this area is used to fill the liquid crystal to display an image.
  • Other components and functions of the first and second display units are the same as those in the prior art, and are not described herein again.
  • the array test electrode region 11 includes four array test electrodes 111, and the boxed electrode region 12 includes four packaged test electrodes 121.
  • the The number of array test electrodes 111 and the set of test electrodes 121 can be set as needed.
  • the second display unit is located on the right side of the first display unit. In other embodiments, the second display unit may also be located on the left side of the first display unit, and the connection relationship and working principle are the same as those in the foregoing embodiment, and details are not described herein again.
  • the array test electrode 111 of the second display unit is connected to the box-shaped test electrode 121 of the second display unit through the array test trace 14 and the periphery of the first display unit in a one-to-one correspondence, and the array test is performed.
  • the wire 14 is completely cut in the cutting process to ensure the normal completion of the array test item, and not only the longitudinal array test trace 14 is prevented from affecting the display signal in the lateral direction of the display area edge (including leakage and staggered position damage). The problem), and can effectively eliminate the impact of electrostatic damage caused by the array test area during the subsequent cutting process on the boxed test project.
  • the array substrate test circuit connects the array test electrodes of the second display unit to the box-shaped test electrodes of the second display unit through the array test traces and the periphery of the first display unit in a one-to-one correspondence to avoid
  • the longitudinal array test traces and the lateral metal traces at the edge of the display area are in an interdigitated positional relationship, thereby controlling the output of the display signal through the boxed test electrodes of the second display unit, thereby completing the second display unit
  • the array test project reduces coupling, leakage and damage problems, thereby improving the production yield of the display panel.
  • FIG. 4 is a structural diagram of a second embodiment of the array substrate test circuit of the present invention.
  • the second embodiment of the array substrate test circuit is different from the above-described first embodiment in that the at least two display units 10 include first to third display units, and the second display unit is located in the first Between the first and third display units, the first to third display units each include an array test electrode region 11 and a cassette test electrode region 12, and the array test electrode region 11 includes a plurality of first array test electrodes 111 and a plurality of a second array of test electrodes 112, the packaged test electrode region 12 includes a plurality of first packaged test electrodes 121 and a plurality of second array test electrodes 122, and a plurality of first array test electrodes 111 of the second display unit pass the The first display unit of the first display unit is electrically connected to the plurality of first box test electrodes 121 of the second display unit, and the plurality of second array test electrodes 112 of the second display unit pass through the third display unit The plurality of second box-forming test
  • the at least two display units 10 each include a display area 13 and scan driving circuits on the left and right sides of the display area 13.
  • the array test electrode area 11 is located above the display area 13, and the box is formed.
  • the test electrode area 12 is located below the display area 13, the first array of test electrodes 111 and the plurality of first box test electrodes 121 are located on the left side, the plurality of second array test electrodes 112 and the A number of second boxed test electrodes 122 are located on the right side.
  • the periphery of the first display unit is an area of the first display unit remote from the left side scan driving circuit and close to the second display unit, and the periphery of the third display unit is the third display unit is far away The right side scans the driving circuit and is adjacent to an area of the second display unit.
  • the specific positions of the first to third display units will change, specifically
  • the array test traces 14 are the shortest, and the array test traces 14 can be cut off optimally in subsequent boxed test items, so the specific positional relationship of the first to third display units is not limited to this.
  • the embodiments of the invention may be changed and set by those skilled in the art according to specific needs.
  • FIG. 5 is a schematic flow chart of a first embodiment of a method for fabricating an array substrate test circuit of the present invention.
  • the method includes:
  • Step S1 providing a substrate 20.
  • the substrate 20 is a glass substrate, and other devices and functions on the substrate are the same as those of the prior art substrate, and details are not described herein again.
  • Step S2 at least two display units 10 are disposed on the substrate 20, and the at least two display units 10 include a first display unit and a second display unit disposed adjacent to the first display unit.
  • Step S3 The first and second display units 10 each include an array test electrode region 11 and a cassette test electrode region 12, and the array test electrode region 11 includes a plurality of array test electrodes 111, and the package test electrode region 12 Including a plurality of cassette test electrodes 121; and
  • Step S4 electrically connecting the plurality of array test electrodes 111 of the second display unit to the plurality of cassette test electrodes 121 of the second display unit through the periphery of the first display unit to pass the first
  • the cassette test electrode area 12 of the two display units drives the output of the display signal.
  • FIG. 6 is a schematic flow chart of a second embodiment of a method for fabricating an array substrate test circuit of the present invention.
  • the method includes:
  • Step S1 providing a substrate 20.
  • the substrate 20 is a glass substrate, and other devices and functions on the substrate are the same as those of the prior art substrate, and details are not described herein again.
  • Step S2 providing at least two display units 10 on the substrate 20, the at least two display units 10 including a first display unit, a second display unit, and a third display unit, wherein the second display unit is located in the Between the first and third display units.
  • the first to third display units each include an array test electrode region 11 and a cassette test electrode region 12, and the array test electrode region 11 includes a plurality of first array test electrodes 111 and a plurality of second array test electrodes 112.
  • the boxed test electrode region 12 includes a plurality of first boxed test electrodes 121 and a plurality of second array test electrodes 122.
  • Step S4 The first array test electrodes 111 of the second display unit are electrically connected to the first plurality of box test electrodes 121 of the second display unit through the periphery of the first display unit.
  • the plurality of second array test electrodes 112 of the second display unit are electrically connected to the plurality of second box test electrodes 122 of the second display unit through the periphery of the third display unit to pass the first
  • the cassette test electrode area 12 of the two display units drives the output of the display signal.
  • the array substrate test circuit connects the array test electrodes of the second display unit to the box test electrodes of the second display unit one by one through the periphery of the first display unit, or passes the first array test electrodes of the second display unit
  • the periphery of the first display unit is connected to the first box-shaped test electrode of the second display unit, and the second array of test electrodes of the second display unit are connected to the second display through the periphery of the third display unit.
  • a second box of test electrodes of the unit to avoid a staggered positional relationship between the longitudinal array test traces and the lateral metal traces at the edges of the display area, thereby controlling the output of the display signals through the boxed test electrodes of the second display unit, Thereby, the array test item of the second display unit is completed, and the occurrence of coupling, leakage and damage problems is reduced, thereby achieving the purpose of improving the production yield of the display panel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种阵列基板测试电路及其制作方法。阵列基板测试电路设于基板（20）上，基板（20）包括至少两个显示单元（10），至少两个显示单元（10）包括第一及相邻设置的第二显示单元（10），第一及第二显示单元（10）均包括阵列测试电极区（11）及成盒测试电极区（12），第二显示单元（10）的阵列测试电极（111）通过第一显示单元（10）的外围对应连接第二显示单元（10）的成盒测试电极（121），以通过第二显示单元（10）的成盒测试电极区（12）驱动显示信号的输出，减少耦合、漏电及炸伤问题的发生，从而提升显示面板生产良率。

Description

阵列基板测试电路及其制作方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板测试电路及其制作方法。
【背景技术】
LTPS（Low temperature Poly Silicon，低温多晶硅）TFT LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器）近年来在手机上得到广泛应用，其高电路整合特性与低成本的优势，在中小尺寸显示面板的应用中有着绝对的优势。LTPS TFT LCD具有高分辨率、反应速度快、高亮度、高开口率等优点，通过将外围驱动电路同时制作在玻璃基板上，达到系统整合的目标、节省空间及驱动芯片的成本。
LTPS TFT LCD中的阵列制程是在一块很大的玻璃基板上均匀有序排布形成一个个阵列电路，所述玻璃基板在经过阵列测试项目并达标后，将在后续成盒制程的切割段被切割成一批小片的显示单元，每个显示单元都有一个独立的阵列电路，用于控制最终成品LCD面板的显示。
LTPS TFT LCD面板在其中一种阵列线路结构设计中，对于单个显示单元来说（如图1及图2所示），通过几根贯穿于显示区域左右两侧的纵向金属走线（统称为阵列基板测试走线），将位于显示区域上方的阵列测试电路相关信号连接到位于显示区域下方的成盒测试电路中，以借用成盒测试电路的部分线路来驱动纵向的显示信号的输出，从而完成阵列测试项目。这几根纵向的阵列基板测试走线与显示区域边缘的横向金属走线始终呈垂直交错的位置关系，在成盒测试项目中，这种交错的位置关系使横向的显示信号受到耦合影响，引起显示面板左右两侧的显示差异；另外交错位置也可能发生漏电，甚至会产生炸伤等异常问题，使显示面板的良率受到影响。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板测试电路及其方法，避免阵列基板测试走线与显示区域边缘的金属走线产生交错，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板测试电路，所述阵列基板测试电路设置于基板上，所述基板包括至少两个显示单元，所述至少两个显示单元包括第一显示单元及与所述第一显示单元相邻设置的第二显示单元，所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极，所述第二显示单元的若干阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干成盒测试电极，以通过所述第二显示单元的成盒测试电极区驱动显示信号的输出。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板测试电路的制作方法，所述方法包括：
提供一基板；
在所述基板上设置至少两个显示单元，所述至少两个显示单元包括第一显示单元及与所述第一显示单元相邻设置的第二显示单元；
所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极；及
将所述第二显示单元的若干阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干成盒测试电极，以通过所述第二显示单元的成盒测试电极区驱动显示信号的输出。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板测试电路的制作方法，所述方法包括：
提供一基板；
在所述基板上设置至少两个显示单元，所述至少两个显示单元包括第一显示单元、第二显示单元及第三显示单元，所述第二显示单元位于所述第一与第三显示单元之间；
所述第一至第三显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干第一阵列测试电极及若干第二阵列测试电极，所述成盒测试电极区包括若干第一成盒测试电极及若干第二阵列测试电极；及
将所述第二显示单元的若干第一阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干第一成盒测试电极，将所述第二显示单元的若干第二阵列测试电极通过所述第三显示单元的外围一一对应电性连接所述第二显示单元的若干第二成盒测试电极，以通过所述第二显示单元的成盒测试电极区驱动显示信号的输出。
本发明的有益效果是：区别于现有技术的情况，本发明的所述阵列基板测试电路将第二显示单元的阵列测试电极通过第一显示单元的外围一一对应连接至第二显示单元的成盒测试电极，或者将第二显示单元的第一阵列测试电极通过第一显示单元的外围一一对应连接至第二显示单元的第一成盒测试电极，并将第二显示单元的第二阵列测试电极通过第三显示单元的外围一一对应连接至第二显示单元的第二成盒测试电极，以避免纵向的阵列测试走线与显示区域边缘的横向金属走线产生交错的位置关系，以此通过第二显示单元的成盒测试电极控制显示信号的输出，从而完成对第二显示单元的阵列测试项目，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
【附图说明】
图1是现有技术的一个显示单元的结构示意图；
图2是现有技术的阵列基板测试电路的结构示意图；
图3是本发明的阵列基板测试电路的第一实施例的结构示意图；
图4是本发明的阵列基板测试电路的第二实施例的结构示意图；
图5是本发明的阵列基板测试电路的制作方法的第一实施例的流程示意图；
图6是本发明的阵列基板测试电路的制作方法的第二实施例的流程示意图。
【具体实施方式】
请参阅图1及图2，是现有技术中显示单元的阵列基板测试电路的结构示意图。图1中位于每个显示单元的显示区域上方的若干阵列测试电极，如四个阵列测试电极1分别经由贯穿于显示区域左右两侧的纵向金属走线3分别连接到位于同一显示单元的显示区域下方的四个成盒测试电极2，这四根金属线3（即阵列基板测试走线）都与显示区域边缘的横向的金属走线（未示出）呈垂直交错的位置关系，在成盒测试项目中，这种交错的位置关系使横向的显示信号受到耦合影响，引起显示面板左右两侧的显示差异，另外交错位置也可能发生漏电，甚至会产生炸伤等异常问题，使显示面板的良率受到影响。
请参考图3，是本发明的阵列基板测试电路的第一实施例的结构示意图。所述阵列基板测试电路设置于基板20上，所述基板20包括至少两个显示单元10，所述至少两个显示单元10包括第一显示单元及与所述第一显示单元相邻设置的第二显示单元，所述第一及第二显示单元均包括阵列测试电极区11及成盒测试电极区12，所述阵列测试电极区11包括若干阵列测试电极111，所述成盒测试电极区12包括若干成盒测试电极121，所述第二显示单元的若干阵列测试电极111通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干成盒测试电极121，以通过所述第二显示单元的成盒测试电极区12驱动显示信号的输出。
具体地，所述至少两个显示单元10均包括显示区域13及位于所述显示区域13左右两侧的扫描驱动电路，所述阵列测试电极区11位于所述显示区域13的上方，所述成盒测试电极区12位于所述显示区域13的下方。
其中，所述第一显示单元的外围是所述第一显示单元远离所述左侧扫描驱动电路且靠近所述第二显示单元的区域。
其中，在本发明所有实施例中，显示区域13是指阵列基板在成盒时处于密封胶内侧的区域，此区域用于填充液晶以显示图像。所述第一及第二显示单元的其他元件及功能与现有技术相同，在此不再赘述。
其中，在本发明的所有实施例中，所述阵列测试电极区11包括四个阵列测试电极111，所述成盒电极区12包括四个成盒测试电极121，在其他实施例中，所述阵列测试电极111及成盒测试电极121的数量可以根据需要进行设置。
在本实施例中，所述第二显示单元位于所述第一显示单元的右侧。在其他实施例中，所述第二显示单元也可位于所述第一显示单元的左侧，其连接关系及工作原理与上述实施例相同，在此不再赘述。
将所述第二显示单元的阵列测试电极111通过阵列测试走线14及所述第一显示单元的外围一一对应连接至所述第二显示单元的成盒测试电极121，所述阵列测试走线14在切割制程中被全部切断，以保证阵列测试项目正常完成的前提下，不仅能避免纵向的阵列测试走线14对于显示区域边缘横向的显示信号的影响（包括漏电及交错位置发生炸伤的问题），而且能有效地消除后续切割过程中阵列测试区域产生的静电击伤对于成盒测试项目造成的影响。
所述阵列基板测试电路将所述第二显示单元的阵列测试电极通过阵列测试走线及所述第一显示单元的外围一一对应连接至所述第二显示单元的成盒测试电极，以避免纵向的阵列测试走线与显示区域边缘的横向金属走线产生交错的位置关系，以此通过所述第二显示单元的成盒测试电极控制显示信号的输出，从而完成对所述第二显单元的阵列测试项目，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
请参阅图4，是本发明的阵列基板测试电路的第二实施例的结构示意图。所述阵列基板测试电路的第二实施例与上述第一实施例的区别之处在于：所述至少两个显示单元10包括第一至第三显示单元，所述第二显示单元位于所述第一与第三显示单元之间，所述第一至第三显示单元均包括阵列测试电极区11及成盒测试电极区12，所述阵列测试电极区11包括若干第一阵列测试电极111及若干第二阵列测试电极112，所述成盒测试电极区12包括若干第一成盒测试电极121及若干第二阵列测试电极122，所述第二显示单元的若干第一阵列测试电极111通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干第一成盒测试电极121，所述第二显示单元的若干第二阵列测试电极112通过所述第三显示单元的外围一一对应电性连接所述第二显示单元的若干第二成盒测试电极122，以通过所述第二显示单元的成盒测试电极区12驱动显示信号的输出。
具体地，所述至少两显示单元10均包括显示区域13及位于所述显示区域13左右两侧的扫描驱动电路，所述阵列测试电极区11位于所述显示区域13的上方，所述成盒测试电极区12位于所述显示区域13的下方，所述若干第一阵列测试电极111及所述若干第一成盒测试电极121均位于左侧，所述若干第二阵列测试电极112及所述若干第二成盒测试电极122均位于右侧。
所述第一显示单元的外围是所述第一显示单元远离所述左侧扫描驱动电路且靠近所述第二显示单元的区域，所述第三显示单元的外围是所述第三显示单元远离所述右侧扫描驱动电路且靠近所述第二显示单元的区域。
在其他实施例中根据所述第一至第三显示单元中阵列测试电极111及成盒测试电极121设置位置的不同，所述第一至第三显示单元的具体位置将发生变化，具体以所述阵列测试走线14为最短、且在后续成盒测试项目中能将所述阵列测试走线14切断为最佳，因此所述第一至第三显示单元的具体位置关系并不限定于本发明的实施例，本领域技术人员可以根据具体需要进行变更和设置。
请参阅图5，是本发明的阵列基板测试电路的制作方法的第一实施例的流程示意图。所述方法包括：
步骤S1：提供一基板20。
具体地，所述基板20为玻璃基板，所述基板上的其他器件及功能与现有技术的基板相同，在此不再赘述。
步骤S2：在所述基板20上设置至少两个显示单元10，所述至少两个显示单元10包括第一显示单元及与所述第一显示单元相邻设置的第二显示单元。
步骤S3：所述第一及第二显示单元10均包括阵列测试电极区11及成盒测试电极区12，所述阵列测试电极区11包括若干阵列测试电极111，所述成盒测试电极区12包括若干成盒测试电极121；及
步骤S4：将所述第二显示单元的若干阵列测试电极111通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干成盒测试电极121，以通过所述第二显示单元的成盒测试电极区12驱动显示信号的输出。
请参阅图6，是本发明的阵列基板测试电路的制作方法的第二实施例的流程示意图。所述方法包括：
步骤S1：提供一基板20。
具体地，所述基板20为玻璃基板，所述基板上的其他器件及功能与现有技术的基板相同，在此不再赘述。
步骤S2：在所述基板20上设置至少两个显示单元10，所述至少两个显示单元10包括第一显示单元、第二显示单元及第三显示单元，所述第二显示单元位于所述第一与第三显示单元之间。
步骤S3：所述第一至第三显示单元均包括阵列测试电极区11及成盒测试电极区12，所述阵列测试电极区11包括若干第一阵列测试电极111及若干第二阵列测试电极112，所述成盒测试电极区12包括若干第一成盒测试电极121及若干第二阵列测试电极122。
步骤S4：将所述第二显示单元的若干第一阵列测试电极111通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干第一成盒测试电极121，将所述第二显示单元的若干第二阵列测试电极112通过所述第三显示单元的外围一一对应电性连接所述第二显示单元的若干第二成盒测试电极122，以通过所述第二显示单元的成盒测试电极区12驱动显示信号的输出。
所述阵列基板测试电路将第二显示单元的阵列测试电极通过第一显示单元的外围一一对应连接至第二显示单元的成盒测试电极，或者将第二显示单元的第一阵列测试电极通过第一显示单元的外围一一对应连接至第二显示单元的第一成盒测试电极，并将第二显示单元的第二阵列测试电极通过第三显示单元的外围一一对应连接至第二显示单元的第二成盒测试电极，以避免纵向的阵列测试走线与显示区域边缘的横向金属走线产生交错的位置关系，以此通过第二显示单元的成盒测试电极控制显示信号的输出，从而完成对第二显示单元的阵列测试项目，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种阵列基板测试电路，其中，所述阵列基板测试电路设置于基板上，所述基板包括至少两个显示单元，所述至少两个显示单元包括第一显示单元及与所述第一显示单元相邻设置的第二显示单元，所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极，所述第二显示单元的若干阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干成盒测试电极，以通过所述第二显示单元的成盒测试电极区驱动显示信号的输出。
  2. 根据权利要求1所述的阵列基板测试电路，其中，所述至少两个显示单元包括第一至第三显示单元，所述第二显示单元位于所述第一与第三显示单元之间，所述第一至第三显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干第一阵列测试电极及若干第二阵列测试电极，所述成盒测试电极区包括若干第一成盒测试电极及若干第二阵列测试电极，所述第二显示单元的若干第一阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干第一成盒测试电极，所述第二显示单元的若干第二阵列测试电极通过所述第三显示单元的外围一一对应电性连接所述第二显示单元的若干第二成盒测试电极，以通过所述第二显示单元的成盒测试电极区驱动显示信号的输出。
  3. 根据权利要求2所述的阵列基板测试电路，其中，所述至少两显示单元均包括显示区域及位于所述显示区域左右两侧的扫描驱动电路，所述阵列测试电极区位于所述显示区域的上方，所述成盒测试电极区位于所述显示区域的下方，所述若干第一阵列测试电极及所述若干第一成盒测试电极均位于左侧，所述若干第二阵列测试电极及所述若干第二成盒测试电极均位于右侧。
  4. 根据权利要求3所述的阵列基板测试电路，其中，所述第一显示单元的外围是所述第一显示单元远离所述左侧扫描驱动电路且靠近所述第二显示单元的区域，所述第三显示单元的外围是所述第三显示单元远离所述右侧扫描驱动电路且靠近所述第二显示单元的区域。
  5. 一种阵列基板测试电路的制作方法，其中，所述方法包括：
    提供一基板；
    在所述基板上设置至少两个显示单元，所述至少两个显示单元包括第一显示单元及与所述第一显示单元相邻设置的第二显示单元；
    所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极；及
    将所述第二显示单元的若干阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干成盒测试电极，以通过所述第二显示单元的成盒测试电极区驱动显示信号的输出。
  6. 根据权利要求5所述的阵列基板测试电路的制作方法，其中，所述在所述基板上设置至少两个显示单元包括：所述至少两个显示单元均包括显示区域及位于所述显示区域左右两侧的扫描驱动电路，所述阵列测试电极区位于所述显示区域的上方，所述成盒测试电极区位于所述显示区域的下方。
  7. 根据权利要求6所述的阵列基板测试电路的制作方法，其中，所述将所述第二显示单元的若干阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干成盒测试电极包括：所述第一显示单元的外围是所述第一显示单元远离所述左侧扫描驱动电路且靠近所述第二显示单元的区域。
  8. 一种阵列基板测试电路的制作方法，其中，所述方法包括：
    提供一基板；
    在所述基板上设置至少两个显示单元，所述至少两个显示单元包括第一显示单元、第二显示单元及第三显示单元，所述第二显示单元位于所述第一与第三显示单元之间；
    所述第一至第三显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干第一阵列测试电极及若干第二阵列测试电极，所述成盒测试电极区包括若干第一成盒测试电极及若干第二阵列测试电极；及
    将所述第二显示单元的若干第一阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干第一成盒测试电极，将所述第二显示单元的若干第二阵列测试电极通过所述第三显示单元的外围一一对应电性连接所述第二显示单元的若干第二成盒测试电极，以通过所述第二显示单元的成盒测试电极区驱动显示信号的输出。
  9. 根据权利要求8所述的阵列基板测试电路的制作方法，其中，所述在所述基板上设置至少两个显示单元包括：所述第一显示单元位于所述第二显示单元的右方，所述第三显示单元位于所述第二显示单元的左方，所述第一显示单元至所述第三显示单元均包括显示区域及位于所述显示区域左右两侧的扫描驱动电路，所述阵列测试电极区位于所述显示区域的上方，所述成盒测试电极区位于所述显示区域的下方，所述若干第一阵列测试电极及所述若干第一成盒测试电极均位于左侧，所述若干第二阵列测试电极及所述若干第二成盒测试电极均位于右侧。
  10. 根据权利要求9所述的阵列基板测试电路的制作方法，其中，所述将所述第二显示单元的若干第一阵列测试电极通过所述第一显示单元的外围一一对应电性连接所述第二显示单元的若干第一成盒测试电极，将所述第二显示单元的若干第二阵列测试电极通过所述第三显示单元的外围一一对应电性连接所述第二显示单元的若干第二成盒测试电极包括：所述第一显示单元的外围是所述第一显示单元远离所述左侧扫描驱动电路且靠近所述第二显示单元的区域，所述第三显示单元的外围是所述第三显示单元远离所述右侧扫描驱动电路且靠近所述第二显示单元的区域。
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CN107065364A (zh) * 2017-06-15 2017-08-18 厦门天马微电子有限公司 阵列基板、显示面板、显示装置、大板及测试方法
CN111445834B (zh) * 2020-05-12 2023-04-18 京东方科技集团股份有限公司 显示基板、显示面板和显示面板的测试方法

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