Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
  • H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
  • H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
  • H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
  • H03F1/304—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device and using digital means
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/56—Modifications of input or output impedances, not otherwise provided for
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
  • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/468—Indexing scheme relating to amplifiers the temperature being sensed
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G2201/00—Indexing scheme relating to subclass H03G
  • H03G2201/10—Gain control characterised by the type of controlled element
  • H03G2201/106—Gain control characterised by the type of controlled element being attenuating element

Definitions

• This invention relates to electronic circuitry, and more particularly to electronic power amplifier circuits.
• Power amplifiers are used in a multitude of electronic systems, particularly radio frequency (RF) systems, such as radios, cellular telephones, WiFi, etc.
• RF radio frequency
• RF transceivers utilize designated time slots within a frequency band to transmit or receive signals.
• TDD time division duplexing
• an RF transceiver PA is operated in a pulsed mode, amplifying an applied RF signal only during each designated time slot, and being powered OFF at other times.
• FIG. 1 is a block diagram of a typical prior art radio transmitter two-stage power amplifier 100.
• an integrated circuit (IC) 102 includes several subcircuits that accept an RF input signal RFin and generate an amplified output signal RFout to a selected destination (e.g. , one or more band filters and/or antenna ports); the IC 102 may also be referred to as a "chip” or "die”.
• an input impedance matching network (IMN) 104 impedance matches the input signal RFin to a first amplifier stage 106 (often called a driver).
• An interstage IMN 108 couples the output of the first amplifier stage 106 to a second amplifier stage 1 10 (in this case, a final stage).
• the amplified RF output of the second amplifier stage 1 10 is coupled to an output IMN 1 12, the output of which is RFout.
• the PA 100 example shown in FIG. 1 has two amplifier stages, but other embodiments may have fewer or more than two amplifier stages.
• One or more of the various IMN circuits 104, 108, 1 12 may be implemented in a tunable configuration, such as by using tunable inductors and/or tunable capacitors; some of the IMN circuits may be optional for some embodiments; and in some embodiments, one or more of the IMN circuits may be off-chip circuits.
• the first amplifier stage 106 and the final amplifier stage 1 10 each have corresponding bias circuits 1 14, 1 16 for controlling the gain of their respective amplifier stages.
• a voltage supply VDD 1 1 8 provides power as needed to specific circuitry in the IC 102, and may be variable as a function of a control parameter to regulate the behavior of the PA 100.
• the voltage supply VDD may be provided from off-chip or may be generated on-chip from an external power source; an off-chip configuration is shown by way of example.
• FIG. 2 is a graph of an example ideal RFout pulse 200 from a TDD PA 100, and of an example realistic RFout pulse 202 from a TDD PA showing output power (Gain) as a function of time.
• the illustrated ideal pulse 200 ideally has a square wave-form over a 4 mS operational interval (such an interval corresponds to a "long packet" in a WiFi system).
• the invention encompasses temperature compensation circuits that adjust one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA.
• Some embodiments of the invention compensate for PA Gain "droop" due to self-heating using an analog and/or digital Sample and Hold (S&H) circuit.
• S&H Sample and Hold
• Gain Control signal is then generated that is a function of the difference between the initial temperature and the subsequently measured operating temperature of the PA as the PA self-heats for the duration of the pulse.
• One or more correction signals - in particular, Gain Control signals - may be applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA. Examples of such circuits include the bias circuit for one or more PA amplifier stages, one or more impedance matching networks (e.g. , input, interstage, and/or output IMNs), one or more auxiliary amplifier stages (e.g.
• Embodiments of the invention can maintain the effective temperatures of the operational components of a PA circuit within 2.5 °C from -40 °C to +85 °C, and maintain RF Gain within about ⁇ 0.05 dB during at least a 4 mS operational pulse.
• aspects of the invention include analog and digital examples of an S&H circuit that may be used in embodiments of the invention, continuous temperature compensation used in combination with compensation for PA self-heating compensation during pulsed operation, use of direct temperature sensing, use of indirect temperature measurement for generation of a Gain control signal to offset PA self-heating during pulsed operation, and placement of temperature sensing circuits on an integrated circuit.
• FIG. 1 is a block diagram of a typical prior art radio transmitter two-stage power amplifier.
• FIG. 2 is a graph of an example ideal RFout pulse from a TDD PA, and of an example realistic RFout pulse from a TDD PA, showing output power (Gain) as a function of time.
• FIG. 3 is a block diagram of a generalized circuit for generating a Gain Control (GC) signal suitable for adjusting one or more circuit parameters of a PA as a function of direct temperature measurement to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA.
• GC Gain Control
• FIG. 4A is a graph of PA Bias Current and Gain versus time for an amplification pulse of a conventional PA.
• FIG. 4B is a graph of PA Bias Current and Gain versus time for an amplification pulse of a PA in which the Bias Current is augmented and varied by a GC signal generated by the GC signal circuit of FIG. 3.
• FIG. 5 is a block diagram of a PA on an integrated circuit having multiple components whose parameters may be adjusted to offset self-heating Gain droop of the PA under control of the GA signal from the circuit of FIG. 3.
• FIG. 6A is a schematic diagram of one embodiment of an analog temperature sensor and S&H circuit that may be used in the circuit of FIG. 3.
• FIG. 6B is a timing diagram showing one example of the control signals for the A, B, and C terminals of the switch of FIG. 6A.
• FIG. 7 is a block diagram of one embodiment of a partially digital S&H circuit.
• FIG. 8 is a schematic diagram of one embodiment of a continuous temperature compensation circuit.
• FIG. 9 is a first embodiment of an indirect temperature measurement gain control signal generation circuit.
• FIG. 10 is a second embodiment of an indirect temperature measurement gain control signal generation circuit.
• FIG. 1 1 is a top plan view of an example layout of an IC that includes a PA.
• FIG. 12 A is a process flow diagram of a first method for temperature compensating a target circuit having one or more performance parameters affected by self-heating during pulsed operation of the target circuit.
• FIG. 12B is a process flow diagram of a second method for temperature compensating a target circuit having one or more performance parameters affected by self- heating during pulsed operation of the target circuit.
• FIG. 12C is a process flow diagram of a third method for temperature compensating a target circuit having one or more performance parameters affected by self-heating during pulsed operation of the target circuit.
• FIG. 12D is a process flow diagram of a method for temperature compensating a target circuit.
• FIG. 12E is a process flow diagram of a method for temperature compensating an integrated circuit including (1) a power amplifier having a corresponding Gain that droops due to self-heating of the power amplifier during pulsed operation and (2) a temperature compensation circuit.
• FIG. 13 is a schematic diagram of another embodiment of an analog temperature sensor and sample-and-hold circuit in combination with a power amplifier having a current mirror circuit and a cascode bias circuit.
• FIG. 14 is a schematic diagram of an example temperature compensated power amplifier having standby mode circuitry.
• FIG. 15 is a process flow diagram of a first method for temperature compensating an integrated circuit, particularly a power amplifier.
• FIG. 16 is a process flow diagram of a second method for temperature compensating an integrated circuit, particularly a power amplifier.
• FIGS. 17A and 17B are a process flow diagram of a third method for temperature compensating an integrated circuit, particularly a power amplifier.
• the invention encompasses temperature compensation circuits that adjust one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA.
• Some embodiments of the invention compensate for PA Gain "droop" due to self-heating using an analog and/or digital Sample and Hold (S&H) circuit.
• S&H Sample and Hold
• a "droop" Gain Control signal is then generated that is a function of the difference between the initial temperature and the subsequently measured operating temperature of the PA as the PA self-heats for the duration of the pulse.
• One or more correction signals - in particular, Gain Control signals - may be applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
• Such circuits include the bias circuit for one or more PA amplifier stages, one or more impedance matching networks (e.g. , input, interstage, and/or output IMNs), one or more auxiliary amplifier stages (e.g. , variable gain amplifiers), one or more adjustable attenuation circuits on the input and/or output of the PA, and/or voltage or current supply circuits within or to the PA.
• Embodiments of the invention can maintain the effective temperatures of the operational components of a PA circuit within 2.5 °C from -40 °C to +85 °C, and maintain RF Gain within about ⁇ 0.05 dB during at least a 4 mS operational pulse.
• aspects of the invention include analog and digital examples of an S&H circuit that may be used in embodiments of the invention, continuous temperature compensation used in combination with compensation for PA self-heating compensation during pulsed operation, use of direct temperature sensing, use of indirect temperature measurement for generation of a Gain control signal to offset PA self-heating during pulsed operation, and placement of temperature sensing circuits on an integrated circuit.
• aspects of the invention are described in the context of power amplifiers operated in a pulsed mode, the temperature compensation circuits encompassed by the invention are also generally applicable to target circuits having performance parameters affected by temperature and for which a flat response is desired, so long as such circuits have some adjustable parameter which allows compensating adjustment of the response.
• FIG. 3 is a block diagram of a generalized circuit 300 for generating a Gain Control (GC) signal suitable for adjusting one or more circuit parameters of a PA as a function of direct temperature measurement to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA.
• the GC signal circuit 300 may be fabricated as part of an IC that includes a PA, but in some applications one or more components of the GC signal circuit 300 may be external to such an IC. In many applications, it may be desirable to have one GC signal circuit 300 per PA amplifier stage.
• One or more temperature sensors 302 capable of measuring the temperature of a PA or of a circuit that closely follows the temperature of a PA (e.g. , a small-scale replica of a PA) are coupled to a sample-and-hold (S&H) circuit 304, optionally through an amplifier or buffer 306.
• S&H sample-and-hold
• Each temperature sensor 302 may include, for example, a PN junction diode, a diode- connected field effect transistor (FET), a resistor, a proportional-to-absolute temperature (PTAT) circuit, a digital temperature sensor, etc.
• FET diode- connected field effect transistor
• PTAT proportional-to-absolute temperature
• the differential amplifier 308 may be, for example, a differential transconductance amplifier that turns a voltage difference between two input terminals into a current at an output terminal.
• other circuits may be used that can generate an output that is a function of the difference between two provided inputs.
• the output signal ⁇ from the differential amplifier 308 may be applied to a correction circuit, such as an optional mapping circuit 310 that maps or associates ⁇ signal values to control signal values (e.g. , voltage or current levels) to output a Gain Control (GC) signal that is a function of the difference between the initial temperature and the subsequently measured PA operating temperature as the PA self-heats for the duration of the pulse.
• a correction circuit such as an optional mapping circuit 310 that maps or associates ⁇ signal values to control signal values (e.g. , voltage or current levels) to output a Gain Control (GC) signal that is a function of the difference between the initial temperature and the subsequently measured PA operating temperature as the PA self-heats for the duration of the pulse.
• GC Gain Control
• the ⁇ output signal of the differential amplifier 308 may be essentially used directly as the GC signal (e.g. , where the "mapping" of the ⁇ output signal to GC signal is linear and properly proportionate).
• the "mapping" of the ⁇ output signal to GC signal may apply an offset linear function, an inverse function, or a nonlinear function (e.g. , a logarithmic function).
• the mapping function may be programmable. Programming such a mapping function for an IC embodying GC signal circuit 300 may be performed once, such as during fabrication or in the field (e.g. , by burning or "blowing" fusible links).
• such programming may vary as a function of programmed input to the IC from an external source, and/or as a function of IC state or status.
• the ⁇ output signal of the differential amplifier 308 may be digitized (e.g. , through an analog-to-digital converter, or ADC) and applied to a look-up table (LUT) programmed with a desired mapping function in order to generate a GC signal; the GC signal output from the LUT may be used directly for digitally adjustable components, or converted back into a voltage or current signal for application to analog circuitry.
• ADC analog-to-digital converter
• the output GC signal generated by the GC signal circuit 300 may be used to offset the Gain droop of a PA as the PA self-heats for the duration of a pulse.
• a variety of circuit parameters can be adjusted to achieve such an offset.
• FIG. 4A is a graph of PA Bias Current 402a and Gain 404a versus time for an amplification pulse of a conventional PA. While the PA Bias Current 402a rises quickly and is then essentially flat for the pulse duration, the corresponding PA Gain 404a exhibits droop over time due to self-heating of the PA.
• FIG. 4B is a graph of PA Bias Current 402b and Gain 404b versus time for an amplification pulse of a PA in which the Bias Current 402b is augmented and varied by a GC signal generated by the GC signal circuit 300 of FIG. 3.
• the GC signal may be a current summed with the normal Bias Current applied to a PA.
• PA Bias Current 402b rises quickly and is then adjusted even higher by the GC signal as a function of PA self-heating temperature rise during the pulse duration. The increased Bias Current 402b to the PA increases the Gain of the PA.
• the droop in Gain of the PA that would otherwise occur due to self-heating is substantially offset by a nearly mirror-image of the drooping Gain curve 404a of FIG. 4A, leading to an essentially flat PA Gain 404b for the duration of the pulse.
• the output GC signal generated by the GC signal circuit 300 may be used to offset the self-heating Gain droop of a PA by varying any PA circuit parameter or set of parameters that controls the effective Gain of the PA output at RFout so as to essentially flatten the effective Gain.
• Such circuit parameters include output power, voltage, current, and/or RF signal amplitude.
• FIG. 5 is a block diagram of a PA 500 on an integrated circuit 502 having multiple components whose parameters may be adjusted to offset self-heating Gain droop of the PA under control of the GA signal from the circuit of FIG. 3.
• an input IMN and/or variable attenuator circuit 504 may be controlled by a coupled GC signal so as to vary the matching characteristics of the circuit and/or the RF signal path attenuation level in order to offset the PA Gain droop.
• a digital step attenuator (DSA) or variable analog attenuator may be configured to always provide a nominal level of signal amplitude attenuation, which may be adjusted downward by the GC signal (converted if necessary to digital form through an ADC) to reduce RF signal attenuation from RFin to RFout, thus compensating for PA Gain droop by increasing the amplitude of the RF signal.
• DSA digital step attenuator
• ADC analog attenuator
• a similar approach may be used for an intermediate IMN and/or variable attenuator circuit 506, and/or for an output IMN and/or variable attenuator circuit 508.
• an auxiliary amplifier 510 such as a variable gain amplifier (VGA) may be placed in the RF signal path between RFin and RFout to provide additional signal amplification (Gain) in response to the GC signal, thus compensating for PA Gain droop.
• VGA variable gain amplifier
• a GC signal may be combined with the output of their respective bias circuits 516, 518 to boost the bias level of one or both amplifier stages (that is, in some applications, only one amplifier stage 512, 514 need be compensated in order to offset the self- heating PA droop of all amplifier stages).
• an analog current representing the GC signal may be summed with the normal bias current applied to one or both amplifier stages.
• a GC signal may be applied to the respective bias circuits 516, 518 to internally adjust the bias level supplied to one or both amplifier stages. Further details regarding biasing of a PA are disclosed in U.S. Patent Application No.
• the voltage supply VDD 520 to the IC 502 may be varied ⁇ e.g. , boosted) as a function of the GC signal to compensate for self-heating PA droop.
• the voltage (and/or current) supplied only to specific components of the PA may be varied as a function of the GC signal to compensate for self-heating PA droop.
• drain voltage sources VDD' 522, 524 may be derived from VDD 520 and applied to the "top" of a corresponding stack of JV FETs comprising each amplifier stage 512, 514 (TV is typically between 3 and 5).
• the drain voltage sources VDD' 522, 524 may be varied by the GC signal to adjust the effective Gain of the stage.
• the drain voltages sources VDD' 522, 524 may be derived from VDD 520 by placing a low drop-out (LDO) voltage regulator between VDD and the drain of a stack of FETs comprising a PA stage. Increasing the output voltage of the LDO would increase the Gain of the FET stack. Accordingly, to compensate for Gain droop, the LDO output voltage could initially be set to a relatively low value, and then increased to maintain an essentially constant Gain.
• LDO low drop-out
• Another alternative is to adjust the gate bias voltages to one or more of the N FETs in an amplifier stage stack to change the drain voltage on the "bottom" FET in the stack, thereby adjusting its gain.
• This approach does not require any additional power supply, but merely redistributes the available VDD across the FETs in the stack to achieve a desired gain adjustment.
• the GC signal from one GC signal circuit 300 may be used to adjust the effective Gain of the PA as a whole during an operational pulse by adjusting only one or a subset of the PA components. Accordingly, it is not necessary that the GC signal from a GC signal circuit 300 associated with a PA amplifier stage be used to adjust only parameters of the associated stage to offset self-heating PA droop. For example, if separate GC signal circuits are associated with a PA driver stage and a PA final stage, and the resulting GC signals are used to control the bias applied to at least one stage, then at least the following configurations are possible:
• FIG. 6A is a schematic diagram of one embodiment of an analog temperature sensor 602 and S&H circuit 604 that may be used in the circuit of FIG. 3.
• the temperature sensor 602 includes a series-coupled resistor R and diode D coupled between a voltage supply and circuit ground. If the diode D is fabricated in reasonably close proximity to an amplifier stage of a PA, the node between the resistor R and diode D will have a voltage Vt that varies as a function of the temperature of the amplifier stage (see further disclosure below regarding placement of temperature sensor circuits). As should be clear, a different temperature sensing circuit could be used in place of the diode-based temperature sensor 602; examples are given above.
• the voltage Vt is coupled to a first input of a differential amplifier 606 which may be, for example, a differential transconductance amplifier (however, as noted above, other circuits may be used that can generate an output that is a function of the difference between two provided inputs).
• the output of the differential amplifier 606 is coupled to a 3-terminal switch 608 that may be implemented with field effect transistors (FETs).
• Terminal A of the switch 608 is coupled to a charge storage capacitor C and to a second input of the differential amplifier 606.
• Terminal B is an open circuit, and terminal C is coupled to a mapping circuit as in FIG. 3, or is directly used as a GC signal.
• the state of the switch 608 is set by control signals essentially derived from the supplied control signal, PA en, that powers the PA ON and OFF, defining a pulse.
• FIG. 6B is a timing diagram showing one example of the control signals for the A, B, and C terminals of the switch 608 of FIG. 6A.
• the temperature sensor 602 and S&H circuit 604 are also powered ON; alternatively, the temperature sensor 602 and S&H circuit 604 may always be ON, but be initialized at the rising edge of PA en signal.
• a Sampling signal is generated and applied to the switch 608 to couple the output of the differential amplifier 606 to terminal A as an initial state.
• capacitor C will be charged up until both inputs to the differential amplifier 606 are equal to Vt, the voltage representing the momentary temperature of an associated amplifier stage of a PA.
• the differential amplifier 606 is a transconductance amplifier
• the voltage on the positive input will be Vt
• the voltage on the negative input and on capacitor C
• the S&H circuit 604 in effect calibrates out all of its offsets during the Sampling phase, and capacitor C is in essence constantly tracking the temperature of the associated PA.
• a Hold signal is generated and applied to the switch 608 to couple the output of the differential amplifier 606 to terminal B and thus uncouple the capacitor C from any further input from the differential amplifier 606; the transition to terminal B provides a non-overlapping switching sequence to reduce sampling errors.
• the Hold signal may be a delayed version of the Sampling signal (the circuits for delaying timing signals are conventional and thus not shown).
• the compensation circuit that includes the S&H circuit 604 may generate a gain step when it transitions to the Hold phase, so this should occur before an RF receiver begins to lock in its gain equalization.
• a Monitor signal is generated and applied to the switch 608 to couple the output of the differential amplifier 606 to terminal C.
• the Monitor signal may be a delayed version of the Sampling signal or of the Hold signal.
• FIG. 7 is a block diagram of one embodiment of a partially digital S&H circuit 700.
• the output Vt of one or more temperature sensors 702 is coupled to the input of a counter-DAC- based circuit 704, optionally through an amplifier or buffer 706. More specifically, the temperature sensors 702 are coupled to the plus-input of a summing circuit 708 in this example.
• the output of the summing circuit 708 is coupled to an optional mapping circuit or may be used directly as a GC signal.
• the output of the summing circuit 708 is also coupled to opposite polarity inputs of two comparators 710a, 710b.
• the other inputs of the comparators 710a, 710b are coupled to associated reference voltages +Vref and -Vref.
• a positive reference voltage +Vref e.g. , +0.5LSB
• a negative reference voltage -Vref e.g. , -0.5LSB
• the outputs of the comparators 710a, 710b are coupled to respective Up and Down inputs of an Up- Down counter 712.
• the count output of the Up-Down counter 712 is coupled to a DAC 714, the analog output of which is coupled to the minus-input of the summing circuit 708.
• a HOLD signal controls enablement of the Up-Down counter 712, and may be a delayed version of the PA en control signal for an associated PA.
• the output of the DAC 714 equals Vt (within a margin of error of ⁇ 0.5 LSB) at a moment in time, the output of the Up-Down counter 712 does not change state. If Vt decreases (indicating an increase in temperature of the associated PA when using a sensor having a negative temperature coefficient, such as the diode-based sensor as in FIG. 6A), then the Up- Down counter 712 will count DOWN until the output of the DAC 714 again equals the Vt (within the margin of error).
• the Up- Down counter 712 will count UP until the output of the DAC 714 again equals the Vt (again, within the margin of error). Accordingly, the output of the DAC 714 represents the continuously tracked temperature of the associated PA while the Up-Down counter 712 is enabled.
• other temperature sensors may have a positive temperature coefficient (i. e. , Vt would increase with increasing temperature and decrease with decreasing temperature); the mapping circuit may be used to account for a sign or function change in the S&H circuit 700.
• the ⁇ value may be used directly as a GC signal or mapped to generate a GC signal as described above.
• two or more continuous temperature sensing circuits can be used to isolate measurements of PA self-heating during pulsed operation without using a sample and hold configuration.
• a first continuous temperature sensing circuit may be located in close proximity to a PA, while a second continuous temperature sensing circuit may be located at a farther distance from the heat-generating components on an IC, particularly the PA amplifier stages, so as to measure general IC temperature while minimizing the influence of heat generated by other circuits on the IC. Examples of such placements are discussed below with respect to FIG. 1 1.
• the measurements from the distant continuous temperature sensing circuit would be subtracted from the measurements from the proximate continuous temperature sensing circuit during pulsed operation of the PA associated with the proximate continuous temperature sensing circuit.
• the resulting difference may be applied to a mapping circuit to generate a Continuous GC signal that reflects essentially only PA self-heating during pulsed operation.
• Tip proximate temperature
• T ⁇ d distant temperature reflecting general IC temperature
• FIG. 8 is a schematic diagram of one embodiment of a continuous temperature compensation circuit 800.
• a temperature sensor 802 includes a series-coupled resistor R and diode D coupled between a voltage supply and circuit ground. The node between the resistor R and diode D will have a voltage Vt that varies as a function of the surrounding temperature.
• the voltage Vt may be amplified by a transconductance amplifier 804 that turns the voltage applied to its input terminal into a current at its output terminal.
• the output of the amplifier 804 represents a continuous measurement of temperature over time, T(t), at the location of the temperature sensor 802.
• T(t) time
• the continuous temperature sensing circuit 800 used for distant temperature measurements may include an optional S&H circuit 806 so that the measured ambient temperature at the beginning of pulse may be sampled and held near the commencement of pulsed operation, thus "locking" the ambient temperature measurement to an invariant value for the duration of the pulse.
• the S&H circuit 806 would be controlled by a Hold signal generated by commencement of a pulse (possibly with some delay). Such a configuration would prevent PA self-heating during pulsed operation from influencing the distant temperature sensor.
• any of the circuits for generating a GC signal described above can be used in conjunction with continuous temperature compensation of bias current to one or more stages of a PA.
• it is often useful to adjust the Gain of a PA to compensate for ambient temperature such as the environment in which an IC is used (e.g. , embedded within a cellular phone enclosure located in a desert).
• a continuous temperature sensing circuit 800 such as shown in FIG. 8 may be located at an appreciable distance from heat-generating components on an IC, particularly the PA amplifier stages, to minimize the influence of heat generated by other circuits on the IC.
• the output of such a continuous temperature sensing circuit 800 may be applied to a mapping circuit to generate an Ambient GC signal.
• an Ambient GC signal is designed to be uncorrelated with such self-heating.
• an Ambient GC signal may be summed with the normal Bias Current applied to a PA to compensate for variations in Gain due to changes in ambient temperature.
• a GC signal or Continuous GC signal may be summed with the normal Bias Current applied to a PA to compensate for variations in Gain due to PA self-heating during pulsed operation.
• PA self-heating during pulsed operation was directly measured by one or more temperature sensor circuits.
• PA self-heating during pulsed operation may be inferred (i. e., indirectly measured). For example, instead of measuring PA temperature rise due to self- heating and using the result to adjust Gain, measurement can be made of another circuit parameter of the PA or of a scaled replica of the PA that varies as a function of self-heating of the PA during pulsed operation. The resulting measurement can be used to adjust the effective Gain of the PA, such as by adding an off-setting current to the bias current for one or more amplifier stages of the PA.
• FIG. 9 is a first embodiment of an indirect temperature measurement gain control signal generation circuit 900.
• the circuit 900 includes a conventional PA 902 having a Gain control adjustment (e.g. , an adjustable bias circuit). Also included is a scaled replica amplifier 904 that, in known fashion, mimics the characteristics and performance behavior of the PA 902, but at a smaller scale (e.g. , 1/8 size).
• the replica amplifier 904 would be fabricated in close proximity to the PA 902 so as to be affected by the self-heating of the PA 902 during pulsed operation.
• the nominal Gain for the replica amplifier 904 generally would be the same as the nominal Gain for the PA 902 to maximize correlation, but may be set to some other value, such as unity, to simply measurement.
• a Reference Signal is applied to the input of the replica amplifier 904 and to a first input of a conventional measurement circuit 906, which may, for example, measure a desired parameter, such as Gain, power, voltage, current, etc.
• a desired parameter such as Gain, power, voltage, current, etc.
• the Reference Signal typically would be an RF or AC signal (e.g. , 0.5V ⁇ lOmV) simply intended to measure the small-signal response of the replica amplifier 904.
• the output of the replica amplifier 904 is coupled to a second input of the measurement circuit 906, which outputs a signal that represents the difference (e.g. , in Gain, power, voltage, current, etc.) between the Reference Signal and the output of the replica amplifier 904.
• the replica amplifier 904 mimics the behavior of the PA 902 and is located in close proximity to the PA 902, self-heating of the PA 902 during pulsed operation will cause a correlated temperature change in the replica amplifier 904.
• the change in temperature of the replica amplifier 904 during a pulse will cause the Gain of the replica amplifier 904 to droop.
• the measurement circuit 906 will output a signal proportional to the amount of droop in comparison to the Reference Signal, which thus represents an indirect, temperature-dependent measurement of the droop occurring in the PA 902 during the pulse.
• the measurement circuit 906 output may be coupled to a mapping and Gain control circuit 908 that provides a suitable GC signal back to the PA 902 and the replica amplifier 904 to boost their respective Gains in an amount sufficient to substantially offset the droop.
• the measured parameter of the replica amplifier circuit 904 (e.g. , change in Gain) is measured only during pulsed operation of the PA 902 and directly takes into account a characteristic that is a function of self-heating of the PA 902 during pulsed operation, no sample and hold circuitry is required.
• a S&H circuit (not shown) may be provided (e.g. , within or after the measurement circuit 906) to capture a DC representation of the measured parameter of the replica amplifier circuit 904 at to and compare that held value to the instantaneous parameter value of the replica amplifier circuit 904 during pulsed-operation of the PA 902 to determine the amount of Gain droop of the amplifier circuit 904 (and hence of the PA 902, due to its self-heating during pulsed operation).
• the difference between the two measured values would be applied to the mapping and Gain control circuit 908 to generate a suitable GC signal back to the PA 902 and the replica amplifier 904 to boost their respective Gains in an amount sufficient to substantially offset the droop.
• the sample-and-hold configuration can be used continuously or as a sampled system. The benefit of using a sampled version is that the adjustment range is minimized (e.g. , A10°C instead of, for example, -40°C to +85°C, which is a difference of 125°C).
• FIG. 10 is a second embodiment of an indirect temperature measurement gain control signal generation circuit 1000.
• the output of the replica amplifiers 1002a, 1002b may be applied to a first differential amplifier 1004.
• the output of the first differential amplifier 1004 represents the gains of the replica amplifiers 1002a, 1002b, which are assumed to be equal and also equal to the gain of the PA 902.
• the output signal represents gain because the DC input signals are assumed to be known and accurate.
• +DC IV + 0.1V
• the gain of the replica amplifiers 1002a, 1002b is 10
• mapping and Gain control circuit 908 generates a suitable GC signal back to the PA 902 and the replica amplifiers 1002a, 1002b to boost their respective Gains in an amount sufficient to substantially offset the droop.
• the configuration of FIG. 10 thus allows determining the small-signal response of the replica amplifiers 1002a, 1002b by using DC measurements only.
• a variant of this architecture can also utilize a S&H circuit (not shown) in a similar fashion to the architecture described above for the S&H circuit variant of FIG. 9.
• a particular power amplifier IC may include one or more temperature sensors for measuring PA self-heating during pulsed operation, and may include one or more temperature sensors for purposes of continuous temperature compensation.
• FIG. 1 1 is a top plan view of an example layout of an IC 1 100 that includes a PA. This example includes a main region 1 102 encompassing the circuitry for a PA, and a secondary region 1 104 encompassing the circuitry for a replica amplifier. Shown are several possible locations A-D for PA pulsed-operation self- heating temperature sensors in close proximity to the main PA region 1 102. Also shown are several possible locations E-H for continuous temperature compensation temperature sensors. Other locations and fewer or more locations may be used for either kind of temperature sensor. As described above, one or more replica amplifiers within the secondary region 1 104 may also be used for indirect measurement of the self-heating of a PA in the adjacent main region 1 102.
• the final stage may generate as much as 80% of the PA heat, with the remainder of the PA heat generated by the driver stage. Accordingly, it is generally beneficial to place a PA pulsed-operation self-heating temperature sensor in close proximity to the final stage.
• temperature sensors in multiple locations, such as locations A-H, and then determine which sensors in specific locations provide better performance (e.g. , faster responding, better accuracy, stronger output signal, etc.).
• locations A-H locations A-H
• 16 PA pulsed-operation self- heating temperature sensors were used to investigate optimal siting. Thereafter, the output from the selected sensors may be coupled to circuitry for compensating for PA self-heating during pulsed operation, or to suitable general continuous temperature compensation circuitry, as described above.
• the output of several temperature sensors in determining a GC signal and/or a Continuous GC signal.
• the output of the temperature sensors at locations A and B in FIG. 1 1 around the periphery of the main PA region 1 102 could be determined (and scaled or weighted, if necessary) so as to provide an average of self-heating temperatures for the main PA region 1 102.
• a proximate location such as A-D may be paired with a distant location E-H.
• FIG. 12 A is a process flow diagram 1200 of a first method for temperature compensating a target circuit having one or more performance parameters affected by self-heating during pulsed operation of the target circuit.
• the method steps include: monitoring the temperature of the target circuit during pulsed operation (STEP 1202); and adjusting one or more circuit parameters of the target circuit sufficient to substantially offset the effect of self-heating of the target circuit on the one or more performance parameters during pulsed operation (STEP 1204).
• FIG. 12B is a process flow diagram 1210 of a second method for temperature compensating a target circuit having one or more performance parameters affected by self- heating during pulsed operation of the target circuit.
• FIG. 12C is a process flow diagram 1220 of a third method for temperature compensating a target circuit having one or more performance parameters affected by self-heating during pulsed operation of the target circuit.
• Variations of the above methods include sampling and holding T(d) near the commencement of pulsed operation; the target circuit including a power amplifier and one of the performance parameters being at least one of a Gain or output power of the power amplifier during pulsed operation of the power amplifier; the target circuit including a power amplifier having at least one amplifier stage configured to receive an input radio frequency signal and output an amplified radio frequency signal, and the correction signal adjusting at least one of: a bias circuit for one or more amplifier stages; one or more impedance matching networks affecting the input radio frequency signal and/or the amplified radio frequency signal; one or more auxiliary amplifier stages for amplifying the input radio frequency signal and/or the amplified radio frequency signal; one or more attenuation circuits affecting the amplitude of the input radio frequency signal and/or the amplified radio frequency signal; one or more voltage and/or current supply circuits within or to the power amplifier.
• FIG. 12D is a process flow diagram 1230 of a method for temperature compensating a target circuit.
• the method includes: monitoring a circuit parameter of one of the target circuit or a scaled replica of the target circuit, where the circuit parameter varies as a function of self- heating of the target circuit during pulsed operation of the target circuit (STEP 1232); and adjusting one or more circuit parameters of the target circuit sufficient to substantially offset the effect of self-heating of the target circuit on the circuit parameter during pulsed operation (STEP 1234).
• a variation of this method includes the target circuit including a power amplifier and the monitored circuit parameter being a Gain of one of the power amplifier or at least one scaled replica of the power amplifier during pulsed operation of the power amplifier.
• FIG. 12E is a process flow diagram 1240 of a method for temperature compensating an integrated circuit including (1) a power amplifier having a corresponding Gain that droops due to self-heating of the power amplifier during pulsed operation and (2) a temperature compensation circuit.
• the method includes: providing at least one scaled replica amplifier in close proximity to the power amplifier, each scaled replica amplifier having an input coupled to a reference signal and outputting an amplified reference signal, wherein each scaled replica amplifier has a corresponding Gain that droops due to self-heating of the power amplifier during pulsed operation of the power amplifier (STEP 1242); and providing a power measurement and correction circuit coupled to the reference signal and to the amplified reference signal, for determining a correction signal as a function of the reference signal and of the amplified reference signal, the correction signal being coupled to the power amplifier to adjust the Gain of the power amplifier sufficient to substantially offset the effect of self-heating of the power amplifier on the Gain of the power amplifier during pulsed operation of the power amplifier (STEP 1244).
• FIG. 13 is a schematic diagram 1300 of another embodiment of an analog temperature sensor and sample-and-hold circuit in combination with a power amplifier having a current mirror circuit and a cascode bias circuit.
• a temperature compensated variable current source circuit 1302 includes a sensor and tracking circuit 1304 (also referred to as a "sample- and-hold" in some embodiments).
• the tracking circuit 1304 is similar to the circuit shown in FIG. 6A, but has several variations.
• the single diode D of FIG. 6A has been replaced by two series-connected (i. e., "stacked") diodes Dl, D2 to provide better voltage range and resolution; more than two diodes may be used if needed.
• Stacked diodes increase the voltage supplied to a first input of a primary differential amplifier 1306, which makes design and operation of the differential amplifier 1306 easier.
• stacked diodes reduce sensitivity to storage capacitor leakage.
• the node between the resistor Rl and the diodes Dl, D2 will have a voltage Yt that varies as a function of the temperature of the amplifier stage (see the disclosure above regarding placement of temperature sensor circuits).
• the resistor Rl is coupled to a regulated voltage, Vref (e.g. , 2.4V).
• the differential amplifier 1306 may be an operational transconductance amplifier (OTA), which produces an output current from differential input voltages.
• the differential amplifier 1306 may include a resistive digital-to-analog converter (RDAC) for selectively regulating the output of the differential amplifier 1306.
• RDAC resistive digital-to-analog converter
• an RDAC is a digitally-controlled electronic component that mimics the analog functions of a potentiometer (hence the variable resistor symbol inside the symbol for the differential amplifier 1306 in FIG. 13), and is often used for trimming and/or scaling analog signals.
• the sensor and sample-and-hold (S&H) circuit 1304 includes a second differential amplifier 1308 having a first input coupled directly to the output of the differential amplifier 1306 and to a first "near" terminal of an output switch Swl, and a second input directly to a second "far” terminal of the output switch Swl .
• the output of the second differential amplifier 1308 is coupled through a sampling switch Sw2 to a node between a storage capacitor C and a second input of the differential amplifier 1306.
• Both switches Swl, Sw2 may be implemented as FET switch devices, which have an ON state resistance, R O , and an OFF state capacitance, C O FF-
• the second differential amplifier 1308 keeps the voltage on both sides of the output switch Swl constant to improve accuracy, as described in greater detail below.
• the states of the two switches Swl, Sw2 are set to essentially mimic the 3-terminal switch 608 of FIG. 6A.
• the output of the differential amplifier 1306 is coupled (i.e. , through the second differential amplifier 1308) to the node between the storage capacitor C and the second input of the differential amplifier 1306.
• the storage capacitor C will be charged up until both inputs to the differential amplifier 1306 are equal to Vt, the voltage representing the momentary temperature of an associated amplifier stage of a PA.
• the differential amplifier 1306 is an OTA
• the voltage on the positive input will be Vt
• the voltage on the negative input and on the storage capacitor C
• the tracking circuit 1304 in effect calibrates out all of its offsets during the Sampling phase, and the storage capacitor C is in essence constantly tracking the temperature of the associated PA.
• a Hold signal sets Sw2 to OPEN while Swl remains OPEN, thus decoupling the output of the differential amplifier 1306 and thereby uncoupling the storage capacitor C from any further input from the differential amplifier 1306 (again, as conveyed through the second differential amplifier 1308); this transition provides a non-overlapping switching sequence to reduce sampling errors.
• uncoupling the output of the differential amplifier 1306 a brief (e.g. , 0.1 - 1 ⁇ 8) transition period allows the circuitry to settle to a new state - thus avoiding transients - while preserving the sampled charge on the storage capacitor C.
• a Monitor signal sets Swl to CLOSED while Sw2 remains OPEN.
• the output of the differential amplifier 1306 is selectively coupled through the output switch Swl to an input node of a bias correction circuit comprising FETs M1 -M4, resistor R2, variable resistor R3 (e.g. , an RDAC), and a differential amplifier 1310, coupled as shown in a current mirror configuration.
• the gates of FETs M2 and M3 are coupled to bias voltages, Vbias (e.g. , 2.4V).
• Vbias bias voltages
• a first input of the differential amplifier 1310 is coupled to a reference voltage Vbg, such as from a band-gap voltage reference, which is a temperature-independent voltage reference circuit widely used in ICs that produces an essentially constant voltage regardless of power supply variations, temperature changes, and load.
• a second input of the differential amplifier 1310 is coupled to a node between FET M4 and variable resistor R3.
• the output of the differential amplifier 1310 is coupled to the gates of FETs M4 and Ml.
• the differential amplifier 1310, the variable resistor R3, and FET M4 form a constant (but settable) current source 1312, with an output current equal to Vbg/R3.
• the constant current source 1312 is used to set a desired average current output for the bias correction circuit. This average current is then summed with the current from the tracking circuit 1304 by connecting the drains of the cascode FETs M2 and M3 together to generate an output 1314 that is a function of ⁇ . This approach makes sure that the tracking circuit 1304 cannot decrease the average current below the current set by the constant current source 1312.
• the operation of the second differential amplifier 1308 can be better understood in light of the above details regarding the configuration of the bias correction circuit.
• the output of the differential amplifier 1306 in an OTA configuration is a high impedance, as is the drain of the FET.
• FET M2 is in a cascode configuration and has a low input impedance, and thus sets the node voltage at the source of FET M2.
• the OTA differential amplifier 1306 output voltage on the "near" terminal of the output switch Swl and at the source of FET M2 (coupled to the "far” terminal of switch Swl) will be at somewhat different voltages when the switch Swl transitions from an OPEN state to a CLOSED state, thus producing a transient that has to settle out.
• the second differential amplifier 1308 works to reduce the voltage across the open output switch Swl .
• the input offset voltage to the OTA differential amplifier 1306 that makes this happen is stored on the storage capacitor C.
• the sampling switch Sw2 is then OPENED and the output switch Swl is CLOSED, resulting in greatly reduced transient events.
• the basic concept is to equalize voltages across switch Swl before and after the switching event. As should be apparent, a number of other circuit configurations may be used to accomplish this goal.
• the summed output 1314 of the temperature compensated variable current source circuit 1302 is coupled to a power amplifier circuit 1322.
• the power amplifier circuit 1322 includes a cascode current mirror circuit 1322, a main amplifier circuit 1324, and a voltage divider bias circuit 1326. To avoid clutter, the input and output terminals of the main amplifier circuit 1324 and other circuit details are omitted.
• the cascode current mirror circuit 1322 may be, for example, a cascode amplifier of the type described in U.S. Patent Application Serial No. 15/268,229, cited above, modified slightly to include input from the temperature compensated variable current source circuit 1302.
• the cascode current mirror circuit 1322 includes a FET stack 1330 of at least two serially-connected FETs; similarly, the main amplifier circuit 1324 includes a FET stack 1332 of at least two serially-connected FETs (note that the stacks need not have the same number of FETs).
• the FETs in the FET stacks 1330, 1332 are biased by voltages derived from the voltage divider bias circuit 1326.
• the voltage divider bias circuit 1326 may comprise two or more series-connected resistors (not labeled), which may be terminated by a diode connected FET Md .
• separate voltage divider bias circuits may be provided for the cascode current mirror circuit 1322 and for the main amplifier circuit 1324.
• the bottom or last FET M b o, M 0 in each FET stack is biased from a common source, described below.
• the purpose of the cascode current mirror circuit 1322 is to essentially act as a current mirror that sees bias voltages similar to the main amplifier circuit 1324, with the FET stack 1330 of transistor devices in the cascode current mirror circuit 1322 being scaled-down replicas of the FET stack 1332 of transistor devices in the main amplifier circuit 1324.
• the illustrated cascode current mirror circuit 1322 is modified from the examples described in U.S. Patent Application Serial No. 15/268,229 by including a differential amplifier 1340 having a first input coupled to the output 1314 of the temperature compensated variable current source circuit 1302, and a second input coupled to a node "X" (which would be coupled directly to the gates of the last FETs M b o, Mo in each FET stack 1330, 1332 as a bias in the absence of the temperature compensated variable current source circuit 1302).
• the output of the differential amplifier 1340 is directly coupled as a bias voltage Vgl to the gates of the last FETs M b o, Mo in each FET stack 1330, 1332; however, the coupling may be indirect, such as through a source follower circuit of the type described below with respect to FIG. 14.
• any deviation of the output 1314 from the nominal bias current at node "X" will cause the differential amplifier 1340 to modify the bias voltage Vgl supplied to the gates of the last FETs M b o, Mo in each FET stack 1330, 1332 to compensate for any measured ⁇ .
• the cascode current mirror circuit 1322 uses the differential amplifier 1340 to adjust the gate voltage Vgl applied to the gates of the last FETs Mbo, M 0 in each FET stack 1330, 1332 until that the voltage drops across resistors R10 and R20 are equalized.
• the voltage across R10 is the resistance R10 times the current from the temperature compensated variable current source circuit 1302, and the voltage across R20 is the resistance R20 times the current in the FET stack 1330 of the cascode current mirror circuit 1322 (i.e. , the replica amplifier stack).
• any FET stack 1330, 1332 can be set to any ratio of the input reference current from the temperature compensated variable current source circuit 1302 by choosing the ratio of FET device widths for the two FET stacks 1330, 1332 and also by scaling the resistors R10 and R20.
• the temperature compensated variable current source circuit 1302 may be used in conjunction with other power amplifier configurations, including the other PA circuits described in U.S. Patent Application Serial No. 15/268,229. Additional examples and details of bias circuit details are described in U.S. Patent Application Serial No. 15/279,274, filed September 28, 2016, entitled “Bias Control for Stacked Transistor Configuration” , and in U.S. Patent No. 9,837,965, issued December 5, 2017, entitled “Standby Voltage Condition for Fast RF Amplifier Bias", both of which are assigned to the assignee of the present invention, the entire contents of each of which are incorporated herein by reference.
• Some of the techniques to address such transient effects include circuits to minimize voltage changes when switching between active and standby modes, particularly for a power amplifier.
• a power amplifier (PA) circuit current flow in some parts of the PA can be restricted when the PA is inactive (i. e. , is in a standby mode), thus avoiding a fully OFF state for at least some FETs within the circuit.
• a temperature compensated variable current source circuit 1302 may be beneficially used with such PAs.
• FIG. 14 is a schematic diagram 1400 of an example temperature compensated power amplifier having standby mode circuitry.
• the illustrated example is similar in many respects to the circuit shown in FIG. 13, and includes a temperature compensated variable current source circuit 1302 (simplified to a symbolic representation), a cascode current mirror circuit 1402, a main amplifier circuit 1324, and a voltage divider bias circuit 1326.
• An added circuit is a standby mode circuit 1404.
• the cascode current mirror circuit 1402 differs in some respects from the cascode current mirror circuit 1332 of FIG. 13.
• the illustrated standby mode circuit 1404 includes a top FET M that is conventionally biased, and a bottom FET MB that is biased from the cascode current mirror circuit 1402.
• the top FET ⁇ prevents excessive drain-source voltage Vds across the bottom FET MB.
• other numbers of FETs may be used in other embodiments of the standby mode circuit 1404.
• the standby mode circuit 1404 is biased to provide a low current signal path (e.g. , about 100 nA) that is always in circuit, but is biased into a low current state when the main amplifier circuit 1324 is switched OFF during periods in which signal amplification is not needed.
• a significant benefit of switching to the standby mode circuit 1404 alone is that doing so keeps FET node voltages constant between active and standby modes, since the less that certain node voltages of FETs within an SOI IC change, the more stable the charge that may accumulate as a result of circuit activity in the active layer of an IC.
• the illustrated cascode current mirror circuit 1402 includes three switches 1406, 1408, 1410 that may be toggled between an active state A and a standby state S (note that the switch symbols are in neutral, unselected state for clarity of their switching function).
• switches 1406, 1408, 1410 When all of the switches 1406, 1408, 1410 are in the active state A, the configuration of the circuit as a whole is essentially identical to the circuit configuration shown in FIG.
• the standby mode circuit 1404 remains operative in a low current state, and the differential amplifier 1340 output is coupled to a source follower transistor MSF, the output of which is coupled to the gates of the last FETs Mbo, M 0 in each stack 1330, 1332 (however, as noted above, the same or a similar source follower circuit may also be used in the circuit of FIG. 13).
• the cascode current mirror circuit 1402 and/or the main amplifier circuit 1324) to an OFF state with respect to input signal amplification (to be clear, portions of the cascode current mirror circuit 1402 may remain active in the standby state S to provide a bias to the standby mode circuit 1404, but the stack 1330 of the cascode current mirror circuit 1402 is rendered inactive, and the cascode current mirror circuit 1402 cannot respond to the temperature change output 1314 from the temperature compensated variable current source circuit 1302).
• the bias provided to the bottom FET MB of the standby mode circuit 1404 is provided through a different path that limits current through the standby mode circuit 1404.
• the temperature compensated variable current source circuit 1302 is disconnected from the cascode current mirror circuit 1402 in the standby state S.
• the resistive divider R0, R0' uses high value resistors for low current consumption and sets a divided voltage that is close to the normal operating range in the active state (in one example embodiment, about Vcc ⁇ 0.2V).
• a resistor R30 and the FETs of the standby mode circuit 1404. This allows the cascode current mirror circuit 1402 to stay active in a closed loop mode of operation. Accordingly, the circuit of FIG. 14 avoids a fully OFF state for at least some FETs within the circuit, and keeps FET node voltages within the IC constant between active and standby modes.
• Another technique would be to omit the standby mode circuit 1404, and keep the differential amplifier 1340 and source follower transistor MSF active in standby mode, but simply reduce the current in the source follower transistor MSF with suitable circuitry.
• the stack 1330 of the cascode current mirror circuit 1402 and the stack 1332 of the main amplifier circuit 1324 would thus remain biased and active, but at a reduced current level.
• FIG. 15 is a process flow diagram 1500 of a first method for temperature compensating an integrated circuit, particularly a power amplifier.
• the first differential amplifier being an operational transconductance amplifier
• the operational transconductance amplifier including a resistive digital-to-analog converter for selectively regulating the output of the operational transconductance amplifier
• least one sensor including a plurality of series-coupled diodes
• the second differential amplifier equalizing voltages across the output switch before and after a switching event; configuring the correction signal to adjust a bias signal to the amplifier during operation of the amplifier; the transient effects including self-heating of the amplifier during operation of the amplifier; providing a constant current source for generating a selected average current output, and providing circuitry for summing the output of the first differential amplifier representing the difference ⁇ with the average current output of the constant current source; and/or wherein the amplifier includes at least one amplifier stage configured to receive an input radio frequency signal and output an amplified radio frequency signal, and further including coupling the correction signal to and adjusting a bias circuit for one or more amplifier stages to substantially offset the effect of self- heating during operation
• the amplifier includes a main amplifier circuit including a stack of field effect transistors (FETs) having a last FET M 0 , a cascode current mirror circuit coupled to the main amplifier circuit, and including a stack of FETs having a last FET Mbo, a first voltage divider bias circuit, coupled to the stack of FETs of the main amplifier circuit, a second voltage divider bias circuit, coupled to the stack of FETs of the cascode current mirror circuit, and a differential amplifier having a first input coupled to a node of the cascode current mirror circuit, a second input coupled to the correction signal from the correction circuit, and an output coupled, directly or indirectly, to bias the last FET Mo and the last FET Mbo; and/or wherein the first voltage divider bias circuit and the second voltage divider bias circuit are the same circuit.
• FETs field effect transistors
• the amplifier includes: a main amplifier circuit including a stack of field effect transistors (FETs) having a last FET M 0 , a low-current standby mode circuit, a cascode current mirror circuit coupled to the main amplifier circuit, and including a stack of FETs having a last FET Mbo, a first voltage divider bias circuit, coupled to the stack of FETs of the main amplifier circuit, a second voltage divider bias circuit, coupled to the stack of FETs of the cascode current mirror circuit, a differential amplifier having a first input, a second input, and an output, a source follower circuit coupled to the output of the differential amplifier, and outputting a bias signal, a first switch configured to couple the first input of the differential amplifier to the correction signal of the correction circuit in an active state, and to a low-current resistive divider in a standby state, a second switch configured to couple the second input of the differential amplifier to a node of the
• FIG. 16 is a process flow diagram 1600 of a second method for temperature compensating an integrated circuit, particularly a power amplifier.
• FETs
• FIGS. 17A and 17B are a process flow diagram 1700 of a second method for temperature compensating an integrated circuit, particularly a power amplifier.
• FETs field
• inventive concepts described above are particularly useful with an SOI-based fabrication process (including SOS), and with fabrication processes having similar characteristics. Fabrication in CMOS on SOI or SOS enables low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (in excess of about 1 GHz, and particularly at the common WiFi frequencies of 2.4GHz and 5GHz, and even higher frequencies).
• Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g. , NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices).
• Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially "stacking" components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents.
• Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functional without significantly altering the functionality of the disclosed circuits.

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