WO2018158302A1 - Halbleiterkörper - Google Patents
Halbleiterkörper Download PDFInfo
- Publication number
- WO2018158302A1 WO2018158302A1 PCT/EP2018/054906 EP2018054906W WO2018158302A1 WO 2018158302 A1 WO2018158302 A1 WO 2018158302A1 EP 2018054906 W EP2018054906 W EP 2018054906W WO 2018158302 A1 WO2018158302 A1 WO 2018158302A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- layer stack
- semiconductor body
- region
- indium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/816—Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
- H10F71/1272—The active layers comprising only Group III-V materials, e.g. GaAs or InP comprising at least three elements, e.g. GaAlAs or InGaAsP
- H10F71/1274—The active layers comprising only Group III-V materials, e.g. GaAs or InP comprising at least three elements, e.g. GaAlAs or InGaAsP comprising nitrides, e.g. InGaN or InGaAlN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/12—Active materials
- H10F77/124—Active materials comprising only Group III-V materials, e.g. GaAs
- H10F77/1248—Active materials comprising only Group III-V materials, e.g. GaAs having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP
- H10F77/12485—Active materials comprising only Group III-V materials, e.g. GaAs having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP comprising nitride compounds, e.g. InGaN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
- H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
Definitions
- An object to be solved is to provide a semiconductor body that can be efficiently operated and manufactured.
- the semiconductor body described here may in particular be based on an I I I / V compound semiconductor material. In this case, it is possible, in particular, for the semiconductor body to be based on a nitride compound semiconductor material.
- the semiconductor body comprises a p-doped region.
- the p-doped region is doped with at least one p-type dopant.
- the p-doped region may comprise one or more p-doped semiconductor layers.
- the p-doped region may extend over the entire lateral extent of the semiconductor body.
- the lateral extent of the semiconductor body is transverse, in particular perpendicular, to a stacking direction of the semiconductor body.
- Semiconductor body an active area. On the active area,
- Area may be arranged, the p-doped region.
- the active region may be configured to emit or detect electromagnetic radiation.
- the semiconductor body is then part of an optoelectronic component.
- the active one
- the region may comprise a plurality of alternately arranged quantum well layers and barrier layers.
- the semiconductor body is part of an electronic component such as a diode, a transistor or an integrated circuit. The active area is then designed accordingly.
- Nitride compound semiconductor material such as gallium nitride (GaN) may be formed.
- the material composition of the nitride compound semiconductor material does not change within the framework of a manufacturing tolerance
- semiconductor body a layer stack containing indium, wherein the indium concentration in the layer stack changes along the stacking direction, and the layer stack is formed with the exception of dopants with exactly one nitride compound semiconductor material.
- exactly one nitride compound semiconductor material means, for example, that the layer stack may have impurities or impurities with a concentration of less than 5%.
- the layer stack has impurities or impurities with a concentration of less than 1%.
- the intermediate layer can be applied, for example grown, to the layer stack.
- the layer stack may comprise various semiconductor layers.
- the Layer stack may be formed with a semiconductor material containing indium.
- the stacking direction of the semiconductor body corresponds to the stacking direction of the layer stack.
- the indium concentration in the layer stack is not constant along the
- the indium concentration in the stack of layers may increase or decrease in the stacking direction, for example. It is possible that the indium concentration in the layer stack changes linearly or in another way. Preferably, the indium concentration in the layer stack changes quasi-continuously or continuously. For example, the temperature or the supply of indium during the growth of the
- the indium concentration in the layer stack can be constant.
- the layer stack is formed with a nitride compound semiconductor material. This means that the entire layer stack with the same
- Regions of the layer stack only in their indium concentration and optionally in their
- Dopant concentration differ from each other.
- the layer stack contains indium, the unwanted incorporation and thus the concentration of
- Impurities in the active area can be avoided or at least reduced.
- the layer stack is formed with exactly one nitride compound semiconductor material
- Semiconductor body can be easily manufactured.
- the intermediate layer is nominally free of indium and disposed between the layer stack and the active region, and the intermediate layer directly adjoins the layer stack.
- the fact that the intermediate layer is nominally free of indium in this case means in particular that during the
- the layer stack, the intermediate layer and the active region are arranged one above the other in the stacking direction and can each extend over the entire lateral extent of the semiconductor body.
- the intermediate layer and / or the layer stack are at least locally n-doped. It is therefore possible that the intermediate layer and the layer stack are partially or completely n-doped. For example, individual layers of the layer stack may be n-doped and other layers are undoped.
- Layer stacks may be doped with silicon, for example.
- the dopant concentration in the intermediate layer and / or in the layer stack can be, for example, at least 5 * 10 17 1 / cm 3 and at most 2 * 10 18 1 / cm 3 . It is also possible that the dopant concentration of
- the layer stack may have regions in which the dopant concentration is at least 2 ⁇ 10 18 1 / cm 3 and at most 3 ⁇ 10 19 1 / cm 3 .
- the thickness in the stacking direction of these higher doped regions may be between 5 ⁇ and 30 ⁇ .
- electrostatic charge can be reduced.
- the semiconductor body may be grown on a substrate.
- the semiconductor body can epitaxially through
- organometallic vapor phase epitaxy grown on a substrate It is also possible that the
- Semiconductor body is free of a growth substrate and is located on a support element, which is subsequently attached to the semiconductor body after growth.
- the semiconductor body may be a thin-film semiconductor body from which the growth substrate is removed.
- form three-dimensional body and be, for example, parallelepiped or cylindrical.
- Semiconductor body a p-doped region, an active
- Dopants formed with exactly one nitride compound semiconductor material are formed with exactly one nitride compound semiconductor material.
- the intermediate layer is nominally free of indium, located between the layer stack and the active region, and adjoins directly to the layer stack.
- Layer stacks are n-doped at least in places.
- the semiconductor body described here is based inter alia on the finding that the semiconductor body can be produced efficiently and inexpensively, since the layer stack is formed with only one material.
- the semiconductor body can also be operated efficiently because the layer stack is formed with indium. It has been shown that by the use of indium in the
- Layer stack prevents or at least reduces the undesired incorporation of impurities into the active area.
- the Layer stack may extend in lateral directions over the entire lateral extent of the semiconductor body.
- the first region may comprise a plurality of semiconductor layers.
- the indium concentration in the first region decreases in the direction of the intermediate layer, so that the indium concentration in the first region at the interface to the
- Interlayer decreases to a minimum value.
- the indium concentration in the first area can decrease continuously.
- the indium concentration in the first region drops to a minimum value of ⁇ 1%.
- the indium concentration in the first region drops to a minimum value of ⁇ 0.5%. If the layer stack is formed, for example, with In x GaN, x is preferably less than 1% and particularly preferably less than 0.5%.
- the failure rate of the semiconductor body may be increased under electrostatic stress.
- the indium concentration according to this embodiment decreases to a minimum value at the interface between the layer stack and the intermediate layer. The continuous lowering of the indium concentration prevents the formation of an interface in which the indium concentration changes significantly.
- a second region of the layer stack is arranged on the side of the layer stack facing away from the first region, and the indium concentration in the second region increases in the direction of
- the second region may extend over the entire lateral extent of the semiconductor body.
- the first and the second area are arranged one above the other in the stacking direction. They do not border, however
- the second region may comprise a plurality of semiconductor layers.
- the indium concentration in the second area increases in
- the indium concentration in the second range increases from a minimum value of ⁇ 1% or more preferably of ⁇ 0.5% to above a threshold value of 1.5%.
- the threshold value is at least 2% and at most 4.9%.
- the indium concentration can increase continuously. If the second region adjoins a layer outside the layer stack which is formed with GaN, the formation of piezoelectric charges at the interface is prevented.
- the indium concentration in the second region of the layer stack increases in the direction of the intermediate layer to at least a threshold value and drops again below the threshold value in the region of the layer stack only within the first region.
- the indium concentration in the layer stack is less than the threshold only within the first and second ranges. Between the first and the second region may be arranged a third region in which the indium concentration is above the threshold value. In this case, the first and the second area each one
- the Layer stack is formed with only one nitride compound semiconductor material, it does not occur even within the layer stack to the formation of piezoelectric charges.
- the first and the second region of the layer stack are n-doped and the third region is undoped.
- the layer stack has no third area. In this embodiment, it is possible that the first and the second area in
- the first region may have a substantially smaller thickness than the second region.
- the thickness of the second region is 2 to 20 times the thickness of the first region.
- the thickness of the second region is three to four times as large as the thickness of the first region.
- the indium concentration in the layer stack decreases in the direction of the
- Interlayer This means that the indium concentration in the layer stack in the direction of the intermediate layer does not increase, but only decreases. In this case, the indium concentration in the layer stack can sink continuously in the direction of the intermediate layer. If the indium concentration at the interface with the intermediate layer in the layer stack drops to a minimum value of ⁇ 1% or preferably ⁇ 0.5%, the formation of piezoelectric charges at the interface is prevented. Because in this embodiment of the Layer stack has only one area, the
- Manufacturing process of the semiconductor body can be simplified.
- the indium concentration in the layer stack increases in the direction of the
- Intermediate layer does not sink, but only rises.
- the indium concentration in the layer stack can increase continuously in the direction of the intermediate layer.
- the intermediate layer may be highly n-doped. This means that the dopant concentration, for example at least 2 * 10 is 18 1 / cm 3 and not more than 3 * 10 19 1 / cm 3.
- Layer stack at least one pair of alternating layers, wherein a first layer of each pair is n-doped and a second layer of each pair is nominally undoped.
- the alternating layers are arranged between the first and the second region of the layer stack.
- the indium concentration in the alternating layers can be constant.
- the first layer of each pair may, for example, be n-doped with silicon. That the second layer of each pair is nominally undoped means that no dopant is provided during growth of the second layer. However, it is possible that dopants from adjacent
- the second layer has a dopant concentration that is significantly lower than the dopant concentration in the adjacent layers.
- the dopant concentration in the adjacent layers is significantly lower.
- the layer stack comprises a plurality of pairs of alternating layers.
- the alternating layers can provide improved protection against
- the first layer of each pair has a different indium concentration than the second layer of each pair.
- the first and the second layer thus each have a constant indium concentration.
- the indium concentration in the first layer may be either greater or less than the indium concentration in the second layer.
- the difference between the absolute indium concentrations in the first and the second layer may be, for example, one percent.
- Layer amount to 2% and amount to 3% in the second layer.
- the layer stack is between the intermediate layer and a layer sequence
- the layer sequence can be a variety of
- Layer sequence directly adjacent to the layer stack This means that the layer sequence, the layer stack and the intermediate layer are arranged one above the other in the stacking direction.
- the fact that the layer sequence is nominally free of indium means that no indium is provided during the growth of the layer sequence. It is possible, however, that
- the layer sequence is designed to contribute to a better protection against electrostatic discharge. To targeted disposals are used. A current pulse can then flow away via unevennesses in the layer sequence generated by the dislocations without damaging the active region. Thus, the failure rate of the semiconductor body in electrostatic charging can be reduced.
- Such a layer sequence is associated with a first
- the active region for generating or detecting is electromagnetic
- Semiconductor body may be, for example, a
- the light-emitting diode can, for example, electromagnetic radiation in a specific
- the layer thickness of the layer stack is preferably at least 15 nm.
- the layer thickness of the layer stack is particularly preferably at least 30 nm and at most 90 nm.
- the layer thickness of the layer stack may be 60 nm.
- the layer thickness of the layer stack is selected so that a relaxation of the layer stack
- Layer thickness of the layer stack in the stacking direction less than 20 nm.
- the layer thickness of Layer stack at least 5 nm and less than 20 nm.
- the indium concentration in the layer stack is less than 5%.
- the indium concentration in the layer stack is less than 3%.
- the indium concentration in the layer stack is approximately 2.7%. Since the indium concentration in the layer stack is relatively small, the
- Layer stacks are grown with a high quality. This means, for example, that less tension is created in the layer stack.
- Figure 1 shows a schematic cross section through a
- FIGS. 2 to 6 show schematic cross sections through a semiconductor body according to others
- FIG. 1 shows a schematic cross section through a semiconductor body 10.
- the semiconductor body 10 comprises a layer stack 41 onto which an intermediate layer 40
- the semiconductor body 10 comprises a p-doped region 20, which is applied to the active region 30.
- the layer stack 41 has a first region 42 which directly adjoins the intermediate layer 40. Furthermore, the layer stack 41 has a second region 43, which on the side facing away from the first region 42 of FIG.
- Layer stack 41 is arranged. Between the first
- Region 42 and the second region 43 is a third region 44.
- the layer stack 41 is formed except for dopants with exactly one nitride compound semiconductor material.
- exactly one nitride compound semiconductor material means that the
- Layers stack impurities or impurities may have a concentration of less than 5%.
- the layer stack has impurities or impurities with a concentration of less than 1%.
- the layer stack 41 contains indium. The indium concentration in the layer stack 41 is not constant. In the second region 43, the indium concentration increases in a stacking direction z over one
- the stacking direction z is perpendicular to the lateral extent of the semiconductor body 10.
- the indium concentration in the second region 43 increases from a minimum value of ⁇ 1% or preferably ⁇ 0.5% to above the threshold value.
- the stacking direction z of the semiconductor body 10 is applied on the z-axis and on the y-axis, the indium concentration in the layer stack 41. In the second region 43, the indium concentration thus increases continuously.
- the indium concentration is constant.
- the indium concentration drops below the threshold again. In this case, the sinks
- the indium concentration in the first region 42 decreases to a minimum value of ⁇ 1% or preferably ⁇ 0.5%.
- Threshold of the indium concentration may be, for example, at least 1.5% and at most 4.9%.
- the threshold value is preferably at least 2% and at most 3%. Since the indium concentration is relatively low, the
- the layer stack 41 may be formed, for example, with InGaN and be at least locally n-doped.
- the layer stack 41 may be doped with silicon.
- the layer stack 41 may have a thickness of at least 5 nm and at most 150 nm.
- the first region 42 and the second region 43 may each have a thickness of less than 5 nm.
- the intermediate layer 40 directly adjoins the layer stack 41 and is arranged between the layer stack 41 and the active region 30. Nominally, the intermediate layer 40 is free of indium. This means that no indium is provided during growth of the intermediate layer 40. However, it is possible that indium from adjacent layers is incorporated into the intermediate layer 40.
- the intermediate layer 40 may be formed with GaN.
- the intermediate layer 40 may be n-doped in partial regions. It can the
- Dopant concentration in the intermediate layer 40 at least 2 * 10 18 1 / cm 3 and at most 3 * 10 19 1 / cm 3 amount.
- the layer stack 41 may also have regions or layers in which the dopant concentration is in this range.
- piezoelectric charges may form at the interface between the two layers. The formation of piezo charges is in this
- Embodiment thereby prevents the indium concentration in the first region 42 decreases to a very low value.
- the active region 30 directly adjoins the intermediate layer 40 and has grown thereon.
- the active region 30 can be designed to generate or detect electromagnetic radiation, in particular light.
- the active area 30 may be, for example, a
- Multiple quantum well structure comprising a plurality of alternately arranged quantum well layers and
- barrier layers can be formed with GaAlN, InGaN or GaN and the
- Quantum well layers can be formed with InAlGaN or InGaN.
- the active region 30 the p-doped region 20 is arranged.
- the layer stack contains 41 indium, the unwanted incorporation and thus the concentration of
- Impurities in the active region 30 can be reduced.
- the semiconductor body 10 can be operated more efficiently.
- the layer stack 41 is formed with exactly one nitride compound semiconductor material
- Semiconductor body 10 are easily manufactured. In addition, the semiconductor body 10 is more robust than a semiconductor body having a larger number of different ones
- FIG. 2 shows a schematic cross section through a semiconductor body 10 according to another
- the structure of the semiconductor body 10 corresponds to the structure shown in FIG. In this embodiment, the third area 44 of the
- Layer stack 41 has pairs of alternating layers.
- a first layer 45 of each pair is n-doped and a second layer 46 of each pair is nominally undoped.
- the first layers 45 may be doped with silicon, for example. That the second layers 46 nominal
- Layers are incorporated into the second layers 46.
- FIG. 3 shows a schematic cross section through a semiconductor body 10 according to another
- the structure of the semiconductor body 10 corresponds to the structure shown in FIG.
- the semiconductor body 10 has a layer sequence 50.
- the layer stack 41 is between the
- Intermediate layer 40 and the layer sequence 50 arranged and the layer sequence 50 is nominally free of indium.
- Layer sequence 50 may be formed with GaN and contribute to protection against electrostatic discharge. For this purpose, deliberately existing dislocations in the layer sequence
- a current pulse can then flow away via unevennesses in the layer sequence 50 generated by the dislocations without damaging the active region 30.
- the failure rate of the semiconductor body 10 upon electrostatic charging can be reduced.
- Layer sequence 50 no piezoelectric charges, because the indium concentration in the second region 43 in the region of
- FIG. 4 shows a schematic cross section through a semiconductor body 10 according to another
- the layer stack 41 thus has only a first region 42 in this case. At the interface with the intermediate layer 40, the indium Concentration in the layer stack 41 maximum.
- the intermediate layer 40 may be partially highly n-doped.
- the indium concentration decreases in the second case, which is shown on the right side.
- Layer stack 41 in the direction of the intermediate layer 40.
- the indium concentration in the layer stack 41 at the interface to the intermediate layer 40 is minimal.
- the formation of piezoelectric charges at this interface is prevented. Since in this embodiment, the layer stack 41 has only a first region 42, the
- Semiconductor body 10 are made particularly easy.
- FIG. 5 shows a schematic cross section through a semiconductor body 10 according to another
- the structure of the semiconductor body 10 corresponds to the structure shown in FIG.
- the first layers 45 and the second layers 46 differ not only in that the first layers 45 are n-doped and the second layers 46 are undoped, but also in that the first
- Layers 45 have a different indium concentration than the second layers 46.
- the indium concentration is the same in all first layers 45 and differs from the indium concentration of the second layers 46. Also in all second layers 46, the indium concentration is the same. Thus, the indium concentration in the first layers 45 may be either greater or less than the indium concentration in the second layers 46. The difference of the indium concentrations of the first layers 45 and the second
- FIG. 6 shows a schematic cross section through a semiconductor body 10 according to another
- the structure of the semiconductor body 10 corresponds to the structure shown in FIG.
- the layer stack 41 in this exemplary embodiment has only a first region 42 and a second region 43.
- the first area 42 directly adjoins the second area 43.
- the thickness of the second region 43 in the stacking direction z is substantially greater than the thickness of the first region 42
- Thickness of the second region 43 is two to 20 times as large as the thickness of the first region 42.
- the thickness of the second region 43 is three to four times as large as the thickness of the first region 42.
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Abstract
Description
Claims
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE112018001095.3T DE112018001095B4 (de) | 2017-03-02 | 2018-02-28 | Halbleiterkörper |
| CN201880015306.0A CN110383505B (zh) | 2017-03-02 | 2018-02-28 | 半导体本体 |
| JP2019565986A JP6924852B2 (ja) | 2017-03-02 | 2018-02-28 | 半導体ボディ |
| US16/488,540 US11018278B2 (en) | 2017-03-02 | 2018-02-28 | Semiconductor body |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102017104370.5 | 2017-03-02 | ||
| DE102017104370.5A DE102017104370A1 (de) | 2017-03-02 | 2017-03-02 | Halbleiterkörper |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2018158302A1 true WO2018158302A1 (de) | 2018-09-07 |
Family
ID=61557273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2018/054906 Ceased WO2018158302A1 (de) | 2017-03-02 | 2018-02-28 | Halbleiterkörper |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11018278B2 (de) |
| JP (1) | JP6924852B2 (de) |
| CN (1) | CN110383505B (de) |
| DE (2) | DE102017104370A1 (de) |
| WO (1) | WO2018158302A1 (de) |
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| CN105308720B (zh) | 2013-06-11 | 2017-10-20 | 欧司朗光电半导体有限公司 | 用于制造氮化物化合物半导体器件的方法 |
| JP6128138B2 (ja) * | 2015-02-10 | 2017-05-17 | ウシオ電機株式会社 | 半導体発光素子 |
| JP6488891B2 (ja) | 2015-06-03 | 2019-03-27 | 三菱電機ビルテクノサービス株式会社 | 保守作業間隔決定装置 |
| JP6327323B2 (ja) | 2015-11-30 | 2018-05-23 | 日亜化学工業株式会社 | 半導体レーザ素子及びその製造方法 |
-
2017
- 2017-03-02 DE DE102017104370.5A patent/DE102017104370A1/de not_active Withdrawn
-
2018
- 2018-02-28 JP JP2019565986A patent/JP6924852B2/ja active Active
- 2018-02-28 US US16/488,540 patent/US11018278B2/en active Active
- 2018-02-28 CN CN201880015306.0A patent/CN110383505B/zh active Active
- 2018-02-28 WO PCT/EP2018/054906 patent/WO2018158302A1/de not_active Ceased
- 2018-02-28 DE DE112018001095.3T patent/DE112018001095B4/de active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10213395A1 (de) * | 2001-03-29 | 2002-10-10 | Lumileds Lighting Us | Indiumgalliumnitrid-Glättungsstrukturen für III-Nitried-Anordnungen |
| KR20080045943A (ko) * | 2006-11-21 | 2008-05-26 | 삼성전기주식회사 | 질화물 반도체 발광소자 |
| WO2011080219A1 (de) | 2009-12-30 | 2011-07-07 | Osram Opto Semiconductors Gmbh | Optoelektronischer halbleiterchip und verfahren zu dessen herstellung |
| DE102009060747A1 (de) * | 2009-12-30 | 2011-07-07 | OSRAM Opto Semiconductors GmbH, 93055 | Halbleiterchip |
Also Published As
| Publication number | Publication date |
|---|---|
| US11018278B2 (en) | 2021-05-25 |
| US20200006594A1 (en) | 2020-01-02 |
| DE102017104370A1 (de) | 2018-09-06 |
| JP6924852B2 (ja) | 2021-08-25 |
| JP2020508586A (ja) | 2020-03-19 |
| CN110383505B (zh) | 2022-07-22 |
| CN110383505A (zh) | 2019-10-25 |
| DE112018001095B4 (de) | 2025-05-15 |
| DE112018001095A5 (de) | 2019-12-19 |
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