WO2018157736A1 - 一种基于嵌入式处理器的三维声学成像实时信号处理装置 - Google Patents

一种基于嵌入式处理器的三维声学成像实时信号处理装置 Download PDF

Info

Publication number
WO2018157736A1
WO2018157736A1 PCT/CN2018/076392 CN2018076392W WO2018157736A1 WO 2018157736 A1 WO2018157736 A1 WO 2018157736A1 CN 2018076392 W CN2018076392 W CN 2018076392W WO 2018157736 A1 WO2018157736 A1 WO 2018157736A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
signal
subsystem
signal processing
embedded
Prior art date
Application number
PCT/CN2018/076392
Other languages
English (en)
French (fr)
Inventor
刘雪松
周凡
赵冬冬
陈耀武
Original Assignee
浙江大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浙江大学 filed Critical 浙江大学
Priority to US16/308,401 priority Critical patent/US11333759B2/en
Publication of WO2018157736A1 publication Critical patent/WO2018157736A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
    • G01S15/8993—Three dimensional imaging systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
    • G01S15/8909—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration
    • G01S15/8929—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration using a three-dimensional transducer configuration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/56—Display arrangements
    • G01S7/62—Cathode-ray tube displays
    • G01S7/6245—Stereoscopic displays; Three-dimensional displays; Pseudo-three dimensional displays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Definitions

  • the invention belongs to the field of three-dimensional acoustic imaging image processing, and in particular relates to a three-dimensional acoustic imaging real-time signal processing device based on an embedded processor.
  • Phased array three-dimensional acoustic imaging is one of the important innovations in underwater applications in recent years. It has the advantages of high resolution, real-time performance, three-dimensional information of observable targets and moving target recognition. Underwater biology, physics, It plays an increasingly important role in underwater applications such as archaeology, geography and military, and has become a hot topic in current research. Governments, institutions, and academics have conducted research on phased array three-dimensional acoustic acoustic imaging systems. In 2004, the Italian government funded six universities, including the University of Verona, the University of Florence, the University of Genoa, and the University of Milan, to conduct research on low-cost 3D imaging and modeling automation systems. The A3US laboratory led by Professor A.
  • Trucco of the University of Genoa in Italy has conducted in-depth research on sparse array design, real-time beamforming and image processing algorithms for phased array 3D acoustic imaging systems.
  • the British CodaOctopus company has successfully developed phased array three-dimensional acoustic imaging products, and phased array three-dimensional acoustic imaging real-time signal processing related technology has been monopolized by developed countries such as the European Union.
  • the first phased array three-dimensional sonar imaging system developed by China Shipbuilding Industry Corporation No. 715 Research Institute and Zhejiang University Digital Technology and Instrument Research Institute has filled the domestic blank.
  • the system adopts 48 ⁇ 48 road two-dimensional.
  • the planar receiving transducer array has a detection range of 200 meters, an angular resolution of 0.4° and a distance resolution of 2 cm.
  • Professor Sang Fangen from Harbin Institute of Technology based on a 16 ⁇ 8 two-dimensional planar array realized a three-dimensional sonar imaging system for underwater robot vision.
  • Nvidia's new Tegra K1 embedded GPU processor is a 192-core Kepler-based GPU designed to perform complex geometry and numerical calculations with powerful 3D image acceleration and ten times more CPU than CPU Even hundreds of times the floating point calculation performance.
  • Tegra K1 embedded GPU supports the widely used 3D graphics program interfaces OpenGL4.4 and OpenGL ES 3.1, which realizes 3D image processing and display efficiently through hardware acceleration.
  • Tegra K1 is embedded.
  • the GPU has 192 CUDA (Compute Unified Device Architecture) cores with 325GFLOPS super floating-point computing performance, making it ideal for intensive data and massively parallel data computing.
  • the Tegra K1 embedded GPU uses an optimized Kepler architecture to monitor each power supply through a Power Management Unit (PMU) to improve power efficiency and reduce power consumption.
  • PMU Power Management Unit
  • Array sparse sampling means that only the channel of the position of the array element of interest is sampled, which can solve the problem that the full array array of transducers brings high bandwidth, high computational complexity and high power consumption of sampled data. After the array is sparsely sampled, the corresponding weighting factor is multiplied to suppress the sidelobe peak.
  • Field Programmable Gate Array features rich I/O pins, precise timing control, and flexible pin definition.
  • multi-chip FPGA can realize synchronous sampling of large-scale arrays;
  • FPGA pins define pins as multiple sets of LVDS interfaces according to requirements, and realize one main FPGA through multiple sets of LVDS interfaces and interconnect with multiple sub-FPGAs. , complete multi-chip FPGA to the main FPGA high-speed data synchronous transmission.
  • the present invention provides a three-dimensional acoustic imaging real-time signal processing apparatus based on an embedded processor, which effectively solves the problem that the sampling data bandwidth is high, the three-dimensional acoustic imaging algorithm is difficult to realize real-time calculation, and low power consumption and miniaturization conditions are The problem of system development.
  • a three-dimensional acoustic imaging real-time signal processing device based on an embedded processor comprising: a plurality of signal acquisition subsystems, a signal interaction subsystem, an embedded GPU signal processing subsystem, and the signal acquisition system is processed according to an embedded GPU signal
  • the command sent by the subsystem collects and receives signal data of any channel in the acoustic array, and preprocesses the signal data, and then sends the preprocessed data to the embedded GPU signal processing subsystem through the signal interaction subsystem;
  • the embedded GPU signal processing subsystem processes the received pre-processed data to obtain image data.
  • the signal acquisition subsystem includes:
  • a command interface configured to receive a command sent by the embedded GPU signal processing subsystem, and send the command to the FPGA chip
  • the FPGA chip is configured to control the programmable switch to turn on or off any channel in the transducer array according to the received command, and receive the preprocessed data after processing the signal data of the partial channel in the transducer array; and according to the preprocessed data Controlling the program-controlled amplification chip to realize real-time gain control, and transmitting the pre-processed data to the LVDS interface;
  • a programmable switch for controlling whether any channel in the transducer array is turned on or off to achieve thinning of the three-dimensional acoustic imaging transducer array
  • An amplification filter chip for amplifying and filtering the received and collected analog signal data
  • a program-controlled amplification chip for real-time gain according to a control signal sent from the FPGA chip, and amplifying the received analog signal data
  • the AD chip is configured to convert the processed analog signal data into digital signal data, obtain preprocessed data, and send the preprocessed data to the FPGA chip;
  • LVDS for forwarding pre-processed data from the received FPGA chip to the signal interaction subsystem.
  • the above signal acquisition subsystem completes simultaneous sampling, amplification, filtering, real-time gain control (TVG), pre-processing and data transmission of multi-channel acoustic signals.
  • TVG real-time gain control
  • the signal interaction subsystem includes:
  • a command interface for receiving commands sent by the signal acquisition subsystem and the embedded GPU signal processing subsystem, and transmitting the commands to the FPGA chip;
  • the FPGA chip and the FPGA chip control multiple sets of LVDS interfaces to receive pre-processed data according to commands sent by the signal acquisition subsystem, and synchronously cache, sort and package the pre-processed data, and then execute commands according to the embedded GPU signal processing subsystem. Transfer the preprocessed data to the PCIe bus;
  • the PCIe bus is used by the FPGA chip to send the received pre-processed data to the embedded GPU signal processing subsystem.
  • the above signal interaction subsystem implements high-bandwidth data exchange and command control by multiple sets of signal acquisition subsystems and signal processing subsystems, and completes the signal processing subsystem to synchronously receive pre-processed data of multiple sets of signal acquisition subsystems.
  • the embedded GPU signal processing subsystem includes:
  • the PCIe bus is configured to receive pre-processed data sent by the signal interaction subsystem and forward the data to the Tegra K1 embedded GPU processor; the PCIe bus implements a data transmission rate of up to 20 Gbps to satisfy a three-dimensional sonar preprocessed data transmission bandwidth. ;
  • Tegra K1 embedded GPU processor is used to control the PCIe bus to receive data, calculate the received pre-processed data, obtain image data, and control the long-distance transmission of image data by Gigabit Ethernet chip and fiber transceiver chip, DSI display Interface display of image data;
  • a transmitting interface for controlling sound waves to be transmitted at a certain timing
  • Gigabit Ethernet chip Gigabit Ethernet interface, used to achieve long-distance transmission of image data
  • Optical fiber transceiver chip Gigabit optical port, used to realize long-distance transmission of image data through optical fiber;
  • DSI display interface for transmitting image data to the display screen to implement display of three-dimensional data
  • a debug interface for receiving commands sent externally to debug the embedded GPU signal processing subsystem.
  • the above embedded GPU signal processing subsystem completes pre-processing data reception, real-time calculation of three-dimensional sonar image algorithm, image data transmission and command control.
  • the Tegra K1 embedded GPU processor has features such as OpenGL4.4, OpenGL ES 3.1 and CUDA, high-performance image parallel processing capability, real-time processing of 3D sonar image algorithm, and rich high-speed data interconnection interface. Achieve large data throughput for large-scale acoustic signals; optimized Kepler-based GPUs enable low power consumption, and ultimately, enable Tegra K1 embedded GPU processors to achieve high-speed data transmission and imaging of 3D acoustic imaging at low power consumption The algorithm is efficient.
  • the invention designs the embedded platform with the Tegra K1 embedded GPU processor as the core, and exerts the strong performance of the Tegra K1 embedded GPU 3D image processing, high parallel computing capability, rich high-speed interconnect interface, low power consumption, combined with the FPGA pin. Rich and precise timing control, the embedded GPU signal processing subsystem is constructed. At the same time, through the signal interaction subsystem, high-speed data interaction between the embedded GPU signal processing subsystem and multiple signal acquisition subsystems can be realized, and the signal processing is completed. The system synchronously receives pre-processed data of multiple sets of signal acquisition subsystems, and the whole device has powerful data interaction capability and real-time parallel processing capability of signals.
  • FIG. 1 is a schematic structural diagram of a three-dimensional acoustic imaging real-time signal processing apparatus according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an embedded GPU signal processing subsystem according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a signal interaction subsystem according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a signal acquisition subsystem according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a three-dimensional acoustic imaging real-time signal processing apparatus based on an embedded processor according to the embodiment, and the apparatus specifically includes: an embedded GPU signal processing subsystem 100, a signal interaction subsystem 200, and a signal acquisition subsystem. 300.
  • the embedded GPU signal processing subsystem 100 includes: a Gigabit Ethernet interface 101 and a Gigabit optical port 102.
  • remote transmission of image data may be performed by any interface; and the debugging interface 103 is configured to receive Externally sent debug commands to the embedded GPU signal processing subsystem 100; the embedded GPU signal processing subsystem 100 and the signal interaction subsystem 200 are interconnected by a PCIe bus, and the signal interaction subsystem 200 passes through multiple LVDSs 201 and multiple The signal acquisition subsystems 300 are interconnected, and the pre-processed data of the plurality of signal acquisition subsystems 300 is synchronously transmitted to the embedded GPU signal processing subsystem 100 via the signal interaction subsystem 200.
  • the embedded GPU signal processing subsystem 100 performs command interaction with the signal interaction subsystem 200 and the signal acquisition subsystem 300 through the command interface 104 to implement simultaneous sampling of multiple signal acquisition subsystems 300, real-time gain control, array sparse sampling control, and code. Update.
  • the device of the present invention can configure different numbers of signal acquisition subsystems 300 according to the requirements of the system algorithm calculation and the needs of the calculation model; meanwhile, the embedded GPU signal processing subsystem 100 can control any sampling channel in the signal acquisition subsystem 300 through the command interface. It is turned on or off, featuring flexible system construction and dynamic configurability of sampling channels.
  • FIG. 2 is a schematic structural diagram of the embedded GPU signal processing subsystem 100 of the present embodiment.
  • the subsystem includes: a Tegra K1 embedded GPU processor 108, a transmitting interface 107, a PCIe bus interface 106, and a DSI display interface 105.
  • a Gigabit Ethernet 109 is connected between the Gigabit Ethernet interface 101 and the Tegra K1 embedded GPU processor 108, and a fiber transceiver chip 110 is connected between the Gigabit optical port 102 and the Tegra K1 embedded GPU processor 108.
  • the transmit interface 107 controls the sound waves to be transmitted at a certain timing; the START signal in the command interface 104 controls the signal acquisition subsystem 300 to simultaneously sample.
  • the Tegra K1 embedded GPU processor 108 receives pre-processed data through the PCIe bus 106, implements real-time calculation of the three-dimensional sonar image algorithm, performs real-time display of image data through the DSI display interface 105, or passes the image data through the optical transceiver chip 110 and the gigabit.
  • the optical port 102 performs long-distance transmission, and the image data is transmitted to the upper computer for display.
  • FIG. 3 is a schematic structural diagram of a signal interaction subsystem 200.
  • the subsystem includes an FPGA chip 204, a PCle bus 203, a command interface 202, and a plurality of groups of LVDS interfaces 201.
  • the plurality of sets of LVDS interfaces 201 synchronously receive the pre-processed data of the plurality of sets of signal acquisition subsystems 300.
  • the FPGA chip 204 synchronously buffers, organizes, and packs the pre-processed data of each frame, and transmits the signals to the embedded GPU through the PCIe bus 203.
  • the processing subsystem 100 implements high-speed data interaction and data synchronous transmission between the multiple sets of signal acquisition subsystems 300 and the embedded GPU signal processing subsystem 100.
  • FIG. 4 is a schematic structural diagram of the signal acquisition subsystem 300 of the embodiment.
  • the system includes: an FPGA chip 307, a highly integrated AD chip 306, a programmable amplifier 305, a filter 304, an amplifier 303, and a programmable switch 302.
  • the FPGA chip 307 performs command interaction with the embedded GPU signal processing subsystem 100 through the command interface 309, and controls the programmable switch 302 to turn on or off any channel in the pre-connector 301 to implement array sparse sampling; meanwhile, the FPGA chip 307
  • the control program-controlled amplifier 305 implements signal real-time gain control; the filter 304 and the amplifier 303 complete signal amplification and filtering, and the highly integrated AD chip 306 performs analog-to-digital conversion of the multi-channel signal.
  • the LVDS interface 308 sends the processed data to the signal interaction subsystem 200.
  • the embedded GPU signal processing subsystem 100 configures array sparse sampling parameters and TVG parameters to the FPGA chip 307 in the signal acquisition subsystem 300 through the command interface 104; then, the FPGA chip 307 controls The programmable switch 302 implements array sparse sampling, and the FPGA chip 307 controls the programmable amplifier 306 to implement TVG control.
  • the embedded GPU signal processing subsystem 100 controls the transmitting interface 107 to emit sound waves at a certain timing, and waits for the echo to arrive at the system, and then sends a synchronous sampling to the plurality of signal collecting subsystems 300 through the START signal in the command interface 104. Command to achieve simultaneous sampling control.
  • the signal acquisition subsystem 300 controls the programmable switch 302, and the amplifier 303, the filter 304, the programmable amplifier 305, and the AD chip 306 start to work, and the collected acoustic echoes are acquired.
  • the signal is amplified, filtered, and AD converted.
  • the programmable switch 302 and the programmable amplifier 305 respectively implement array sparse sampling and TVG functions, and the FPGA chip 307 performs preprocessing on the sampled data, such as weight coefficient multiplication, Fourier transform, etc., and then passes LVDS.
  • Interface 308 transmits the pre-processed data to signal interaction subsystem 200.
  • the signal interaction subsystem 200 synchronously receives the pre-processed data of the plurality of sets of signal acquisition subsystems 300, and the FPGA chip 204 synchronously buffers, organizes, and packs the multiple sets of pre-processed data for each frame through the PCIe bus 203.
  • the method is transmitted to the embedded GPU signal processing subsystem 100 to implement high-speed data interaction and data synchronous transmission between the multiple sets of signal acquisition subsystems 300 and the embedded GPU signal processing subsystem 100.
  • the embedded GPU signal processing subsystem 100 receives the preprocessed data transmitted by the signal interaction subsystem 200 through the PCIe bus 106, and the Tegra K1 embedded GPU processor 108 The real-time calculation of the three-dimensional sonar image algorithm is realized, the image data is displayed in real time through the DSI display interface 105, or the image data is transmitted remotely through the optical transceiver chip 110 and the gigabit optical port 102, and the image data is transmitted to the upper computer for display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • General Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
  • Image Processing (AREA)

Abstract

一种基于嵌入式处理器的三维声学成像实时信号处理装置，运用模块化设计，系统包括嵌入式GPU信号处理子系统（100）、信号交互子系统（200）、信号采集子系统（300）。嵌入式GPU信号处理子系统（100）以Tegra K1嵌入式GPU处理器（108）为核心，Tegra K1嵌入式GPU处理器（108）拥有OpenGL4.4、OpenGL ES 3.1和CUDA特性，具有高性能的图像并行处理能力，丰富的高速数据互连接口，适用于三维声学成像实时信号处理装置高速率数据传输与图像算法高效计算;同时，通过信号交互子系统（200），可实现嵌入式GPU信号处理子系统（100）与多个信号采集子系统（300）高速数据交互，整个装置具有强大的数据交互能力和信号实时并行处理能力。

Description

一种基于嵌入式处理器的三维声学成像实时信号处理装置 技术领域
本发明属于三维声学成像图像处理领域，具体涉及一种基于嵌入式处理器的三维声学成像实时信号处理装置。
背景技术
相控阵三维声学成像作为近些年水下应用领域的重要革新之一，具有分辨率高、实时性强、可观测目标三维信息以及动目标识别等优势，在水下生物学、物理学、考古学、地理学及军事等水下应用领域中扮演着越来越重要的角色，已经成为了当前研究的热点。各国政府、机构和学者对相控阵三维声学声学成像系统的开展了相关研究。2004年，意大利政府资助维罗纳大学、佛罗伦萨大学、热那亚大学、米兰大学等六所大学开展了低成本三维成像与建模自动化系统的研究。意大利热那亚大学的A.Trucco教授领导的A3US实验室对相控阵三维声学成像系统的稀疏阵列设计、实时波束形成和图像处理算法展开了深入了研究。但是，目前国际上只有英国CodaOctopus公司成功研制出相控阵三维声学成像产品，相控阵三维声学成像实时信号处理相关技术一直被欧盟等发达国家所垄断。在国内，中国船舶重工集团第715研究所与浙江大学数字技术及仪器研究所合作研制开发的国内首台相控阵三维声纳成像系统，填补了国内空白，该系统采用48×48路二维平面接收换能器阵列，探测距离200米，角度分辨率0.4°，距离分辨率2厘米。哈尔滨工业大学桑方恩教授团队基于16×8二维平面阵列，实现了用于水下机器人视觉的三维声纳成像系统。
虽然相控阵三维声学成像系统相关的研究至今已取得了一定的进展，但是为满足工程应用需求，仍需解决以下难题：1)实时三维声学成像算法所需要的数字信号处理计算量非常庞大，难以实现实时计算；2)低功耗和小型化条件下的超高速嵌入式并行实时计算系统开发，并对三维图像进行有效的重建、识别与分析；3)系统采用的声学接收阵列包含多达几千个换能器，原始采样数据量庞大。
Nvidia公司最新推出的Tegra K1嵌入式GPU处理器是具有192个核心的开普勒架构GPU，专为执行复杂的几何和数值计算而设计，拥有强大的3D图像加速功能和强于CPU数十倍乃至上百倍的浮点计算性能。在3D图像处理方面，Tegra K1嵌入式GPU支持业界广泛采用的3D图形程序接口OpenGL4.4和OpenGL ES 3.1，通过硬件加速，高效率地实现3D图像处理和显示；在数值计算方面，Tegra K1嵌入式GPU具有192个CUDA(Compute Unified Device Architecture)核心，具有325GFLOPS超强浮点计算性能，非常适合于密集型数据和大规模并行数据计算。同时，Tegra K1嵌入式GPU采用优化的开普勒架构，通过电源管理单元(Power Management Unit，PMU)监控各个电源，提高电源效率，有效降低功耗。
阵列稀疏采样是指仅对感兴趣的阵元位置的通道进行采样，可以解决全布阵换能器阵列带来采样数据高带宽，高计算量、高功耗的问题。阵列稀疏采样后，需乘以相应权重系数以抑制旁瓣峰值。
现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)具有I/O管脚丰富，时序控制精确，管脚定义灵活的特点。在同步信号的触发下，可实现多片FPGA对大规模阵列进行同步采样；FPGA管脚根据需求将管脚定义为多组LVDS接口，实现一片主FPGA通过多组LVDS接口与多片子FPGA互连，完成多片子FPGA至主FPGA高速数据同步传输。
发明内容
鉴于上述，本发明提供了一种基于嵌入式处理器的三维声学成像实时信号处理装置，该装置有效地解决采样数据带宽高、三维声学成像算法难以实现实时计算以及低功耗和小型化条件下系统开发的难题。
一种基于嵌入式处理器的三维声学成像实时信号处理装置，包括：多个信号采集子系统、信号交互子系统、嵌入式GPU信号处理子系统，所述的信号采集系统根据嵌入式GPU信号处理子系统发来的命令采集和接收声学阵列中任意通道的信号数据，并对信号数据进行预处理，然后将预处理数据通过所述的信号交互子系统发送至嵌入式GPU信号处理子系统；所述的嵌入式GPU信号处理子系统对接收的预处理数据进行处理，得到图像数据。
所述的信号采集子系统包括：
命令接口，用于接收嵌入式GPU信号处理子系统发送的命令，并将该命令输送至FPGA芯片；
FPGA芯片，用于根据接收的命令控制可编程开关对换能器阵列中任意通道开启或关闭，接收对换能器阵列中部分通道的信号数据经过处理后的预处理数据；并根据预处理数据控制程控放大芯片实现实时增益控制，且将预处理数据发送至LVDS接口；
可编程开关，用于控制换能器阵列中任意通道开启或关闭，实现三维声学成像换能器阵列稀疏化；
放大滤波芯片，用于对接收和采集的模拟信号数据进行放大和滤波处理；
程控放大芯片，用于根据FPGA芯片发来的控制信号进行实时增益，并对接收的模拟信号数据进行放大；
AD芯片，用于将处理后的模拟信号数据转化为数字信号数据，得到预处理数据，并将预处理数据发送至FPGA芯片；
LVDS，用于将接收的FPGA芯片中的预处理数据转送至信号交互子系统。
以上的信号采集子系统完成多路通道声学信号同步采样，放大，滤波，实时增益控制TVG(Time Varied Gain，TVG)，预处理和数据传输。
所述的信号交互子系统包含：
命令接口，用于接收信号采集子系统和嵌入式GPU信号处理子系统发来的命令，并将该些命令传送至FPGA芯片；
多组LVDS，用于FPGA芯片同步接收多个信号采集子系统发送的预处理数据；
FPGA芯片，FPGA芯片根据信号采集子系统发来的命令控制多组LVDS接口接收预处理数据，并对预处理数据进行同步缓存、整理与打包，然后根据嵌入式GPU信号处理子系统发来的命令将预处理数据转送至PCIe总线；
PCIe总线，用于FPGA芯片将接收的预处理数据发送至嵌入式GPU信号处理子系统。
以上的信号交互子系统实现多组信号采集子系统与信号处理子系统进行高带宽数据交换和命令控制，完成信号处理子系统同步接收多组信号采集子系统的预处理数据。
所述的嵌入式GPU信号处理子系统包括：
命令接口，用于嵌入式GPU发送命令至信号交互子系统和信号采集子系统；
PCIe总线，用于接收信号交互子系统发送来的预处理数据，并将该 数据转送至Tegra K1嵌入式GPU处理器；该PCIe总线实现最高20Gbps数据传输速率，满足三维声纳预处理数据传输带宽；
Tegra K1嵌入式GPU处理器，用于控制PCIe总线接收数据，对接收的预处理数据进行计算，得到图像数据，并控制千兆以太网芯片、光纤收发芯片对图像数据的远距离传输，DSI显示接口对图像数据的显示；
发射接口，用于控制声波按一定时序进行发射；
千兆以太网芯片、千兆以太网接口，用于实现对图像数据的远距离传输；
光纤收发芯片、千兆光口，用于通过光纤实现对图像数据的远距离传输；
DSI显示接口，用于将图像数据传输至显示屏，实施显示三维数据；
调试接口，用于接收外部发来对嵌入式GPU信号处理子系统进行调试的命令。
以上的嵌入式GPU信号处理子系统完成了预处理数据接收，三维声纳图像算法的实时计算，图像数据传输和命令控制。
所述的Tegra K1嵌入式GPU处理器拥有OpenGL4.4，OpenGL ES 3.1和CUDA等特性，具有高性能的图像并行处理能力，实现三维声纳图像算法的实时处理；丰富的高速数据互连接口，实现大规模声学信号巨大数据吞吐量；优化的开普勒架构GPU，实现了低功耗，最终，使得Tegra K1嵌入式GPU处理器在低功耗下，实现三维声学成像高速率数据传输与图像算法高效计算。
本发明以Tegra K1嵌入式GPU处理器为核心设计嵌入式平台，发挥Tegra K1嵌入式GPU 3D图像处理性能强，并行计算能力高，高速互连接口丰富，功耗低的特性，结合FPGA管脚丰富、时序控制精确的优点，构 建了嵌入式GPU信号处理子系统，同时，通过信号交互子系统，可实现嵌入式GPU信号处理子系统与多个信号采集子系统高速数据交互，完成信号处理子系统同步接收多组信号采集子系统的预处理数据，整个装置具有强大的数据交互能力和信号实时并行处理能力。
附图说明
图1为本发明实施例三维声学成像实时信号处理装置结构示意图；
图2为本发明实施例嵌入式GPU信号处理子系统结构示意图；
图3为本发明实施例信号交互子系统结构示意图；
图4为本发明实施例信号采集子系统结构示意图。
具体实施方式
为了更为具体地描述本发明，下面结合附图1～4及具体实施方式对本发明的技术方案进行详细说明。
图1所述的是本实施例基于嵌入式处理器的三维声学成像实时信号处理装置的结构示意图，该装置具体包括：嵌入式GPU信号处理子系统100、信号交互子系统200、信号采集子系统300。其中，嵌入式GPU信号处理子系统100包括：千兆以太网接口101和千兆光口102，根据实际工作环境需要，可以任一接口进行图像数据的远距离传输；调试接口103，用于接收外部发来的对嵌入式GPU信号处理子系统100进行调试命令；嵌入式GPU信号处理子系统100与信号交互子系统200通过PCIe总线互连，信号交互子系统200通过多个LVDS 201与多个信号采集子系统300互连，实现多个信号采集子系统300的预处理数据通过信号交互子系统200同步传输至嵌入式GPU信号处理子系统100。嵌入式GPU信号处理子系统100 通过命令接口104与信号交互子系统200和信号采集子系统300进行命令交互，实现多个信号采集子系统300同步采样，实时增益控制，阵列稀疏化采样控制以及代码更新。
本发明装置可根据系统算法计算的需求和计算模型的需要配置不同数量的信号采集子系统300；同时，嵌入式GPU信号处理子系统100通过命令接口可以控制信号采集子系统300中任意采样通道的开启或关闭，具有系统搭建灵活，采样通道动态可配置等特点。
如图2所示的是本实施例嵌入式GPU信号处理子系统100的结构示意图，该子系统包括：Tegra K1嵌入式GPU处理器108、发射接口107、PCIe总线接口106、DSI显示接口105、命令接口104、调试接口103、千兆光口102以及千兆以太网接口101。其中，千兆以太网接口101与TegraK1嵌入式GPU处理器108之间连接有千兆以太网109，千兆光口102与Tegra K1嵌入式GPU处理器108之间连接有光纤收发芯片110。发射接口107控制声波按一定时序进行发射；命令接口104中的START信号控制信号采集子系统300同步采样。Tegra K1嵌入式GPU处理器108通过PCIe总线106接收预处理数据，实现三维声纳图像算法的实时计算，通过DSI显示接口105进行图像数据实时显示，或将图像数据通过光纤收发芯片110与千兆光口102进行远距离传输，图像数据传输至上位机显示。
如图3所示的是信号交互子系统200的结构示意图，该子系统包括：FPGA芯片204、PCle总线203、命令接口202以及多组LVDS接口201。其中，多组LVDS接口201同步接收多组信号采集子系统300的预处理数据，FPGA芯片204对每帧多组预处理数据进行同步缓存、整理与打包，通过PCIe总线203传输至嵌入式GPU信号处理子系统100，实现多组信号采集子系统300与嵌入式GPU信号处理子系统100之间高速数据交互 与数据同步传输。
如图4所示的是本实施例信号采集子系统300的结构示意图，该系统包括：FPGA芯片307、高集成度AD芯片306、程控放大器305、滤波器304、放大器303、可编程开关302、前置连接器301、LVDS接口308以及命令接口309。其中，FPGA芯片307通过命令接口309与嵌入式GPU信号处理子系统100进行命令交互，控制可编程开关302开启或关闭前置连接器301中任意通道，实现阵列稀疏化采样；同时，FPGA芯片307控制程控放大器305实现信号实时增益控制；滤波器304与放大器303完成信号的放大与滤波，高集成度AD芯片306完成多通道信号的模数转换。LVDS接口308将处理后的数据发送至信号交互子系统200。
本实施例基于嵌入式处理器的三维声学成像实时信号处理装置的工作流程如下：
(1)稀疏化参数和TVG参数配置：嵌入式GPU信号处理子系统100通过命令接口104向信号采集子系统300中的FPGA芯片307配置阵列稀疏化采样参数和TVG参数；然后，FPGA芯片307控制可编程开关302实现阵列稀疏化采样，FPGA芯片307控制程控放大器306实现TVG控制。
(2)发射信号：嵌入式GPU信号处理子系统100控制发射接口107按一定时序发射声波，等待回波到达系统后，通过命令接口104中START信号向多个信号采集子系统300下发同步采样命令，实现同步采样控制。
(3)数据采集和预处理：信号采集子系统300接收到START信号后，控制可编程开关302，放大器303、滤波器304、程控放大器305以及AD芯片306开始工作，对采集到的声学回波信号进行放大、滤波以及AD转换，可编程开关302和程控放大器305分别实现阵列稀疏采样和TVG功 能，FPGA芯片307对采样数据进行预处理，如权重系数乘法、傅里叶变换等，然后通过LVDS接口308将预处理数据传输至信号交互子系统200。
(4)数据接收与转发：信号交互子系统200同步接收多组信号采集子系统300的预处理数据，FPGA芯片204对每帧多组预处理数据进行同步缓存、整理与打包，通过PCIe总线203传输至嵌入式GPU信号处理子系统100，实现多组信号采集子系统300与嵌入式GPU信号处理子系统100之间高速数据交互与数据同步传输。
(5)数据的接收、处理、显示以及传输，控制下一次发射：嵌入式GPU信号处理子系统100通过PCIe总线106接收信号交互子系统200传输的预处理数据，Tegra K1嵌入式GPU处理器108实现三维声纳图像算法的实时计算，通过DSI显示接口105进行图像数据实时显示，或将图像数据通过光纤收发芯片110与千兆光口102进行远距离传输，图像数据传输至上位机显示。
以上所述的具体实施方式对本发明的技术方案和有益效果进行了详细说明，应理解的是以上所述仅为本发明的最优选实施例，并不用于限制本发明，凡在本发明的原则范围内所做的任何修改、补充和等同替换等，均应包含在本发明的保护范围之内。

Claims (4)

  1. 一种基于嵌入式处理器的三维声学成像实时信号处理装置，其特征在于，包括：多个信号采集子系统、信号交互子系统、嵌入式GPU信号处理子系统，所述的信号采集系统根据嵌入式GPU信号处理子系统发来的命令采集和接收声学阵列中任意通道的信号数据，并对信号数据进行预处理，然后将预处理数据通过所述的信号交互子系统发送至嵌入式GPU信号处理子系统；所述的嵌入式GPU信号处理子系统对接收的预处理数据进行处理，得到图像数据。
  2. 如权利要求1所述的基于嵌入式处理器的三维声学成像实时信号处理装置，其特征在于，所述的信号采集子系统包括：
    命令接口，用于接收嵌入式GPU信号处理子系统发送的命令，并将该命令输送至FPGA芯片；
    FPGA芯片，用于根据接收的命令控制可编程开关对换能器阵列中任意通道开启或关闭，接收对换能器阵列中部分通道的信号数据经过处理后的预处理数据；并根据预处理数据控制程控放大芯片实现实时增益控制，且将预处理数据发送至LVDS接口；
    可编程开关，用于控制换能器阵列中任意通道开启或关闭，实现三维声学成像换能器阵列稀疏化；
    放大滤波芯片，用于对接收和采集的模拟信号数据进行放大和滤波处理；
    程控放大芯片，用于根据FPGA芯片发来的控制信号进行实时增益，并对接收的模拟信号数据进行放大；
    AD芯片，用于将处理后的模拟信号数据转化为数字信号数据，得到 预处理数据，并将预处理数据发送至FPGA芯片；
    LVDS，用于将接收的FPGA芯片中的预处理数据转送至信号交互子系统。
  3. 如权利要求1所述的基于嵌入式处理器的三维声学成像实时信号处理装置，其特征在于，所述的信号交互子系统包含：
    命令接口，用于接收信号采集子系统和嵌入式GPU信号处理子系统发来的命令，并将该些命令传送至FPGA芯片；
    多组LVDS，用于FPGA芯片同步接收多个信号采集子系统发送的预处理数据；
    FPGA芯片，FPGA芯片根据信号采集子系统发来的命令控制多组LVDS接口接收预处理数据，并对预处理数据进行同步缓存、整理与打包，然后根据嵌入式GPU信号处理子系统发来的命令将预处理数据转送至PCIe总线；
    PCIe总线，用于FPGA芯片将接收的预处理数据发送至嵌入式GPU信号处理子系统。
  4. 如权利要求1所述的基于嵌入式处理器的三维声学成像实时信号处理装置，其特征在于，所述的嵌入式GPU信号处理子系统包括：
    命令接口，用于嵌入式GPU发送命令至信号交互子系统和信号采集子系统；
    PCIe总线，用于接收信号交互子系统发送来的预处理数据，并将该数据转送至Tegra K1嵌入式GPU处理器；该PCIe总线实现最高20Gbps数据传输速率，满足三维声纳预处理数据传输带宽；
    Tegra K1嵌入式GPU处理器，用于控制PCIe总线接收数据，对接收的预处理数据进行计算，得到图像数据，并控制千兆以太网芯片、光纤收 发芯片对图像数据的远距离传输，DSI显示接口对图像数据的显示；
    发射接口，用于控制声波按一定时序进行发射；
    千兆以太网芯片、千兆以太网接口，用于实现对图像数据的远距离传输；
    光纤收发芯片、千兆光口，用于通过光纤实现对图像数据的远距离传输；
    DSI显示接口，用于将图像数据传输至显示屏，实施显示三维数据；
    调试接口，用于接收外部发来对嵌入式GPU信号处理子系统进行调试的命令。
PCT/CN2018/076392 2017-03-01 2018-02-12 一种基于嵌入式处理器的三维声学成像实时信号处理装置 WO2018157736A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/308,401 US11333759B2 (en) 2017-03-01 2018-02-12 Embedded processor-based three-dimensional acoustic imaging real-time signal processing device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710118201.5 2017-03-01
CN201710118201.5A CN106990406B (zh) 2017-03-01 2017-03-01 一种基于嵌入式处理器的三维声学成像实时信号处理装置

Publications (1)

Publication Number Publication Date
WO2018157736A1 true WO2018157736A1 (zh) 2018-09-07

Family

ID=59412120

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/076392 WO2018157736A1 (zh) 2017-03-01 2018-02-12 一种基于嵌入式处理器的三维声学成像实时信号处理装置

Country Status (3)

Country Link
US (1) US11333759B2 (zh)
CN (1) CN106990406B (zh)
WO (1) WO2018157736A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114896194A (zh) * 2022-04-29 2022-08-12 南京熊猫通信科技有限公司 基于fpga和dsp的多路信号采集处理板

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106990406B (zh) * 2017-03-01 2019-06-25 浙江大学 一种基于嵌入式处理器的三维声学成像实时信号处理装置
CN108650470A (zh) * 2018-06-27 2018-10-12 宁波舜宇智能科技有限公司 图像处理系统及图像处理方法
CN111084617A (zh) * 2019-12-25 2020-05-01 杭州航弈生物科技有限责任公司 生物电信号处理系统
CN111722232B (zh) * 2020-05-12 2023-07-11 浙江大学 一种具备三维定位能力的多波束成像声纳实时信号处理装置
CN112416844B (zh) * 2020-11-27 2022-06-21 浙江大学 基于FPGA与GPU的Spike信号检测与分类装置
CN113126069B (zh) * 2021-03-23 2022-07-26 浙江工业大学 一种基于zynq的前视声呐信号处理硬件系统
CN113607346A (zh) * 2021-07-14 2021-11-05 东莞市鑫泰仪器仪表有限公司 一种基于嵌入式处理器的三维声学成像实时信号处理装置
CN114500649A (zh) * 2022-01-25 2022-05-13 许昌许继软件技术有限公司 一种集中计量数据采集方法、装置及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101996146A (zh) * 2009-08-26 2011-03-30 戴尔产品有限公司 多模式处理模块及其使用方法
CN102096069A (zh) * 2010-12-17 2011-06-15 浙江大学 一种相控阵三维声学摄像声纳实时处理系统和方法
CN102918466A (zh) * 2010-04-01 2013-02-06 视瑞尔技术公司 用于在全息系统中编码包含透明物体的三维场景的方法和装置
JP2016209512A (ja) * 2015-07-23 2016-12-15 株式会社三共 遊技機
CN106990406A (zh) * 2017-03-01 2017-07-28 浙江大学 一种基于嵌入式处理器的三维声学成像实时信号处理装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6852081B2 (en) * 2003-03-13 2005-02-08 Siemens Medical Solutions Usa, Inc. Volume rendering in the acoustic grid methods and systems for ultrasound diagnostic imaging
CN101625412A (zh) * 2009-08-03 2010-01-13 浙江大学 基于多fpga并行处理的海底三维声纳图像成像系统
TWI378255B (en) * 2009-09-30 2012-12-01 Pai Chi Li Ultrasonic image processing system and ultrasonic image processing method thereof
CN102389321B (zh) * 2011-06-23 2013-04-03 深圳市开立科技有限公司 一种快速光声三维成像装置
CL2013000947A1 (es) * 2013-04-08 2014-01-10 Univ De Chile 35 Un dispositivo de ecografia portatil y manual, con control y procesamiento centralizado en el hardware y con salidas de visualizacion y que opera en tiempo real con una alta tasa de refresco en sus imagenes
CN103592650B (zh) * 2013-11-22 2016-04-06 中国船舶重工集团公司第七二六研究所 基于图形处理器的三维声纳成像系统及其三维成像方法
CN105974399B (zh) * 2016-05-09 2018-03-09 浙江大学 一种相控阵三维声学摄像声呐系统的故障检测方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101996146A (zh) * 2009-08-26 2011-03-30 戴尔产品有限公司 多模式处理模块及其使用方法
CN102918466A (zh) * 2010-04-01 2013-02-06 视瑞尔技术公司 用于在全息系统中编码包含透明物体的三维场景的方法和装置
CN102096069A (zh) * 2010-12-17 2011-06-15 浙江大学 一种相控阵三维声学摄像声纳实时处理系统和方法
JP2016209512A (ja) * 2015-07-23 2016-12-15 株式会社三共 遊技機
CN106990406A (zh) * 2017-03-01 2017-07-28 浙江大学 一种基于嵌入式处理器的三维声学成像实时信号处理装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YIN, MINGMING ET AL.: "Study on 3D image sonar based on GPU", TECHNICAL ACOUSTICS, vol. 33, no. 5, pages 54 - 56 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114896194A (zh) * 2022-04-29 2022-08-12 南京熊猫通信科技有限公司 基于fpga和dsp的多路信号采集处理板

Also Published As

Publication number Publication date
US20190196014A1 (en) 2019-06-27
CN106990406B (zh) 2019-06-25
CN106990406A (zh) 2017-07-28
US11333759B2 (en) 2022-05-17

Similar Documents

Publication Publication Date Title
WO2018157736A1 (zh) 一种基于嵌入式处理器的三维声学成像实时信号处理装置
WO2019109824A1 (zh) 一种基于通用雷达前端芯片的毫米波成像安检雷达系统
WO2012079465A1 (zh) 一种相控阵三维声学摄像声纳实时处理系统和方法
CN101625412A (zh) 基于多fpga并行处理的海底三维声纳图像成像系统
CN110477956A (zh) 一种基于超声图像引导的机器人诊断系统的智能扫查方法
CN109946666A (zh) 基于MPSoC的毫米波雷达信号处理系统
CN107071324A (zh) 一种视觉图像处理系统及其设计方法
CN107942284B (zh) 基于二维正交非均匀线阵的水下波达方向估计方法与装置
CN109714586A (zh) 基于zynq的实时双目立体视觉软硬件协同设计方法
CN107766812A (zh) 一种基于MiZ702N的实时人脸检测识别系统
CN205486304U (zh) 低功耗便携式实时图像目标检测与跟踪装置
CN105843166B (zh) 一种特型多自由度自动对接装置及其工作方法
CN202095037U (zh) 一种实时三维声源图像监控系统
CN102697524A (zh) 全聚焦超声成像方法及其在血流成像中的运用
CN111722232B (zh) 一种具备三维定位能力的多波束成像声纳实时信号处理装置
CN104013424A (zh) 一种基于深度信息的超声宽景成像方法
CN110275163B (zh) 一种基于神经网络的毫米波雷达探测目标成像方法
CN103217120A (zh) 一种激光测厚方法及装置
CN105068066A (zh) 一种嵌入式定浮点多波束测深声纳信号采集与处理平台
CN103092219A (zh) 一种fsm远程实时控制时间补偿系统及方法
CN109144092A (zh) 无人机飞行辅助方法、装置及无人机
CN209765035U (zh) 一种阵列雷达数字化实验系统
WO2021135629A1 (zh) 波束合成处理方法、装置、计算机设备和存储介质
CN207135259U (zh) 一种基于虚拟化阵元技术的超声波收发一体换能器
CN205028112U (zh) 一种基于硬件复位的机器人数据采集系统

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18761342

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18761342

Country of ref document: EP

Kind code of ref document: A1