WO2018157736A1 - Dispositif de traitement de signal en temps réel d'imagerie acoustique tridimensionnelle basé sur un processeur intégré - Google Patents

Dispositif de traitement de signal en temps réel d'imagerie acoustique tridimensionnelle basé sur un processeur intégré Download PDF

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Publication number
WO2018157736A1
WO2018157736A1 PCT/CN2018/076392 CN2018076392W WO2018157736A1 WO 2018157736 A1 WO2018157736 A1 WO 2018157736A1 CN 2018076392 W CN2018076392 W CN 2018076392W WO 2018157736 A1 WO2018157736 A1 WO 2018157736A1
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data
signal
subsystem
signal processing
embedded
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PCT/CN2018/076392
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English (en)
Chinese (zh)
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刘雪松
周凡
赵冬冬
陈耀武
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浙江大学
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Priority to US16/308,401 priority Critical patent/US11333759B2/en
Publication of WO2018157736A1 publication Critical patent/WO2018157736A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
    • G01S15/8993—Three dimensional imaging systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
    • G01S15/8909—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration
    • G01S15/8929—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration using a three-dimensional transducer configuration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/56—Display arrangements
    • G01S7/62—Cathode-ray tube displays
    • G01S7/6245—Stereoscopic displays; Three-dimensional displays; Pseudo-three dimensional displays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Definitions

  • the invention belongs to the field of three-dimensional acoustic imaging image processing, and in particular relates to a three-dimensional acoustic imaging real-time signal processing device based on an embedded processor.
  • Phased array three-dimensional acoustic imaging is one of the important innovations in underwater applications in recent years. It has the advantages of high resolution, real-time performance, three-dimensional information of observable targets and moving target recognition. Underwater biology, physics, It plays an increasingly important role in underwater applications such as archaeology, geography and military, and has become a hot topic in current research. Governments, institutions, and academics have conducted research on phased array three-dimensional acoustic acoustic imaging systems. In 2004, the Italian government funded six universities, including the University of Verona, the University of Florence, the University of Genoa, and the University of Milan, to conduct research on low-cost 3D imaging and modeling automation systems. The A3US laboratory led by Professor A.
  • Trucco of the University of Genoa in Italy has conducted in-depth research on sparse array design, real-time beamforming and image processing algorithms for phased array 3D acoustic imaging systems.
  • the British CodaOctopus company has successfully developed phased array three-dimensional acoustic imaging products, and phased array three-dimensional acoustic imaging real-time signal processing related technology has been monopolized by developed countries such as the European Union.
  • the first phased array three-dimensional sonar imaging system developed by China Shipbuilding Industry Corporation No. 715 Research Institute and Zhejiang University Digital Technology and Instrument Research Institute has filled the domestic blank.
  • the system adopts 48 ⁇ 48 road two-dimensional.
  • the planar receiving transducer array has a detection range of 200 meters, an angular resolution of 0.4° and a distance resolution of 2 cm.
  • Professor Sang Fangen from Harbin Institute of Technology based on a 16 ⁇ 8 two-dimensional planar array realized a three-dimensional sonar imaging system for underwater robot vision.
  • Nvidia's new Tegra K1 embedded GPU processor is a 192-core Kepler-based GPU designed to perform complex geometry and numerical calculations with powerful 3D image acceleration and ten times more CPU than CPU Even hundreds of times the floating point calculation performance.
  • Tegra K1 embedded GPU supports the widely used 3D graphics program interfaces OpenGL4.4 and OpenGL ES 3.1, which realizes 3D image processing and display efficiently through hardware acceleration.
  • Tegra K1 is embedded.
  • the GPU has 192 CUDA (Compute Unified Device Architecture) cores with 325GFLOPS super floating-point computing performance, making it ideal for intensive data and massively parallel data computing.
  • the Tegra K1 embedded GPU uses an optimized Kepler architecture to monitor each power supply through a Power Management Unit (PMU) to improve power efficiency and reduce power consumption.
  • PMU Power Management Unit
  • Array sparse sampling means that only the channel of the position of the array element of interest is sampled, which can solve the problem that the full array array of transducers brings high bandwidth, high computational complexity and high power consumption of sampled data. After the array is sparsely sampled, the corresponding weighting factor is multiplied to suppress the sidelobe peak.
  • Field Programmable Gate Array features rich I/O pins, precise timing control, and flexible pin definition.
  • multi-chip FPGA can realize synchronous sampling of large-scale arrays;
  • FPGA pins define pins as multiple sets of LVDS interfaces according to requirements, and realize one main FPGA through multiple sets of LVDS interfaces and interconnect with multiple sub-FPGAs. , complete multi-chip FPGA to the main FPGA high-speed data synchronous transmission.
  • the present invention provides a three-dimensional acoustic imaging real-time signal processing apparatus based on an embedded processor, which effectively solves the problem that the sampling data bandwidth is high, the three-dimensional acoustic imaging algorithm is difficult to realize real-time calculation, and low power consumption and miniaturization conditions are The problem of system development.
  • a three-dimensional acoustic imaging real-time signal processing device based on an embedded processor comprising: a plurality of signal acquisition subsystems, a signal interaction subsystem, an embedded GPU signal processing subsystem, and the signal acquisition system is processed according to an embedded GPU signal
  • the command sent by the subsystem collects and receives signal data of any channel in the acoustic array, and preprocesses the signal data, and then sends the preprocessed data to the embedded GPU signal processing subsystem through the signal interaction subsystem;
  • the embedded GPU signal processing subsystem processes the received pre-processed data to obtain image data.
  • the signal acquisition subsystem includes:
  • a command interface configured to receive a command sent by the embedded GPU signal processing subsystem, and send the command to the FPGA chip
  • the FPGA chip is configured to control the programmable switch to turn on or off any channel in the transducer array according to the received command, and receive the preprocessed data after processing the signal data of the partial channel in the transducer array; and according to the preprocessed data Controlling the program-controlled amplification chip to realize real-time gain control, and transmitting the pre-processed data to the LVDS interface;
  • a programmable switch for controlling whether any channel in the transducer array is turned on or off to achieve thinning of the three-dimensional acoustic imaging transducer array
  • An amplification filter chip for amplifying and filtering the received and collected analog signal data
  • a program-controlled amplification chip for real-time gain according to a control signal sent from the FPGA chip, and amplifying the received analog signal data
  • the AD chip is configured to convert the processed analog signal data into digital signal data, obtain preprocessed data, and send the preprocessed data to the FPGA chip;
  • LVDS for forwarding pre-processed data from the received FPGA chip to the signal interaction subsystem.
  • the above signal acquisition subsystem completes simultaneous sampling, amplification, filtering, real-time gain control (TVG), pre-processing and data transmission of multi-channel acoustic signals.
  • TVG real-time gain control
  • the signal interaction subsystem includes:
  • a command interface for receiving commands sent by the signal acquisition subsystem and the embedded GPU signal processing subsystem, and transmitting the commands to the FPGA chip;
  • the FPGA chip and the FPGA chip control multiple sets of LVDS interfaces to receive pre-processed data according to commands sent by the signal acquisition subsystem, and synchronously cache, sort and package the pre-processed data, and then execute commands according to the embedded GPU signal processing subsystem. Transfer the preprocessed data to the PCIe bus;
  • the PCIe bus is used by the FPGA chip to send the received pre-processed data to the embedded GPU signal processing subsystem.
  • the above signal interaction subsystem implements high-bandwidth data exchange and command control by multiple sets of signal acquisition subsystems and signal processing subsystems, and completes the signal processing subsystem to synchronously receive pre-processed data of multiple sets of signal acquisition subsystems.
  • the embedded GPU signal processing subsystem includes:
  • the PCIe bus is configured to receive pre-processed data sent by the signal interaction subsystem and forward the data to the Tegra K1 embedded GPU processor; the PCIe bus implements a data transmission rate of up to 20 Gbps to satisfy a three-dimensional sonar preprocessed data transmission bandwidth. ;
  • Tegra K1 embedded GPU processor is used to control the PCIe bus to receive data, calculate the received pre-processed data, obtain image data, and control the long-distance transmission of image data by Gigabit Ethernet chip and fiber transceiver chip, DSI display Interface display of image data;
  • a transmitting interface for controlling sound waves to be transmitted at a certain timing
  • Gigabit Ethernet chip Gigabit Ethernet interface, used to achieve long-distance transmission of image data
  • Optical fiber transceiver chip Gigabit optical port, used to realize long-distance transmission of image data through optical fiber;
  • DSI display interface for transmitting image data to the display screen to implement display of three-dimensional data
  • a debug interface for receiving commands sent externally to debug the embedded GPU signal processing subsystem.
  • the above embedded GPU signal processing subsystem completes pre-processing data reception, real-time calculation of three-dimensional sonar image algorithm, image data transmission and command control.
  • the Tegra K1 embedded GPU processor has features such as OpenGL4.4, OpenGL ES 3.1 and CUDA, high-performance image parallel processing capability, real-time processing of 3D sonar image algorithm, and rich high-speed data interconnection interface. Achieve large data throughput for large-scale acoustic signals; optimized Kepler-based GPUs enable low power consumption, and ultimately, enable Tegra K1 embedded GPU processors to achieve high-speed data transmission and imaging of 3D acoustic imaging at low power consumption The algorithm is efficient.
  • the invention designs the embedded platform with the Tegra K1 embedded GPU processor as the core, and exerts the strong performance of the Tegra K1 embedded GPU 3D image processing, high parallel computing capability, rich high-speed interconnect interface, low power consumption, combined with the FPGA pin. Rich and precise timing control, the embedded GPU signal processing subsystem is constructed. At the same time, through the signal interaction subsystem, high-speed data interaction between the embedded GPU signal processing subsystem and multiple signal acquisition subsystems can be realized, and the signal processing is completed. The system synchronously receives pre-processed data of multiple sets of signal acquisition subsystems, and the whole device has powerful data interaction capability and real-time parallel processing capability of signals.
  • FIG. 1 is a schematic structural diagram of a three-dimensional acoustic imaging real-time signal processing apparatus according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an embedded GPU signal processing subsystem according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a signal interaction subsystem according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a signal acquisition subsystem according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a three-dimensional acoustic imaging real-time signal processing apparatus based on an embedded processor according to the embodiment, and the apparatus specifically includes: an embedded GPU signal processing subsystem 100, a signal interaction subsystem 200, and a signal acquisition subsystem. 300.
  • the embedded GPU signal processing subsystem 100 includes: a Gigabit Ethernet interface 101 and a Gigabit optical port 102.
  • remote transmission of image data may be performed by any interface; and the debugging interface 103 is configured to receive Externally sent debug commands to the embedded GPU signal processing subsystem 100; the embedded GPU signal processing subsystem 100 and the signal interaction subsystem 200 are interconnected by a PCIe bus, and the signal interaction subsystem 200 passes through multiple LVDSs 201 and multiple The signal acquisition subsystems 300 are interconnected, and the pre-processed data of the plurality of signal acquisition subsystems 300 is synchronously transmitted to the embedded GPU signal processing subsystem 100 via the signal interaction subsystem 200.
  • the embedded GPU signal processing subsystem 100 performs command interaction with the signal interaction subsystem 200 and the signal acquisition subsystem 300 through the command interface 104 to implement simultaneous sampling of multiple signal acquisition subsystems 300, real-time gain control, array sparse sampling control, and code. Update.
  • the device of the present invention can configure different numbers of signal acquisition subsystems 300 according to the requirements of the system algorithm calculation and the needs of the calculation model; meanwhile, the embedded GPU signal processing subsystem 100 can control any sampling channel in the signal acquisition subsystem 300 through the command interface. It is turned on or off, featuring flexible system construction and dynamic configurability of sampling channels.
  • FIG. 2 is a schematic structural diagram of the embedded GPU signal processing subsystem 100 of the present embodiment.
  • the subsystem includes: a Tegra K1 embedded GPU processor 108, a transmitting interface 107, a PCIe bus interface 106, and a DSI display interface 105.
  • a Gigabit Ethernet 109 is connected between the Gigabit Ethernet interface 101 and the Tegra K1 embedded GPU processor 108, and a fiber transceiver chip 110 is connected between the Gigabit optical port 102 and the Tegra K1 embedded GPU processor 108.
  • the transmit interface 107 controls the sound waves to be transmitted at a certain timing; the START signal in the command interface 104 controls the signal acquisition subsystem 300 to simultaneously sample.
  • the Tegra K1 embedded GPU processor 108 receives pre-processed data through the PCIe bus 106, implements real-time calculation of the three-dimensional sonar image algorithm, performs real-time display of image data through the DSI display interface 105, or passes the image data through the optical transceiver chip 110 and the gigabit.
  • the optical port 102 performs long-distance transmission, and the image data is transmitted to the upper computer for display.
  • FIG. 3 is a schematic structural diagram of a signal interaction subsystem 200.
  • the subsystem includes an FPGA chip 204, a PCle bus 203, a command interface 202, and a plurality of groups of LVDS interfaces 201.
  • the plurality of sets of LVDS interfaces 201 synchronously receive the pre-processed data of the plurality of sets of signal acquisition subsystems 300.
  • the FPGA chip 204 synchronously buffers, organizes, and packs the pre-processed data of each frame, and transmits the signals to the embedded GPU through the PCIe bus 203.
  • the processing subsystem 100 implements high-speed data interaction and data synchronous transmission between the multiple sets of signal acquisition subsystems 300 and the embedded GPU signal processing subsystem 100.
  • FIG. 4 is a schematic structural diagram of the signal acquisition subsystem 300 of the embodiment.
  • the system includes: an FPGA chip 307, a highly integrated AD chip 306, a programmable amplifier 305, a filter 304, an amplifier 303, and a programmable switch 302.
  • the FPGA chip 307 performs command interaction with the embedded GPU signal processing subsystem 100 through the command interface 309, and controls the programmable switch 302 to turn on or off any channel in the pre-connector 301 to implement array sparse sampling; meanwhile, the FPGA chip 307
  • the control program-controlled amplifier 305 implements signal real-time gain control; the filter 304 and the amplifier 303 complete signal amplification and filtering, and the highly integrated AD chip 306 performs analog-to-digital conversion of the multi-channel signal.
  • the LVDS interface 308 sends the processed data to the signal interaction subsystem 200.
  • the embedded GPU signal processing subsystem 100 configures array sparse sampling parameters and TVG parameters to the FPGA chip 307 in the signal acquisition subsystem 300 through the command interface 104; then, the FPGA chip 307 controls The programmable switch 302 implements array sparse sampling, and the FPGA chip 307 controls the programmable amplifier 306 to implement TVG control.
  • the embedded GPU signal processing subsystem 100 controls the transmitting interface 107 to emit sound waves at a certain timing, and waits for the echo to arrive at the system, and then sends a synchronous sampling to the plurality of signal collecting subsystems 300 through the START signal in the command interface 104. Command to achieve simultaneous sampling control.
  • the signal acquisition subsystem 300 controls the programmable switch 302, and the amplifier 303, the filter 304, the programmable amplifier 305, and the AD chip 306 start to work, and the collected acoustic echoes are acquired.
  • the signal is amplified, filtered, and AD converted.
  • the programmable switch 302 and the programmable amplifier 305 respectively implement array sparse sampling and TVG functions, and the FPGA chip 307 performs preprocessing on the sampled data, such as weight coefficient multiplication, Fourier transform, etc., and then passes LVDS.
  • Interface 308 transmits the pre-processed data to signal interaction subsystem 200.
  • the signal interaction subsystem 200 synchronously receives the pre-processed data of the plurality of sets of signal acquisition subsystems 300, and the FPGA chip 204 synchronously buffers, organizes, and packs the multiple sets of pre-processed data for each frame through the PCIe bus 203.
  • the method is transmitted to the embedded GPU signal processing subsystem 100 to implement high-speed data interaction and data synchronous transmission between the multiple sets of signal acquisition subsystems 300 and the embedded GPU signal processing subsystem 100.
  • the embedded GPU signal processing subsystem 100 receives the preprocessed data transmitted by the signal interaction subsystem 200 through the PCIe bus 106, and the Tegra K1 embedded GPU processor 108 The real-time calculation of the three-dimensional sonar image algorithm is realized, the image data is displayed in real time through the DSI display interface 105, or the image data is transmitted remotely through the optical transceiver chip 110 and the gigabit optical port 102, and the image data is transmitted to the upper computer for display.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • General Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
  • Image Processing (AREA)

Abstract

L'invention concerne un dispositif de traitement de signal en temps réel d'imagerie acoustique tridimensionnelle basé sur un processeur intégré. Le système est d'une conception modulaire et comprend un sous-système de traitement de signal d'unité de traitement graphique (GPU) intégré (100), un sous-système d'interaction de signal (200) et des sous-systèmes d'acquisition de signal (300). Le sous-système de traitement de signal GPU intégré (100) utilise un processeur GPU intégré Tegra K1 (108) en tant que cœur. Le processeur GPU intégré Tegra K1 (108) a les caractéristiques d'OpenGL4.4, OpenGL ES 3.1 et CUDA, a une capacité de traitement parallèle d'image haute performance et un grand nombre d'interfaces d'interconnexion de données à grande vitesse, et convient à la transmission de données à grande vitesse d'un dispositif de traitement de signal en temps réel d'imagerie acoustique tridimensionnelle et au calcul efficace d'un algorithme d'image. Par ailleurs, au moyen du sous-système d'interaction de signal (200), une interaction de données à grande vitesse peut être mise en œuvre entre le sous-système de traitement de signal de GPU intégré (100) et la pluralité de sous-systèmes d'acquisition de signal (300), et l'ensemble du dispositif a des capacités d'interaction de données puissantes et des capacités de traitement de signal parallèle en temps réel.
PCT/CN2018/076392 2017-03-01 2018-02-12 Dispositif de traitement de signal en temps réel d'imagerie acoustique tridimensionnelle basé sur un processeur intégré WO2018157736A1 (fr)

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