WO2018157589A1 - 反相控制电路、其驱动方法、显示面板及显示装置 - Google Patents
反相控制电路、其驱动方法、显示面板及显示装置 Download PDFInfo
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- WO2018157589A1 WO2018157589A1 PCT/CN2017/103036 CN2017103036W WO2018157589A1 WO 2018157589 A1 WO2018157589 A1 WO 2018157589A1 CN 2017103036 W CN2017103036 W CN 2017103036W WO 2018157589 A1 WO2018157589 A1 WO 2018157589A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to an inverter control circuit, a driving method thereof, a display panel, and a display device.
- the Gate Driver on Array (GOA) technology integrates a Thin Film Transistor (TFT) gate drive circuit on the array substrate of the display panel to form a scan drive for the display panel, thereby eliminating the need for
- TFT Thin Film Transistor
- the gate driving circuit of the GOA needs to drive the clock signal with high and low potentials to switch back and forth according to a certain period, and as the complexity of the gate driving circuit of the GOA increases, the required clock signal also increases correspondingly, which easily causes coupling.
- the fluctuation of the voltage causes the display panel to be abnormal, such as Aging horizontal stripes.
- an embodiment of the present disclosure provides an inverting control circuit, including: an input circuit, a switching control circuit, a first output circuit, and a second output circuit;
- the input circuit is respectively connected to the input signal end, the reference signal end, the first node and the second node; the input circuit is configured to respectively provide the signal of the reference signal end to the signal under the control of the input signal end a first node and the second node;
- the switching control circuit is respectively connected to the first switching control signal end, the second switching control signal end, the first node, and the second node; the switching control circuit is configured to be at the first switching control signal Providing, by the terminal, the signal of the first switching control signal end to the first node, and providing the signal of the second switching control signal end to the second node under the control of the second switching control signal end;
- the first output circuit is respectively connected to the input signal end, the reference signal end and an inverted signal output end of the inverting control circuit; the first output circuit is configured to be controlled at the input signal end And providing a signal of the reference signal end to the inverted signal output end;
- the second output circuit is respectively connected to the first switching control signal end, the second switching control signal end, the first node, the second node, and the inverted signal output end;
- the second output circuit is configured to provide a signal of the first switching control signal end to the inverted signal output terminal under the control of the signal of the first node, under the control of the signal of the second node A signal of the second switching control signal terminal is supplied to the inverted signal output terminal.
- the switching control circuit includes: a first switching transistor and a second switching transistor; wherein
- the control pole of the first switching transistor and its first pole are both connected to the first switching control signal end, and the second pole is connected to the first node;
- the control pole of the second switching transistor and its first pole are both connected to the second switching control signal end, and the second pole is connected to the second node.
- the input circuit includes: a third switching transistor and a fourth switching transistor; wherein
- a control pole of the third switching transistor is connected to the input signal end, a first pole is connected to the reference signal end, and a second pole is connected to the first node;
- a control pole of the fourth switching transistor is connected to the input signal terminal, and the first pole and the reference The test signal ends are connected, and the second pole is connected to the second node.
- the first output circuit includes: a fifth switching transistor; wherein
- the control pole of the fifth switching transistor is connected to the input signal terminal, the first pole is connected to the reference signal end, and the second pole is connected to the inverted signal output end.
- the second output circuit includes: a sixth switching transistor and a seventh switching transistor; wherein
- a control pole of the sixth switching transistor is connected to the first node, a first pole is connected to the first switching control signal end, and a second pole is connected to the inverted signal output end;
- the control electrode of the seventh switching transistor is connected to the second node, the first pole is connected to the second switching control signal end, and the second pole is connected to the inverted signal output end.
- the embodiment of the present disclosure further provides a driving method of the foregoing reverse control circuit, including:
- the input circuit supplies signals of the reference signal end to the first node and the second node respectively under control of the input signal end;
- the first output circuit is at the input signal Providing a signal of the reference signal end to the inverted signal output end under the control of the terminal;
- the switching control circuit provides a signal of the first switching control signal end to the first node under control of the first switching control signal end, and the second output circuit is at the first Providing a signal of the first switching control signal end to the inverted signal output terminal under control of a signal of the node; or, in a second phase, the switching control circuit is under the control of the second switching control signal end a signal of the second switching control signal end is provided to the second node, and the second output circuit provides a signal of the second switching control signal end to the inversion under the control of a signal of the second node Signal output.
- an embodiment of the present disclosure further provides another inverting control circuit, including: an input circuit, a switching control circuit, a first output circuit, and a second output circuit;
- the input circuit is respectively connected to the input signal end, the reference signal end and the first node; the input circuit is configured to provide the signal of the reference signal end to the first node under the control of the input signal end;
- the switching control circuit is respectively connected to the switching control signal end and the first node; the switching control circuit is configured to provide the signal of the switching control signal end to the first under the control of the switching control signal end node;
- the first output circuit is respectively connected to the input signal end, the reference signal end and an inverted signal output end of the inverting control circuit; the first output circuit is configured to be controlled at the input signal end And providing a signal of the reference signal end to the inverted signal output end;
- the second output circuit is respectively connected to the switching control signal end, the first node, and the inverted signal output end; the second output circuit is configured to be under the control of the signal of the first node And supplying a signal of the switching control signal end to the inverted signal output end.
- the switching control circuit includes: a first switching transistor; wherein
- the control pole of the first switching transistor and its first pole are both connected to the switching control signal end, and the second pole is connected to the first node.
- the input circuit includes: a second switching transistor; wherein
- the control electrode of the second switching transistor is connected to the input signal end, the first pole is connected to the reference signal end, and the second pole is connected to the first node.
- the first output circuit comprises: a third switching transistor; wherein
- the control electrode of the third switching transistor is connected to the input signal terminal, the first pole is connected to the reference signal end, and the second pole is connected to the inverted signal output end.
- the second output circuit includes: a fourth switching transistor; wherein
- the control electrode of the fourth switching transistor is connected to the first node, the first pole is connected to the switching control signal end, and the second pole is connected to the inverted signal output end.
- the embodiment of the present disclosure further provides a driving method of the foregoing reverse control circuit, including:
- the input circuit provides a signal of the reference signal terminal to the first node under control of the input signal terminal;
- the first output circuit uses the reference under the control of the input signal terminal a signal at the signal end is supplied to the inverted signal output terminal;
- the switching control circuit provides a signal of the switching control signal end to the first node under control of the switching control signal end; the second output circuit is at the first The signal of the switching control signal terminal is supplied to the inverted signal output terminal under the control of the signal of the node.
- an embodiment of the present disclosure further provides a display panel including at least one clock signal line, further comprising: an inverted clock signal line corresponding to each of the clock signal lines, and each The clock signal line corresponds to any one of the above-mentioned inverting control circuits provided by the embodiments of the present disclosure;
- the input signal end of the inverting control circuit is connected to a corresponding clock signal line, and the inverted signal output end is connected to a corresponding inverted clock signal line.
- the display panel includes at most three clock signal lines.
- the display panel comprises three clock signal lines.
- each of the clock signal lines, each of the inverted clock signal lines, and each of the inverting control circuits are located in a non-display area of the display panel.
- an embodiment of the present disclosure provides a display device including any of the above display panels provided by the embodiments of the present disclosure.
- FIG. 1 is a schematic diagram of a clock signal used by a GOA gate driving circuit in the related art
- FIG. 2 is a schematic structural diagram of an inversion control circuit according to an embodiment of the present disclosure
- FIG. 3a is a schematic structural diagram of the inverting control circuit shown in FIG. 2;
- Figure 3b is a second structural schematic diagram of the inverting control circuit shown in Figure 2;
- FIG. 4 is another schematic structural diagram of an inversion control circuit according to an embodiment of the present disclosure.
- Figure 5a is a schematic structural diagram of the inverting control circuit shown in Figure 4.
- Figure 5b is a second structural schematic diagram of the inverting control circuit shown in Figure 4.
- Figure 6a is a timing diagram of the inverting control circuit shown in Figure 3a;
- Figure 6b is a timing diagram of the inverting control circuit shown in Figure 5a;
- FIG. 7 is a flow chart of a driving method of the inverting control circuit shown in FIG. 2;
- FIG. 8 is a second flowchart of the driving method of the inverting control circuit shown in FIG. 2;
- FIG. 9 is a flowchart of a driving method of the inverting control circuit shown in FIG. 4;
- FIG. 10a is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
- FIG. 10b is a second schematic structural diagram of a display panel according to an embodiment of the present disclosure.
- FIG. 11 is a schematic diagram of signals in a clock signal line and an inverted clock signal line in a display panel according to an embodiment of the present disclosure
- FIG. 12 is a schematic structural diagram of a shift register unit in a display panel according to an embodiment of the present disclosure.
- the gate driving circuit of the GOA takes an example of inputting six clock signals to the gate driving circuit.
- the clock signal CLK1 and the clock signal CLK4 are mutually The anti-signal
- the clock signal CLK2 and the clock signal CLK5 are reciprocal signals
- the clock signal CLK3 and the clock signal CLK6 are reciprocal signals; wherein each clock signal is a low potential signal before the first high potential, that is, at this time
- the above three sets of clock signals in the segment are not mutually reciprocal, so that fluctuations in the coupling voltage are easily caused, causing display abnormality of the display panel, such as Aging horizontal stripes.
- An embodiment of the present disclosure provides an inverting control circuit, as shown in FIG. 2, including: an input circuit 11, a switching control circuit 12, a first output circuit 13, and a second output circuit 14;
- the input circuit 11 is respectively connected to the input signal terminal Input, the reference signal terminal Vref, the first node A and the second node B; the input circuit 11 is configured to respectively provide the signal of the reference signal terminal Vref under the control of the input signal terminal Input First node A and second node B;
- the switching control circuit 12 is respectively connected to the first switching control signal terminal CS1, the second switching control signal terminal CS2, the first node A and the second node B; the switching control circuit 12 is configured to be in the first switching The signal of the first switching control signal terminal CS1 is supplied to the first node A under the control of the control signal terminal CS1, and the signal of the second switching control signal terminal CS2 is provided to the second node under the control of the second switching control signal terminal CS2. B;
- the first output circuit 13 is respectively connected to the input signal terminal Input, the reference signal terminal Vref and the inverted signal output terminal Output of the inverting control circuit; the first output circuit 13 is configured to connect the reference signal terminal under the control of the input signal terminal Input The signal of Vref is supplied to the inverted signal output terminal Output;
- the second output circuit 14 is respectively connected to the first switching control signal terminal CS1, the second switching control signal terminal CS2, the first node A, the second node B, and the inverted signal output terminal Output; the second output circuit 14 is configured to be
- the signal of the first switching control signal terminal CS1 is supplied to the inverted signal output terminal Output under the control of the signal of the first node A, and the signal of the second switching control signal terminal CS2 is provided under the control of the signal of the second node B. Inverting signal output Output.
- the inverting control circuit provided by the embodiment of the present disclosure can make the potential of the input signal terminal Input and the potential of the inverted signal output terminal opposite, such as completely opposite or substantially opposite, by the mutual cooperation of the above four circuits, thereby
- one clock signal is used as an input signal
- the output signal is a clock signal with opposite phases.
- the inverting control circuit when the potential of the effective pulse signal of the input signal terminal Input is high, the potential of the reference signal terminal Vref is low; at the input signal terminal, the effective pulse signal is When the potential is low, the potential of the reference signal terminal Vref is high.
- the potential of the first switching control signal terminal CS1 is opposite potential within each adjacent preset interval duration; the potential of the first switching control signal terminal CS1 and the second The potential of the switching control signal terminal CS2 is an opposite potential; wherein the preset interval duration is a time for displaying N frames; N is an integer greater than or equal to 1.
- the potential of the first switching control signal terminal CS1 is high (or low), and the potential of the second switching control signal terminal CS2 is low (or high); at the next preset During the interval duration, the potential of the first switching control signal terminal CS1 is low (or high), and the potential of the second switching control signal terminal CS2 is high (or low); and after the next preset interval duration, A switching control signal terminal CS1 and a second switching control signal terminal CS2 are repeatedly executed. The process of the current preset interval duration and the next preset interval duration until the display is stopped.
- the preset interval duration is a time for displaying N frames; N is an integer greater than or equal to 1. In the actual application, for example, the preset interval duration may be 2 to 4 s. Of course, the specific time of the preset interval duration needs to be determined according to the actual application environment, which is not limited herein.
- the input circuit 11 may include: a third switching transistor M3 and a fourth switching transistor M4;
- the control electrode of the third switching transistor M3 is connected to the input signal terminal Input, the first pole is connected to the reference signal terminal Vref, and the second pole is connected to the first node A;
- the control electrode of the fourth switching transistor M4 is connected to the input signal terminal Input, the first pole is connected to the reference signal terminal Vref, and the second pole is connected to the second node B.
- the third switching transistor M3 and the fourth switching transistor M4 may be N-type transistors.
- the third switching transistor M3 is in an on state when the effective pulse signal of the input signal terminal Input is high, and supplies the low potential of the reference signal terminal Vref to the first node A.
- the fourth switching transistor M4 is in an on state when the effective pulse signal of the input signal terminal Input is high, and supplies the low potential of the reference signal terminal Vref to the second node B.
- the third switching transistor M3 and the fourth switching transistor M4 may also be P-type transistors.
- the third switching transistor M3 is in an on state when the effective pulse signal of the input signal terminal Input is low, and supplies the high potential of the reference signal terminal Vref to the first node A.
- the fourth switching transistor M4 is in an on state when the effective pulse signal of the input signal terminal Input is low, and supplies the high potential of the reference signal terminal Vref to the second node B.
- the switching control circuit 12 may include: a first switching transistor M1 and a second switching transistor M2;
- the control pole and the first pole of the first switching transistor M1 are both connected to the first switching control signal terminal CS1, and the second pole is connected to the first node A;
- the control pole of the second switching transistor M2 and its first pole are both opposite to the second switching control signal terminal CS2 Connected, the second pole is connected to the second node B.
- the first switching transistor M1 and the second switching transistor M2 may be N-type transistors.
- the first switching transistor M1 is in an on state when the first switching control signal terminal CS1 is at a high potential, and supplies the high potential of the first switching control signal terminal CS1 to the first node A.
- the second switching transistor M2 is in an on state when the second switching control signal terminal CS2 is at a high potential, and supplies the high potential of the second switching control signal terminal CS2 to the second node B.
- the first switching transistor M1 and the second switching transistor M2 may also be P-type transistors.
- the first switching transistor M1 is in an on state when the first switching control signal terminal CS1 is at a low potential, and supplies the low potential of the first switching control signal terminal CS1 to the first node A.
- the second switching transistor M2 is in an on state when the second switching control signal terminal CS2 is at a low potential, and supplies a low potential of the second switching control signal terminal CS2 to the second node B.
- the first switching transistor M1 and the second switching transistor M2 can be alternately turned on instead of being always in The Stress state reduces the influence of Stress on the electrical performance of the first switching transistor M1 and the second switching transistor M2, thereby improving reliability.
- the channel width to length ratio of the third switching transistor M3 is set to be larger than the channel width to length ratio of the first switching transistor M1 at the time of process preparation, such setting
- the third switching transistor M3 supplies the signal of the reference signal terminal Vref to the first node A under the control of the input signal terminal Input to be greater than the first switching transistor M1 at the first switching control.
- the signal of the first switching control signal terminal CS1 is supplied to the first node A1 under the control of the signal terminal CS1, thereby ensuring that the potential of the first node A is opposite to the potential when the input signal terminal Input is a valid pulse signal.
- the channel width to length ratio of the fourth switching transistor M4 is set to be larger than the channel width to length ratio of the second switching transistor M2 at the time of process preparation, such that When the input signal terminal Input is a valid pulse signal, the fourth switching transistor M4 is at the input signal
- the signal of the reference signal terminal Vref is supplied to the second node B under the control of the terminal input
- the signal of the second switching control signal terminal CS2 is supplied to the second switching transistor M2 under the control of the second switching control signal terminal CS2.
- the rate of the two nodes B thereby ensuring that the potential of the second node B is opposite to the potential when the input signal terminal Input is a valid pulse signal.
- the channel width to length ratio of the first switching transistor M1 and the channel width to length ratio of the third switching transistor M3 may satisfy a 1:2 relationship
- the second switching transistor M2 The channel width to length ratio and the channel width to length ratio of the fourth switching transistor M4 can satisfy a 1:2 relationship.
- the channel width to length ratio of the first switching transistor M1 and the third switching transistor M3 The relationship between the channel width-to-length ratio may be other proportional relationship, and the relationship between the channel width-to-length ratio of the second switching transistor M2 and the channel width-to-length ratio of the fourth switching transistor M4 may be other proportional relationship. This is not limited.
- the first output circuit 13 may include: a fifth switching transistor M5;
- the control electrode of the fifth switching transistor M5 is connected to the input signal terminal Input, the first pole is connected to the reference signal terminal Vref, and the second pole is connected to the inverted signal output terminal Output.
- the fifth switching transistor M5 may be an N-type transistor. At this time, the fifth switching transistor M5 is in an on state when the effective pulse signal of the input signal terminal Input is high, and supplies the low potential of the reference signal terminal Vref to the inverted signal output terminal Output.
- the fifth switching transistor M5 may also be a P-type transistor. At this time, the fifth switching transistor M5 is in an on state when the effective pulse signal of the input signal terminal Input is low, and supplies the high potential of the reference signal terminal Vref to the inverted signal output terminal Output.
- the second output circuit 14 may include: a sixth switching transistor M6 and a seventh switching transistor M7;
- the control pole of the sixth switching transistor M6 is connected to the first node A, the first pole is connected to the first switching control signal terminal CS1, and the second pole is connected to the inverted signal output terminal Output;
- the control electrode of the seventh switching transistor M7 is connected to the second node B, the first pole is connected to the second switching control signal terminal CS2, and the second pole is connected to the inverted signal output terminal Output.
- the sixth switching transistor M6 and the seventh switching transistor M7 may be N-type transistors.
- the sixth switching transistor M6 is in an on state when the first node A is at a high potential, and supplies a signal of the first switching control signal terminal CS1 to the inverted signal output terminal Output.
- the seventh switching transistor M7 is in an on state when the second node B is at a high potential, and supplies a signal of the second switching control signal terminal CS2 to the inverted signal output terminal Output.
- the sixth switching transistor M6 and the seventh switching transistor M7 may also be P-type transistors.
- the sixth switching transistor M6 is in an on state when the first node A is at a low potential, and supplies a signal of the first switching control signal terminal CS1 to the inverted signal output terminal Output.
- the seventh switching transistor M7 is in an on state when the second node B is at a potential, and supplies a signal of the second switching control signal terminal CS2 to the inverted signal output terminal Output.
- the channel width to length ratio of the fifth switching transistor M5 is set to be larger than the channel width to length ratio of the sixth switching transistor M6 at the time of process preparation, such that When the input signal terminal Input is a valid pulse signal, the fifth switching transistor M5 supplies the signal of the reference signal terminal Vref to the inverted signal output terminal Output under the control of the input signal terminal Input to be greater than the sixth switching transistor M6 at the first node. Under the control of A, the signal of the first switching control signal terminal CS1 is supplied to the output of the inverted signal output terminal, thereby ensuring that the potential of the inverted signal output terminal Output is opposite to the potential when the input signal terminal Input is the effective pulse signal.
- the channel width-to-length ratio of the fifth switching transistor M5 is set to be larger than the channel width-to-length ratio of the seventh switching transistor M7 at the time of process preparation, such that When the input signal terminal Input is a valid pulse signal, the fifth switching transistor M5 supplies the signal of the reference signal terminal Vref to the inverted signal output terminal Output under the control of the input signal terminal Input to be greater than the seventh switching transistor M7 at the second node.
- the signal of the second switching control signal terminal CS2 is supplied to the output of the inverted signal output terminal, thereby ensuring that the potential of the inverted signal output terminal Output is opposite to the potential when the input signal terminal Input is the effective pulse signal.
- the channel of the sixth switching transistor M6 The width-to-length ratio and the channel width-to-length ratio of the fifth switching transistor M5 can satisfy a 1:6 relationship, and the channel width-to-length ratio of the seventh switching transistor M7 and the channel width-to-length ratio of the fifth switching transistor M5 can satisfy 1: 6, of course, in practical applications, the relationship between the channel width-to-length ratio of the sixth switching transistor M6 and the channel width-to-length ratio of the fifth switching transistor M5 may be other proportional relationship, and the seventh switching transistor M7 The relationship between the channel width-to-length ratio and the channel width-to-length ratio of the fifth switching transistor M5 may be other proportional relationships, which is not limited herein.
- each circuit in the inverting control circuit provided by the embodiment of the present disclosure.
- the specific structure of each circuit is not limited to the above structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. It is not limited here.
- all switching transistors generally use switching transistors of the same material.
- all of the switching transistors may be N-type transistors, and the N-type transistor is turned on under a high potential, and is turned off under a low potential. At this time, the potential of the effective pulse signal of the input signal terminal Input is high. Potential.
- all of the switching transistors may also be P-type transistors. The P-type transistor is turned off under a high potential, and is turned on under a low potential, and the potential of the effective pulse signal of the input signal terminal is low. It is not limited here.
- the switching transistor mentioned in the above-mentioned embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited herein.
- TFT thin film transistor
- MOS metal oxide semiconductor field effect transistor
- the control of the switching transistors is extremely gated, and the first pole and the second pole can use the first pole as the source or the drain of the switching transistor and the second pole according to the type of the switching transistor and the signal of the signal terminal.
- the drain or source of the switching transistor is not limited herein.
- the preset interval duration is an example of displaying one frame time.
- a high potential signal is indicated by 1, and 0 represents a low potential signal, wherein 1 and 0 represent their logic potentials, which are only for better explanation of the operation of the inverting control circuit provided by the embodiment of the present disclosure, and The potential applied to the gate of each switching transistor is not specifically implemented.
- all of the switching transistors in the inverting control circuit are N-type transistors; the corresponding input-output timing diagram is as shown in FIG. 6a, specifically, the input as shown in FIG. 6a is mainly selected.
- the work process of the T11 phase and the T12 phase is repeated until the next step.
- the frame display time begins.
- a dark state Blacking Time is generally set between adjacent display frames. Therefore, the potential of the first switching control signal terminal CS1 and the potential of the second switching control signal terminal CS2 can be Both switch during the Blacking Time phase of the dark state.
- the inverting control circuit provided by the embodiment of the present disclosure may make the voltage of the inverted signal output terminal opposite to the potential of the input signal terminal Input by only a plurality of switching transistors, for example, completely opposite or substantially completely opposite, and related art.
- the inverting control circuit formed by combining the capacitor and the transistor since the occupied space of the switching transistor is smaller than the occupation of the capacitor, for example, the occupied space of the three transistors in the embodiment of the present disclosure is compared with the two capacitors in the related art.
- the occupied space is also small, so that the space occupied area can be reduced.
- the embodiment of the present disclosure further provides a driving method of the foregoing inversion control circuit provided by the embodiment of the present disclosure. As shown in FIG. 7, the method includes: a first stage and a second stage;
- the input circuit supplies the signal of the reference signal end to the first node and the second node respectively under the control of the input signal end; the first output circuit provides the signal of the reference signal end to the inversion under the control of the input signal end.
- the switching control circuit provides the signal of the first switching control signal end to the first node under the control of the first switching control signal end; the second output circuit performs the first switching under the control of the signal of the first node.
- the signal at the control signal terminal is supplied to the inverted signal output terminal.
- FIG. 8 comprising: a first phase and a second phase;
- the input circuit supplies the signal of the reference signal end to the first node and the second node respectively under the control of the input signal end; the first output circuit provides the signal of the reference signal end to the inversion under the control of the input signal end.
- the switching control circuit provides the signal of the second switching control signal end to the second node under the control of the second switching control signal end; the second output circuit switches the second switching under the control of the signal of the second node.
- the signal at the control signal terminal is supplied to the inverted signal output terminal.
- the embodiment of the present disclosure further provides another inverting control circuit, as shown in FIG. 4, including: an input circuit 21, a switching control circuit 22, a first output circuit 23, and a second output circuit 24;
- the input circuit 21 is respectively connected to the input signal terminal Input, the reference signal terminal Vref and the first node A; the input circuit 21 is configured to connect the reference signal terminal Vref under the control of the input signal terminal Input Number is provided to the first node A;
- the switching control circuit 22 is connected to the switching control signal terminal CS and the first node A; the switching control circuit 22 is configured to provide the signal of the switching control signal terminal CS to the first node A under the control of the switching control signal terminal CS;
- the first output circuit 23 is respectively connected to the input signal terminal Input, the reference signal terminal Vref and the inverted signal output terminal Output of the inverting control circuit; the first output circuit 23 is configured to connect the reference signal terminal under the control of the input signal terminal Input The signal of Vref is supplied to the inverted signal output terminal Output;
- the second output circuit 24 is respectively connected to the switching control signal terminal CS, the first node A and the inverted signal output terminal Output; the second output circuit 24 is configured to switch the control signal terminal CS under the control of the signal of the first node A The signal is supplied to the inverted signal output Output.
- the above-mentioned inverting control circuit provided by the embodiment of the present disclosure can make the potential of the input signal terminal Input and the potential of the inverted signal output terminal opposite, such as completely opposite or substantially opposite, by the mutual cooperation of the above four circuits, thereby
- the inverting control circuit is applied to the display panel, one clock signal is used as an input signal, and the output signal is a clock signal with opposite phases.
- the inverting control circuit when the potential of the effective pulse signal of the input signal terminal Input is high, the potential of the reference signal terminal Vref is low, and the potential of the switching control signal terminal CS is high.
- the potential of the effective pulse signal of the input signal terminal Input is low, the potential of the reference signal terminal Vref is at a high potential, and the potential of the switching control signal terminal CS is low.
- the input circuit 21 may specifically include: a second switching transistor M2;
- the control electrode of the second switching transistor M2 is connected to the input signal terminal Input, the first pole is connected to the reference signal terminal Vref, and the second pole is connected to the first node A.
- the second switching transistor M2 may be an N-type transistor. At this time, the second switching transistor M2 is in an on state when the effective pulse signal of the input signal terminal Input is high, and supplies the low potential of the reference signal terminal Vref to the first node A.
- the second switching crystal The body tube M2 can also be a P-type transistor.
- the second switching transistor M2 is in an on state when the effective pulse signal of the input signal terminal Input is high, and supplies the signal of the reference signal terminal Vref to the first node A.
- the switching control circuit 22 may include: a first switching transistor M1;
- the control pole and the first pole of the first switching transistor M1 are both connected to the switching control signal terminal CS, and the second pole is connected to the first node A.
- the first switching transistor M1 may be an N-type transistor. At this time, the first switching transistor M1 is in an on state when the switching control signal terminal CS is at a high potential, and supplies the high potential of the switching control signal terminal CS to the first node A.
- the first switching transistor M1 may also be a P-type transistor. At this time, the first switching transistor M1 is in an on state when the switching control signal terminal CS is at a high potential, and supplies the high potential of the switching control signal terminal CS to the first node A.
- the channel width to length ratio of the second switching transistor M2 is set to be larger than the channel width to length ratio of the first switching transistor M1 at the time of process preparation, such that When the input signal terminal Input is a valid pulse signal, the second switching transistor M2 supplies the signal of the reference signal terminal Vref to the first node A under the control of the input signal terminal Input to be greater than the first switching transistor M1 at the switching control signal terminal CS.
- the rate at which the signal of the switching control signal terminal CS is supplied to the first node A is controlled under the control, thereby ensuring that the potential of the first node A is opposite to the potential when the input signal terminal Input is a valid pulse signal.
- the channel width to length ratio of the first switching transistor M1 and the channel width to length ratio of the second switching transistor M2 may satisfy a 1:2 relationship.
- the relationship between the channel width-to-length ratio of the first switching transistor M1 and the channel width-to-length ratio of the second switching transistor M2 may be other proportional relationship, which is not limited herein.
- the first output circuit 23 may include: a third switching transistor M3;
- the control electrode of the third switching transistor M3 is connected to the input signal terminal Input, the first pole and the reference signal The terminal Vref is connected, and the second pole is connected to the inverted signal output terminal Output.
- the third switching transistor M3 may be an N-type transistor. At this time, the third switching transistor M3 is in an on state when the effective pulse signal of the input signal terminal Input is high, and supplies the signal of the reference signal terminal Vref to the inverted signal output terminal Output.
- the third switching transistor M3 may also be a P-type transistor. At this time, the third switching transistor M3 is in an on state when the effective pulse signal of the input signal terminal Input is high, and supplies the signal of the reference signal terminal Vref to the inverted signal output terminal Output.
- the second output circuit 24 may include: a fourth switching transistor M4;
- the control electrode of the fourth switching transistor M4 is connected to the first node A, the first pole is connected to the switching control signal terminal CS, and the second pole is connected to the inverted signal output terminal Output.
- the fourth switching transistor M4 may be an N-type transistor. At this time, the fourth switching transistor M4 is in an on state when the first node A is at a high potential, and supplies a signal of the switching control signal terminal CS to the inverted signal output terminal Output.
- the fourth switching transistor M4 may also be a P-type transistor. At this time, the fourth switching transistor M4 is in an on state when the first node A is at a low potential, and supplies a signal of the switching control signal terminal CS to the inverted signal output terminal Output.
- the channel width to length ratio of the third switching transistor M3 is set to be larger than the channel width to length ratio of the fourth switching transistor M4 at the time of process preparation, such that When the input signal terminal Input is a valid pulse signal, the third switching transistor M3 supplies the signal of the reference signal terminal Vref to the inverted signal output terminal Output under the control of the input signal terminal Input to be greater than the fourth switching transistor M4 at the first node. Under the control of A, the signal of the switching control signal terminal CS is supplied to the output of the inverted signal output terminal, thereby ensuring that the potential of the inverted signal output terminal Output is opposite to the potential when the input signal terminal Input is a valid pulse signal.
- the channel width to length ratio of the fourth switching transistor M4 and the channel width to length ratio of the third switching transistor M3 may satisfy a 1:6 relationship.
- the relationship between the channel width-to-length ratio of the fourth switching transistor M4 and the channel width-to-length ratio of the third switching transistor M3 may be other proportional relationship, which is not limited herein.
- all switching transistors generally use switching transistors of the same material.
- all of the switching transistors may be N-type transistors, and the N-type transistor is turned on under a high potential, and is turned off under a low potential. At this time, the potential of the effective pulse signal of the input signal terminal Input is high. Potential.
- all of the switching transistors may also be P-type transistors. The P-type transistor is turned off under a high potential, and is turned on under a low potential, and the potential of the effective pulse signal of the input signal terminal is low. It is not limited here.
- the switching transistor mentioned in the embodiment of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited herein.
- the control of the switching transistors is extremely gated, and the first pole and the second pole can use the first pole as the source or the drain of the switching transistor and the second pole according to the type of the switching transistor and the signal of the signal terminal.
- the drain or source of the switching transistor is not limited herein.
- all the switching transistors in the inverting control circuit are N-type transistors; the corresponding input and output timing diagram is shown in FIG. 6b.
- the display in the input/output timing diagram shown in FIG. 6b is mainly selected. Two stages of T11 and T12 in one frame time T1; the next one shows two stages of T21 and T22 in one frame time T2.
- both the second switching transistor M2 and the third switching transistor M3 are turned on.
- the first switching transistor M1 is turned on and supplies the signal of the high-potential switching control signal terminal CS to the first node A, while the second switching transistor M2 is turned on and the reference signal terminal Vref of the low potential is turned on.
- the signal is supplied to the first node A, and the channel width-to-length ratio of the third switching transistor M3 is larger than the channel width-to-length ratio of the first switching transistor M1, and thus the potential of the first node A is low. Since the potential of the first node A is low, the fourth switching transistor M4 is turned off.
- the inverted signal output terminal Output outputs a low potential signal, that is, opposite to the potential of the input signal terminal Input. .
- the specific working process is basically the same as the working process of the above T11 stage, and will not be described in detail here.
- a dark state Blacking Time is generally set between adjacent display frames.
- the inverting control circuit provided by the embodiment of the present disclosure may make the voltage of the inverted signal output terminal opposite to the potential of the input signal terminal Input by only a plurality of switching transistors, for example, completely opposite or substantially completely opposite, and the related art adopts Inverted control circuit composed of a combination of a capacitor and a transistor Compared with the circuit, since the occupied space of the switching transistor is smaller than the occupation of the capacitor, for example, the occupied space of the three transistors in the embodiment of the present disclosure is smaller than the occupied space of the two capacitors in the related art, thereby reducing the space occupied area. When the embodiment of the present disclosure is applied to a display panel, the narrow bezel design of the display panel is facilitated.
- the embodiment of the present disclosure further provides a driving method of any one of the above-mentioned inverting control circuits provided by the embodiment of the present disclosure. As shown in FIG. 9, the method includes: a first stage and a second stage;
- the input circuit supplies the signal of the reference signal end to the first node under the control of the input signal end;
- the first output circuit supplies the signal of the reference signal end to the inverted signal output end under the control of the input signal end;
- the switching control circuit supplies the signal of the switching control signal end to the first node under the control of the switching control signal end; the second output circuit provides the signal of the switching control signal end to the signal of the first node under the control of the signal of the first node. Inverting signal output.
- the embodiment of the present disclosure further provides a display panel, as shown in FIG. 10a and FIG. 10b, including: at least one clock signal line clk_m (m is an integer greater than or equal to 1 and less than or equal to M; wherein M is a clock signal line The total number of the inverter signal line nclk_m corresponding to each clock signal line clk_m, and any one of the inverting control circuit RP_m provided by the embodiment of the present disclosure corresponding to each clock signal line clk_m;
- the input signal terminal Input of the inverting control circuit RP_m is connected to the corresponding clock signal line clk_m, and the inverted signal output terminal Output is connected to the corresponding inverted clock signal line nclk_m.
- the signal of the corresponding inverted clock signal line nclk_1 is the clock signal CLK4; when the clock signal CLK2 is input to the clock signal line clk_2, the signal of the corresponding inverted clock signal line nclk_2 is the clock signal CLK5; After the clk_3 input clock signal CLK3, the signal of the corresponding inverted clock signal line nclk_3 is the clock signal CLK6, so that the potential of the signal of the clock signal line and the corresponding inverted clock signal line can be opposite, for example, completely opposite or substantially opposite.
- the fluctuation of the overall capacitive coupling voltage of the clock signal can be reduced. And by reversing
- the control circuit can reduce the number of clock signal lines by a factor of two, which can save the Layout space of the border trace.
- a display panel employing GOA technology inputs a scan signal to a gate line in a display panel through a gate driving circuit to turn on a pixel to charge a pixel.
- the gate driving circuits are generally composed of a plurality of cascaded shift register units: GOA1, GOA2, GOA3, ..., and sequentially implemented to the display panel through the shift register units of each stage.
- a scanning signal is input to each of the upper gate lines.
- Each stage of the shift register unit may include a first reference signal terminal VDD1, a second reference signal terminal VDD2, a third reference signal terminal VSS, a clock signal terminal CLK, a cascade signal input terminal IN, and a scan signal output terminal OUT.
- the first reference signal terminal VDD1 of each shift register unit is connected to the same signal line Vdd1 for inputting the first reference signal
- the second reference signal terminal VDD2 of each shift register unit is used for the same strip.
- the signal line Vdd2 input to the second reference signal is connected, and the third reference signal terminal VSS of each stage of the shift register unit is connected to the same signal line Vss for inputting the third reference signal.
- the signal in the signal line Vdd1 and the signal of the first switching control signal terminal CS1 can be set to the same signal, that is, the signal line Vdd1 is connected to the first switching control signal terminal CS1;
- the signal in the signal line Vdd2 and the signal of the second switching control signal terminal CS2 are set to the same signal, that is, the signal line Vdd2 is connected to the second switching control signal terminal CS2;
- the signal in the signal line Vss and the reference signal terminal Vref are The signal is set to the same signal, that is, the signal line Vss is connected to the reference signal terminal Vref.
- the manner of the signal input to the above-mentioned shift register is the same as that of the prior art, and should be understood by those skilled in the art, and should not be described herein, nor should it be limited.
- the 6k-5th shift is performed in conjunction with FIG. 10a, FIG. 10b, and FIG.
- the clock signal terminal CLK of the register unit is connected to the same clock signal line clk_1, and the clock signal terminal CLK of the 6k-4th stage shift register unit is connected to the same clock signal line clk_2, and the 6k-3th stage shift register unit is connected.
- the clock signal terminal CLK is connected to the same clock signal line clk_3, and the clock signal terminal CLK of the 6k-2th stage shift register unit is inverted with the same line.
- the clock signal line nclk_1 is connected, and the clock signal terminal CLK of the 6k-1th stage shift register unit is connected to the same inverted clock signal line nclk_2, and the clock signal terminal CLK of the 6kth stage shift register unit is inverted with the same line.
- the clock signal line nclk_3 is connected; wherein k is a positive integer.
- the shift register unit may include sixteen input transistors, which are a first input transistor Tr1 to a sixteenth input transistor Tr16, respectively.
- the specific connection method and the driving method are the same as those of the related art, and those of ordinary skill in the art can understand that it is not described herein, nor should it be limited to the present application.
- the display panel includes at most three clock signal lines, that is, a clock signal line clk_1, a clock signal line clk_2, and a clock signal line clk_3.
- the display panel may also include more than three clock signal lines.
- the display panel includes three clock signal lines.
- each of the clock signal lines, each of the inverted clock signal lines, and each of the inverting control circuits are located in a non-display area of the display panel.
- the embodiment of the present disclosure further provides a display device, including the above display panel provided by the embodiment of the present disclosure.
- the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the disclosure.
- the inverting control circuit, the driving method thereof, the display panel and the display device provided by the embodiment of the present disclosure include: an input circuit, a switching control circuit, a first output circuit, and a second output circuit; wherein, through the cooperation of the above four circuits
- the potential of the input signal end can be opposite to the potential of the inverted signal output end, so that when the inverting control circuit should be configured as a display panel, one clock signal is used as an input signal, and the output signal is a clock signal of opposite phase.
Abstract
Description
Claims (25)
- 一种反相控制电路,其特征在于,包括:输入电路、切换控制电路、第一输出电路以及第二输出电路;其中,所述输入电路分别与输入信号端、参考信号端、第一节点以及第二节点相连;所述输入电路被配置为在所述输入信号端的控制下分别将所述参考信号端的信号提供给所述第一节点与所述第二节点;所述切换控制电路分别与第一切换控制信号端、第二切换控制信号端、所述第一节点以及所述第二节点相连;所述切换控制电路被配置为在所述第一切换控制信号端的控制下将所述第一切换控制信号端的信号提供给所述第一节点,在所述第二切换控制信号端的控制下将所述第二切换控制信号端的信号提供给所述第二节点;所述第一输出电路分别与所述输入信号端、所述参考信号端以及所述反相控制电路的反相信号输出端相连;所述第一输出电路被配置为在所述输入信号端的控制下将所述参考信号端的信号提供给所述反相信号输出端;所述第二输出电路分别与所述第一切换控制信号端、所述第二切换控制信号端、所述第一节点、所述第二节点以及所述反相信号输出端相连;所述第二输出电路被配置为在所述第一节点的信号的控制下将所述第一切换控制信号端的信号提供给所述反相信号输出端,在所述第二节点的信号的控制下将所述第二切换控制信号端的信号提供给所述反相信号输出端。
- 如权利要求1所述的反相控制电路,其特征在于,所述第一切换控制信号端的电位在每相邻的预设间隔时长内为相反的电位;所述第一切换控制信号端的电位和所述第二切换控制信号端的电位为相反的电位;所述预设间隔时长为显示N帧的时间;N为大于或等于1的整数。
- 如权利要求1所述的反相控制电路,其特征在于,所述输入信号端的有效脉冲信号的电位为高电位,所述参考信号端的电位为低电位;或,所述输入信号端的有效脉冲信号的电位为低电位,所述参考信号端的电位为高电位。
- 如权利要求1所述的反相控制电路,其特征在于,所述切换控制电路包括:第一开关晶体管与第二开关晶体管;其中,所述第一开关晶体管的控制极和第一极均与所述第一切换控制信号端相连,第二极与所述第一节点相连;所述第二开关晶体管的控制极和第一极均与所述第二切换控制信号端相连,第二极与所述第二节点相连。
- 如权利要求4所述的反相控制电路,其特征在于,所述输入电路包括:第三开关晶体管与第四开关晶体管;其中,所述第三开关晶体管的控制极与所述输入信号端相连,第一极与所述参考信号端相连,第二极与所述第一节点相连;所述第四开关晶体管的控制极与所述输入信号端相连,第一极与所述参考信号端相连,第二极与所述第二节点相连。
- 如权利要求5所述的反相控制电路,其特征在于,所述第一开关晶体管的沟道宽长比与所述第三开关晶体管的沟道宽长比的比例为1:2;第二开关晶体管的沟道宽长比与所述第四开关晶体管的沟道宽长比的比例为1:2。
- 如权利要求1所述的反相控制电路,其特征在于,所述第一输出电路包括:第五开关晶体管;其中,所述第五开关晶体管的控制极与所述输入信号端相连,第一极与所述参考信号端相连,第二极与所述反相信号输出端相连。
- 如权利要求7所述的反相控制电路,其特征在于,所述第二输出电路包括:第六开关晶体管与第七开关晶体管;其中,所述第六开关晶体管的控制极与所述第一节点相连,第一极与所述第一切换控制信号端相连,第二极与所述反相信号输出端相连;所述第七开关晶体管的控制极与所述第二节点相连,第一极与所述第二 切换控制信号端相连,第二极与所述反相信号输出端相连。
- 如权利要求8所述的反相控制电路,其特征在于,所述第六开关晶体管的沟道宽长比与所述第五开关晶体管的沟道宽长比的比例为1:6;所述第七开关晶体管的沟道宽长比与所述第五开关晶体管的沟道宽长比的比例为1:6。
- 一种如权利要求1-9任一项所述的反向控制电路的驱动方法,其特征在于,包括:在第一阶段,所述输入电路在所述输入信号端的控制下将所述参考信号端的信号分别提供给所述第一节点与所述第二节点;所述第一输出电路在所述输入信号端的控制下将所述参考信号端的信号提供给所述反相信号输出端;在第二阶段,所述切换控制电路在所述第一切换控制信号端的控制下将所述第一切换控制信号端的信号提供给所述第一节点,所述第二输出电路在所述第一节点的信号的控制下将所述第一切换控制信号端的信号提供给所述反相信号输出端;或,在第二阶段,所述切换控制电路在所述第二切换控制信号端的控制下将所述第二切换控制信号端的信号提供给所述第二节点,所述第二输出电路在所述第二节点的信号的控制下将所述第二切换控制信号端的信号提供给所述反相信号输出端。
- 一种反相控制电路,其特征在于,包括:输入电路、切换控制电路、第一输出电路以及第二输出电路;其中,所述输入电路分别与输入信号端、参考信号端以及第一节点相连;所述输入电路被配置为在所述输入信号端的控制下将所述参考信号端的信号提供给所述第一节点;所述切换控制电路分别与切换控制信号端以及所述第一节点相连;所述切换控制电路被配置为在所述切换控制信号端的控制下将所述切换控制信号端的信号提供给所述第一节点;所述第一输出电路分别与所述输入信号端、所述参考信号端以及所述反 相控制电路的反相信号输出端相连;所述第一输出电路被配置为在所述输入信号端的控制下将所述参考信号端的信号提供给所述反相信号输出端;所述第二输出电路分别与所述切换控制信号端、所述第一节点以及所述反相信号输出端相连;所述第二输出电路被配置为在所述第一节点的信号的控制下将所述切换控制信号端的信号提供给所述反相信号输出端。
- 如权利要求11所述的反相控制电路,其特征在于,所述输入信号端的有效脉冲信号的电位为高电位,所述参考信号端的电位为低电位,所述切换控制信号端的电位为高电位;或,所述输入信号端的有效脉冲信号的电位为低电位,所述参考信号端的电位为高电位,所述切换控制信号端的电位为低电位。
- 如权利要求11所述的反相控制电路,其特征在于,所述切换控制电路包括:第一开关晶体管;其中,所述第一开关晶体管的控制极和第一极均与所述切换控制信号端相连,第二极与所述第一节点相连。
- 如权利要求13所述的反相控制电路,其特征在于,所述输入电路包括:第二开关晶体管;其中,所述第二开关晶体管的控制极与所述输入信号端相连,第一极与所述参考信号端相连,第二极与所述第一节点相连。
- 如权利要求14所述的反相控制电路,其特征在于,所述第一开关晶体管M1的沟道宽长比与所述第二开关晶体管M2的沟道宽长比的比例为1:2。
- 如权利要求11所述的反相控制电路,其特征在于,所述第一输出电路包括:第三开关晶体管;其中,所述第三开关晶体管的控制极与所述输入信号端相连,第一极与所述参考信号端相连,第二极与所述反相信号输出端相连。
- 如权利要求16所述的反相控制电路,其特征在于,所述第二输出电路包括:第四开关晶体管;其中,所述第四开关晶体管的控制极与所述第一节点相连,第一极与所述切换 控制信号端相连,第二极与所述反相信号输出端相连。
- 如权利要求17所述的反相控制电路,其特征在于,所述第四开关晶体管的沟道宽长比与所述第三开关晶体管的沟道宽长比的比例为1:6。
- 一种如权利要求11-18任一项所述的反向控制电路的驱动方法,其特征在于,包括:在第一阶段,所述输入电路在所述输入信号端的控制下将所述参考信号端的信号提供给所述第一节点;所述第一输出电路在所述输入信号端的控制下将所述参考信号端的信号提供给所述反相信号输出端;在第二阶段,所述切换控制电路在所述切换控制信号端的控制下将所述切换控制信号端的信号提供给所述第一节点;所述第二输出电路在所述第一节点的信号的控制下将所述切换控制信号端的信号提供给所述反相信号输出端。
- 一种显示面板,包括至少一条时钟信号线,其特征在于,还包括:与各所述时钟信号线一一对应的反相时钟信号线,以及与各所述时钟信号线一一对应的如权利要求1-9、11-18任一项所述的反相控制电路;所述反相控制电路的输入信号端与对应的时钟信号线相连,反相信号输出端与对应的反相时钟信号线相连。
- 如权利要求20所述的显示面板,其特征在于,还包括:栅极驱动电路,所述栅极驱动电路包括多个级联的移位寄存器单元构成;各级所述移位寄存器单元的第一参考信号端均与同一条被配置为输入第一参考信号的信号线相连,各级所述移位寄存器单元的第二参考信号端均与同一条用于输入第二参考信号的信号线相连,各级所述移位寄存器单元的第三参考信号端均与同一条用于输入第三参考信号的信号线相连;所述用于输入第一参考信号的信号线与所述反相控制电路的第一切换控制信号端相连,所述用于输入第二参考信号的信号线与所述反相控制电路的第二切换控制信号端相连,所述用于输入第三参考信号的信号线与所述反相控制电路的参考信号端相连。
- 如权利要求20所述的显示面板,其特征在于,所述显示面板最多包括三条时钟信号线。
- 如权利要求22所述的显示面板,其特征在于,所述显示面板包括三条时钟信号线。
- 如权利要求20-23任一项所述的显示面板,其特征在于,各所述时钟信号线、各所述反相时钟信号线以及各所述反相控制电路均位于所述显示面板的非显示区域内。
- 一种显示装置,其特征在于,包括如权利要求20-24任一项所述的显示面板。
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