WO2018153104A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2018153104A1
WO2018153104A1 PCT/CN2017/105459 CN2017105459W WO2018153104A1 WO 2018153104 A1 WO2018153104 A1 WO 2018153104A1 CN 2017105459 W CN2017105459 W CN 2017105459W WO 2018153104 A1 WO2018153104 A1 WO 2018153104A1
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Prior art keywords
signal
node
output
circuit
transistor
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Ceased
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PCT/CN2017/105459
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English (en)
French (fr)
Inventor
王博
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/777,715 priority Critical patent/US11170695B2/en
Publication of WO2018153104A1 publication Critical patent/WO2018153104A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • AMOLED (Active Matrix Driving OLED) display device has the advantages of low manufacturing cost, high response speed, power saving, DC drive for portable devices, large operating temperature range, and the like, and more and more The ground is used in the field of high performance display.
  • a pixel circuit for emitting light is disposed in a pixel of the AMOLED display panel.
  • the brightness of different ambient light is different to the human eye. For example, when the ambient light is bright, the brightness of the display needs to be increased to make the display clearer; when the ambient light is dark, the brightness of the display needs to be lowered to avoid the glare of the display with higher brightness. Therefore, people need to adjust the brightness of the display according to different viewing environments.
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which are capable of adjusting a signal pulse width input to a pixel circuit line by line when a user's demand changes, and The signal output from the shift register unit to the pixel circuit is stabilized.
  • a shift register unit includes a first input circuit coupled to a first node for outputting a potential signal to the first node, a first output circuit, and a signal output end And the first node connection, configured to output a potential signal to the signal output terminal under the control of the first node; the second input circuit is connected to the second node, and the second input circuit is configured to The second node outputs a potential signal; the second output circuit is connected to the signal output end and the second node, The second output circuit is configured to output a potential signal to the signal output terminal under the control of the second node; the stabilization circuit is connected to the first node and the second node, and the stabilization circuit is used When the first output circuit outputs a potential signal to the signal output terminal, the potential of the second node is stabilized such that the second output circuit has no signal output; or, when the second output circuit is When the signal output terminal outputs the potential signal, the potential of the first node is stabilized, so that the first output circuit has
  • the stabilizing circuit is further connected to the first voltage end, and the stabilizing is configured to output the signal of the first voltage end to the second node under the control of the first node; or Outputting, by the second node, a signal of the first voltage terminal to the first node;
  • the stabilization circuit includes: a first transistor and a second transistor; wherein a width to length ratio of the first transistor A gate length of the first transistor is connected to the first node, a first pole is connected to the first voltage end, and a second pole is connected to the second node; The gate of the second transistor is connected to the second node, the first pole is connected to the first voltage end, and the second pole is connected to the first node.
  • the first input circuit is further connected to a signal input end, and the first input circuit is configured to output a potential signal of the signal input end to the first node under the control of the signal input end
  • the first input circuit includes a third transistor, a gate of the third transistor and a first pole connected to the signal input terminal, and a second pole connected to the first node.
  • the first output circuit is further connected to the first clock signal end, and the first output circuit is configured to output the signal of the first clock signal end under the control of the first node To the signal output end;
  • the first output circuit includes a fourth transistor, a gate of the fourth transistor is connected to the first node, a first pole is connected to the first clock signal end, and a second pole is The signal outputs are connected.
  • the second input circuit is further connected to the second clock signal end and the second voltage end, and the second input circuit is configured to, under the control of the second clock signal end, a signal of the second voltage terminal is output to the second node;
  • the second input circuit includes a fifth transistor, a gate of the fifth transistor is connected to the second clock signal end, and a first pole is connected to the second voltage end The second pole is connected to the second node.
  • the second output circuit is further connected to the first voltage end, and the second output circuit is configured to output the signal of the first voltage terminal to the control under the control of the second node
  • the second output circuit of the signal output terminal includes a sixth transistor and a storage capacitor; a gate of the sixth transistor is connected to the second node, a first pole is connected to the first voltage end, and a second pole is connected to the second pole
  • the signal output ends are connected; one end of the storage capacitor is connected to the first voltage end, and the other end is connected to the second node.
  • Another aspect of an embodiment of the present disclosure provides a gate driving circuit including a plurality of cascaded shift register units as described above; a signal input terminal and a start signal of the first stage shift register unit The terminal is connected; in addition to the first stage shift register unit, the signal output terminal of the shift register unit of the previous stage is connected to the signal input terminal of the shift register unit of the next stage.
  • a display device comprising the gate drive circuit as described above.
  • a method for driving any one of the above shift register units includes: in a first stage, a first input circuit Outputting a potential signal to the first node; the first output circuit outputs a first signal to the signal output terminal under control of the first node; the stabilization circuit stabilizes the potential of the second node to cause the second output circuit No signal output; in the second phase, the first output circuit remains in an open state, and outputs a second signal to the signal output terminal; the stabilization circuit stabilizes the potential of the second node such that the second output circuit has no signal output In the third stage, the second input circuit outputs a potential signal to the second node; under the control of the second node, the second output circuit outputs the first signal to the signal output terminal; The circuit stabilizes the potential of the first node such that the first output circuit has no signal output; the first signal and the second signal are high and low with each other.
  • the stabilizing circuit stabilizing the potential of the first node or the second node comprises: under the control of the first node, The stabilization circuit outputs a signal of the first voltage terminal to the second node; or under the control of the second node, the stabilization circuit outputs a signal of the first voltage terminal to the first node.
  • the outputting the potential signal by the first input circuit to the first node comprises: controlling the first input circuit at the signal input end And outputting the signal of the potential signal input terminal to the first node.
  • the outputting the potential signal to the signal output end by the first output circuit includes: under the control of the first node, the An output circuit outputs the potential signal of the first clock signal terminal to the signal output terminal.
  • the second input circuit when the second input circuit further connects the second clock signal end and the second voltage end, the second input circuit outputs a signal to the second node, the second input circuit is in the The signal of the second voltage terminal is output to the second node under the control of the second clock signal terminal.
  • the stabilizing circuit when the stabilizing circuit is further connected to the first voltage end, the first input circuit is further connected to the signal input end, the first output circuit is further connected to the first clock signal end, the second input circuit Also connecting a second clock signal terminal and a second voltage terminal, wherein the second output circuit is further connected to the first voltage terminal; and when the stabilization circuit comprises a first transistor and a second transistor, the first input circuit A third transistor is included, the first output circuit includes a fourth transistor, the second input circuit includes a fifth transistor, the second output circuit includes a sixth transistor and a storage capacitor; and the transistors are all P-type transistors In the case where the shift register unit is driven in an image frame, the second voltage terminal inputs a low level, and the first voltage terminal inputs a high level; in the first stage, the signal input end with The second clock signal terminal inputs a low level, the first clock signal terminal inputs a high level; the fourth transistor, the third transistor, the fifth transistor, and the first transistor are turned on, The remaining transistors are turned off; the signal
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the shift register unit includes a first input circuit, a first output circuit, a second input circuit, a second output circuit, and a stabilization circuit.
  • the first input circuit is coupled to the first node, and the first input circuit is configured to output a signal to the first node.
  • the first output circuit is coupled to the signal output and the first node, the first output circuit for outputting a signal to the signal output.
  • the second input circuit is coupled to the second node, the second input circuit for outputting a signal to the second node.
  • the second output circuit is coupled to the signal output terminal and the second node, the second output circuit for outputting a signal to the signal output terminal.
  • the stabilizing circuit is connected to the first voltage end, the first node and the second node, and the stabilizing circuit is configured to stabilize the potential of the second node when the first output circuit outputs a signal to the signal output end, so that the second output circuit has no signal output Or alternatively, when the second output circuit outputs a signal to the signal output terminal, the potential of the first node is stabilized so that the first output circuit has no signal output.
  • the shift register unit can shift the signal at the signal input end and shift The signal after the bit is output through the signal output.
  • the gate drive circuit is configured by using the plurality of cascaded shift registers
  • the rest of the shift register unit is The signal pulse width outputted by the signal output also changes, so that the pulse width of the signal received by each row of pixel circuits changes accordingly. Therefore, when the user's demand for display brightness changes, it is only necessary to adjust the pulse width of the output signal of the signal output terminal of the first stage shift register unit, thereby simplifying the adjustment process.
  • the stabilization circuit of the shift register unit can stabilize the potentials of the first node and the second node, respectively, the potential of the second node can be stabilized when the first output circuit is turned on to ensure the second output.
  • the circuit is in a closed state, or when the second output circuit is turned on, the potential of the first node is stabilized to ensure that the first output circuit is in a closed state, thereby making the signal outputted from the signal output end of the shift register unit stable.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural view of each circuit of FIG. 2;
  • FIG. 5 is a schematic structural view of a gate driving circuit constructed using a plurality of shift register units as shown in FIG. 2 or FIG.
  • the embodiment of the present disclosure provides a shift register unit, as shown in FIG. 1, including a stabilization circuit 10, a first input circuit 20, a first output circuit 30, a second input circuit 40, and a second output circuit 50.
  • the first input circuit 20 is connected to the first node N1.
  • the first input circuit 20 is for outputting a potential signal to the first node N1.
  • the first input circuit 20 when the first input circuit 20 is further connected to the signal input terminal INT, the first input circuit 20 is configured to signal the signal input terminal INT under the control of the signal input terminal INT. Output to the first node N1.
  • the second output circuit 50 is connected to the signal output terminal OUT and the second node N2.
  • the second output circuit 50 is configured to output a potential signal to the signal output terminal OUT under the control of the second node N2.
  • the second output circuit 50 when the second output circuit 50 is further connected to the first voltage terminal VGH, the second output circuit 50 is configured to, under the control of the second node N2, the first voltage terminal VGH. The signal is output to the signal output terminal OUT.
  • the stabilization circuit 10 connects the first node N1 and the second node N2.
  • the stabilizing circuit 10 is configured to stabilize the potential of the second node N2 when the first output circuit 30 outputs the potential signal to the signal output terminal OUT, so that the second output circuit 50 has no signal output; or, for the second output circuit When 50 outputs a potential signal to the signal output terminal OUT, the potential of the first node N1 is stabilized so that the first output circuit 30 has no signal output.
  • the stabilization circuit 10 when the stabilization circuit 10 is further connected to the first voltage terminal VGH, the stabilization circuit 10 is configured to output the signal of the first voltage terminal VGH to the first node N1 under the control of the first node N1.
  • the second node N2 or under the control of the second node N2, outputs the signal of the first voltage terminal VGH to the first node N1.
  • the shift register unit can perform the signal of the signal input terminal INT. Shift and output the shifted signal through the signal output terminal OUT.
  • the gate drive circuit is configured by using the plurality of cascaded shift registers
  • the pulse width of the output signal of the signal output terminal OUT of the first stage shift register unit changes
  • the signals of the remaining shift register units are The signal pulse width of the output of the output terminal OUT also changes, so that the pulse width of the signal received by each row of pixel circuits changes accordingly. Therefore, when the user's demand for display brightness changes, it is only necessary to adjust the pulse width of the output signal of the first stage shift register unit signal output terminal OUT, thereby simplifying the adjustment process.
  • the stabilization circuit 10 of the shift register unit can stabilize the potentials of the first node N1 and the second node N2, the first node N1 can control the first output circuit 30 to output a signal to the signal output terminal OUT, the second The node N2 can control the second output circuit 50 to output a signal to the signal output terminal OUT.
  • the stabilization circuit 10 can stabilize the potential of the first node N1, thereby ensuring that the first output circuit 30 has no signal output, thereby stabilizing the signal output from the signal output terminal OUT.
  • the stabilization circuit 10 includes a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is connected to the first node N1, the first pole is connected to the first voltage terminal VGH, and the second pole is connected to the second node N2.
  • the gate of the second transistor T2 is connected to the second node N2, the first pole is connected to the first voltage terminal VGH, and the second pole is connected to the first node N1.
  • First transistor T1 and the second transistor T2 can be interlocked.
  • First transistor T1 And the second transistor T2 is a P-type transistor, and the first voltage terminal VGH outputs a high level as an example.
  • the first transistor T1 is turned on, the high level output by the first voltage terminal VGH passes through the first transistor.
  • T1 is output to the gate of the second transistor T2 such that the second transistor T2 is in an off state.
  • the second transistor T2 is turned on, the high level output by the first voltage terminal VGH is output to the gate of the first transistor T1 through the second transistor T2, so that the first transistor T1 is in an off state.
  • the aspect ratio of the first transistor T1 is greater than the aspect ratio of the second transistor T2.
  • the output capability of the first transistor T1 is greater than the output capability of the second transistor T2, so that the first transistor T1 can precede the second transistor when the gates of the first transistor T1 and the second transistor T2 are both low. T2 is turned on.
  • the first input circuit 20 includes a third transistor T3, the gate of the third transistor T3 and the first pole are connected to the signal input terminal INT, and the second pole is connected to the first node N1.
  • the first output circuit 30 includes a fourth transistor T4 having a gate connected to the first node N1, a first pole connected to the first clock signal terminal CK1, and a second pole connected to the signal output terminal OUT.
  • the second input circuit 40 includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second clock signal terminal CK2, the first electrode is connected to the second voltage terminal VGL, and the second electrode is connected to the second node N2.
  • the second output circuit 50 includes a sixth transistor T6 and a storage capacitor C.
  • the gate of the sixth transistor T6 is connected to the second node N2, the first pole is connected to the first voltage terminal VGH, and the second pole is connected to the signal output terminal OUT.
  • One end of the storage capacitor C is connected to the first voltage terminal VGH, and the other end is connected to the second node N2.
  • the transistor may be a P-type transistor.
  • the second voltage terminal VGL inputs a constant low level
  • the first voltage terminal VGH inputs a constant high level.
  • the signals input from the remaining signal terminals are shown in Figure 4.
  • the above may also be an N-type transistor. In this case, it is necessary to invert the signal input to each signal terminal as shown in FIG.
  • the first source of the transistor is the first source and the second terminal is the drain. Or the first extreme drain, the second extreme source.
  • the signal input terminal INT inputs a low level
  • the third transistor T3 is turned on
  • the low level of the signal input terminal INT is output to the first node N1 through the third transistor T3.
  • the fourth transistor T4 is turned on, and outputs a high level outputted by the first clock signal terminal CK1 to the signal output terminal OUT.
  • the sixth transistor T6 is turned off by the interlocking action of the first transistor T1 and the second transistor T2, so that the signal output terminal OUT receives only the signal output by the first clock signal terminal CK1.
  • the signal input terminal INT inputs a high level
  • the third transistor T3 is turned off.
  • the width and length of the fourth transistor T4 are relatively large, so the parasitic capacitance of the fourth transistor T4 itself will continue to maintain the low level stored in the previous stage, and the first node N1 is at the low level. Based on this, the fourth transistor T4 can be kept in an on state, and the low level of the first clock signal terminal CK1 is output to the signal output terminal OUT.
  • the gate line connected to the signal output terminal OUT of the shift register unit receives the low level, and turns the low level as a gate driving signal to turn on the transistor in the pixel circuit connected to the gate line.
  • the first transistor T1 under the control of the first node N1, the first transistor T1 is turned on, and the high level of the first voltage terminal VGH is output to the second node N2.
  • the second node N2 controls the second transistor T2 and the sixth transistor T6 to be turned off. Therefore, the potential of the second node N2 can be stabilized at this stage by the first transistor T1, and the potential of the second node N2 is prevented from being unstable, so that the sixth transistor T6 is turned on, and the high level of the first voltage terminal VGH is erroneously outputted to the signal. Output OUT.
  • the second clock signal terminal CK2 is input with a low level
  • the fifth transistor T5 is turned on
  • the low level of the second voltage terminal VGL is output to the second node N2, and is stored by the storage capacitor C.
  • the sixth transistor T6 and the second transistor T2 are turned on. Based on this, the high level of the first voltage terminal VGH is output to the signal output terminal OUT through the sixth transistor T6.
  • the second transistor T2 is turned on to output the high level of the first voltage terminal VGH to the first node N1, at which time the first transistor T1 and the fourth transistor T4 are turned off. Thereby, the potential of the first node N1 can be stabilized at this stage by the second transistor T2.
  • the signal output terminal of the shift register unit outputs a low level, thereby turning on a transistor in the pixel circuit connected to the signal output terminal OUT of the shift register unit.
  • the sixth transistor T6 remains in an on state, so that the signal is output.
  • the terminal OUT maintains the state of the high level output.
  • Embodiments of the present disclosure provide a gate driving circuit, as shown in FIG. 5, including a plurality of cascaded shift register units (RS1, RS2, ..., RS(n-1), RSn) as described above. Connection grid Lines (G1, G2, ..., G(n-1), Gn). Where n is a positive integer greater than 2.
  • the signal input terminal INT of the first stage shift register unit RS1 is connected to the start signal terminal STV.
  • the signal input end of the first stage shift register unit RS1 is connected to the start signal terminal STV.
  • the start signal terminal STV is used to input a start signal, so that the gate drive circuit receiving the start signal starts to work.
  • the signal output terminal OUT of the shift register unit of the previous stage is connected to the signal input terminal INT of the shift register unit of the next stage.
  • the shift register unit constituting the above-described gate driving circuit has the same configuration and advantageous effects as the shift register unit provided in the foregoing embodiment. Since the foregoing embodiment has described the structure and advantageous effects of the shift register unit in detail, it will not be described herein.
  • Embodiments of the present disclosure provide a display device including any of the gate driving circuits as described above, having the same structure and advantageous effects as the gate driving circuit provided in the foregoing embodiments. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the gate driving circuit, details are not described herein again.
  • the display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device.
  • the display device may be any display product such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer. component.
  • the detailed structure of the array substrate has been described in detail in the foregoing embodiments, and details are not described herein again.
  • Embodiments of the present disclosure provide a driving method of a shift register unit, and a driving method of the shift register unit in an image frame includes:
  • the first input circuit 20 outputs a signal to the first node N1.
  • the first output circuit 30 outputs a first signal to the signal output terminal OUT.
  • the stabilizing circuit 10 stabilizes the potential of the second node N2 so that the second output circuit 50 has no signal output.
  • the first signal and the second signal are high and low levels.
  • the transistor of the pixel circuit connected to the shift register unit is a P-type transistor, the first signal is at a high level and the second signal is at a low level.
  • the transistor of the pixel circuit connected to the shift register unit is exemplified as a P-type transistor.
  • the first input circuit 20 when the first input circuit 20 is further connected to the signal input terminal INT, the first input circuit 20 outputs a signal to the first node N1, including: the first input circuit 20 is at the signal input end. Under the control of INT, the signal of the signal input terminal INT is output to the first node N1.
  • the first output circuit 30 when the first output circuit 30 is further connected to the first clock signal terminal CK1, the first output circuit 30 outputs a signal to the signal output terminal OUT.
  • the first output circuit 30 outputs the signal of the first clock signal terminal CK1 to the signal. Output OUT.
  • the stabilization circuit 10 includes the first transistor T1 and the second transistor T2 as shown in FIG.
  • the first input circuit 10 includes a third transistor T3, and the first output circuit includes a fourth transistor.
  • the second input circuit 40 includes a fifth transistor T5.
  • the second output circuit 50 includes a sixth transistor T6 and a storage capacitor C, and in the case where the above transistors are all P-type transistors, in the first stage P1 described above:
  • the signal input terminal INT inputs a low level, the third transistor T3 is turned on, and the low level of the signal input terminal INT is output to the first node N1 through the third transistor T3.
  • the fourth transistor T4 is turned on, and outputs a high level outputted by the first clock signal terminal CK1 to the signal output terminal OUT.
  • the second clock signal terminal CK2 inputs a low level
  • the fifth transistor T5 is turned on
  • the low level of the second voltage terminal VGL is output to the second node N2 through the fifth transistor T5.
  • the gates of the first transistor T1 and the second transistor T2 are both low. Since the aspect ratio of the first transistor T1 is greater than the aspect ratio of the second transistor T2, the first transistor T1 takes precedence over the first transistor T1.
  • the second transistor T2 is turned on. In this way, when the first transistor T1 is turned on, the high level of the first voltage terminal VGH is output to the second node N2 through the first transistor T1, so that the second node N2 is at a high level. At this time, under the control of the second node N2, the sixth transistor T6 and the second transistor T2 are kept in an off state.
  • the sixth transistor T6 is turned off by the interlocking action of the first transistor T1 and the second transistor T2, so that the signal output terminal OUT receives only the signal output by the first clock signal terminal CK1.
  • the first output circuit 30 remains in an on state, and a second signal is output to the signal output terminal OUT.
  • the stabilizing circuit 10 stabilizes the potential of the second node N2 so that the second output circuit 50 has no signal output.
  • the second input circuit 40 outputs a signal to the second node N2.
  • the second output circuit 50 outputs a first signal to the signal output terminal OUT.
  • the stabilizing circuit 10 stabilizes the potential of the first node N1 so that the first output circuit 30 has no signal output.
  • the second input circuit 40 when the second input circuit 40 is further connected to the second clock signal terminal CK2 and the second voltage terminal VGL, the second input circuit 40 outputs the signal to the second node N2, including: The input circuit 40 outputs the signal of the second voltage terminal VGL to the second node N2 under the control of the second clock signal terminal CK2.
  • the second output circuit 50 When the second output circuit 50 is further connected to the first voltage terminal VGH, the second output circuit 50 outputs a signal to the signal output terminal OUT.
  • the second output circuit 50 stores the potential of the second node N2. And under the control of the second node N2, the signal of the first voltage terminal VGH is output to the signal output terminal OUT.
  • the stabilizing circuit 10 when the stabilizing circuit 10 is further connected to the first voltage terminal VGH, the stabilizing circuit 10 stabilizes the potential of the first node N1 or the second node N2 includes: under the control of the first node N1, the stabilizing circuit 10 sets the first voltage terminal VGH The signal is output to the second node N2; or under the control of the second node N2, the stabilization circuit 10 outputs the signal of the first voltage terminal VGH to the first node N1.
  • the second clock signal terminal CK2 inputs a low level
  • the fifth transistor is turned on, outputs a low level of the second voltage terminal VGL to the second node N2, and is stored by the storage capacitor C.
  • the sixth transistor T6 and the second transistor T2 are turned on. Based on this, the high level of the first voltage terminal VGH is output to the signal output terminal OUT through the sixth transistor T6.
  • the second transistor T2 is turned on to output the high level of the first voltage terminal VGH to the first node N1, at which time the first transistor T1 and the fourth transistor T4 are turned off. Thereby, the potential of the first node N1 can be stabilized at this stage by the second transistor T2.

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Abstract

一种移位寄存器单元(RS1,RS2……RS(n-1),RSn)及其驱动方法、栅极驱动电路、显示装置，涉及显示技术领域，能够当用户需求发生变化时，无需逐行对输入至像素电路的信号脉宽进行调整，且使得移位寄存器单元向该像素电路输出的信号稳定。该移位寄存器单元包括第一输入电路(20)、第一输出电路(30)、第二输入电路(40)、第二输出电路(50)、稳定电路(10)。该稳定电路(10)用于当第一输出电路(30)向信号输出端(OUT)输出信号时，稳定第二节点(N2)的电位，以使得第二输出电路(50)无信号输出；或者，用于当第二输出电路(50)向信号输出端(OUT)输出信号时，稳定第一节点(N1)的电位，以使得第一输出电路(30)无信号输出。

Description

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
交叉引用
本申请要求于2017年2月24日提交的申请号为201710106147.2、名称为“移位寄存器单元及其驱动方法、栅极驱动电路、显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。
背景技术
AMOLED(Active Matrix Driving OLED，有源矩阵驱动有机发光二极管)显示装置具有低制造成本、高应答速度、省电、可用于便携式设备的直流驱动、工作温度范围大等等优点，而越来越多地被应用于高性能显示领域当中。
AMOLED显示面板的像素中设置有用于发光的像素电路，然而在使用AMOLED显示器观看显示画面的过程中，不同的环境光线的亮度对人眼的感受程度不同。例如，当环境光线较亮时，需要调高显示器的亮度，以使得显示画面更加清晰；当环境光线较暗时，需要调低显示器的亮度，以避免亮度较高的显示画面带来刺眼的感觉，因此人们需要根据不同的观看环境对显示画面的亮度进行调节。
在此情况下，当用户需求发生变化时，现有技术中需要逐行对输入至上述像素电路的信号的脉宽进行调整，以达到调整像素发光亮度的目的，然而逐行调整调节过程较复杂，导致生产效率降低。
发明内容
本公开的实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置，能够当用户需求发生变化时，无需逐行对输入至像素电路的信号脉宽进行调整，且使得移位寄存器单元向该像素电路输出的信号稳定。
为达到上述目的，本公开的实施例采用如下技术方案：
本公开实施例的一方面，提供的一种移位寄存器单元，包括第一输入电路，与第一节点连接，用于向所述第一节点输出电位信号；第一输出电路，与信号输出端以及所述第一节点连接，用于在所述第一节点的控制下，向所述信号输出端输出电位信号；第二输入电路，与第二节点连接，所述第二输入电路用于向所述第二节点输出电位信号；第二输出电路，与所述信号输出端以及第二节点连接， 所述第二输出电路用于在所述第二节点的控制下，向所述信号输出端输出电位信号；所述稳定电路连接所述第一节点以及所述第二节点，所述稳定电路用于当所述第一输出电路向所述信号输出端输出电位信号时，稳定所述第二节点的电位，以使得第二输出电路无信号输出；或者，用于当所述第二输出电路向所述信号输出端输出电位信号时，稳定所述第一节点的电位，以使得所述第一输出电路无信号输出。
在一个实施方式中，所述稳定电路还连接第一电压端，所述稳定用于在所述第一节点的控制下，将所述第一电压端的信号输出至所述第二节点；或在所述第二节点的控制下，将所述第一电压端的信号输出至所述第一节点；所述稳定电路包括：第一晶体管和第二晶体管；其中，所述第一晶体管的宽长比大于所述第二晶体管的宽长比；所述第一晶体管的栅极连接所述第一节点，第一极连接所述第一电压端，第二极与所述第二节点相连接；所述第二晶体管的栅极连接所述第二节点，第一极连接所述第一电压端，第二极与所述第一节点相连接。
在一个实施方式中，所述第一输入电路还连接信号输入端，所述第一输入电路用于在所述信号输入端的控制下，将所述信号输入端的电位信号输出至所述第一节点；所述第一输入电路包括第三晶体管，所述第三晶体管的栅极和第一极连接所述信号输入端，第二极与所述第一节点相连接。
在一个实施方式中，所述第一输出电路还连接所述第一时钟信号端，所述第一输出电路用于在所述第一节点的控制下，将所述第一时钟信号端的信号输出至所述信号输出端；所述第一输出电路包括第四晶体管，所述第四晶体管的栅极连接所述第一节点，第一极连接所述第一时钟信号端，第二极与所述信号输出端相连接。
在一个实施方式中，所述第二输入电路还连接所述第二时钟信号端以及第二电压端，所述第二输入电路用于在所述第二时钟信号端的控制下，将所述第二电压端的信号输出至所述第二节点；所述第二输入电路包括第五晶体管，所述第五晶体管的栅极连接所述第二时钟信号端，第一极连接所述第二电压端，第二极与所述第二节点相连接。
在一个实施方式中，所述第二输出电路还连接所述第一电压端，所述第二输出电路用于在所述第二节点的控制下，将所述第一电压端的信号输出至所述信号输出端所述第二输出电路包括第六晶体管和存储电容；所述第六晶体管的栅极连接所述第二节点，第一极连接所述第一电压端，第二极与所述信号输出端相连接；所述存储电容的一端连接第一电压端，另一端与所述第二节点相连接。
本公开实施例的另一方面，提供一种栅极驱动电路，包括多个级联的如上所述的任意一种移位寄存器单元；第一级移位寄存器单元的信号输入端与起始信号端相连接；除了第一级移位寄存器单元以外，上一级移位寄存器单元的信号输出端连接下一级移位寄存器单元的信号输入端。
本公开实施例的又一方面，提供一种显示装置包括如上所述的栅极驱动电路。
本公开实施例的再一方面，提供一种用于驱动上述任意一种移位寄存器单元的方法，一图像帧内所述移位寄存器单元的驱动方法包括：在第一阶段，第一输入电路向所述第一节点输出电位信号；在第一节点的控制下，所述第一输出电路向信号输出端输出第一信号；稳定电路对第二节点的电位进行稳定，以使得第二输出电路无信号输出；在第二阶段，第一输出电路保持开启状态，向所述信号输出端输出第二信号；所述稳定电路对第二节点的电位进行稳定，以使得第二输出电路无信号输出；在第三阶段，第二输入电路向第二节点输出电位信号；在所述第二节点的控制下，所述第二输出电路向所述信号输出端输出所述第一信号；所述稳定电路对第一节点的电位进行稳定，以使得第一输出电路无信号输出；所述第一信号与所述第二信号互为高低电平。
在一个实施方式中，当所述稳定电路还连接第一电压端时，所述稳定电路稳定所述第一节点或所述第二节点的电位包括：在所述第一节点的控制下，所述稳定电路将所述第一电压端的信号输出至所述第二节点；或在所述第二节点的控制下，所述稳定电路将所述第一电压端的信号输出至所述第一节点。
在一个实施方式中，当所述第一输入电路还连接信号输入端时，所述第一输入电路向所述第一节点输出电位信号包括：所述第一输入电路在所述信号输入端的控制下，将所述电位信号输入端的信号输出至所述第一节点。
在一个实施方式中，当所述第一输出电路还连接第一时钟信号端时，所述第一输出电路向信号输出端输出电位信号包括：在所述第一节点的控制下，所述第一输出电路将所述第一时钟信号端的电位信号输出至信号输出端。
在一个实施方式中，当所述第二输入电路还连接第二时钟信号端以及第二电压端时，所述第二输入电路向第二节点输出信号包括：所述第二输入电路在所述第二时钟信号端的控制下，将所述第二电压端的信号输出至第二节点。
在一个实施方式中，当所述第二输出电路还连接所述第一电压端时，所述第二输出电路向所述信号输出端输出信号包括：所述第二输出电路将所述第二节点的电位进行存储，并在所述第二节点的控制下，将第一电压端的信号输出至所述信号输出端。
在一个实施方式中，当所述稳定电路还连接第一电压端，所述第一输入电路还连接信号输入端，所述第一输出电路还连接第一时钟信号端，所述第二输入电路还连接第二时钟信号端以及第二电压端，所述第二输出电路还连接所述第一电压端时；且当所述稳定电路包括第一晶体管和第二晶体管，所述第一输入电路包括第三晶体管，所述第一输出电路包括第四晶体管，所述第二输入电路包括第五晶体管，所述第二输出电路包括第六晶体管和存储电容；且上述晶体管均为P型晶体管的情况下，一图像帧内所述移位寄存器单元的驱动方法包括：所述第二电压端输入低电平，所述第一电压端输入高电平；在第一阶段，所述信号输入端和 所述第二时钟信号端输入低电平，所述第一时钟信号端输入高电平；所述第四晶体管、所述第三晶体管、所述第五晶体管以及所述第一晶体管导通，其余晶体管截止；所述第一时钟信号端的信号通过所述第四晶体管输出至所述信号输出端；在第二阶段，所述信号输入端和所述第二时钟信号端输入高电平，所述第一时钟信号端输入低电平；所述第四晶体管、所述第一晶体管导通，其余晶体管截止；所述第一时钟信号端的信号通过所述第四晶体管输出至所述信号输出端；在第三阶段，所述信号输入端和所述第一时钟信号端输入高电平，所述第二时钟信号端输入低电平；所述第五晶体管、所述第二晶体管以及所述第六晶体管导通，其余晶体管截止；所述第一电压端的信号通过所述第六晶体管输出至所述信号输出端。
本公开实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。该移位寄存器单元包括第一输入电路、第一输出电路、第二输入电路、第二输出电路以及稳定电路。其中，第一输入电路连接第一节点，该第一输入电路用于在向第一节点输出信号。第一输出电路连接信号输出端以及第一节点，该第一输出电路用于向信号输出端输出信号。第二输入电路连接第二节点，该第二输入电路用于向第二节点输出信号。第二输出电路连接信号输出端以及第二节点，该第二输出电路用于向信号输出端输出信号。稳定电路连接第一电压端、第一节点以及第二节点，该稳定电路用于当第一输出电路向信号输出端输出信号时，稳定第二节点的电位，以使得第二输出电路无信号输出；或者，用于当第二输出电路向信号输出端输出信号时，稳定第一节点的电位，以使得第一输出电路无信号输出。
这样一来，一方面，在上述第一输入电路、第一输出电路、第二输入电路以及第二输出电路的作用下，上述移位寄存器单元可以将信号输入端的信号进行移位，并将移位后的信号通过信号输出端输出。基于此，在采用上述多个级联的移位寄存器构成栅极驱动电路的情况下，当第一级移位寄存器单元的信号输出端输出信号的脉宽发生变化后，其余移位寄存器单元的信号输出端输出的信号脉宽也会随之变化，从而使得每一行像素电路接收到的信号脉宽随之变化。因此，当用户对显示亮度的需求发生变化时，只需对第一级移位寄存器单元信号输出端输出信号的脉宽进行调整即可，从而简化了调整过程。
另一方面，由于该移位寄存器单元的稳定电路能够分别稳定第一节点和第二节点的电位，从而可以在第一输出电路开启时，对第二节点的电位进行稳定，以保证第二输出电路处于关闭状态，或者在第二输出电路开启时，对第一节点的电位进行稳定个，以保证第一输出电路处于关闭状态，进而使得该移位寄存器单元的信号输出端输出的信号稳定。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种移位寄存器单元的结构示意图；
图2为本公开实施例提供的另一种移位寄存器单元的结构示意图；
图3为图2中各个电路的具体结构示意图；
图4为用于控制图3所示的移位寄存器单元的各个控制信号的时序图；
图5为采用如图2或图3所示的多个移位寄存器单元构成的栅极驱动电路的结构示意图。
附图标记：
10-稳定电路；20-第一输入电路；30-第一输出电路；40-第二输入电路；50-第二输出电路。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种移位寄存器单元，如图1所示，包括稳定电路10、第一输入电路20、第一输出电路30、第二输入电路40以及第二输出电路50。
其中，第一输入电路20连接第一节点N1。该第一输入电路20用于向第一节点N1输出电位信号。
可选的，例如，如图2所示，当第一输入电路20还连接信号输入端INT时，该第一输入电路20用于在信号输入端INT的控制下，将信号输入端INT的信号输出至第一节点N1。
第一输出电路30连接信号输出端OUT以及第一节点N1。该第一输出电路30用于在第一节点N1的控制下，向信号输出端OUT输出电位信号。
可选的，例如，如图2所示，当第一输出电路30还连接第一时钟信号端CK1时，该第一输出电路30用于在第一节点N1的控制下，将第一时钟信号端CK1的信号输出至信号输出端OUT。
第二输入电路40连接第二节点N2。该第二输入电路40用于向第二节点N2输出信号。
可选的，例如，如图2所示，当第二输入电路40还连接第二时钟信号端CK2、第二电压端VGL时，该第二输入电路40用于在第二时钟信号端CK2的控制下，将第二电压端VGL的信号输出至第二节点N2。
第二输出电路50连接信号输出端OUT以及第二节点N2。该第二输出电路50用于在第二节点N2的控制下，向信号输出端OUT输出电位信号。
可选的，例如，如图2所示，当第二输出电路50还连接第一电压端VGH时，该第二输出电路50用于在第二节点N2的控制下，将第一电压端VGH的信号输出至信号输出端OUT。
稳定电路10连接第一节点N1以及第二节点N2。该稳定电路10用于当第一输出电路30向信号输出端OUT输出电位信号时，稳定第二节点N2的电位，以使得第二输出电路50无信号输出；或者，用于当第二输出电路50向信号输出端OUT输出电位信号时，稳定第一节点N1的电位，以使得第一输出电路30无信号输出。
可选的，例如，如图2所示，当稳定电路10还连接第一电压端VGH时，该稳定电路10用于在第一节点N1的控制下，将第一电压端VGH的信号输出至第二节点N2；或在第二节点N2的控制下，将第一电压端VGH的信号输出至第一节点N1。
这样一来，一方面，在上述第一输入电路20、第一输出电路30、第二输入电路40以及第二输出电路50的作用下，上述移位寄存器单元可以将信号输入端INT的信号进行移位，并将移位后的信号通过信号输出端OUT输出。基于此，当采用上述多个级联的移位寄存器构成栅极驱动电路时，当第一级移位寄存器单元的信号输出端OUT输出信号的脉宽发生变化后，其余移位寄存器单元的信号输出端OUT输出的信号脉宽也会随之变化，从而使得每一行像素电路接收到的信号脉宽随之变化。因此，当用户对显示亮度的需求发生变化时，只需对第一级移位寄存器单元信号输出端OUT输出信号的脉宽进行调整即可，从而简化了调整过程。
另一方面，由于该移位寄存器单元的稳定电路10能够稳定第一节点N1和第二节点N2的电位，而第一节点N1可以控制第一输出电路30向信号输出端OUT输出信号，第二节点N2可以控制第二输出电路50向信号输出端OUT输出信号。这样一来，当第一输出电路30开启时，通过该稳定电路10可以稳定第二节点N2的电位，从而确保第二输出电路50无信号输出，或者在第二输出电路50开启时，通过该稳定电路10可以稳定第一节点N1的电位，从而确保第一输出电路30无信号输出，进而使得信号输出端OUT输出的信号稳定。
以下对如图2中各个电路的具体结构进行详细的说明。
具体的，如图3所示，该稳定电路10包括：第一晶体管T1和第二晶体管T2。
其中，第一晶体管T1的栅极连接第一节点N1，第一极连接第一电压端VGH，第二极与第二节点N2相连接。
第二晶体管T2的栅极连接第二节点N2，第一极连接第一电压端VGH，第二极与第一节点N1相连接。
在此情况下，第一晶体管T1与第二晶体管T2能够互锁。以第一晶体管T1 和第二晶体管T2均为P型晶体管，且第一电压端VGH输出高电平为例，当第一晶体管T1导通时，上述第一电压端VGH输出的高电平通过所述第一晶体管T1输出至所述第二晶体管T2的栅极，从而使得该第二晶体管T2处于截止状态。或者当第二晶体管T2导通时，上述第一电压端VGH输出的高电平通过该第二晶体管T2输出至第一晶体管T1的栅极，从而使得第一晶体管T1处于截止状态。
此外，第一晶体管T1的宽长比大于第二晶体管T2的宽长比。这样一来，第一晶体管T1的输出能力大于第二晶体管T2的输出能力，从而在第一晶体管T1和第二晶体管T2的栅极均为低电平时，第一晶体管T1能够先于第二晶体管T2导通。
此外，第一输入电路20包括第三晶体管T3，第三晶体管T3的栅极和第一极连接信号输入端INT，第二极与第一节点N1相连接。
第一输出电路30包括第四晶体管T4，该第四晶体管T4的栅极连接第一节点N1，第一极连接第一时钟信号端CK1，第二极与信号输出端OUT相连接。
第二输入电路40包括第五晶体管T5，该第五晶体管T5的栅极连接第二时钟信号端CK2，第一极连接第二电压端VGL，第二极与第二节点N2相连接。
第二输出电路50包括第六晶体管T6和存储电容C。
其中，第六晶体管T6的栅极连接第二节点N2，第一极连接第一电压端VGH，第二极与信号输出端OUT相连接。
存储电容C的一端连接第一电压端VGH，另一端与第二节点N2相连接。
需要说明的是，上述晶体管可以为P型晶体管，在此情况下，上述第二电压端VGL输入恒定的低电平，第一电压端VGH输入恒定的高电平。其余信号端输入的信号如图4所示。或者，上述也可以为N型晶体管，在此情况下，需要对如图4中的各个信号端输入的信号进行翻转。
此外，上述晶体管的第一极为源极，第二极为漏极。或者第一极为漏极，第二极为源极。
以下，以图3中的各个晶体管均为P型晶体管为例，结合图4对上述各个晶体管在一图像帧内各个阶段的通断状态进行详细的举例说明。其中，本公开中，第一电压端VGH输出恒定的高电平，例如7V，第二电压端VGL输出恒定的低电平，例如-7V。且与该移位寄存器单元相连接的像素电路的晶体管通常为P型晶体管。
在一图像帧的第一阶段P1，INT＝0，CK1＝1，CK2＝0，OUT＝1。其中本申请中“1”表示高电平，“0”表示低电平。
在此情况下，信号输入端INT输入低电平，第三晶体管T3导通，信号输入端INT的低电平通过上述第三晶体管T3输出至第一节点N1。在该第一节点N1的控制下，第四晶体管T4导通，并将第一时钟信号端CK1输出的高电平输出至信号输出端OUT。
此外，第二时钟信号端CK2输入低电平，第五晶体管T5导通，第二电压端VGL的低电平通过上述第五晶体管T5输出至第二节点N2。在此情况下，第一晶体管T1和第二晶体管T2的栅极均为低电平，由于第一晶体管T1的宽长比大于第二晶体管T2的宽长比，因此第一晶体管T1优先于第二晶体管T2导通。这样一来，当第一晶体管T1导通时，第一电压端VGH的高电平通过该第一晶体管T1输出至第二节点N2，以使得该第二节点N2为高电平。此时在该第二节点N2的控制下，第六晶体管T6和第二晶体管T2保持截止状态。
这样一来，通过上述第一晶体管T1和第二晶体管T2的互锁作用使得第六晶体管T6截止，从而使得信号输出端OUT只接收第一时钟信号端CK1输出的信号。
在一图像帧的第二阶段P2，INT＝1，CK1＝0，CK2＝1，OUT＝0。
在此情况下，信号输入端INT输入高电平，第三晶体管T3截止。通常第四晶体管T4的宽长比较大，因此该第四晶体管T4自身的寄生电容将继续保持上一阶段存储的低电平，而使第一节点N1为低电平。基于此，该第四晶体管T4可以保持开启状态，将第一时钟信号端CK1的低电平输出至信号输出端OUT。
此时与该移位寄存器单元的信号输出端OUT相连接的栅线接收到上述低电平，并将该低电平作为栅极驱动信号将该栅线相连接的像素电路中的晶体管导通。
在此基础上，在第一节点N1的控制下，第一晶体管T1导通，将第一电压端VGH的高电平输出至第二节点N2。此时第二节点N2控制第二晶体管T2和第六晶体管T6截止。从而可以通过第一晶体管T1在该阶段稳定第二节点N2的电位，避免第二节点N2的电位不稳定使得，第六晶体管T6导通，将第一电压端VGH的高电平误输出至信号输出端OUT。
在一图像帧的第三阶段P3，INT＝1，CK1＝1，CK2＝0，OUT＝1。
在此情况下，第二时钟信号端CK2输入低电平，第五晶体管T5导通，将第二电压端VGL的低电平输出至第二节点N2，并通过存储电容C进行存储。此时该第六晶体管T6和第二晶体管T2导通。基于此，第一电压端VGH的高电平通过第六晶体管T6输出至信号输出端OUT。此外，第二晶体管T2导通，将第一电压端VGH的高电平输出至第一节点N1，此时第一晶体管T1和第四晶体管T4截止。从而可以通过第二晶体管T2在该阶段稳定第一节点N1的电位。
综上所述，只有在第二阶段P2，上述移位寄存器单元的信号输出端输出低电平，从而将像素电路中与该移位寄存器单元的信号输出端OUT相连接的晶体管导通。
此外，在下一图像帧到来之前，即信号输入端INT再次输出低电平之前，在存储电容C的放电作用以及第二时钟信号端CK2的控制下，第六晶体管T6保持开启状态，使得信号输出端OUT保持高电平输出的状态。
本公开实施例提供一种栅极驱动电路，如图5所示，包括多个级联的如上所述的任意一种移位寄存器单元(RS1、RS2……RS(n-1)、RSn)，分别连接栅 线(G1、G2……G(n-1)、Gn)。其中，n为大于2的正整数。
第一级移位寄存器单元RS1的信号输入端INT与起始信号端STV相连接。其中，第一级移位寄存器单元RS1的信号输入端连接起始信号端STV。其中该起始信号端STV用于输入起始信号，从而使得接收该起始信号的栅极驱动电路开始工作。
除了第一级移位寄存器单元RS1以外，上一级移位寄存器单元的信号输出端OUT连接下一级移位寄存器单元的信号输入端INT。
需要说明的是，构成上述栅极驱动电路的移位寄存器单元具有与前述实施例提供的移位寄存器单元相同的结构和有益效果。由于前述实施例已经对移位寄存器单元的结构和有益效果进行了详细的描述，此处不再赘述。
本公开实施例提供一种显示装置，包括如上所述的任意一种栅极驱动电路，具有与前述实施例提供的栅极驱动电路相同的结构和有益效果。由于前述实施例已经对栅极驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
在本公开实施例中，显示装置具体至少可以包括液晶显示装置和有机发光二极管显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。其中，阵列基板的详细结构已在前述实施例中做了详细的描述，此处不再赘述。
本公开实施例提供一种移位寄存器单元的驱动方法，一图像帧内该移位寄存器单元的驱动方法包括：
在一图像帧的第一阶段P1，第一输入电路20向第一节点N1输出信号。在第一节点N1的控制下，第一输出电路30向信号输出端OUT输出第一信号。该稳定电路10对第二节点N2的电位进行稳定，以使得第二输出电路50无信号输出。其中，上述第一信号和第二信号互为高低电平。当与该移位寄存器单元相连接的像素电路的晶体管为P型晶体管时，上述第一信号为高电平，第二信号为低电平。以下为了方便说明，均是以与该移位寄存器单元相连接的像素电路的晶体管为P型晶体管为例。
可选的，例如，如图2所示，当第一输入电路20还连接信号输入端INT时，该第一输入电路20向第一节点N1输出信号包括：第一输入电路20在信号输入端INT的控制下，将信号输入端INT的信号输出至第一节点N1。
此外，当第一输出电路30还连接第一时钟信号端CK1时，该第一输出电路30向信号输出端OUT输出信号包括：第一输出电路30将第一时钟信号端CK1的信号输出至信号输出端OUT。
具体的，当该稳定电路10如图3所示包括第一晶体管T1和第二晶体管T2。第一输入电路10包括第三晶体管T3，所述第一输出电路包括第四晶体管。第二输入电路40包括第五晶体管T5。第二输出电路50包括第六晶体管T6和存储电容C，且上述晶体管均为P型晶体管情况下，在上述第一阶段P1：
信号输入端INT输入低电平，第三晶体管T3导通，信号输入端INT的低电平通过上述第三晶体管T3输出至第一节点N1。在该第一节点N1的控制下，第四晶体管T4导通，并将第一时钟信号端CK1输出的高电平输出至信号输出端OUT。
此外，第二时钟信号端CK2输入低电平，第五晶体管T5导通，第二电压端VGL的低电平通过上述第五晶体管T5输出至第二节点N2。在此情况下，第一晶体管T1和第二晶体管T2的栅极均为低电平，由于第一晶体管T1的宽长比大于第二晶体管T2的宽长比，因此第一晶体管T1优先于第二晶体管T2导通。这样一来，当第一晶体管T1导通时，第一电压端VGH的高电平通过该第一晶体管T1输出至第二节点N2，以使得该第二节点N2为高电平。此时在第二节点N2的控制下，第六晶体管T6和第二晶体管T2保持截止状态。
这样一来，通过上述第一晶体管T1和第二晶体管T2的互锁作用使得第六晶体管T6截止，从而使得信号输出端OUT只接收第一时钟信号端CK1输出的信号。
在一图像帧的第二阶段P2，第一输出电路30保持开启状态，向信号输出端OUT输出第二信号。稳定电路10对第二节点N2的电位进行稳定，以使得第二输出电路50无信号输出。
具体的，信号输入端INT输入高电平，第三晶体管T3截止。通常第四晶体管T4的宽长比较大，因此该第四晶体管T4自身的寄生电容将继续保持上一阶段存储的低电平，而使第一节点N1为低电平。基于此，该第四晶体管T4可以保持开启状态，将第一时钟信号端CK1的低电平输出至信号输出端OUT。此时，与该移位寄存器单元的信号输出端OUT相连接的栅线接收到上述低电平，从而将像素电路中与该栅线相连接的晶体管导通。
在此基础上，在第一节点N1的控制下，第一晶体管T1导通，将第一电压端VGH的高电平输出至第二节点N2。此时第二节点N2控制第二晶体管T2和第六晶体管T6截止。从而可以通过第一晶体管T1在该阶段稳定第二节点N2的电位，避免第二节点N2的电位不稳定使得，第六晶体管T6导通，将第一电压端VGH的高电平误输出至信号输出端OUT。
在一图像帧的第三阶段P3，第二输入电路40向第二节点N2输出信号。在第二节点N2的控制下，第二输出电路50向信号输出端OUT输出第一信号。稳定电路10对第一节点N1的电位进行稳定，以使得第一输出电路30无信号输出。
可选的，例如，如图2所示，当第二输入电路40还连接第二时钟信号端CK2以及第二电压端VGL时，第二输入电路40向第二节点N2输出信号包括：第二输入电路40在第二时钟信号端CK2的控制下，将第二电压端VGL的信号输出至第二节点N2。
当第二输出电路50还连接第一电压端VGH时，该第二输出电路50向信号输出端OUT输出信号包括：第二输出电路50将第二节点N2的电位进行存储， 并在第二节点N2的控制下，将第一电压端VGH的信号输出至信号输出端OUT。
此外，当稳定电路10还连接第一电压端VGH时，稳定电路10稳定第一节点N1或第二节点N2的电位包括：在第一节点N1的控制下，稳定电路10将第一电压端VGH的信号输出至第二节点N2；或在第二节点N2的控制下，稳定电路10将第一电压端VGH的信号输出至第一节点N1。
此外，第二时钟信号端CK2输入低电平，第五晶体管导通，将第二电压端VGL的低电平输出至第二节点N2，并通过存储电容C进行存储。此时，该第六晶体管T6和第二晶体管T2导通。基于此，第一电压端VGH的高电平通过第六晶体管T6输出至信号输出端OUT。此外，第二晶体管T2导通，将第一电压端VGH的高电平输出至第一节点N1，此时第一晶体管T1和第四晶体管T4截止。从而可以通过第二晶体管T2在该阶段稳定第一节点N1的电位。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种移位寄存器单元，包括：
    第一输入电路，与第一节点连接，用于向所述第一节点输出电位信号；
    第一输出电路，与信号输出端以及所述第一节点连接，用于在所述第一节点的控制下，向所述信号输出端输出电位信号；
    第二输入电路，与第二节点连接，所述第二输入电路用于向所述第二节点输出电位信号；
    第二输出电路，与所述信号输出端以及第二节点连接，所述第二输出电路用于在所述第二节点的控制下，向所述信号输出端输出电位信号；
    所述稳定电路连接所述第一节点以及所述第二节点，所述稳定电路用于当所述第一输出电路向所述信号输出端输出电位信号时，稳定所述第二节点的电位，以使得第二输出电路无信号输出；或者，用于当所述第二输出电路向所述信号输出端输出电位信号时，稳定所述第一节点的电位，以使得所述第一输出电路无信号输出。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述稳定电路还连接第一电压端，所述稳定电路用于在所述第一节点的控制下，将所述第一电压端的信号输出至所述第二节点；或在所述第二节点的控制下，将所述第一电压端的信号输出至所述第一节点；
    所述稳定电路包括：第一晶体管和第二晶体管；其中，所述第一晶体管的宽长比大于所述第二晶体管的宽长比；
    所述第一晶体管的栅极连接所述第一节点，第一极连接所述第一电压端，第二极与所述第二节点相连接；
    所述第二晶体管的栅极连接所述第二节点，第一极连接所述第一电压端，第二极与所述第一节点相连接。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述第一输入电路还连接信号输入端，所述第一输入电路用于在所述信号输入端的控制下，将所述信号输入端的电位信号输出至所述第一节点；
    所述第一输入电路包括第三晶体管，所述第三晶体管的栅极和第一极连接所述信号输入端，第二极与所述第一节点相连接。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述第一输出电路还连接所述第一时钟信号端，所述第一输出电路用于在所述第一节点的控制下，将所述第一时钟信号端的信号输出至所述信号输出端；
    所述第一输出电路包括第四晶体管，所述第四晶体管的栅极连接所述第一节点，第一极连接所述第一时钟信号端，第二极与所述信号输出端相连接。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述第二输入电路还连接所述第二时钟信号端以及第二电压端，所述第二输入电路用于在所述第二时钟信 号端的控制下，将所述第二电压端的信号输出至所述第二节点；
    所述第二输入电路包括第五晶体管，所述第五晶体管的栅极连接所述第二时钟信号端，第一极连接所述第二电压端，第二极与所述第二节点相连接。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述第二输出电路还连接所述第一电压端，所述第二输出电路用于在所述第二节点的控制下，将所述第一电压端的信号输出至所述信号输出端；
    所述第二输出电路包括第六晶体管和存储电容；
    所述第六晶体管的栅极连接所述第二节点，第一极连接所述第一电压端，第二极与所述信号输出端相连接；
    所述存储电容的一端连接第一电压端，另一端与所述第二节点相连接。
  7. 一种栅极驱动电路，其中，包括多个级联的如权利要求1-6任一项所述的移位寄存器单元；
    第一级移位寄存器单元的信号输入端与起始信号端相连接；
    除了第一级移位寄存器单元以外，上一级移位寄存器单元的信号输出端连接下一级移位寄存器单元的信号输入端。
  8. 一种显示装置，其中，包括如权利要求7所述的栅极驱动电路。
  9. 一种驱动如权利要求1-6任一项所述的移位寄存器单元的方法，其中，一图像帧内所述移位寄存器单元的驱动方法包括：
    在第一阶段，第一输入电路向所述第一节点输出电位信号；在第一节点的控制下，所述第一输出电路向信号输出端输出第一信号；稳定电路对第二节点的电位进行稳定，以使得第二输出电路无信号输出；
    在第二阶段，第一输出电路保持开启状态，向所述信号输出端输出第二信号；所述稳定电路对第二节点的电位进行稳定，以使得第二输出电路无信号输出；
    在第三阶段，第二输入电路向第二节点输出电位信号；在所述第二节点的控制下，所述第二输出电路向所述信号输出端输出所述第一信号；所述稳定电路对第一节点的电位进行稳定，以使得第一输出电路无信号输出；
    所述第一信号与所述第二信号互为高低电平。
  10. 根据权利要求9所述的移位寄存器单元的驱动方法，其中，当所述稳定电路还连接第一电压端时，所述稳定电路稳定所述第一节点或所述第二节点的电位包括：在所述第一节点的控制下，所述稳定电路将所述第一电压端的信号输出至所述第二节点；或在所述第二节点的控制下，所述稳定电路将所述第一电压端的信号输出至所述第一节点。
  11. 根据权利要求9所述的移位寄存器单元的驱动方法，其中，当所述第一输入电路还连接信号输入端时，所述第一输入电路向所述第一节点输出电位信号包括：所述第一输入电路在所述信号输入端的控制下，将所述电位信号输入端的信号输出至所述第一节点。
  12. 根据权利要求9所述的移位寄存器单元的驱动方法，其中，当所述第一输出电路还连接第一时钟信号端时，所述第一输出电路向信号输出端输出信号包括：在所述第一节点的控制下，所述第一输出电路将所述第一时钟信号端的信号输出至信号输出端。
  13. 根据权利要求9所述的移位寄存器单元的驱动方法，其中，当所述第二输入电路还连接第二时钟信号端以及第二电压端时，所述第二输入电路向第二节点输出信号包括：所述第二输入电路在所述第二时钟信号端的控制下，将所述第二电压端的信号输出至第二节点。
  14. 根据权利要求9所述的移位寄存器单元的驱动方法，其中，当所述第二输出电路还连接所述第一电压端时，所述第二输出电路向所述信号输出端输出信号包括：所述第二输出电路将所述第二节点的电位进行存储，并在所述第二节点的控制下，将第一电压端的信号输出至所述信号输出端。
  15. 根据权利要求9所述的移位寄存器单元的驱动方法，其中，当所述稳定电路还连接第一电压端，所述第一输入电路还连接信号输入端，所述第一输出电路还连接第一时钟信号端，所述第二输入电路还连接第二时钟信号端以及第二电压端，所述第二输出电路还连接所述第一电压端时；且当所述稳定电路包括第一晶体管和第二晶体管，所述第一输入电路包括第三晶体管，所述第一输出电路包括第四晶体管，所述第二输入电路包括第五晶体管，所述第二输出电路包括第六晶体管和存储电容；且上述晶体管均为P型晶体管的情况下，一图像帧内所述移位寄存器单元的驱动方法包括：所述第二电压端输入低电平，所述第一电压端输入高电平；
    在第一阶段，所述信号输入端和所述第二时钟信号端输入低电平，所述第一时钟信号端输入高电平；
    所述第四晶体管、所述第三晶体管、所述第五晶体管以及所述第一晶体管导通，其余晶体管截止；所述第一时钟信号端的信号通过所述第四晶体管输出至所述信号输出端；
    在第二阶段，所述信号输入端和所述第二时钟信号端输入高电平，所述第一时钟信号端输入低电平；
    所述第四晶体管、所述第一晶体管导通，其余晶体管截止；所述第一时钟信号端的信号通过所述第四晶体管输出至所述信号输出端；
    在第三阶段，所述信号输入端和所述第一时钟信号端输入高电平，所述第二时钟信号端输入低电平；
    所述第五晶体管、所述第二晶体管以及所述第六晶体管导通，其余晶体管截止；所述第一电压端的信号通过所述第六晶体管输出至所述信号输出端。
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