WO2018152769A1 - 晶体振荡器及其控制电路 - Google Patents

晶体振荡器及其控制电路 Download PDF

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Publication number
WO2018152769A1
WO2018152769A1 PCT/CN2017/074766 CN2017074766W WO2018152769A1 WO 2018152769 A1 WO2018152769 A1 WO 2018152769A1 CN 2017074766 W CN2017074766 W CN 2017074766W WO 2018152769 A1 WO2018152769 A1 WO 2018152769A1
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Prior art keywords
signal
oscillating
circuit
amplifier
peak
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PCT/CN2017/074766
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English (en)
French (fr)
Inventor
张孟文
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/074766 priority Critical patent/WO2018152769A1/zh
Priority to CN201780000079.XA priority patent/CN108781056B/zh
Publication of WO2018152769A1 publication Critical patent/WO2018152769A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/06—Modifications of generator to ensure starting of oscillations

Definitions

  • Embodiments of the present invention relate to the field of circuit technologies, and in particular, to a crystal oscillator and a control circuit thereof.
  • the crystal oscillator has no input signal, but only provides a driving signal to the crystal oscillator during the start-up phase, and then the crystal oscillator enters the oscillation stabilization phase.
  • the driving signal for maintaining the oscillation is small, which is about the start-up phase.
  • the required drive signal is on the order of 1/10. Therefore, it is necessary to reduce the driving ability of the driving signal of the start-up phase after entering the oscillation stabilization phase to further reduce the power consumption of the stable oscillation phase.
  • the MOS transistor M2, the capacitor C1, the capacitor C2 and the crystal constitute an oscillating circuit for generating an oscillating signal Vxi or Vxo;
  • the MOS transistor M3, the capacitor C3, and the resistor R1 constitute an amplitude detecting circuit for detecting an amplitude of the oscillating signal Vxi or Vxo;
  • the capacitor C5, the capacitor C4 and the resistor R2 form a low-pass filter for filtering the AC component of the output signal of the amplifier M3 to retain only the DC component;
  • the MOS transistor M4 and the resistor R3 form a transconductance circuit for converting the DC voltage into a DC current.
  • the MOS transistor M5 serves as a bias circuit for converting the output current of the MOS transistor M4 into a bias voltage;
  • the MOS transistors M6 and M1 function as a current mirror circuit for mirroring the current flowing through the MOS transistor M5.
  • the oscillation amplitude of the oscillation signal Vxi of the crystal oscillator is gradually increased, so that the crystal oscillator enters the start-up phase.
  • the average value of the output signal of the MOS transistor M3 is reduced, and then the capacitor C5, the capacitor C4,
  • the low-pass filter formed by the resistor R2 removes the amount of alternating current in the output signal of the MOS transistor M3, and only retains the direct current amount, which is transmitted to the gate of the MOS transistor M4, so that the MOS transistor generates a linear output signal when the direct current amount Transmitted to the voltage of the gate of MOS transistor M4 Down, the current of the MOSFET M4 source to ground drops, further causing the MOS transistor M5 to reduce the current from the drain to the ground; since the MOS transistor M1 and the MOS transistor M5 are mirror images, the gate signal input to the MOS transistor M1 Also weakened, further causing the MOS tube source-to-ground current to be smaller, so that the oscillating signal V
  • the drain of the MOS transistor M3 is pulled to the ground, thereby causing a short circuit between the gate and the drain of the MOS transistor, thereby eventually causing the source of the MOS transistor M3.
  • the ground current is also 0, and the drain-to-ground current of the MOS transistor is also 0; and when the amplitude of the oscillating signal Vxi starts to increase, the ground current of the MOS transistor M6 is still reduced, and the entire circuit enters positive feedback, making the whole The oscillating circuit cannot be started and cannot enter the oscillation stabilization phase.
  • an embodiment of the present invention provides a crystal oscillator control circuit, including:
  • a peak detecting unit for detecting a peak value of an oscillation signal of an oscillation circuit of the crystal oscillator
  • a voltage control unit configured to generate a driving signal according to a peak value of the oscillating signal of the oscillating circuit and a reference signal, wherein the driving signal is used to oscillate the oscillating circuit and enter an oscillation stabilization phase, and an amplitude of the driving signal The oscillation circuit is lowered after entering the oscillation stabilization phase.
  • the peak detecting unit includes:
  • a first amplifier configured to receive an oscillating signal of the oscillating circuit and an output signal of the peak detecting unit
  • a first switch when the oscillating signal of the oscillating circuit is greater than an output signal of the peak detecting unit, the first switch is turned on, so that an output signal of the peak detecting unit follows an oscillating signal of the oscillating circuit The peak value of the oscillating signal is detected.
  • the positive phase end of the first amplifier receives an oscillating signal of the oscillating circuit
  • the negative phase end of the first amplifier receives an output signal of the peak detecting unit
  • the peak detecting unit further includes: a first bleed a capacitor and a first current source, wherein when the oscillating signal of the oscillating circuit is smaller than an output signal of the peak detecting unit, the first current source is configured to bleed charge stored in the first bleed capacitor The output signal of the peak detecting unit is reset such that an output signal of the peak detecting unit follows an oscillating signal of the oscillating circuit to detect a peak value of the oscillating signal.
  • the peak detecting unit includes a second amplifier, a third amplifier, and a second switch, and a voltage dividing resistor is disposed between the second amplifier and the third amplifier, a positive phase terminal of the second amplifier receives an oscillating signal of the oscillating circuit, the second switch is disposed between a positive phase terminal and an inverting terminal of the second amplifier, and an inverting terminal of the third amplifier receives the An output signal of the peak detecting unit, when the oscillating signal of the oscillating circuit is greater than an input signal of the voltage dividing resistor, the second switch is turned on, so that an output signal of the peak detecting unit follows the oscillating circuit The oscillating signal detects the peak of the oscillating signal.
  • the peak detecting unit further includes: a third switch, a second bleeder capacitor, and a second current source, wherein the third switch is disposed at the positive of the second amplifier Between the phase end and the inverting terminal, when the oscillating signal of the oscillating circuit is greater than the input signal of the voltage dividing resistor, the second switch is turned off, the third switch is turned on, and the second current source is The charge stored in the second bleeder capacitor is bleed such that an output signal of the peak detecting unit follows an oscillating signal of the oscillating circuit to detect a peak value of the oscillating signal.
  • the method further includes: a difference unit, configured to calculate a difference signal between a peak of the oscillating signal of the oscillating circuit and a reference signal, according to the oscillating A difference signal between the peak of the oscillating signal of the circuit and the reference signal generates a drive signal.
  • a difference unit configured to calculate a difference signal between a peak of the oscillating signal of the oscillating circuit and a reference signal, according to the oscillating A difference signal between the peak of the oscillating signal of the circuit and the reference signal generates a drive signal.
  • the method further includes: a control unit, configured to generate a control signal according to a difference signal between a peak of the oscillating signal of the oscillating circuit and the reference signal, and correspondingly, the voltage
  • the control unit generates the drive signal according to the control signal.
  • the difference unit is a differential amplifier, and the differential amplifier is configured to calculate a difference signal between a peak value of the oscillating signal of the oscillating circuit and a reference signal, where the control
  • the unit is an integrating capacitor that is disposed between an inverting end and an output end of the differential amplifier, and the integrating capacitor is used to integrate the difference signal to generate a control signal.
  • the difference unit is a transconductance amplifier, and the transconductance amplifier is configured to calculate a difference signal between a peak value of the oscillating signal of the oscillating circuit and a reference signal;
  • the control unit is an integrating capacitor, and the integrating capacitor is disposed at an output of the transconductance amplifier Between the end and the ground, the integrating capacitor is used to integrate the difference signal to generate a control signal.
  • the transconductance amplifier includes the transconductance amplifier including a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, the first PMOS a gate of the tube is connected to the output signal of the peak detecting unit, a gate of the second PMOS transistor is connected to the reference signal, and a source of the first PMOS transistor and a source of the second PMOS transistor are respectively connected to the power source a voltage connection, a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor, and a drain of the second PMOS transistor is connected to a drain of the second PMOS transistor and serves as a terminal for outputting the control signal, a gate of the first NMOS transistor is connected to a gate of the second NMOS transistor, a source of the first NMOS transistor and a source of the second NMOS transistor are respectively connected to the ground, and a gate of the first PNMOS transistor is connected To the drain of the first PMOS transistor, a second PMOS
  • Embodiments of the present invention also provide a crystal oscillator including a crystal and a control circuit connected to the crystal, the control circuit being the control circuit described in any of the above embodiments.
  • the peak value of the oscillation signal of the oscillation circuit of the crystal oscillator is detected by the peak detecting unit; the voltage control unit generates a driving signal according to the peak value of the oscillation signal of the oscillation circuit and a reference signal, and the driving signal is used for
  • the oscillating circuit is oscillated and enters an oscillation stabilization phase, and the amplitude of the driving signal is lowered after the oscillating circuit enters an oscillation stabilization phase, thereby preventing the entire circuit from entering positive feedback, so that the oscillator can be normally started, and then enter The oscillation stabilization phase.
  • Embodiment 1 is a structural block diagram of a peak detecting unit in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a specific circuit of a peak detecting unit according to Embodiment 2 of the present invention.
  • FIG. 3 is a structural block diagram of a peak detecting unit according to Embodiment 3 of the present invention.
  • FIG. 4 is a schematic structural diagram of a specific circuit of a peak detecting unit according to Embodiment 4 of the present invention.
  • FIG. 5 is a schematic structural diagram of a combination of a differential unit and a control unit according to Embodiment 5 of the present invention.
  • FIG. 6 is a schematic structural diagram of a combination of a difference unit and a control unit according to Embodiment 6 of the present invention.
  • FIG. 7 is a schematic structural diagram of a combination of a difference unit and a control unit according to Embodiment 7 of the present invention.
  • FIG. 8 is a schematic structural diagram of a transconductance amplifier according to Embodiment 8 of the present invention.
  • FIG. 9 is a schematic structural diagram of a voltage control unit according to Embodiment 9 of the present invention.
  • FIG. 10 is a schematic block diagram of a crystal oscillator according to Embodiment 10 of the present invention.
  • FIG. 11 is a schematic structural diagram of a crystal oscillator according to Embodiment 11 of the present invention.
  • Embodiment 12 is a schematic waveform diagram of each signal in Embodiment 12 of the present invention.
  • FIG. 13 is a schematic structural diagram of a crystal oscillator according to Embodiment 13 of the present invention.
  • Fig. 14 is a diagram showing an exemplary oscillation circuit structure in the prior art.
  • the oscillator control circuit in the following embodiments of the present invention includes: a voltage control unit for detecting a peak value of an oscillation signal of the oscillation circuit, and a peak detection unit for using the oscillation circuit according to the oscillation circuit
  • the peak of the oscillating signal and the reference signal generate a drive signal that causes the oscillating circuit to oscillate and enter an oscillation stabilization phase, and the amplitude of the drive signal decreases after the oscillating circuit enters an oscillation stabilization phase.
  • FIG. 1 is a structural block diagram of a peak detecting unit according to Embodiment 1 of the present invention; as shown in FIG. 1, the first amplifier 101, the first switch 102, the first bleeder capacitor 103, and the first current source 104 are The first amplifier 101 is configured to receive an oscillating signal of the oscillating circuit and an output signal of the peak detecting unit. Specifically, for example, an oscillating signal of the oscillating circuit is received by a positive phase end of the first amplifier 101, the first amplifier 101 The inverting terminal receives the output signal of the peak detecting unit.
  • the first switch 102 When the oscillating signal of the oscillating circuit is greater than the output signal of the peak detecting unit, the first switch 102 is turned on, and the first bleeder capacitor 103 is in a charging phase, so that the output signal of the peak detecting unit follows the oscillation
  • the oscillating signal of the circuit detects the peak of the oscillating signal.
  • the first current source 104 is configured to bleed charge stored in the first bleed capacitor 103 to reset the peak detection when an oscillating signal of the oscillating circuit is smaller than an output signal of the peak detecting unit
  • the output signal of the unit is such that an output signal of the peak detecting unit follows an oscillating signal of the oscillating circuit to detect a peak value of the oscillating signal.
  • FIG. 2 is a schematic structural diagram of a specific circuit of a peak detecting unit according to Embodiment 2 of the present invention, which is visible A specific implementation of the embodiment shown in FIG. 1; as shown in FIG. 2, the first switch 102 can select an NMOS transistor, and correspondingly, the relationship between each circuit structural component in the peak detecting unit is as follows:
  • the first phase of the first amplifier 101 receives the oscillation signal Vxi of the oscillation circuit, the inverting terminal of the first amplifier 101 receives the output signal Vpd of the peak detection unit;
  • the gate of the NMOS transistor as the first switch 102 is connected to the output terminal of the first amplifier 101, the drain terminal of the NMOS transistor is connected to the voltage source Vdd, and the source of the NMOS transistor serves as the output end of the output signal Vpd;
  • One end formed by the parallel connection of the first bleeder capacitor 103 and the first current source 104 is connected to the source of the NMOS transistor, and the other end formed in parallel is connected to the ground Vgnd.
  • the oscillating signal of the oscillating circuit is small to large, and the oscillating signal to the oscillating circuit is greater than the output signal, and the NMOS transistor as the first switch 102 is turned on, so that the first bleeder capacitor 103 is in a charging state, as the first switch 102
  • the NMOS transistor has a strong pull-up capability, and the output signal is gradually increased until the magnitude of the oscillating signal of the oscillating circuit is approximately equal, thereby realizing that the output signal of the peak detecting unit follows the oscillating circuit.
  • the NMOS transistor as the first switch 102 is turned off.
  • the first bleeder capacitor 103 is in a discharging state, and the first vent is discharged.
  • the charge stored in the discharge capacitor 103 is specifically discharged through the first current source 104 such that the output signal becomes small, but since the NMOS transistor as the first switch 102 has a weak pull-down capability, the output signal becomes The output signal is reset to be approximately equal to the magnitude of the oscillating signal of the oscillating circuit, thereby achieving an output signal of the peak detecting unit following the oscillating signal of the oscillating circuit.
  • the peak value of the oscillating signal is detected.
  • the first switch 102 may also be a PMOS transistor.
  • the negative phase end of the first amplifier 101 can receive the oscillating signal Vxi of the oscillating circuit, which is widely used as long as it is first.
  • the switch 102 can be deformed by any circuit that forms negative feedback with the first amplifier 101, and details are not described herein again.
  • FIG. 3 is a structural block diagram of a peak detecting unit according to Embodiment 3 of the present invention; as shown in FIG. 3, the second amplifier 301, the third amplifier 302, the second switch 303, the third switch 304, and the second bleeder capacitor are included in FIG.
  • a first voltage dividing resistor 307 is disposed between the inverting terminal of the second amplifier 301 and the inverting terminal of the third amplifier 302, and the first voltage dividing resistor 307 is disposed between the second amplifier 301
  • the positive phase terminal receives the oscillation signal of the oscillation circuit
  • the second switch 303 is disposed between the positive phase terminal and the inverting terminal of the second amplifier 301
  • the inverting terminal of the third amplifier 302 receives the The output signal of the peak detecting unit, when the oscillating signal of the oscillating circuit is greater than the input signal of the first voltage dividing resistor 307, the second switch 303 is turned on, and the second bleeder capacitor 305 is in the charging phase, so that The input signal of the positive terminal of the three amplifiers 302 is increased until the input signal of the first voltage dividing resistor 307, the output signal of the peak detecting unit, and the input signal of the positive terminal of the third amplifier 302 are equal
  • the input signal of the positive phase of the amplifier 302 is increased, thereby finally realizing that the output signal of the peak detecting unit follows the oscillating signal of the oscillating circuit to detect the peak value of the oscillating signal.
  • the output signal of the second amplifier is decreased, the second switch 303 is turned off, and the third switch 304 is turned on.
  • the input signal of the first voltage dividing resistor 307 follows the oscillation signal of the oscillating circuit, and the input signal of the first voltage dividing resistor 307 is kept equal to the oscillating signal of the oscillating circuit, and the peak detection is caused by the cutoff of the second switch 303.
  • the output signal of the unit maintains the input signal of the positive phase terminal of the third amplifier, thereby finally realizing that the output signal of the peak detecting unit follows the oscillation signal of the oscillation circuit to detect the peak value of the oscillation signal.
  • FIG. 4 is a schematic structural diagram of a specific circuit of a peak detecting unit according to Embodiment 4 of the present invention, which can be regarded as a specific implementation manner of the embodiment shown in FIG. 3.
  • the second switch 303 is schematically a first diode
  • the third switch 304 is schematically a second diode; correspondingly, the connection relationship of each circuit structural component in the peak detecting unit is as follows:
  • the positive phase terminal of the second amplifier 301 receives the oscillation signal Vxi of the oscillation circuit, and the first voltage dividing resistor 307 is disposed between the second amplifier 302, for example, as the inverse of the inverting terminal of the second amplifier 301 and the third amplifier 302
  • the first voltage dividing resistor 307 is disposed between the phase ends.
  • the inverting terminal of the second amplifier 301 is connected to one end of the first voltage dividing resistor 307 and connected to the anode of the third switch 304, and the output terminal of the second amplifier 301 is connected to the anode of the second switch 303 and is connected to the third terminal.
  • the negative pole of the switch 304 is connected;
  • the positive phase of the third amplifier 302 is connected to the negative terminal of the second switch 303, the negative phase of the third amplifier 302 is connected to the other end of the first voltage dividing resistor 307, and the output of the third amplifier 302 is used as the output of the peak detecting unit. End, output the output signal Vpd of the peak detecting unit;
  • An end formed by the second bleeder capacitor 305 in parallel with the second current source 306 is connected between the negative terminal of the second switch 303 and the positive phase terminal of the third amplifier 302, and the other end formed in parallel is connected to the ground Vgnd.
  • the peak detection circuit of this embodiment works as follows:
  • the second switch 303 When the oscillating signal Vxi of the oscillating circuit is greater than the input signal Vfb of the first voltage dividing resistor 307, the second switch 303 is turned on, and the second bleeder capacitor 305 is in a charging phase, so that the third amplifier 302 is in the positive phase.
  • the input signal Vh of the terminal is increased until the input signal Vfb of the first voltage dividing resistor 307, the output signal Vpd of the peak detecting unit, and the input signal Vh of the positive terminal of the third amplifier 302 are equal.
  • the third amplifier The input signal Vh of the 302 positive phase terminal is increased, thereby finally realizing that the output signal of the peak detecting unit follows the oscillation signal of the oscillation circuit to detect the peak value of the oscillation signal.
  • the input signal Vfb of the first voltage dividing resistor 307 follows the oscillating signal Vxi of the oscillating circuit, and the input signal Vfb of the first voltage dividing resistor 307 is kept equal to the oscillating signal Vxi of the oscillating circuit, due to the second
  • the off of the switch 303 is such that the output signal Vpd of the peak detecting unit maintains the input signal Vh of the positive phase terminal of the third amplifier, thereby finally realizing that the output signal of the peak detecting unit follows the oscillating signal of the oscillating circuit to oscillate the oscillating signal The peak value is detected.
  • the crystal oscillator control circuit may further include a difference unit for calculating a difference signal between a peak value of the oscillation signal of the oscillation circuit and the reference signal, according to The difference signal between the peak of the oscillating signal of the oscillating circuit and the reference signal generates a driving signal.
  • the crystal oscillator control circuit may further include: a control unit configured to generate a control signal according to a difference signal between a peak value of the oscillation signal of the oscillation circuit and the reference signal, correspondingly And the voltage control unit generates a driving signal according to the control signal generated by the difference signal between the peak value of the oscillation signal and the reference signal.
  • FIG. 5 is a schematic structural diagram of a combination of a differential unit and a control unit according to Embodiment 5 of the present invention; as shown in FIG. 5, the differential unit is a transconductance amplifier 501, and the transconductance amplifier 501 is used to calculate the vibration. a difference signal between a peak of the oscillating signal of the swash circuit and the reference signal, the control unit being an integrating capacitor Ci, the integrating capacitor Ci being disposed between the inverting end and the output end of the transconductance amplifier, The integrating capacitor Ci is used to integrate the difference signal to generate a control signal.
  • the non-inverting terminal of the transconductance amplifier 501 is connected to the output signal Vpd of the peak detecting unit, and the negative phase terminal of the transconductance amplifier 501 is connected to the reference signal Vr, and the transconductance amplifier 501 is used to
  • An integrating capacitor Ci is connected between a negative phase terminal of the transconductance amplifier 501 and an output terminal of the transconductance amplifier 501, and the integrating capacitor Ci integrates an output signal I of the transconductance amplifier output, thereby Finally, a control signal Vc is generated.
  • FIG. 6 is a schematic diagram of a combined structure of a difference unit and a control unit according to Embodiment 6 of the present invention; as shown in FIG. 6 , in the embodiment, the difference unit is specifically a differential amplifier 502, which is negative. The phase end is connected to one end of the second voltage dividing resistor 503 to receive the output signal Vfb of the second voltage dividing resistor 503, and the other end of the second voltage dividing resistor 503 receives the reference signal Vr, and the control unit is specifically an integrating capacitor Ci.
  • the difference unit is specifically a differential amplifier 502, which is negative.
  • the phase end is connected to one end of the second voltage dividing resistor 503 to receive the output signal Vfb of the second voltage dividing resistor 503, and the other end of the second voltage dividing resistor 503 receives the reference signal Vr
  • the control unit is specifically an integrating capacitor Ci.
  • the differential amplifier 502 forms a negative feedback through the integrating capacitor Ci, so that the positive phase terminal and the negative phase terminal of the differential amplifier 502 are in a virtual short state, so that the signal difference between the second voltage dividing resistor 503 is the peak detecting unit.
  • a difference between the output signal Vpd and the reference signal Vr received at the other end of the second voltage dividing resistor 503, so that the oscillating signal of the oscillating circuit is calculated by the differential amplifier 502 together with the second voltage dividing resistor 503
  • the difference signal between the peak value and the reference signal Vr is further converted into the output signal I by the second voltage dividing resistor 503, and then integrated by the integrating capacitor Ci to obtain the control signal Vc.
  • FIG. 7 is a schematic structural diagram of a combination of a differential unit and a control unit according to Embodiment 7 of the present invention; as shown in FIG. 7, the differential unit is a transconductance amplifier 501, and the transconductance amplifier 501 is configured to calculate an oscillation of the oscillation circuit. a difference signal between the peak of the signal and the reference signal; the control unit being an integrating capacitor Ci, the integrating capacitor Ci being disposed between an output of the transconductance amplifier 501 and ground, the integrating capacitor Ci being used The difference signal is subjected to integration processing to generate a control signal Vc.
  • the positive phase terminal of the transconductance amplifier 501 receives the output signal Vpd of the peak detecting unit
  • the negative phase terminal of the transconductance amplifier 501 receives the reference signal Vr
  • the peak is passed through the transconductance amplifier 501.
  • FIG. 8 is a schematic structural diagram of a transconductance amplifier according to Embodiment 8 of the present invention; as shown in FIG. 8, the first PMOS transistor 811, the second PMOS transistor 821, the first NMOS transistor 831, and the second NMOS transistor 841 are described.
  • the gate of the first PMOS transistor 811 is connected to the output signal Vpd of the peak detecting unit
  • the gate of the second PMOS transistor 821 is connected to the reference signal Vr, the source of the first PMOS transistor 811, and the second PMOS.
  • the source of the transistor 821 is connected to the power supply voltage Vdd
  • the drain of the first PMOS transistor 811 is connected to the drain of the first NMOS transistor 831, the drain of the second PMOS transistor 821 and the drain of the second NMOS transistor 841.
  • a gate of the first NMOS transistor 831 is connected to a gate of the second NMOS transistor 841, a source of the first NMOS transistor 831, and a second NMOS transistor
  • the sources of 841 are respectively connected to the ground Vgd
  • the gate of the first NMOS transistor 831 is connected to the drain of the first PMOS transistor 811.
  • a voltage control unit is specifically a PMOS transistor M4, and a source receiving voltage of a PMOS transistor as the voltage control unit is shown.
  • the source VDD receives the control signal Vc in the above embodiment as the gate of the PMOS transistor of the voltage control unit, and the drain of the PMOS transistor as the voltage control unit is connected to the driving unit of the oscillation circuit for forming a negative feedback. In order to control the output signal of the driving unit, and finally realize the control of the driving signal of the oscillating circuit.
  • FIG. 10 is a schematic block diagram of a crystal oscillator according to Embodiment 10 of the present invention; as shown in FIG. 10, the method includes: a differential unit 1001, a control unit 1002, a voltage control unit 1003, an oscillation circuit 1004, a peak detection circuit 1005, and each module unit.
  • a differential unit 1001 a control unit 1002
  • a voltage control unit 1003 a voltage control unit 1003
  • an oscillation circuit 1004 a peak detection circuit 1005
  • each module unit for detailed functions, refer to the above embodiments, and details are not described herein again.
  • the difference unit 1001 can select any of the above-mentioned difference units in FIG. 5-7.
  • the control unit 1002 can refer to the description of FIG. 5-7 above.
  • the voltage control unit 1003 can refer to the above-mentioned FIG. 9, and the oscillation circuit 1004 and the peak detection circuit 1005 can be used. Refer to the related description in the above embodiments, and details are not described herein again.
  • FIG. 11 is a schematic structural diagram of a crystal oscillator according to Embodiment 11 of the present invention; as shown in FIG. 11, it includes the same peak detecting unit 1005 as the peak detecting unit shown in FIG. 2, and the same difference as the differential unit in FIG. Unit 1001, the same control unit 1002 as the control unit in FIG. 5, and a diagram
  • the voltage control unit of 9 has the same voltage control unit 1003.
  • the connection relationship of the internal components of each circuit structural unit is not described again, and only the connection relationship between the respective circuit structural units of the crystal oscillator is as follows:
  • the output end of the peak detecting unit 1005 is connected to the positive phase end of the differential unit 1001, so that the positive phase end of the differential unit 1001 can receive the output signal Vpd of the peak detecting unit 1005, and the capacitance Ch in the figure is the above-mentioned FIG. First bleeder capacitor 103;
  • An output end of the combination structure of the difference unit 1001 and the control unit 1002 is connected to a gate of a PMOS tube as the voltage control unit 1003;
  • the driving transistor M1 as a driving circuit such as the source of the PMOS transistor, is connected to the drain of the PMOS transistor as the voltage control unit 1003, and the driving transistor of the driving circuit, such as the gate of the PMOS transistor, receives a bias voltage Vb as a driving circuit.
  • a driving transistor such as a drain of the PMOS transistor is connected to an input end of the oscillating circuit 1004;
  • the oscillating circuit 1004 is illustratively a Pierce oscillating circuit 1004 structure, which specifically includes an oscillating transistor such as an NMOS transistor, a crystal placed between the drain and the gate of the oscillating transistor, and two filter capacitors C1 and C2.
  • the Pierce oscillating circuit 1004 has a detailed structure. No longer.
  • FIG. 12 is a schematic diagram of waveforms of signals in the twelfth embodiment of the present invention. referring to the waveforms of FIG. 12, the crystal oscillator in FIG. 11 works as follows:
  • the control signal is 0, the oscillation circuit starts to oscillate, the drive signal and the oscillation signal Vxi of the oscillation circuit gradually increase, and the output signal Vpd of the peak detection unit also increases, and the output signal Vpd of the peak detection unit and the reference signal Vr
  • the difference signal ⁇ V gradually becomes smaller until the output signal Vpd of the peak detecting unit is greater than the reference signal Vr, and a corresponding output signal I is generated at the output end of the differential unit, and then the integration signal is integrated to make the control signal Vc gradually increase.
  • the channel resistance of the PMOS transistor as the voltage control unit gradually increases, thereby increasing the source-to-ground voltage feedback of the PMOS transistor as the driving unit, so that the PMOS transistor as the driving unit
  • the output current of the drain terminal is reduced, so that the drive signal outputted from the drain terminal of the PMOS transistor as the driving unit is reduced, eventually causing the oscillation signal Vxi of the oscillation circuit to be reduced.
  • FIG. 13 is a schematic structural diagram of a crystal oscillator according to Embodiment 13 of the present invention; as shown in FIG. 13, the same peak detecting unit 1005 as the peak detecting unit shown in FIG. 4 and the same differential unit as the differential unit in FIG. 6 are included. 1001, the same control unit 1002 as the control unit of FIG. 6, and the same voltage control unit 1003 as the voltage control unit of FIG. In this embodiment, the connection relationship of the internal components of each circuit structural unit is not described again, and only the specific circuit structural units of the crystal oscillator are specifically described. The connection relationship is as follows:
  • the output end of the peak detecting unit 1005 is connected to the positive phase end of the differential unit 1001, so that the positive phase end of the differential unit 1001 can receive the output signal Vpd of the peak detecting unit 1005, and the capacitance Ch in the figure is the above-mentioned FIG. Second bleeder capacitor 305;
  • An output end of the combination structure of the difference unit 1001 and the control unit 1002 is connected to a gate of a PMOS tube as the voltage control unit 1003;
  • the driving transistor M1 as a driving circuit such as the source of the PMOS transistor, is connected to the drain of the PMOS transistor as the voltage control unit 1003, and the driving transistor of the driving circuit, such as the gate of the PMOS transistor, receives a bias voltage Vb as a driving circuit.
  • a driving transistor such as a drain of the PMOS transistor is connected to an input end of the oscillating circuit 1004;
  • the oscillating circuit 1004 is illustratively a Pierce oscillating circuit 1004 structure, which specifically includes an oscillating transistor such as an NMOS transistor, a crystal placed between the drain and the gate of the oscillating transistor, and two filter capacitors C1 and C2.
  • the Pierce oscillating circuit 1004 has a detailed structure. No longer.
  • the apparatus provided by the embodiments of the present application can be implemented by a computer program.
  • Those skilled in the art should be able to understand that the foregoing unit and module division manners are only one of a plurality of division manners. If the division is other units or modules or does not divide the blocks, as long as the information object has the above functions, it should be in the present application. Within the scope of protection.
  • embodiments of the present application can be provided as a method, apparatus (device), or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • These computer program instructions can also be stored in a bootable computer or other programmable data processing device.
  • a computer readable memory that operates in a particular manner, causing instructions stored in the computer readable memory to produce an article of manufacture comprising an instruction device implemented in one or more flows and/or block diagrams of the flowchart The function specified in the box or in multiple boxes.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种晶体振荡器及其控制电路，其包括：峰值检测单元（1005），用于检测晶体振荡器的振荡电路（1004）的振荡信号的峰值；压控单元（1003），用于根据所述振荡电路（1004）的振荡信号的峰值与一参考信号生成驱动信号，所述驱动信号用于使所述振荡电路（1004）起振并进入振荡稳定阶段，且所述驱动信号的振幅在所述振荡电路（1004）进入振荡稳定阶段之后降低，从而可使得振荡器正常启动，继而进入振荡稳定阶段。

Description

晶体振荡器及其控制电路 技术领域
本发明实施例涉及电路技术领域，尤其涉及一种晶体振荡器及其控制电路。
背景技术
晶体振荡器没有输入信号，只是在起振阶段向晶体振荡器提供了一个驱动信号，随后晶体振荡器进入振荡稳定阶段，而在振荡稳定阶段，维持振荡的驱动信号较小，约为起振阶段所需驱动信号的1/10量级。因此，当进入振荡稳定阶段之后需要对起振阶段的驱动信号的驱动能力进行减小处理，以进一步减小稳定振荡阶段的功耗。
现有技术中，为了对起振阶段的驱动信号的驱动能力进行减小处理引入了振荡电路振幅的检测机制，进而通过反馈机制控制驱动信号的驱动能力，为此形成的现有技术中的示例性振荡电路结构具体如图14所示。图14所示振荡电路结构如下：
MOS管M2、电容C1、电容C2和晶体组成振荡电路，用于产生提供振荡信号Vxi或Vxo；MOS管M3、电容C3、电阻R1组成振幅检测电路，用于检测振荡信号Vxi或Vxo的振幅；电容C5、电容C4以及电阻R2组成低通滤波器，用于滤除放大器M3输出信号中交流分量只保留直流分量；MOS管M4、电阻R3组成跨导电路，用于将直流电压转换成直流电流；MOS管M5作为偏置电路，用于将MOS管M4输出电流转换成偏置电压；MOS管M6、M1作为电流镜电路，用于按比例镜像流过MOS管M5的电流。
上述示例性振荡电路的缺陷分析如下：
晶体振荡器的振荡信号Vxi振荡幅度逐渐增加使得晶体振荡器进入起振阶段，通过MOS管M3的处理之后，使得MOS管M3的输出信号的平均值会减小，再经过电容C5、电容C4、电阻R2构成的低通滤波器去除了MOS管M3的输出信号中的交流量，只保留了直流量，该直流量传输到MOS管M4的栅极，使得MOS管产生线性的输出信号，当直流量传输到MOS管M4的栅极的电压下 降，MOS管M4源极到地的电流下降，进一步导致MOS管M5从漏极对地电流也减小；由于MOS管M1与MOS管M5是镜像关系，因此输入到MOS管M1的栅极信号也减弱，进一步导致MOS管源极对地电流较小，从而使得振荡信号Vxi较小；同理，MOS管M6漏极对地电流减小，进一步导致MOS管M3漏极对地电流减小，从而降低了图14的晶体振荡器的功耗。
但是，如果MOS管M6的对地电流减小直至0，导致MOS管M3的漏极被拉到地，进而导致MOS管的栅极与漏极之间短路，从而最终导致MOS管M3的源极对地电流也为0，同理MOS管的漏极对地电流也为0；而当振荡信号Vxi的幅度开始增加，MOS管M6的对地电流仍然减小，整个电路进入正反馈，使得整个振荡电路无法启动，继而无法进入振荡稳定阶段。
发明内容
本发明实施例的目的在于提供一种晶体振荡器及其控制电路，用以至少解决现有技术中的上述问题。
为实现本发明实施例的目的，本发明实施例提供了一种晶体振荡器控制电路，其包括：
峰值检测单元，用于检测晶体振荡器的振荡电路的振荡信号的峰值；
压控单元，用于根据所述振荡电路的振荡信号的峰值与一参考信号生成驱动信号，所述驱动信号用于使所述振荡电路起振并进入振荡稳定阶段，且所述驱动信号的振幅在所述振荡电路进入振荡稳定阶段之后降低。
可选地，在本发明的一实施例中，所述峰值检测单元包括：
第一放大器，用于接收所述振荡电路的振荡信号以及所述峰值检测单元的输出信号；
第一开关，在所述振荡电路的振荡信号大于所述峰值检测单元的输出信号时，所述第一开关导通，以使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
可选地，在本发明的一实施例中，所述第一放大器的正相端接收所述振荡电路的振荡信号，所述第一放大器的负相端接收所述峰值检测单元的输出信号。
可选地，在本发明的一实施例中，所述峰值检测单元还包括：第一泄放 电容以及第一电流源，在所述振荡电路的振荡信号小于所述峰值检测单元的输出信号时，所述第一电流源用于对所述第一泄放电容中存储的电荷进行泄放以复位所述峰值检测单元的输出信号，使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
可选地，在本发明的一实施例中，所述峰值检测单元包括第二放大器、第三放大器、第二开关，所述第二放大器和第三放大器之间设置有分压电阻，所述第二放大器的正相端接收所述振荡电路的振荡信号，所述第二开关设置在所述第二放大器的正相端和反相端之间，所述第三放大器的反相端接收所述峰值检测单元的输出信号，当所述振荡电路的振荡信号大于所述分压电阻的输入信号时，所述第二开关导通，以使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
可选地，在本发明的一实施例中，所述峰值检测单元还包括：第三开关、第二泄放电容以及第二电流源，所述第三开关设置在所述第二放大器的正相端和反相端之间，所述振荡电路的振荡信号大于所述分压电阻的输入信号时，所述第二开关截止，所述第三开关导通，通过所述第二电流源对所述第二泄放电容中存储的电荷进行泄放，使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
可选地，在本发明的一实施例中，还包括：差分单元，所述差分单元用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号，以根据所述振荡电路的振荡信号的峰值与参考信号的差值信号产生驱动信号。
可选地，在本发明的一实施例中，还包括：控制单元，用于根据所述振荡电路的振荡信号的峰值与参考信号之间的差值信号生成控制信号，对应地，所述压控单元根据所述控制信号生成所述驱动信号。
可选地，在本发明的一实施例中，所述差分单元为差分放大器，所述差分放大器用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号，所述控制单元为积分电容，所述积分电容设置所述差分放大器的反相端与输出端之间，所述积分电容用于对所述差值信号进行积分处理以生成控制信号。
可选地，在本发明的一实施例中，所述差分单元为跨导放大器，所述跨导放大器用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号；所述控制单元为积分电容，所述积分电容设置在所述跨导放大器的输出 端与地之间，所述积分电容用于对所述差值信号进行积分处理以生成控制信号。
可选地，在本发明的一实施例中，所述跨导放大器包括所述跨导放大器包括第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管，所述第一PMOS管的栅极连接至所述峰值检测单元的输出信号，第二PMOS管的栅极连接至所述参考信号，所述第一PMOS管的源极、第二PMOS管的源极分别于与电源电压连接，所述第一PMOS管的漏极与第一NMOS管的漏极连接，第二PMOS管的漏极与第二PMOS管的漏极连接并作为输出所述控制信号的端子，所述第一NMOS管的栅极与所述第二NMOS管的栅极连接，所述第一NMOS管的源极、第二NMOS管的源极分别与地连接，第一PNMOS管的栅极跨接到第一PMOS管的漏极。
本发明实施例还提供一种晶体振荡器，包括晶体和连接到晶体的控制电路，所述控制电路为上述任一实施例中所述的控制电路。
本发明实施例中，通过峰值检测单元检测晶体振荡器的振荡电路的振荡信号的峰值；压控单元根据所述振荡电路的振荡信号的峰值与一参考信号生成驱动信号，所述驱动信号用于使所述振荡电路起振并进入振荡稳定阶段，且所述驱动信号的振幅在所述振荡电路进入振荡稳定阶段之后降低，从而避免整个电路进入正反馈，可使得振荡器正常启动，继而可进入振荡稳定阶段。
附图说明
图1为本发明实施例一中峰值检测单元的结构框图；
图2为本发明实施例二中峰值检测单元的具体电路结构示意图；
图3为本发明实施例三中峰值检测单元的结构框图；
图4为本发明实施例四中峰值检测单元的具体电路结构示意图，
图5为本发明实施例五中差分单元和控制单元的组合结构示意图；
图6为本发明实施例六中差分单元和控制单元的组合结构示意图；
图7为本发明实施例七中差分单元和控制单元的组合结构示意图；
图8为本发明实施例八中跨导放大器的结构示意图；
图9为本发明实施例九中压控单元的结构示意图；
图10为本发明实施例十中晶体振荡器的模块示意图；
图11为本发明实施例十一中晶体振荡器的具体结构示意图；
图12为本发明实施例十二中各信号的波形示意图；
图13为本发明实施例十三中晶体振荡器的具体结构示意图；
图14为现有技术中的示例性振荡电路结构。
具体实施方式
以下将配合图式及实施例来详细说明本申请的实施方式，藉此对本申请如何应用技术手段来解决技术问题并达成技术功效的实现过程能充分理解并据以实施。
本发明下述实施例中的振荡器控制电路包括：压控单元、峰值检测单元，所述峰值检测单元用于检测振荡电路的振荡信号的峰值，所述压控单元用于根据所述振荡电路的振荡信号的峰值与参考信号生成驱动信号，所述驱动信号使所述振荡电路起振并进入振荡稳定阶段，且所述驱动信号的振幅在所述振荡电路进入振荡稳定阶段之后降低。
下述将分别上述振荡器控制电路包括的各个部件逐一进行说明。
图1为本发明实施例一中峰值检测单元的结构框图；如图1所示，其包括：第一放大器101、第一开关102、第一泄放电容103以及第一电流源104，所述第一放大器101用于接收所述振荡电路的振荡信号以及所述峰值检测单元的输出信号，具体如，第一放大器101的正相端接收所述振荡电路的振荡信号，所述第一放大器101的反相端接收所述峰值检测单元的输出信号。在所述振荡电路的振荡信号大于所述峰值检测单元的输出信号时，第一开关102导通，第一泄放电容103处于充电阶段，进而使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。在所述振荡电路的振荡信号小于所述峰值检测单元的输出信号时，所述第一电流源104用于对所述第一泄放电容103中存储的电荷进行泄放以复位所述峰值检测单元的输出信号，使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
图2为本发明实施例二中峰值检测单元的具体电路结构示意图，其可视 为图1所示实施例的一种具体实现方式；如图2所示，第一开关102可以选用NMOS管，对应的，峰值检测单元中各个电路结构件之间的关系如下：
第一放大器101的正相端接收所述振荡电路的振荡信号Vxi，所述第一放大器101的反相端接收所述峰值检测单元的输出信号Vpd；
作为第一开关102的NMOS管的栅极连接到第一放大器101的输出端，该NMOS管的漏端连接到电压源Vdd，该NMOS管的源极作为所述输出信号Vpd的输出端；
第一泄放电容103和第一电流源104并联后形成的一端连接到所述一NMOS管的源极，并联后形成的另外一端连接到地Vgnd。
本实施例中的峰值检测单元工作过程如下：
振荡电路的振荡信号由小到大，至振荡电路的振荡信号大于所述输出信号，作为第一开关102的NMOS管导通，使得第一泄放电容103处于充电状态，由于作为第一开关102的NMOS管具有较强的上拉能力，可使所述输出信号逐渐增大直至与所述振荡电路的振荡信号大小近似相等，进而实现了所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测；
振荡电路的振荡信号由大到小，至振荡电路的振荡信号小于所述输出信号时，作为第一开关102的NMOS管关断，此时，第一泄放电容103处于放电状态，第一泄放电容103中存储的电荷具体通过所述第一电流源104泄放，使得所述输出信号变小，但是，由于作为第一开关102的NMOS管具有较弱的下拉能力，所述输出信号变小的并不会太多，使所述输出信号复位从而逐渐与所述振荡电路的振荡信号大小近似相等，进而实现了所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
另外，在其他实施例中，上述第一开关102也可以为PMOS管，此时，第一放大器101的负相端可以接收所述振荡电路的振荡信号Vxi，推而广之，只要是第一开关102可与第一放大器101形成负反馈的任一电路变形均可，详细不再赘述。
图3为本发明实施例三中峰值检测单元的结构框图；如图3所示，其包括：第二放大器301、第三放大器302、第二开关303、第三开关304、第二泄放电容305以及第二电流源306，所述第二放大器301和第三放大器302之 间设置有第一分压电阻307，具体地，所述第二放大器301的反相端和第三放大器302的反相端之间设置有第一分压电阻307，所述第二放大器301的正相端接收所述振荡电路的振荡信号，所述第二开关303设置在所述第二放大器301的正相端和反相端之间，所述第三放大器302的反相端接收所述峰值检测单元的输出信号，当所述振荡电路的振荡信号大于所述第一分压电阻307的输入信号时，所述第二开关303导通，第二泄放电容305处于充电阶段，使得第三放大器302正相端的输入信号增加，直至所述第一分压电阻307的输入信号、所述峰值检测单元的输出信号、第三放大器302正相端的输入信号三者相等，此时，第三放大器302正相端的输入信号增加，从而最终实现了所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。当所述振荡电路的振荡信号小于所述第一分压电阻307的输入信号时，第二放大器的输出信号减小，所述第二开关303截止，所述第三开关304导通，此时，第一分压电阻307的输入信号跟随所述振荡电路的振荡信号，保持第一分压电阻307的输入信号跟随所述振荡电路的振荡信号相等，由于第二开关303的截止，使得峰值检测单元的输出信号维持第三放大器正相端的输入信号，从而最终实现了所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
图4为本发明实施例四中峰值检测单元的具体电路结构示意图，其可视为图3所示实施例的一种具体实现方式。如图4所示，第二开关303示意性地为第一二极管，第三开关304示意性地为第二二极管；对应地，峰值检测单元中各个电路结构件的连接关系如下：
第二放大器301的正相端接收振荡电路的振荡信号Vxi，第二放大器302之间设置有第一分压电阻307，示例性地如第二放大器301的反相端与第三放大器302的反相端之间设置有所述第一分压电阻307。具体地，第二放大器301的反相端与第一分压电阻307的一端连接并与第三开关304的正极连接，第二放大器301的输出端与第二开关303的正极连接并与第三开关304的负极连接；
第三放大器302的正相端与第二开关303的负极连接，第三放大器302的负相端与第一分压电阻307的另外一端连接，第三放大器302的输出端作为峰值检测单元的输出端，输出峰值检测单元的输出信号Vpd；
第二泄放电容305与第二电流源306并联后形成的一端连接在所述第二开关303的负极与第三放大器302的正相端之间，并联后形成的另外一端连接到地Vgnd。
类似的，本实施例的峰值检测电路工作过程如下：
当所述振荡电路的振荡信号Vxi大于所述第一分压电阻307的输入信号Vfb时，所述第二开关303导通，第二泄放电容305处于充电阶段，使得第三放大器302正相端的输入信号Vh增加，直至所述第一分压电阻307的输入信号Vfb、所述峰值检测单元的输出信号Vpd、第三放大器302正相端的输入信号Vh三者相等，此时，第三放大器302正相端的输入信号Vh增加，从而最终实现了所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。当所述振荡电路的振荡信号Vxi小于所述第一分压电阻307的输入信号Vfb时，第二放大器301的输出信号Vo减小，所述第二开关303截止，所述第三开关304导通，此时，第一分压电阻307的输入信号Vfb跟随所述振荡电路的振荡信号Vxi，保持第一分压电阻307的输入信号Vfb跟随所述振荡电路的振荡信号Vxi相等，由于第二开关303的截止，使得峰值检测单元的输出信号Vpd维持第三放大器正相端的输入信号Vh，从而最终实现了所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
在上述图1-图4的基础上，晶体振荡器控制电路还可以包括差分单元，所述差分单元用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号，以根据所述振荡电路的振荡信号的峰值与参考信号的差值信号产生驱动信号。
在上述图1-图4的基础上，晶体振荡器控制电路还可以包括：控制单元，用于根据所述振荡电路的振荡信号的峰值与参考信号之间的差值信号生成控制信号，对应地，所述压控单元根据所述振荡信号的峰值与参考信号之间的差值信号生成的控制信号生成驱动信号。
图5为本发明实施例五中差分单元和控制单元的组合结构示意图；如图5所示，所述差分单元为跨导放大器501，所述跨导放大器501用于计算所述振 荡电路的振荡信号的峰值与参考信号之间的差值信号，所述控制单元为积分电容Ci，所述积分电容Ci设置在所述跨导放大器的反相端与输出端之间，所述积分电容Ci用于对所述差值信号进行积分处理以生成控制信号。
本实施例中，所述跨导放大器501的正相端连接所述峰值检测单元的输出信号Vpd，所述跨导放大器501的负相端连接参考信号Vr,通过所述跨导放大器501对所述峰值检测单元的输出信号Vpd与参考信号Vr的差值信号ΔV进行处理，从而在所述跨导放大器的输出端产生对应的输出信号I＝ΔV*gm，gm表示差分单元的增益；所述积分电容Ci跨接在所述跨导放大器501的负相端与所述跨导放大器501的输出端之间，所述积分电容Ci对所述跨导放大器输出端的输出信号I进行积分处理，从而最终生成控制信号Vc。
图6为本发明实施例六中差分单元和控制单元的组合结构示意图；如图6所示，与上述图5实施例不同的是，本实施例中，差分单元具体为差分放大器502，其负相端连接第二分压电阻503的一端以接收第二分压电阻503的输出信号Vfb，第二分压电阻503的另外一端接收参考信号Vr，控制单元具体为积分电容Ci。
本实施例中，所述差分放大器502通过积分电容Ci形成负反馈，使得差分放大器502的正相端和负相端虚短状态，使得第二分压电阻503两端的信号差为峰值检测单元的输出信号Vpd与第二分压电阻503的另一端接收的参考信号Vr之间的差值，从而通过所述差分放大器502与所述第二分压电阻503一起计算得到所述振荡电路的振荡信号的峰值与参考信号Vr之间的差值信号，该差值信号再经过第二分压电阻503转换成上述输出信号I，再通过积分电容Ci积分处理后得到控制信号Vc。
图7为本发明实施例七中差分单元和控制单元的组合结构示意图；如图7所示，所述差分单元为跨导放大器501，所述跨导放大器501用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号；所述控制单元为积分电容Ci，所述积分电容Ci设置在所述跨导放大器501的输出端与地之间，所述积分电容Ci用于对所述差值信号进行积分处理以生成控制信号Vc。
具体地，跨导放大器501的正相端接收峰值检测单元的输出信号Vpd，跨导放大器501的负相端接收参考信号Vr，通过所述跨导放大器501对所述峰 值检测单元的输出信号Vpd与参考信号Vr的差值信号ΔV进行处理在所述差分单元的输出端产生对应的输出信号I，所述积分电容Ci对所述差分单元输出端的输出信号I进行积分处理，从而最终生成控制信号Vc；
图8为本发明实施例八中跨导放大器的结构示意图；如图8所示，其包括第一PMOS管811、第二PMOS管821、第一NMOS管831、第二NMOS管841，所述第一PMOS管811的栅极连接至所述峰值检测单元的输出信号Vpd，第二PMOS管821的栅极连接至所述参考信号Vr，所述第一PMOS管811的源极、第二PMOS管821的源极分别与电源电压Vdd连接，所述第一PMOS管811的漏极与第一NMOS管831的漏极连接，第二PMOS管821的漏极与第二NMOS管841的漏极连接并作为输出所述控制信号Vc的端子，所述第一NMOS管831的栅极与所述第二NMOS管841的栅极连接，所述第一NMOS管831的源极、第二NMOS管841的源极分别与地Vgd连接，第一NMOS管831的栅极跨接到第一PMOS管811的漏极。
图9为本发明实施例九中压控单元的结构示意图；如图9所示，本实施例中，压控单元具体为PMOS管M4，作为所述压控单元的PMOS管的源极接收电压源VDD，作为所述压控单元的PMOS管的栅极接收上述实施例中的控制信号Vc，作为所述压控单元的PMOS管的漏极与振荡电路的驱动单元连接，用于形成负反馈，以控制驱动单元的输出信号，进而最终实现对振荡电路的驱动信号的控制。
图10为本发明实施例十中晶体振荡器的模块示意图；如图10所示，其包括：差分单元1001、控制单元1002、压控单元1003、振荡电路1004、峰值检测电路1005，各个模块单元的详细功能参见上述实施例，在此不再赘述。
差分单元1001可选用上述图5-7中的任一差分单元，控制单元1002可参见上述图5-7的描述，压控单元1003可参见上述图9记载，振荡电路1004、峰值检测电路1005可参见上述实施例中的相关记载，在此不再赘述。
图11为本发明实施例十一中晶体振荡器的具体结构示意图；如图11所示，其包括与图2所示峰值检测单元相同的峰值检测单元1005、与图5中差分单元相同的差分单元1001、与图5中控制单元相同的控制单元1002、与图 9中的压控单元相同的压控单元1003。本实施例中，各个电路结构单元内部元件的连接关系不再赘述，只具体说明晶体振荡器的各个电路结构单元之间的连接关系如下：
峰值检测单元1005的输出端与差分单元1001的正相端连接，以使得所述差分单元1001的正相端可接收峰值检测单元1005的输出信号Vpd，图中的电容Ch即为上述图2中的第一泄放电容103；
所述差分单元1001与所述控制单元1002组合结构的输出端与作为压控单元1003的PMOS管的栅极连接；
作为驱动电路的驱动管M1如PMOS管的源极与作为压控单元1003的PMOS管的漏极连接，作为驱动电路的驱动管如PMOS管的栅极接收一偏置电压Vb，作为驱动电路的驱动管如PMOS管的漏极连接到振荡电路1004的输入端；
振荡电路1004示意性地为皮尔斯振荡电路1004结构，其具体包括振荡晶体管如NMOS管、置于振荡晶体管漏极与栅极之间的晶体、两个滤波电容C1、C2，皮尔斯振荡电路1004结构详细不再赘述。
图12为本发明实施例十二中各信号的波形示意图；参照图12的波形，图11中的晶体振荡器工作过程如下：
起初控制信号为0，振荡电路开始起振，驱动信号以及振荡电路的振荡信号Vxi逐渐增大，峰值检测单元的输出信号Vpd也随之增大，峰值检测单元的输出信号Vpd与参考信号Vr的差值信号ΔV逐渐变小直至峰值检测单元的输出信号Vpd大于参考信号Vr,并在所述差分单元的输出端产生对应的输出信号I，进而再经过积分电容积分处理后使得控制信号Vc逐渐增大，随着控制信号Vc的增大，作为压控单元的PMOS管的沟道电阻逐渐增大，进而使得作为驱动单元的PMOS管的源极对地电压反馈增强，使得作为驱动单元的PMOS管的漏极端的输出电流减小，从而使得作为驱动单元的PMOS管的漏极端输出的驱动信号减小，最终使得振荡电路的振荡信号Vxi减小。
图13为本发明实施例十三中晶体振荡器的具体结构示意图；如图13所示，包括与图4所示峰值检测单元相同的峰值检测单元1005、与图6中差分单元相同的差分单元1001、与图6中控制单元相同的控制单元1002、与图9中的压控单元相同的压控单元1003。本实施例中，各个电路结构单元内部元件的连接关系不再赘述，只具体说明晶体振荡器的各个电路结构单元之间的 连接关系如下：
峰值检测单元1005的输出端与差分单元1001的正相端连接，以使得所述差分单元1001的正相端可接收峰值检测单元1005的输出信号Vpd，图中的电容Ch即为上述图4中的第二泄放电容305；
所述差分单元1001与所述控制单元1002组合结构的输出端与作为压控单元1003的PMOS管的栅极连接；
作为驱动电路的驱动管M1如PMOS管的源极与作为压控单元1003的PMOS管的漏极连接，作为驱动电路的驱动管如PMOS管的栅极接收一偏置电压Vb，作为驱动电路的驱动管如PMOS管的漏极连接到振荡电路1004的输入端；
振荡电路1004示意性地为皮尔斯振荡电路1004结构，其具体包括振荡晶体管如NMOS管、置于振荡晶体管漏极与栅极之间的晶体、两个滤波电容C1、C2，皮尔斯振荡电路1004结构详细不再赘述。
本申请的实施例所提供的装置可通过计算机程序实现。本领域技术人员应该能够理解，上述的单元以及模块划分方式仅是众多划分方式中的一种，如果划分为其他单元或模块或不划分块，只要信息对象的具有上述功能，都应该在本申请的保护范围之内。
本领域的技术人员应明白，本申请的实施例可提供为方法、装置(设备)、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、装置(设备)和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设 备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种晶体振荡器控制电路，其特征在于，包括：
    峰值检测单元，用于检测晶体振荡器的振荡电路的振荡信号的峰值；
    压控单元，用于根据所述振荡电路的振荡信号的峰值与一参考信号生成驱动信号，所述驱动信号用于使所述振荡电路起振并进入振荡稳定阶段，且所述驱动信号的振幅在所述振荡电路进入振荡稳定阶段之后降低。
  2. 根据权利要求1所述的控制电路，其特征在于，所述峰值检测单元包括：
    第一放大器，用于接收所述振荡电路的振荡信号以及所述峰值检测单元的输出信号；
    第一开关，在所述振荡电路的振荡信号大于所述峰值检测单元的输出信号时，所述第一开关导通，以使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
  3. 根据权利要求2所述的控制电路，其特征在于，所述第一放大器的正相端接收所述振荡电路的振荡信号，所述第一放大器的负相端接收所述峰值检测单元的输出信号。
  4. 根据权利要求2所述的控制电路，其特征在于，所述峰值检测单元还包括：第一泄放电容以及第一电流源，在所述振荡电路的振荡信号小于所述峰值检测单元的输出信号时，所述第一电流源用于对所述第一泄放电容中存储的电荷进行泄放以复位所述峰值检测单元的输出信号，使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
  5. 根据权利要求1所述的控制电路，其特征在于，所述峰值检测单元包括第二放大器、第三放大器、第二开关，所述第二放大器和第三放大器之间设置有分压电阻，所述第二放大器的正相端接收所述振荡电路的振荡信号，所述第二开关设置在所述第二放大器的正相端和反相端之间，所述第三放大器的反相端接收所述峰值检测单元的输出信号，当所述振荡电路的振荡信号大于所述分压电阻的输入信号时，所述第二开关导通，以使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
  6. 根据权利要求5所述的控制电路，其特征在于，所述峰值检测单元还包括：第三开关、第二泄放电容以及第二电流源，所述第三开关设置在所述第二放大器的正相端和反相端之间，所述振荡电路的振荡信号大于所述分压电阻的输入信号时，所述第二开关截止，所述第三开关导通，通过所述第二电流源对所述第二泄放电容中存储的电荷进行泄放，使得所述峰值检测单元的输出信号跟随所述振荡电路的振荡信号以对所述振荡信号的峰值进行检测。
  7. 根据权利要求1所述的控制电路，其特征在于，还包括：差分单元，所述差分单元用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号，以根据所述振荡电路的振荡信号的峰值与参考信号的差值信号产生驱动信号。
  8. 根据权利要求7所述的控制电路，其特征在于，还包括：控制单元，用于根据所述振荡电路的振荡信号的峰值与参考信号之间的差值信号生成控制信号，对应地，所述压控单元根据所述振荡信号的峰值控制信号生成所述驱动信号。
  9. 根据权利要求8所述的控制电路，其特征在于，所述差分单元为差分放大器，所述差分放大器用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号，所述控制单元为积分电容，所述积分电容设置所述差分放大器的反相端与输出端之间，所述积分电容用于对所述差值信号进行积分处理以生成控制信号。
  10. 根据权利要求8所述的控制电路，其特征在于，所述差分单元为跨导放大器，所述跨导放大器用于计算所述振荡电路的振荡信号的峰值与参考信号之间的差值信号；所述控制单元为积分电容，所述积分电容设置在所述跨导放大器的输出端与地之间，所述积分电容用于对所述差值信号进行积分处理以生成控制信号。
  11. 根据权利要求10所述的控制电路，其特征在于，所述跨导放大器包括第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管，所述第一PMOS管的栅极连接至所述峰值检测单元的输出信号，第二PMOS管的栅极连接至所述参考信号，所述第一PMOS管的源极、第二PMOS管的源极分别与电源电压连接，所述第一PMOS管的漏极与第一NMOS管的漏极连接，第二PMOS管的漏极与第二PMOS管的漏极连接并作为输出所述控制信号的端子，所述第一NMOS 管的栅极与所述第二NMOS管的栅极连接，所述第一NMOS管的源极、第二NMOS管的源极分别与地连接，第一NMOS管的栅极跨接到第一PMOS管的漏极。
  12. 一种晶体振荡器，包括晶体和连接到晶体的控制电路，其特征在于，所述控制电路为权利要求1-11任一项所述的控制电路。
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